DISPLAY PANEL AND DISPLAY DEVICE

Abstract

The present disclosure relates to the field of display technology and provides a display panel and a display device. The display panel includes a display region and a fan-out region located in the display region. The display panel further includes a base substrate, a plurality of data lines, a plurality of first data fan-out lines, and a plurality of second data fan-out lines. The orthographic projections of the data lines on the base substrate are distributed along a first direction and extend along a second direction, wherein the first direction and the second direction intersect.The orthographic projections of the first data fan-out lines on the base substrate are distributed along the second direction at a distance from each other and extend along the first direction. The first data fan-out lines are provided correspondingly to the data lines, and the first data fan-out line is connected to the corresponding data line. The orthographic projections of the second data fan-out lines on the base substrate are distributed along the first direction at a distance from each other and extend along the second direction. The second data fan-out lines are provided correspondingly to the first data fan-out lines, and the second data fan-out line is connected to the corresponding first data fan-out line. This display panel enables a narrower bezel design.

Description

Display panel and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202210935801.1, filed on August 4, 2022, entitled “Display Panel and Display Device.” The disclosure of the aforementioned Chinese patent application is hereby incorporated by reference in its entirety as part of this application. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0004] In the related art, the border of the display panel is relatively wide.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0006] Summary of the Invention

[0007] According to one aspect of the present disclosure, a display panel is provided, comprising a display area and a fan-out area located in the display area. The display panel further comprises: a substrate, a plurality of data lines, a plurality of first data fan-out lines, and a plurality of second data fan-out lines. The plurality of data lines are located in the display area, the orthographic projections of the data lines on the substrate being spaced apart along a first direction and extending along a second direction, the first direction and the second direction intersecting; the plurality of first data fan-out lines are located in the fan-out area, the orthographic projections of the first data fan-out lines on the substrate being spaced apart along the second direction and extending along the first direction, the first data fan-out lines being arranged correspondingly to the data lines, and the first data fan-out lines being connected to the corresponding data lines; the plurality of second data fan-out lines are located in the fan-out area, the orthographic projections of the second data fan-out lines on the substrate being spaced apart along the first direction and extending along the second direction, the second data fan-out lines being arranged correspondingly to the first data fan-out lines, and the second data fan-out lines being connected to the corresponding first data fan-out lines.

[0008] In an exemplary embodiment of the present disclosure, the display panel further includes: a plurality of first signal lines and a plurality of second signal lines, wherein the plurality of first signal lines are located in the display area, the orthographic projections of the first signal lines on the substrate extend along the first direction and are spaced apart along the second direction, the plurality of first signal lines include first sub-signal lines, and at least a portion of the structure of the first sub-signal lines is used to form the first data fan-out lines; a plurality of second signal lines are located in the display area and are located in a different conductive layer from the first signal lines, the orthographic projections of the second signal lines on the substrate extend along the second direction and are spaced apart along the first direction, the plurality of second signal lines include second sub-signal lines, and at least a portion of the structure of the second sub-signal lines is used to form the second data fan-out lines.

[0009] In an exemplary embodiment of the present disclosure, the minimum distance between the orthographic projections of two adjacent first signal lines on the substrate in the second direction is S1, and the maximum distance between the orthographic projections of two adjacent first signal lines on the substrate in the second direction is S2, wherein (S2-S1) / S1 is greater than or equal to 0 and less than or equal to 0.2; and / or, the minimum distance between the orthographic projections of two adjacent second signal lines on the substrate in the first direction is S3, and the maximum distance between the orthographic projections of two adjacent second signal lines on the substrate in the first direction is S4, wherein (S4-S3) / S3 is greater than or equal to 0 and less than or equal to 0.2.

[0010] In an exemplary embodiment of the present disclosure, the first sub-signal line also includes a first analog line spaced apart from the first data fan-out line, and the second sub-signal line also includes a second analog line spaced apart from the second data fan-out line; the fan-out area includes a first fan-out area and a second fan-out area, the first data fan-out line is located in the first fan-out area, and the second data fan-out line is located in the second fan-out area; the plurality of first signal lines also include a third analog line, and the third analog line is located in a display area outside the first fan-out area; the plurality of second signal lines also include a fourth analog line, and the fourth analog line is located in a display area outside the second fan-out area.

[0011] In an exemplary embodiment of the present disclosure, the display panel also includes a pixel driving circuit and a light-emitting unit, and the pixel driving circuit is connected to the first electrode of the light-emitting unit; the display panel also includes: a common electrode layer, and the common electrode layer is used to form the second electrode of the light-emitting unit; wherein the first analog line, the second analog line, the third analog line, and the fourth analog line are connected to the common electrode layer.

[0012] In an exemplary embodiment of the present disclosure, the first simulation line is connected to the fourth simulation line intersecting with its orthographic projection on the substrate through a via; the third simulation line is connected to the second simulation line and the fourth simulation line intersecting with their orthographic projection on the substrate through a via.

[0013] In an exemplary embodiment of the present disclosure, the display panel also includes a border area located around the display area, the border area includes a first border area and a second border area arranged opposite to each other, and the fan-out area is located on a side close to the second border area; the display panel also includes: an electrode ring and a power supply circuit, the electrode ring is located in the border area and is connected to the common electrode layer, at least part of the structure of the electrode ring located in the first border area is connected to the second analog line and the fourth analog line; the power supply circuit is bound to the second border area, the power supply circuit is connected to at least part of the structure of the electrode ring located in the second border area, and the power supply circuit is used to provide a power supply signal to the electrode ring.

[0014] In an exemplary embodiment of the present disclosure, the first fan-out area includes a first sub-fan-out area and a second sub-fan-out area, and the first sub-fan-out area and the second sub-fan-out area are located on both sides of the second fan-out area in the first direction; the plurality of second signal lines also include at least one fifth analog line, a partial structure of the fifth analog line is located in the second fan-out area, and the fifth analog line is respectively connected to the first analog line and the third analog line that intersect with its orthographic projection on the substrate through vias.

[0015] In an exemplary embodiment of the present disclosure, multiple first signal lines are located in the same conductive layer, and multiple second signal lines are located in the same conductive layer; the conductive layer where the second signal lines are located is located on a side of the conductive layer where the first signal lines are located away from the base substrate.

[0016] In an exemplary embodiment of the present disclosure, the display panel further includes: a first source-drain layer and a second source-drain layer, the first source-drain layer being located on one side of the base substrate, the first source-drain layer including the first signal line; the second source-drain layer being located on a side of the first source-drain layer away from the base substrate, the second source-drain layer including the second signal line and the data line; the orthographic projection of the second signal line on the base substrate being located between the orthographic projections of two adjacent data lines on the base substrate.

[0017] In an exemplary embodiment of the present disclosure, the first signal line includes a plurality of first via contacts and a first extension, the orthographic projections of the plurality of first via contacts on the substrate being spaced apart along the first direction, the first extension being connected to the first via contact, and the orthographic projection of the first via contact on the substrate being larger than the orthographic projection of the first extension on the substrate in the second direction; the second signal line includes a plurality of second via contacts and a second extension, the orthographic projections of the plurality of second via contacts on the substrate being spaced apart along the second direction, the second extension being connected to the second via contact, and the orthographic projection of the second via contact on the substrate being larger than the orthographic projection of the second extension on the substrate in the first direction; wherein the first via contacts and the second via contacts are arranged correspondingly, the orthographic projection of the first via contact on the substrate and the orthographic projection of the corresponding second via contact on the substrate at least partially overlap, and at least part of the first via contacts are connected to the corresponding second via contacts through vias.

[0018] In an exemplary embodiment of the present disclosure, the minimum distance between the orthographic projections of adjacent first via contact portions on the substrate in the first direction is S5, and the maximum distance between the orthographic projections of adjacent first via contact portions on the substrate in the first direction is S6, wherein (S6-S5) / S5 is greater than or equal to 0 and less than or equal to 0.2; and / or, the minimum distance between the orthographic projections of adjacent second via contact portions on the substrate in the second direction is S7, and the maximum distance between the orthographic projections of adjacent second via contact portions on the substrate in the second direction is S8, wherein (S8-S7) / S7 is greater than or equal to 0 and less than or equal to 0.2.

[0019] In an exemplary embodiment of the present disclosure, the plurality of first via contact portions include a first real hole contact portion, and the plurality of second via contact portions include a second real hole contact portion and a second virtual hole contact portion; the first real hole contact portion and the corresponding second real hole contact portion are connected through a via hole, and the second virtual hole contact portion and the first signal line intersecting with its orthographic projection on the substrate are insulated.

[0020] In an exemplary embodiment of the present disclosure, the plurality of first via contact portions further include a first dummy hole contact portion, and the first dummy hole contact portion and the corresponding second dummy hole contact portion are insulated from each other.

[0021] In an exemplary embodiment of the present disclosure, the display panel includes: a first planar layer, the first planar layer is located between the first source / drain layer and the second source / drain layer, and the thickness of the first planar layer is less than or equal to 1.6 um.

[0022] In an exemplary embodiment of the present disclosure, the display panel further includes: a passivation layer and a first flat layer, the passivation layer being located between the conductive layer where the first signal line is located and the conductive layer where the second signal line is located; the first flat layer being located between the passivation layer and the conductive layer where the second signal line is located; wherein a first opening is formed on the first flat layer, and the orthographic projection of the first opening on the base substrate at least partially overlaps with the orthographic projection of the second virtual hole contact portion on the base substrate.

[0023] In an exemplary embodiment of the present disclosure, the display panel further includes: a passivation layer and a first flat layer, the passivation layer being located between the conductive layer where the first signal line is located and the conductive layer where the second signal line is located; the first flat layer being located between the passivation layer and the conductive layer where the second signal line is located; wherein a second opening is formed on the passivation layer, and the orthographic projection of the second opening on the base substrate at least partially overlaps with the orthographic projection of the second virtual hole contact portion on the base substrate.

[0024] In an exemplary embodiment of the present disclosure, the size of the orthographic projection of the break between the first data fan-out line and the first simulation line on the substrate in the first direction is 1.5um-3.5um; and / or the size of the orthographic projection of the break between the second data fan-out line and the second simulation line on the substrate in the second direction is 1.5um-3.5um.

[0025] In an exemplary embodiment of the present disclosure, the data line whose orthographic projection on the substrate is located on two adjacent sides of the second signal line includes a third extension portion, a fourth extension portion, and a fifth extension portion, and the fourth extension portion is connected between the third extension portion and the fifth extension portion; the second via contact portion and at least part of the structure of the fourth extension portion are relatively arranged in the first direction, and the orthographic projection of the fourth extension portion on the substrate and the orthographic projection of the second extension portion on the substrate in the first direction are larger than the orthographic projection of the third extension portion on the substrate and the orthographic projection of the second extension portion on the substrate in the first direction, and the orthographic projection of the fourth extension portion on the substrate and the orthographic projection of the second extension portion on the substrate in the first direction are larger than the orthographic projection of the fifth extension portion on the substrate and the orthographic projection of the second extension portion on the substrate in the first direction.

[0026] In an exemplary embodiment of the present disclosure, the display panel also includes a pixel driving circuit and a light-emitting unit, the pixel driving circuit is connected to the first electrode of the light-emitting unit, and the display panel also includes: an electrode layer, the electrode layer is located on one side of the base substrate, the electrode layer includes a plurality of electrode portions, and the electrode portions are used to form the first electrode of the light-emitting unit; the orthographic projection of the break between the first data fan-out line and the first analog line on the base substrate does not overlap with the orthographic projection of the electrode portion on the base substrate; and / or, the orthographic projection of the break between the second data fan-out line and the second analog line on the base substrate does not overlap with the orthographic projection of the electrode portion on the base substrate.

[0027] In an exemplary embodiment of the present disclosure, the display panel also includes a pixel driving circuit and a light-emitting unit, the pixel driving circuit is connected to the first electrode of the light-emitting unit, and the display panel also includes: an electrode layer, the electrode layer is located on one side of the base substrate, the electrode layer includes a plurality of electrode portions, and the electrode portions are used to form the first electrode of the light-emitting unit; the orthographic projection of the first via contact portion on the base substrate and the orthographic projection of the electrode portion on the base substrate do not overlap; the orthographic projection of the second via contact portion on the base substrate and the orthographic projection of the electrode portion on the base substrate do not overlap.

[0028] In an exemplary embodiment of the present disclosure, the display panel also includes a plurality of pixel driving circuits and a plurality of light-emitting units, and the plurality of pixel driving circuits are arrayed along the first direction and the second direction, and the pixel driving circuit is connected to the first electrode of the light-emitting unit; the pixel driving circuit includes a driving transistor, a sixth transistor, and a seventh transistor, the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit, the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit. The display panel also includes: a first active layer and a first gate layer, the first active layer is located on one side of the base substrate, the first active layer includes a sixth active portion and a seventh active portion, the sixth active portion is used to form a channel region of the sixth transistor, and the seventh active portion is used to form a channel region of the seventh transistor; a first gate layer is located on the side of the first active layer away from the base substrate, the first gate layer includes an enable signal line and a second reset signal line, the orthographic projection of the enable signal line on the base substrate extends along the first direction and covers the orthographic projection of the sixth active portion on the base substrate, and the orthographic projection of the second reset signal line on the base substrate extends along the first direction and covers the orthographic projection of the seventh active portion on the base substrate; wherein, the first direction is a row direction, and the orthographic projection of the first signal line on the base substrate is located between the orthographic projection of the enable signal line on the base substrate and the orthographic projection of the second reset signal line on the base substrate in the same row of pixel driving circuits.

[0029] In an exemplary embodiment of the present disclosure, the display panel further includes a plurality of pixel driving circuits and a plurality of light-emitting units, wherein the plurality of pixel driving circuits are arrayed along the first direction and the second direction, the pixel driving circuits being connected to the first electrodes of the light-emitting units; the pixel driving circuits including a driving transistor, a sixth transistor, and a first transistor, wherein the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit, the first electrode of the first transistor is connected to a first initial signal line, and the second electrode of the first transistor is connected to the gate of the driving transistor. The display panel further includes a first gate layer and a second gate layer, wherein the first gate layer is located on one side of the substrate, the first gate layer including an enable signal line, a portion of the structure of the enable signal line being used to form the gate of the sixth transistor; the second gate layer is located on a side of the first gate layer facing away from the substrate, the second gate layer including the first initial signal line; the orthographic projection of a first extension portion of the first signal line on the substrate being located between the orthographic projection of the first initial signal line in the pixel driving circuit of the current row on the substrate and the orthographic projection of the enable signal line in the pixel driving circuit of the next adjacent row on the substrate.

[0030] In an exemplary embodiment of the present disclosure, the display panel includes a plurality of repeating units arrayed in the first direction and the second direction, the repeating unit including n rows and m columns of sub-repeating units, where n and m are positive integers greater than or equal to 1; the sub-repeating unit includes two pixel driving circuits adjacently distributed in the first direction, and the two pixel driving circuits in the same sub-repeating unit are mirror-symmetrically arranged; the plurality of repeating units distributed in the second direction form a repeating unit column, and a second signal line is correspondingly arranged between two adjacent repeating unit columns in the first direction; the plurality of repeating units distributed in the first direction form a repeating unit row, and each repeating unit row is correspondingly provided with a first signal line.

[0031] In an exemplary embodiment of the present disclosure, the display panel also includes a light-emitting unit, the pixel driving circuit is connected to the first electrode of the light-emitting unit, and the display panel also includes: an electrode layer, the electrode layer includes a plurality of electrode portions, and the electrode portions are used to form the first electrode of the light-emitting unit; wherein, in two adjacent sub-repeating units in the first direction, the orthographic projections of two adjacent data lines on the base substrate intersect with the orthographic projection of the same electrode portion on the base substrate, and are located on both sides of the orthographic projection of the second signal line on the base substrate.

[0032] In an exemplary embodiment of the present disclosure, m is a positive integer greater than or equal to 2; in the adjacent columns of repeating units in the first direction, the minimum distance between the orthographic projections of two adjacent data lines on the substrate in the first direction is L1; in the two sub-repeating units located in the same repeating unit and adjacent in the first direction, the minimum distance between the orthographic projections of two adjacent data lines on the substrate in the first direction is L2; ​​wherein L1 is greater than L2.

[0033] In an exemplary embodiment of the present disclosure, n is a positive integer greater than or equal to 2; the display panel further includes a light-emitting unit, the pixel driving circuit includes a driving transistor, a sixth transistor, and a seventh transistor, the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit, the gate of the sixth transistor is connected to the enable signal line, the first electrode of the seventh transistor is connected to the second initial signal line, the second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit, and the gate of the seventh transistor is connected to the second reset signal line; the same repeating unit row includes a first pixel driving circuit row and a second pixel driving circuit row, the first pixel driving circuit row includes a plurality of pixel driving circuits distributed along the first direction, and the second pixel driving circuit row includes a plurality of pixel driving circuits distributed along the first direction. The pixel driving circuit row includes a plurality of pixel driving circuits distributed along the first direction; the orthographic projection of the first signal line on the substrate is located between the orthographic projection of the enable signal line in the first pixel driving circuit row on the substrate and the orthographic projection of the second reset signal line in the first pixel driving circuit row on the substrate; in the first pixel driving circuit row, the minimum distance between the orthographic projection of the enable signal line on the substrate and the orthographic projection of the second reset signal line on the substrate in the second direction is L3; in the second pixel driving circuit row, the minimum distance between the orthographic projection of the enable signal line on the substrate and the orthographic projection of the second reset signal line on the substrate in the second direction is L4; wherein, L3 is greater than L4.

[0034] In an exemplary embodiment of the present disclosure, the display panel includes a pixel driving circuit and a light-emitting unit, and the pixel driving circuit includes a driving transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a capacitor; the first electrode of the first transistor is connected to the first initial signal line, and the second electrode is connected to the gate of the driving transistor; the first electrode of the second transistor is connected to the gate of the driving transistor, and the second electrode is connected to the second electrode of the driving transistor; the first electrode of the fourth transistor is connected to the data line, and the second electrode is connected to the first electrode of the driving transistor; the first electrode of the fifth transistor is connected to the power line, and the second electrode is connected to the first electrode of the driving transistor; the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light-emitting unit; the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode is connected to the first electrode of the light-emitting unit; the first electrode of the capacitor is connected to the gate of the driving transistor, and the second electrode is connected to the power line.

[0035] In an exemplary embodiment of the present disclosure, the display panel further comprises: a first active layer, a first gate layer, a second active layer, and a third gate layer. The first active layer is located on one side of the substrate base, the first active layer comprises a third active portion, a fourth active portion, a fifth active portion, a sixth active portion, and a seventh active portion, the third active portion being used to form the channel region of the driving transistor, the fourth active portion being used to form the channel region of the fourth transistor, the fifth active portion being used to form the channel region of the fifth transistor, the sixth active portion being used to form the channel region of the sixth transistor, and the seventh active portion being used to form the channel region of the seventh transistor; the first gate layer is located on the side of the first active layer away from the substrate base, the first gate layer comprises a first gate line, an enable signal line, a second reset signal line, a first conductive portion, an orthographic projection of the first gate line on the base substrate extending along the first direction and covering an orthographic projection of the fourth active portion on the base substrate, an orthographic projection of the enable signal line on the base substrate extending along the first direction and covering an orthographic projection of the fifth active portion on the base substrate and an orthographic projection of the sixth active portion on the base substrate, an orthographic projection of the second reset signal line on the base substrate extending along the first direction and covering an orthographic projection of the seventh active portion on the base substrate, and the first conductive portion on the base substrate. The orthographic projection on the board covers the orthographic projection of the third active part on the base substrate; the second active layer is located on the side of the first gate layer away from the base substrate, the second active layer includes a first active part and a second active part, the first active part is used to form the channel region of the first transistor, and the second active part is used to form the channel region of the second transistor; the third gate layer is located on the side of the second active layer away from the base substrate, the third gate layer includes a second gate line and a first reset signal line, the orthographic projection of the second gate line on the base substrate extends along the first direction and covers the orthographic projection of the second active part on the base substrate, the orthographic projection of the first reset signal line on the base substrate extends along the first direction and covers the orthographic projection of the first active part on the base substrate; wherein, the orthographic projection of the second reset signal line on the base substrate, the orthographic projection of the enable signal line on the base substrate, the orthographic projection of the first conductive part on the base substrate, the orthographic projection of the second gate line on the base substrate, the orthographic projection of the first gate line on the base substrate, and the orthographic projection of the first reset signal line on the base substrate are distributed in sequence along the second direction.

[0036] In an exemplary embodiment of the present disclosure, the first direction is a row direction, the second direction is a column direction, and the first gate line in the pixel driving circuit of a current row is multiplexed as a second reset signal line in the pixel driving circuit of the next adjacent row.

[0037] In an exemplary embodiment of the present disclosure, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are P-type transistors, and the first transistor and the second transistor are N-type transistors.

[0038] In an exemplary embodiment of the present disclosure, the second signal line includes a plurality of second via contact portions, and the orthographic projections of the plurality of second via contact portions on the substrate are spaced apart along the second direction; in the same second signal line, the distance between the orthographic projections of two adjacent second via contact portions on the substrate in the second direction is A1, and the size of the orthographic projection of the break between the second data fan-out line and the second analog line on the substrate in the second direction is A2; A1 / A2 is greater than or equal to 27 and less than or equal to 68.

[0039] According to one aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel.

[0040] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0042] FIG1 is a schematic structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0043] FIG2 is a schematic structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0044] FIG3 is a partially enlarged view of the first area K1 in FIG2 ;

[0045] FIG4 is a partial structural diagram of the conductive layer where the first signal line in FIG3 is located;

[0046] FIG5 is a partial structural diagram of the conductive layer where the second signal line is located in FIG3;

[0047] FIG6 is a partially enlarged view of the second area K2 in FIG2 ;

[0048] FIG7 is a partial structural diagram of the conductive layer where the first signal line in FIG6 is located;

[0049] FIG8 is a partial structural diagram of the conductive layer where the second signal line is located in FIG6;

[0050] FIG9 is a partially enlarged view of the third area K3 in FIG2 ;

[0051] FIG10 is a partial structural layout diagram of the conductive layer where the first signal line in FIG9 is located;

[0052] FIG11 is a partial structural layout diagram of the conductive layer where the second signal line in FIG9 is located;

[0053] FIG12 is a partial enlarged view of the fourth area K4 in FIG2 ;

[0054] FIG13 is a partial structural layout diagram of the conductive layer where the first signal line in FIG12 is located;

[0055] FIG14 is a partial structural layout diagram of the conductive layer where the second signal line in FIG12 is located;

[0056] FIG15 is a partial enlarged view of the fifth area K5 in FIG2 ;

[0057] FIG16 is a partial structural layout diagram of the conductive layer where the first signal line in FIG15 is located;

[0058] FIG17 is a partial structural layout diagram of the conductive layer where the second signal line in FIG15 is located;

[0059] FIG18 is a partial enlarged view of the sixth area K6 in FIG2 ;

[0060] FIG19 is a partial structural layout diagram of the conductive layer where the first signal line in FIG18 is located;

[0061] FIG20 is a partial structural layout diagram of the conductive layer where the second signal line is located in FIG18;

[0062] FIG21 is a partial enlarged view of the seventh area K7 in FIG2 ;

[0063] FIG22 is a structural layout diagram of the conductive layer where the first signal line in FIG21 is located;

[0064] FIG23 is a structural layout diagram of the conductive layer where the second signal line in FIG21 is located;

[0065] FIG24 is a structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0066] FIG25 is a structural layout diagram of the conductive layer where the first signal line in FIG24 is located;

[0067] FIG26 is a structural layout diagram of the conductive layer where the second signal line in FIG24 is located;

[0068] FIG27 is a structural diagram of the electrode layer in FIG24;

[0069] FIG28 is a partial cross-sectional view of the display panel shown in FIG3 along the dotted line CC;

[0070] FIG29 is a schematic structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0071] FIG30 is a schematic structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0072] FIG31 is a schematic structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0073] FIG32 is a schematic diagram of the circuit structure of a pixel driving circuit in a display panel disclosed herein;

[0074] FIG33 is a timing diagram of each node in a driving method of the pixel driving circuit in FIG32;

[0075] FIG34 is a partial layout of the sixth area K6 in FIG2 ;

[0076] FIG35 is a structural diagram of the shielding layer in FIG34;

[0077] FIG36 is a structural layout diagram of the first active layer in FIG34;

[0078] FIG37 is a structural layout diagram of the first gate layer in FIG34;

[0079] FIG38 is a structural layout diagram of the second gate layer in FIG34;

[0080] FIG39 is a structural layout diagram of the second active layer in FIG34;

[0081] FIG40 is a structural layout diagram of the third gate layer in FIG34;

[0082] FIG41 is a structural layout diagram of the first source and drain layer in FIG34 ;

[0083] FIG42 is a structural layout diagram of the second source and drain layer in FIG34;

[0084] FIG43 is a structural diagram of the electrode layer in FIG34;

[0085] FIG44 is a structural layout diagram of the shielding layer and the first active layer in FIG34 ;

[0086] FIG45 is a structural layout diagram of the shielding layer, the first active layer, and the first gate layer in FIG34 ;

[0087] FIG46 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, and the second gate layer in FIG34 ;

[0088] FIG47 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in FIG34 ;

[0089] FIG48 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in FIG34 ;

[0090] FIG49 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source and drain layer in FIG34 ;

[0091] FIG50 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source-drain layer, and the second source-drain layer in FIG34 ;

[0092] FIG51 is a structural diagram of a single repeating unit in FIG34 ;

[0093] FIG52 is a structural diagram of the shielding layer in FIG51;

[0094] FIG53 is a structural layout diagram of the first active layer in FIG51;

[0095] FIG54 is a structural layout diagram of the first gate layer in FIG51;

[0096] FIG55 is a structural layout diagram of the second gate layer in FIG51;

[0097] FIG56 is a structural diagram of the second active layer in FIG51;

[0098] FIG57 is a structural layout diagram of the third gate layer in FIG51;

[0099] FIG58 is a structural layout diagram of the first source and drain layer in FIG51;

[0100] FIG59 is a structural layout diagram of the second source and drain layer in FIG51;

[0101] FIG60 is a structural diagram of the electrode layer in FIG51;

[0102] FIG61 is a structural layout diagram of the shielding layer and the first active layer in FIG51;

[0103] FIG62 is a structural layout diagram of the shielding layer, the first active layer, and the first gate layer in FIG51;

[0104] FIG63 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, and the second gate layer in FIG51;

[0105] FIG64 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in FIG51 ;

[0106] FIG65 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in FIG51;

[0107] FIG66 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source and drain layer in FIG51 ;

[0108] FIG67 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source-drain layer, and the second source-drain layer in FIG51 ;

[0109] FIG68 is a partial cross-sectional view of the display panel shown in FIG51 taken along dotted line EE. DETAILED DESCRIPTION

[0110] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0111] The terms "a", "an", and "said" are used to indicate that there are one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0112] As shown in FIG1 , it is a schematic structural diagram of an exemplary embodiment of a display panel disclosed herein. The display panel may include a display area AA, and a fan-out area FT located in the display area AA. The display panel also includes a base substrate, a plurality of data lines Da, a first data fan-out line Fa1, and a second data fan-out line Fa2. The data lines Da are located in the display area AA, and the orthographic projections of the data lines Da on the base substrate are spaced apart along a first direction X and extend along a second direction Y. The first direction X and the second direction Y may intersect. For example, the first direction X may be a row direction, and the second direction Y may be a column direction. The first data fan-out line Fa1 is located in the fan-out area FT, and the orthographic projections of the first data fan-out line Fa1 on the base substrate may be spaced apart along a second direction Y and extend along the first direction X. The first data fan-out line Fa1 is arranged corresponding to the data line Da, and the first data fan-out line Fa1 is connected to the corresponding data line Da. The second data fan-out lines Fa2 are located in the fan-out region FT. Their orthographic projections on the substrate are spaced apart along the first direction X and extend along the second direction Y. The second data fan-out lines Fa2 are arranged corresponding to the first data fan-out lines Fa1 and are connected to their corresponding first data fan-out lines Fa1. The display panel provided in this exemplary embodiment places the fan-out region within the display area, avoiding the need for a fan-out region within the border area. This reduces the area of ​​the lower border and lower corner of the display panel, thus achieving a narrow border configuration.

[0113] As shown in Figure 1, a dividing line XX divides the display area AA into two display areas distributed in a first direction X. A data line Da, located farther from the dividing line XX, is connected to a second data fan-out line Fa2, located closer to the dividing line XX, via a first data fan-out line Fa1. The fan-out area FT may include a first fan-out area FT1 and a second fan-out area FT2. The first data fan-out line Fa1 is located in the first fan-out area FT1, and the second data fan-out line Fa2 is located in the second fan-out area FT2. The first fan-out area FT1 may include a first sub-fan-out area FT11 and a second sub-fan-out area FT12. The first sub-fan-out area FT11 and the second sub-fan-out area FT12 are located on either side of the second fan-out area FT2 in the first direction X.

[0114] It should be understood that in other exemplary embodiments, the first data fan-out line Fa1 and the second data fan-out line Fa2 can be arranged in other ways. For example, the data line Da on the side close to the dividing line XX can be connected to the second data fan-out line Fa2 on the side close to the dividing line XX via the first data fan-out line Fa1; or the data line Da on the side away from the dividing line XX can be connected to the second data fan-out line Fa2 on the side away from the dividing line XX via the first data fan-out line Fa1. For another example, the length of the first data fan-out line Fa1 can also gradually increase from the upper frame to the lower frame.

[0115] In this exemplary embodiment, the display panel is further provided with first and second data fan-out lines Fa1 and Fa2 in the fan-out region FT. These lines are not provided in the display area outside the fan-out region FT. Because the first and second data fan-out lines Fa1 and Fa2 reflect and block light, when the display panel is off, the fan-out region and the rest of the display region exhibit different reflective and light-transmitting properties, resulting in dark shadows on the display panel.

[0116] Based on this, this exemplary embodiment provides another display panel. FIG2 is a schematic diagram of the structure of another exemplary embodiment of a display panel disclosed herein. This display panel may include multiple first signal lines H1 and multiple second signal lines V2. The first signal lines H1 are located in the display area AA. Their orthographic projections on the substrate extend along the first direction X and are spaced apart along the second direction Y. The multiple first signal lines H1 include first sub-signal lines H11 and third analog lines Dm3. The first sub-signal lines H11 include spaced apart first data fan-out lines Fa1 and first analog lines Dm1. The third analog lines Dm3 are located in the display area AA outside the first fan-out area FT1. Second signal lines V2 are located in the display area AA and are located on a different conductive layer than the first signal lines H1. Their orthographic projections on the substrate extend along the second direction Y and are spaced apart along the first direction X. The multiple second signal lines V2 include second sub-signal lines V22 and fourth analog lines Dm4. The second sub-signal line V22 includes a second data fan-out line Fa2 and a second analog line Dm2 that are spaced apart. The fourth analog line Dm4 is located in the display area AA outside the second fan-out area FT2.

[0117] As shown in Figure 2, this exemplary embodiment adds first, second, third, and fourth analog lines Dm1, Dm2, Dm3, and Dm4 to achieve a nearly uniform signal line density across the entire display area AA, thereby resolving the aforementioned technical issue of dark shadows. It should be noted that when the first and second data fan-out lines Fa1 and Fa2 are distributed in other ways, the present disclosure can also eliminate the aforementioned dark shadows by adding analog lines.

[0118] In this exemplary embodiment, multiple first signal lines H1 can be located in the same conductive layer, and multiple second signal lines V2 can be located in the same conductive layer. The conductive layer where the second signal lines V2 are located can be located on a side of the conductive layer where the first signal lines H1 are located that is away from the base substrate. For example, the first signal lines H1 can be located in the first source / drain layer of the display panel, and the second signal lines V2 can be located in the second source / drain layer of the display panel. Furthermore, the data lines Da can also be located in the second source / drain layer of the display panel, and the orthographic projection of the second signal lines V2 on the base substrate can be located between the orthographic projections of two adjacent data lines Da on the base substrate.

[0119] It should be understood that in other exemplary embodiments, the first signal line and the second signal line may also be located in other conductive layers. For example, the first signal line may also be located in the first gate layer, the second gate layer, and the third gate layer in the display panel. The first signal line and the second signal line may also be located in an additional conductive layer. In addition, the first signal line and the second signal line may also be located in the same conductive layer.

[0120] As shown in Figures 3, 4, and 5, Figure 3 is a partial enlarged view of the first area K1 in Figure 2, Figure 4 is a partial structural layout of the conductive layer where the first signal line is located in Figure 3, and Figure 5 is a partial structural layout of the conductive layer where the second signal line is located in Figure 3. Part of the first area K1 is located in the first sub-fan-out area FT11, part of the first area K1 is located in the second fan-out area FT2, and part of the first area K1 is located in the display area of ​​the first sub-fan-out area FT11 away from the second fan-out area FT2. As shown in Figures 2-5, the first data fan-out line Fa1 can be connected to the data line Da through a via H, and can also be connected to the second data fan-out line Fa2 through a via. The black circles in Figure 2 represent the locations of the vias, and the black squares in Figure 3 represent the locations of the vias.

[0121] As shown in Figures 6, 7, and 8, Figure 6 is a partially enlarged view of the second region K2 in Figure 2, Figure 7 is a partial structural layout of the conductive layer where the first signal line is located in Figure 6, and Figure 8 is a partial structural layout of the conductive layer where the second signal line is located in Figure 6. The second region K2 is located in the display area of ​​the first sub-fan-out region FT11, which is remote from the second fan-out region FT2. As shown in Figures 2, 6-8, in the second region K2, the fourth analog line Dm4 is connected to the first analog line Dm1, whose orthographic projection on the substrate intersects, via a via H. The black squares in Figure 6 indicate the location of the vias. Furthermore, the display area of ​​the second sub-fan-out region FT12, which is remote from the second fan-out region FT2, can have the same structure as the second region K2.

[0122] As shown in Figures 9, 10, and 11, Figure 9 is a partially enlarged view of the third area K3 in Figure 2, Figure 10 is a partial structural layout of the conductive layer where the first signal line is located in Figure 9, and Figure 11 is a partial structural layout of the conductive layer where the second signal line is located in Figure 9. The third area K3 is located in the first sub-fan-out area FT11. As shown in Figures 2, 9-11, the first data fan-out line Fa1 is disconnected from the second analog line Dm2 and the fourth analog line Dm4, whose orthographic projections intersect on the substrate. The structures of the first sub-fan-out area FT11 and the second sub-fan-out area FT12 can be identical.

[0123] As shown in Figures 12, 13, and 14, Figure 12 is a partial enlarged view of the fourth region K4 in Figure 2, Figure 13 is a partial structural layout of the conductive layer where the first signal line is located in Figure 12, and Figure 14 is a partial structural layout of the conductive layer where the second signal line is located in Figure 12. The fourth region K4 is located in the second fan-out region FT2. As shown in Figures 2, 12-14, the second data fan-out line Fa2 is disconnected from the first analog line Dm1 whose orthographic projection intersects with it on the substrate.

[0124] As shown in Figures 15, 16, and 17, Figure 15 is a partial enlarged view of the fifth region K5 in Figure 2, Figure 16 is a partial structural layout of the conductive layer where the first signal line in Figure 15 is located, and Figure 17 is a partial structural layout of the conductive layer where the second signal line in Figure 15 is located. The fifth region K5 is located in the middle of the second fan-out region FT2 in the first direction X. As shown in Figures 2, 15-17, the plurality of second signal lines V2 also include a fifth analog line Dm5. Part of the structure of the fifth analog line Dm5 is located in the second fan-out region FT2, and the fifth analog line Dm5 is connected to the first analog line Dm1 and the third analog line Dm3, whose orthographic projections intersect on the substrate, via vias. The black squares in Figure 15 indicate the locations of the vias. In this exemplary embodiment, there can be only one fifth analog line. It should be understood that in other exemplary embodiments, there can be multiple fifth analog lines.

[0125] As shown in Figures 18, 19, and 20, Figure 18 is a partially enlarged view of the sixth region K6 in Figure 2, Figure 19 is a partial structural layout of the conductive layer where the first signal line is located in Figure 18, and Figure 20 is a partial structural layout of the conductive layer where the second signal line is located in Figure 18. The sixth region K6 is located in the display area on the side of the fan-out region away from the bottom bezel of the display panel. As shown in Figures 2, 18-20, in the sixth region K6, the third analog line Dm3 is connected to the fourth analog line Dm4, which intersects its orthographic projection on the substrate, through a via. The black squares in Figure 18 indicate the locations of the vias.

[0126] In this exemplary embodiment, as shown in FIG2-20 , the minimum distance between the orthographic projections of two adjacent first signal lines H1 on the substrate in the second direction Y is S1, and the maximum distance between the orthographic projections of two adjacent first signal lines H1 on the substrate in the second direction Y is S2, where (S2-S1) / S1 may be greater than or equal to 0 and less than or equal to 0.2. For example, (S2-S1) / S1 may be equal to 0, 0.05, 0.1, 0.2, etc. When (S2-S1) / S1 is equal to 0, the orthographic projections of the first signal lines H1 on the substrate are equally spaced in the second direction Y. As shown in FIG2-20 , the minimum distance between the orthographic projections of two adjacent second signal lines V2 on the substrate in the first direction X is S3, and the maximum distance between the orthographic projections of two adjacent second signal lines V2 on the substrate in the first direction X is S4, where (S4-S3) / S3 is greater than or equal to 0 and less than or equal to 0.2. For example, (S4-S3) / S3 can be equal to 0, 0.05, 0.1, 0.2, etc. When (S4-S3) / S3 is equal to 0, the orthographic projections of the second signal lines V2 on the substrate are evenly spaced in the first direction X. This arrangement can evenly distribute the first signal lines H1 and the second signal lines V2 in the display area, thereby further eliminating the aforementioned dark shadow problem.

[0127] In this exemplary embodiment, the display panel may further include a pixel driving circuit and a light-emitting unit, wherein the pixel driving circuit is connected to the first electrode of the light-emitting unit. The display panel may further include: a common electrode layer, wherein the common electrode layer is used to form the second electrode of the light-emitting unit. The first analog line Dm1, the second analog line Dm2, the third analog line Dm3, and the fourth analog line Dm4 can be connected to the common electrode layer. For example, the first analog line Dm1, the second analog line Dm2, the third analog line Dm3, and the fourth analog line Dm4 can be connected to the common electrode layer through a via located in the border area around the display area. The first analog line Dm1, the second analog line Dm2, the third analog line Dm3, and the fourth analog line Dm4 forming a grid structure can reduce the resistance of the common electrode layer itself, thereby reducing the voltage difference of the second electrodes of the light-emitting units at different positions on the display panel. This setting can improve the uniformity of the display of the display panel.

[0128] As shown in Figures 21-23, Figure 21 is a partial enlarged view of the seventh area K7 in Figure 2, Figure 22 is a structural layout of the conductive layer where the first signal line is located in Figure 21, and Figure 23 is a structural layout of the conductive layer where the second signal line is located in Figure 21. As shown in Figure 2, the display panel may further include a border area BB located around the display area AA, the border area BB including a first border area BB1 and a second border area BB2 arranged opposite each other, and the fan-out area FT is located on a side close to the second border area BB2. The display panel may further include: an electrode ring VSS and a power supply circuit (not shown). The electrode ring VSS is located in the border area BB, and the electrode ring VSS can be a ring structure located in the border area BB. The electrode ring VSS can be connected to the common electrode layer at different positions. The portion of the electrode ring VSS located in the first border area BB1 is connected to the second analog line Dm2 and the fourth analog line Dm4. The power supply circuit can be bound to the second border area BB2, and the power supply circuit is connected to at least a portion of the structure of the electrode ring VSS located in the second border area BB2. The power supply circuit can be used to provide a power signal to the electrode ring VSS. The common electrode layer away from the power circuit has a large voltage drop. The present application provides power voltage to the second analog line Dm2 and the fourth analog line Fm4 through the electrode ring VSS located in the first border area BB1, thereby reducing the voltage drop of the common electrode layer in the second direction Y.

[0129] As shown in Figures 21-23, the electrode ring VSS may include a first electrode ring 4VSS and a second electrode ring 5VSS. The orthographic projection of the first electrode ring 4VSS on the substrate at least partially overlaps the orthographic projection of the second electrode ring 5VSS on the substrate. The second electrode ring 5VSS is connected to the first electrode ring 4VSS via a via. The black squares in Figure 21 indicate the locations of the vias. The electrode rings with a double conductive layer can reduce the electrode ring's own resistance. A power connection line VDDx may also be provided in the first border area B1. The power connection line VDDx may include a first power connection line 4VDD and a second power connection line 5VDD. The orthographic projections of the first power connection line 4VDD and the second power connection line 5VDD on the substrate at least partially overlap. The first power connection line 4VDD and the second power connection line 5VDD are connected via a via. The power connection line VDDx may be connected to the power line VDD located in the display area.

[0130] In this exemplary embodiment, as shown in FIG. 2-20 , the first signal line H1 may include a plurality of first via contacts Ht1 and a first extension Lt1. The orthographic projections of the plurality of first via contacts Ht1 on the base substrate are spaced apart along the first direction X. The first extension Lt1 is connected to the first via contact Ht1. The orthographic projections of the first via contact Ht1 on the base substrate in the second direction Y are larger than the orthographic projections of the first extension Lt1 on the base substrate in the second direction Y. The second signal line V2 may include a plurality of second via contacts Ht2 and a second extension Lt2. The orthographic projections of the plurality of second via contacts Ht2 on the base substrate are spaced apart along the second direction Y. The second extension Lt2 is connected to the second via contact Ht2. The orthographic projections of the second via contacts Ht2 on the base substrate in the first direction X are larger than the orthographic projections of the second extension Lt2 on the base substrate in the first direction X. The first via contact portion Ht1 and the second via contact portion Ht2 are correspondingly provided, and the orthographic projection of the first via contact portion Ht1 on the base substrate at least partially overlaps with the orthographic projection of the corresponding second via contact portion Ht2 on the base substrate.

[0131] As shown in Figure 2-20, the first via contact portion Ht1 may include a first solid hole contact portion Htr1 and a first virtual hole contact portion Htd1, and the second via contact portion Ht2 may include a second solid hole contact portion Htr2 and a second virtual hole contact portion Htd2. The first solid hole contact portion Htr1 and the corresponding second solid hole contact portion Htr2 are connected through a via hole, that is, the first signal line H1 and the second signal line V2 can be connected through the first solid hole contact portion Htr1 and the second solid hole contact portion Htr2 via holes. The first virtual hole contact portion Htd1 and the corresponding second virtual hole contact portion Htd2 are insulated. The first virtual hole contact portion Htd1 can simulate the reflection phenomenon of the first solid hole contact portion Htr1, and the second virtual hole contact portion Htd2 can simulate the reflection phenomenon of the second solid hole contact portion Htr2. Therefore, the first virtual hole contact portion Htd1 and the second virtual hole contact portion Htd2 can improve the dark shadow problem of the display panel when the screen is off. In addition, the first virtual hole contact portion Htd1 can simulate the parasitic capacitance of the first real hole contact portion Htr1, and the second virtual hole contact portion Htd2 can simulate the parasitic capacitance of the second real hole contact portion Htr2, so that the first virtual hole contact portion Htd1 and the second virtual hole contact portion Htd2 can improve the display uniformity of the display panel.

[0132] In this exemplary embodiment, the orthographic projections of the first virtual hole contact portion Htd1 and the second virtual hole contact portion Htd2 on the base substrate overlap, so that from the perspective of light reflection, the display panel can selectively set either the first virtual hole contact portion Htd1 or the second virtual hole contact portion Htd2.

[0133] In this exemplary embodiment, as shown in FIG2-20 , the minimum distance between the orthographic projections of adjacent first via contacts Ht1 on the base substrate in the first direction X is S5, and the maximum distance between the orthographic projections of adjacent first via contacts Ht1 on the base substrate in the first direction X is S6, where (S6-S5) / S5 can be greater than or equal to 0 and less than or equal to 0.2, for example, (S6-S5) / S5 can be equal to 0, 0.05, 0.1, 0.2, etc. When (S6-S5) / S5 is equal to 0, the orthographic projections of the first via contacts Ht1 on the base substrate are evenly spaced in the first direction X. The evenly spaced first via contacts Ht1 can further improve the dark shadow problem of the display panel when the screen is off. As shown in FIG2-20 , the minimum distance between the orthographic projections of adjacent second via contacts Ht2 on the base substrate in the second direction Y is S7, and the maximum distance between the orthographic projections of adjacent second via contacts Ht2 on the base substrate in the second direction Y is S8, where (S8-S7) / S7 is greater than or equal to 0 and less than or equal to 0.2. For example, (S8-S7) / S7 can be equal to 0, 0.05, 0.1, 0.2, etc. When (S8-S7) / S7 is equal to 0, the orthographic projections of the second via contacts Ht2 on the base substrate are evenly spaced in the second direction Y. The evenly spaced second via contacts Ht2 can further improve the shadow problem when the display panel is off.

[0134] In this exemplary embodiment, the display panel further includes a pixel driving circuit and a light-emitting unit, the pixel driving circuit being connected to the first electrode of the light-emitting unit. The display panel further includes an electrode layer for forming the first electrode of the light-emitting unit. As shown in Figures 24, 25, 26, and 27, Figure 24 is a structural layout diagram of another exemplary embodiment of the display panel disclosed herein, Figure 25 is a structural layout diagram of the conductive layer where the first signal line is located in Figure 24, Figure 26 is a structural layout diagram of the conductive layer where the second signal line is located in Figure 24, and Figure 27 is a structural layout diagram of the electrode layer in Figure 24. The electrode layer may include multiple electrode portions, including a first electrode portion R, a second electrode portion B, and a third electrode portion G. The first electrode portion R can be used to form the first electrode of the red light-emitting unit; the second electrode portion B can be used to form the first electrode of the blue light-emitting unit; and the third electrode portion G can be used to form the first electrode of the green light-emitting unit. The display panel further includes a pixel definition layer located on the side of the electrode layer facing away from the base substrate, with pixel openings formed on the pixel definition layer for forming the light-emitting units. The orthographic projection of the first electrode portion R on the substrate coincides with the orthographic projection of the corresponding pixel opening on the pixel definition layer on the substrate substrate, the orthographic projection of the third electrode portion G on the substrate coincides with the orthographic projection of the corresponding pixel opening on the substrate substrate, and the orthographic projection of the second electrode portion B on the substrate coincides with the orthographic projection of the corresponding pixel opening on the substrate substrate.

[0135] As shown in Figures 24-27, the orthographic projection of the break D1 between the first data fan-out line Fa1 and the first analog line Dm1 on the substrate does not overlap with the orthographic projection of the electrode portion on the substrate; and the orthographic projection of the break D2 between the second data fan-out line Fa2 and the second analog line Dm2 on the substrate does not overlap with the orthographic projection of the electrode portion on the substrate. This arrangement can improve the flatness of the electrode portion, allowing a highly flat luminescent material layer to be formed on the highly flat electrode portion, thereby improving the uniformity of the display panel.

[0136] In this exemplary embodiment, the first solid hole contact portion Htr1 and the second solid hole contact portion Htr2 are connected by a via. At the via hole location, the second solid hole contact portion Htr2 is recessed toward the substrate, and the second solid hole contact portion Htr2 exhibits strong light reflection at the recessed location. However, because the first virtual hole contact portion Htd1 and the second virtual hole contact portion Htd2 are not connected, the second virtual hole contact portion Htd2 is relatively flat, and the second virtual hole contact portion Htd2 exhibits weak light reflection. The inconsistent light reflection capabilities of the second virtual hole contact portion Htd2 and the second solid hole contact portion Htr2 can easily cause dark shadows to appear when the display panel is off.

[0137] As shown in Figure 28, it is a partial cross-sectional view of the display panel shown in Figure 3 along the dotted line CC. The first signal line is located in the first source and drain layer, and the second signal line is located in the second source and drain layer. The display panel may further include a passivation layer 97 and a first flat layer 98 located on one side of the base substrate 90. The passivation layer 97 is located between the first source and drain layer and the second source and drain layer. The first flat layer 98 is located between the passivation layer 97 and the second source and drain layer. The thickness of the first flat layer 98 is much greater than the thickness of the passivation layer 97. In this exemplary embodiment, the depth of the recess of the second real hole contact Htr2 at the via position can be reduced by reducing the thickness of the passivation layer 97 and / or the first flat layer 98, thereby improving the above-mentioned shadow problem. In this exemplary embodiment, the thickness of the first flat layer 98 can be less than or equal to 1.6um, for example, the thickness of the first flat layer 98 can be 1.2um, 1.3um, 1.4um, 1.5um, or 1.6um; the thickness of the passivation layer 97 can be 1000 angstroms to 5000 angstroms, for example, the thickness of the passivation layer 97 can be 1000 angstroms, 2000 angstroms, 3000 angstroms, 4000 angstroms, or 5000 angstroms.

[0138] Figure 29 shows a schematic diagram of the structure of another exemplary embodiment of a display panel according to the present disclosure. In this display panel, only a first planarization layer 98 may be provided between the first source / drain layer and the second source / drain layer. This arrangement can also reduce the depth of the second solid hole contact portion Htr2 at the via hole location, thereby improving the aforementioned shadow problem.

[0139] Figure 30 shows a schematic diagram of the structure of another exemplary embodiment of a display panel disclosed herein. In this exemplary embodiment, a first opening H3 is formed in the first planar layer 98. The orthographic projection of the first opening H3 on the base substrate at least partially overlaps with the orthographic projection of the second virtual hole contact portion Htd2 on the base substrate. This arrangement allows the second virtual hole contact portion Htd2 to form a groove facing the base substrate 90, thereby improving the uniformity of light reflection in the display area by increasing the reflective capability of the second virtual hole contact portion Htd2. The first opening H3 can be an opening that penetrates the first planar layer 98 or a blind hole that does not penetrate the first planar layer 98.

[0140] Figure 31 shows a schematic diagram of the structure of another exemplary embodiment of the display panel disclosed herein. In this exemplary embodiment, a second opening H2 is formed in the passivation layer 97, and the orthographic projection of the second opening H2 on the base substrate at least partially overlaps with the orthographic projection of the second virtual hole contact portion Htd2 on the base substrate. This arrangement allows the second virtual hole contact portion Htd2 to form a recessed groove facing the base substrate 90, thereby improving the uniformity of light reflection in the display area by increasing the reflective ability of the second virtual hole contact portion Htd2. The second opening H2 can be an opening that penetrates the passivation layer 97, or it can be a blind hole that does not penetrate the passivation layer 97.

[0141] In this exemplary embodiment, because the orthographic projections of the first via contact Ht1 and the second via contact Ht2 on the base substrate overlap, the second via contact Ht2 has a higher protrusion than other locations. Furthermore, because a local area of ​​the second via contact Htr2 has a recess, to improve the flatness of the electrode portion, as shown in FIG. 24 , in this exemplary embodiment, the orthographic projection of the first via contact Ht1 on the base substrate does not overlap with the orthographic projection of the electrode portion; and the orthographic projection of the second via contact Ht2 on the base substrate does not overlap with the orthographic projection of the electrode portion on the base substrate.

[0142] As shown in Figure 26, the data lines Da located on both sides of the second signal line V2 include a third extension portion Lt3, a fourth extension portion Lt4, and a fifth extension portion Lt5. The fourth extension portion Lt4 is connected between the third extension portion Lt3 and the fifth extension portion Lt5. The data lines Da located on both sides of the second signal line V2 are data lines that have no other data lines between them and the second signal line V2. At least portions of the second via contact portion Ht2 and the fourth extension portion Lt4 are arranged relative to each other in the first direction X. The orthographic projections of the fourth extension portion Lt4 and the second extension portion Lt2 on the substrate in the first direction X are larger than the orthographic projections of the third extension portion Lt3 and the second extension portion Lt2 on the substrate in the first direction X. Furthermore, the orthographic projections of the fourth extension portion Lt4 and the second extension portion Lt2 on the substrate in the first direction X are larger than the orthographic projections of the fifth extension portion Lt5 and the second extension portion Lt2 on the substrate in the first direction X. Structure A and structure B are arranged relative to each other in the first direction. This means that the area covered by the orthographic projection of structure A on the substrate in the first direction and the area covered by the orthographic projection of structure B on the substrate in the first direction overlap. This arrangement provides ample space for the second via contact portion Ht2.

[0143] As shown in Figures 24-27, the size of the orthogonal projection of the break D1 between the first data fan-out line Fa1 and the first dummy line Dm1 on the substrate in the first direction X can be 1.5 μm to 3.5 μm. For example, the size of the orthogonal projection of the break D1 on the substrate in the first direction X can be 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, etc. The size of the orthogonal projection of the break D2 on the substrate in the second direction Y between the second data fan-out line Fa2 and the second dummy line Dm2 on the substrate can be 1.5 μm to 3.5 μm. For example, the size of the orthogonal projection of the break D2 on the substrate in the second direction Y can be 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, etc. When the sizes of the orthogonal projections of the break D1 on the substrate in the first direction X and the break D2 on the substrate in the second direction Y are small, no obvious dark shadows appear on the display panel.

[0144] In this exemplary embodiment, in the same second signal line, the distance between two adjacent second via contact portions Ht2 in the second direction Y and the orthographic projections on the substrate substrate is A1, and the size of the orthographic projection of the break D2 between the second data fan-out line Fa2 and the second analog line Dm2 on the substrate substrate in the second direction Y is A2; A1 / A2 can be greater than or equal to 27 and less than or equal to 68, for example, A1 / A2 can be equal to 27, 28, 29, 35, 40, 54, 50, 55, 60, 65, 66, 67, etc.

[0145] As shown in Figure 32, it is a schematic diagram of the circuit structure of the pixel driving circuit in the display panel of the present disclosure. The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. Among them, the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, the second electrode of the fourth transistor T4 is connected to the first electrode of the driving transistor T3, and the gate of the fourth transistor T4 is connected to the first gate driving signal terminal G1; the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T3, and the gate of the fifth transistor T5 is connected to the enable signal terminal EM; the gate of the driving transistor T3 is connected to the node N; the first electrode of the second transistor T2 is connected to the node N, the second electrode of the second transistor T2 is connected to the second electrode of the driving transistor T3, and the gate of the second transistor T2 is connected to the second gate driving signal terminal G 2; a first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, a second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7, a gate of the sixth transistor T6 is connected to the enable signal terminal EM, a first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and a gate of the seventh transistor T7 is connected to the second reset signal terminal Re2; a second electrode of the first transistor T1 is connected to the node N, a first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, and a gate of the first transistor T1 is connected to the first reset signal terminal Re1; a first electrode of the capacitor C is connected to the node N, and a second electrode of the capacitor C is connected to the first power supply terminal VDD. The pixel driving circuit can be connected to a light-emitting unit OLED, and the pixel driving circuit is used to drive the light-emitting unit OLED to emit light. The first electrode of the light-emitting unit OLED can be connected to the second electrode of the sixth transistor T6, and the second electrode of the light-emitting unit can be connected to the second power supply terminal VSS. The first electrode of the light-emitting unit can be an anode of the light-emitting unit, and the second electrode of the light-emitting unit can be a cathode of the light-emitting unit. The first transistor T1 and the second transistor T2 may be N-type transistors, for example, N-type metal oxide transistors (NMOTs). N-type transistors have low leakage current, thereby preventing leakage of power from node N through the first transistor T1 and the second transistor T2 during the light-emitting phase. Meanwhile, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors, for example, P-type low-temperature polysilicon transistors (LTPS). P-type transistors have high carrier mobility, thereby facilitating the realization of display panels with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal and the second initial signal terminal may output the same or different voltage signals, depending on actual conditions.

[0146] As shown in Figure 33, this is a timing diagram of each node in a driving method of the pixel driving circuit in Figure 32. In particular, G1 represents the timing of the first gate driving signal terminal G1, G2 represents the timing of the second gate driving signal terminal G2, Re1 represents the timing of the first reset signal terminal Re1, Re2 represents the timing of the second reset signal terminal Re2, EM represents the timing of the enable signal terminal EM, and Da represents the timing of the data signal terminal Da. The driving method of the pixel driving circuit may include a reset phase t1, a data writing phase t2, and a light-emitting phase t3. In the reset phase t1: the first reset signal terminal Re1 outputs a high-level signal, the second reset signal terminal Re2 outputs a low-level signal, the first transistor T1 and the seventh transistor T7 are turned on, the first initial signal terminal Vinit1 inputs the first initial signal to the node N, and the second initial signal terminal Vinit2 inputs the second initial signal to the first electrode of the light-emitting unit OLED. During the data writing phase t2, the second gate drive signal terminal G2 outputs a high-level signal, the first gate drive signal terminal G1 outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal terminal Da outputs a data signal to write the compensation voltage Vdata+Vth to the node N, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the driving transistor T3. During the light-emitting phase t3, the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in the capacitor C.

[0147] The output current formula of the driving transistor is as follows: I=(μWCox / 2L)(Vgs-Vth) 2

[0148] Where I is the output current of the driver transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driver transistor channel, L is the length of the driver transistor channel, Vgs is the gate-source voltage difference of the driver transistor, and Vth is the threshold voltage of the driver transistor. The output current of the driver transistor in the pixel driving circuit of the present disclosure is I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current. It should be understood that in other exemplary embodiments, this pixel driving circuit can also have other driving methods. For example, the seventh transistor T7 can reset the first electrode of the light-emitting unit during the period between the data writing phase t2 and the light-emitting phase t3.

[0149] In this exemplary embodiment, the display panel may include a base substrate, a blocking layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source and drain layer, a second source and drain layer, and an electrode layer stacked in sequence, wherein an insulating layer may be provided between the above adjacent layers. As shown in Figures 34-50, Figure 34 is a local layout of the sixth area K6 in Figure 2, Figure 35 is the structural layout of the blocking layer in Figure 34, Figure 36 is the structural layout of the first active layer in Figure 34, Figure 37 is the structural layout of the first gate layer in Figure 34, Figure 38 is the structural layout of the second gate layer in Figure 34, Figure 39 is the structural layout of the second active layer in Figure 34, Figure 40 is the structural layout of the third gate layer in Figure 34, Figure 41 is the structural layout of the first source and drain layer in Figure 34, Figure 42 is the structural layout of the second source and drain layer in Figure 34, Figure 43 is the structural layout of the electrode layer in Figure 34, Figure 44 is the structural layout of the blocking layer and the first active layer in Figure 34, and Figure 45 is the structural layout of the blocking layer, the first active layer, and the first gate layer in Figure 34. FIG46 is a structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in FIG34 ; FIG47 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in FIG34 ; FIG48 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in FIG34 ; FIG49 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source and drain layer in FIG34 ; and FIG50 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source and drain layer, and the second source and drain layer in FIG34 . The display panel may include a plurality of pixel driving circuits shown in FIG32 . As shown in FIG50 , the plurality of pixel driving circuits may include a first pixel driving circuit P1 and a second pixel driving circuit P2 adjacently distributed in a first direction X, and the first pixel driving circuit P1 and the second pixel driving circuit P2 may be arranged in mirror symmetry with respect to a mirror symmetry plane DD. The mirror symmetry plane DD may be perpendicular to the substrate. The orthographic projection of the first pixel driving circuit P1 on the substrate and the orthographic projection of the second pixel driving circuit P2 on the substrate may be arranged symmetrically with the intersection of the mirror symmetry plane DD and the substrate as the axis of symmetry. The first pixel driving circuit P1 and the second pixel driving circuit P2 may form a sub-repeating unit, and the display panel may include a plurality of sub-repeating units distributed in an array in the first direction X and the second direction Y. Four sub-repeating units distributed in a two-by-two array may form a repeating unit Pc.As shown in Figures 51-67, Figure 51 is the structural layout of a single repeating unit in Figure 34, Figure 52 is the structural layout of the blocking layer in Figure 51, Figure 53 is the structural layout of the first active layer in Figure 51, Figure 54 is the structural layout of the first gate layer in Figure 51, Figure 55 is the structural layout of the second gate layer in Figure 51, Figure 56 is the structural layout of the second active layer in Figure 51, Figure 57 is the structural layout of the third gate layer in Figure 51, Figure 58 is the structural layout of the first source and drain layer in Figure 51, Figure 59 is the structural layout of the second source and drain layer in Figure 51, Figure 60 is the structural layout of the electrode layer in Figure 51, Figure 61 is the structural layout of the blocking layer and the first active layer in Figure 51, and Figure 62 is the structural layout of the blocking layer, the first active layer, and the first gate layer in Figure 51. Figure 63 is the structural layout of the blocking layer, the first active layer, the first gate layer, and the second gate layer in Figure 51, Figure 64 is the structural layout of the blocking layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in Figure 51, Figure 65 is the structural layout of the blocking layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in Figure 51, Figure 66 is the structural layout of the blocking layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source and drain layer in Figure 51, and Figure 67 is the structural layout of the blocking layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source and drain layer, and the second source and drain layer in Figure 51.

[0150] In this exemplary embodiment, the first signal line and the second signal line can be added to the display panel by compressing the repeating units. A plurality of the repeating units distributed in the first direction X form a repeating unit row, with each repeating unit row corresponding to a first signal line H1. A second signal line V2 is correspondingly provided between adjacent repeating units in the first direction X.

[0151] As shown in Figures 34, 35, 44, 51, 52, and 61, the shielding layer may include multiple shielding portions 61, and adjacent shielding portions 61 may be interconnected. As shown in Figure 35, in adjacent repeating units in the first direction X, the minimum distance between the orthogonal projections of adjacent shielding portions 61 on the substrate in the first direction X is L5; in two adjacent sub-repeating units in the same repeating unit in the first direction X, the minimum distance between the orthogonal projections of adjacent shielding portions 61 on the substrate in the first direction X is L6. L6 is less than L5. In adjacent repeating units in the second direction Y, the minimum distance between the orthogonal projections of adjacent shielding portions 61 on the substrate in the second direction Y is L16; in two adjacent sub-repeating units in the same repeating unit in the second direction Y, the minimum distance between the orthogonal projections of adjacent shielding portions 61 on the substrate in the second direction Y is L15. L15 is less than L16. It should be understood that in other exemplary embodiments, the display panel may not include a shielding layer.

[0152] As shown in Figures 34, 36, 45, 51, 53, and 62, the first active layer may include a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, and a seventh active portion 77. The third active portion 73 may be used to form the channel region of the driving transistor T3; the fourth active portion 74 may be used to form the channel region of the fourth transistor T4; the fifth active portion 75 may be used to form the channel region of the fifth transistor T5; the sixth active portion 76 may be used to form the channel region of the sixth transistor T6; and the seventh active portion 77 may be used to form the channel region of the seventh transistor T7. The first active layer also includes a ninth active portion 79, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, and a thirteenth active portion 713. The ninth active portion 79 is connected to a side of the fifth active portion 75 away from the third active portion 73, and is connected between two adjacent fifth active portions 75 in adjacent sub-repeating units in the first direction X. The tenth active portion 710 is connected between the sixth active portion 76 and the seventh active portion 77, the eleventh active portion 711 is connected between the sixth active portion 76 and the third active portion 73, the twelfth active portion 712 is connected to an end of the fourth active portion 74 away from the third active portion 73, and the thirteenth active portion 713 is connected to an end of the seventh active portion 77 away from the sixth active portion 76. The orthographic projection of the shielding portion 61 on the substrate can cover the orthographic projection of the third active portion 73 on the substrate, and the shielding portion 61 can reduce the impact of light on the driving characteristics of the driving transistor T3. As shown in FIG36 , in adjacent repeating units in the first direction X, the orthogonal projection of the ninth active portion 79 connected between adjacent fifth active portions 75 on the substrate has a dimension L7 in the first direction X. In two adjacent sub-repeating units located in the same repeating unit in the first direction X, the orthogonal projection of the ninth active portion 79 connected between adjacent fifth active portions 75 on the substrate has a dimension L8 in the first direction X, where L7 is greater than L8. In adjacent repeating units in the second direction Y, the minimum distance between the orthogonal projections of adjacent twelfth active portions 712 and ninth active portions 79 on the substrate in the second direction Y is L18. In two adjacent sub-repeating units located in the same repeating unit in the second direction Y, the minimum distance between the orthogonal projections of adjacent twelfth active portions 712 and ninth active portions 79 on the substrate in the second direction Y is L17, where L18 is greater than L17. The first active layer may be formed of polysilicon material. Accordingly, the driving transistor T3 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , and the seventh transistor T7 may be P-type low-temperature polysilicon thin film transistors.

[0153] As shown in Figures 34, 37, 45, 51, 54, and 62, the first gate layer may include: a first conductive portion 11, a first gate line G1, an enable signal line EM, and a second reset signal line Re2. The first gate line G1 can be used to provide the first gate drive signal terminal in Figure 32; the enable signal line EM can be used to provide the enable signal terminal in Figure 32; and the second reset signal line Re2 can be used to provide the second reset signal terminal in Figure 32. The orthographic projection of the first gate line G1 on the base substrate, the orthographic projection of the enable signal line EM on the base substrate, and the orthographic projection of the second reset signal line Re2 on the base substrate can all extend along the first direction X. The orthographic projection of the first gate line G1 on the base substrate covers the orthographic projection of the fourth active portion 74 on the base substrate, and a portion of the structure of the first gate line G1 is used to form the gate of the fourth transistor. The orthographic projection of the enable signal line EM on the substrate overlaps the orthographic projection of the fifth active portion 75 and the orthographic projection of the sixth active portion 76 on the substrate. Portions of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the second reset signal line Re2 on the substrate overlaps the orthographic projection of the seventh active portion 77 on the substrate. Portions of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7. The orthographic projection of the first conductive portion 11 on the substrate overlaps the orthographic projection of the third active portion 73 on the substrate. The first conductive portion 11 can be used to form the gate of the drive transistor T3 and the first electrode of the capacitor C. As shown in Figures 45 and 62, the first gate line G1 in the pixel drive circuit of one row can be reused as the second reset signal line Re2 in the pixel drive circuit of the next row. The display panel can be driven row by row from top to bottom or from bottom to top. This configuration can improve the integration of the pixel drive circuit and reduce the layout area of ​​the pixel drive circuit. The shielding layer can also be connected to a stable power supply terminal. For example, the shielding layer can be connected to the first power supply terminal, the first initial signal terminal, the second initial signal terminal, etc. in Figure 32. The shielding portion 61 can shield the noise impact of other signals on the driving transistor T3. As shown in Figure 50, a plurality of repeating units distributed in a first direction X form a repeating unit row. The same repeating unit row includes a first pixel driving circuit row Ph1 and a second pixel driving circuit row Ph2. The first pixel driving circuit row Ph1 includes a plurality of pixel driving circuits distributed along the first direction X, and the second pixel driving circuit row Ph2 includes a plurality of pixel driving circuits distributed along the first direction.As shown in FIG37 , in the first pixel driving circuit row Ph1, the minimum distance between the orthographic projection of the enable signal line EM on the substrate and the orthographic projection of the second reset signal line Re2 on the substrate in the second direction Y is L3. In the second pixel driving circuit row Ph2, the distance between the orthographic projection of the enable signal line EM on the substrate and the orthographic projection of the second reset signal line Re2 on the substrate in the second direction Y is L4, where L3 is greater than L4. In adjacent repeating units in the first direction X, the minimum distance between the orthographic projections of adjacent first conductive portions 11 on the substrate in the first direction X is L19. In two adjacent sub-repeating units within the same repeating unit, the minimum distance between the orthographic projections of adjacent first conductive portions 11 on the substrate in the first direction X is L20. L20 is less than L19. In addition, the display panel can use the first gate layer as a mask to conduct the first active layer, that is, the area of ​​the first active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first gate layer forms a conductor structure.

[0154] As shown in Figures 34, 38, 46, 51, 55, and 63, the second gate layer may include: a first initial signal line Vinit1, a third reset signal line 2Re1, a third gate line 2G2, and a plurality of second conductive portions 22. The first initial signal line Vinit1 is used to provide the first initial signal terminal in Figure 32, the third reset signal line 2Re1 can be used to provide the first reset signal terminal in Figure 32, and the third gate line 2G2 can be used to provide the second gate drive signal terminal in Figure 32. The orthographic projection of the first initial signal line Vinit1 on the base substrate, the orthographic projection of the third reset signal line 2Re1 on the base substrate, and the orthographic projection of the third gate line 2G2 on the base substrate can all extend along the first direction X. As shown in Figures 38 and 55, the second gate layer may further include a plurality of connecting portions 23. In adjacent sub-repeating units in the first direction X, the connecting portion 23 is connected between two adjacent second conductive portions 22 in the first direction X. As shown in FIG38 , in adjacent repeating units in the first direction X, the orthogonal projection of the connecting portion 23 connecting adjacent second conductive portions 22 onto the substrate has a dimension L10 in the first direction X. In two adjacent sub-repeating units located in the same repeating unit in the first direction X, the orthogonal projection of the connecting portion 23 connecting adjacent second conductive portions 22 onto the substrate has a dimension L9 in the first direction X, with L10 being greater than L9. In adjacent repeating units in the second direction Y, the orthogonal projection of adjacent second conductive portions and the first initial signal line Vinit1 onto the substrate has a dimension L22 in the first direction X. In two adjacent sub-repeating units located in the same repeating unit in the second direction Y, the orthogonal projection of adjacent second conductive portions and the first initial signal line Vinit1 onto the substrate has a dimension L21 in the first direction X, with L22 being greater than L21. Furthermore, in other exemplary embodiments, adjacent second conductive portions 22 may be connected within the same repeating unit.

[0155] As shown in Figures 34, 39, 47, 51, 56, and 64, the second active layer may include an active portion 8, which may include a first active portion 81, a second active portion 82, a fourteenth active portion 814, a fifteenth active portion 815, and a sixteenth active portion 816. The first active portion 81 is used to form the channel region of the first transistor T1, and the second active portion 82 is used to form the channel region of the second transistor T2. The fifteenth active portion 815 is connected between the first active portion 81 and the second active portion 82. The fourteenth active portion 814 is connected to the end of the first active portion 81 away from the second active portion 82, and the sixteenth active portion 816 is connected to the end of the second active portion 82 away from the first active portion 81. As shown in FIG39 , in adjacent repeating units in a first direction X, the minimum distance between the orthogonal projections of adjacent active portions 8 on the substrate in the first direction X is L11. In two adjacent sub-repeating units in the same repeating unit in the first direction X, the minimum distance between the orthogonal projections of adjacent active portions 8 on the substrate in the first direction X is L12, with L11 being greater than L12. In adjacent repeating units in a second direction Y, the minimum distance between the orthogonal projections of adjacent active portions 8 on the substrate in the second direction Y is L24. In the same repeating unit in the second direction Y, the minimum distance between the orthogonal projections of adjacent active portions 8 on the substrate in the second direction Y is L23, with L24 being greater than L23. The second active layer may be formed of indium gallium zinc oxide, and accordingly, the first transistor T1 and the second transistor T2 may be N-type metal oxide thin film transistors. The orthographic projection of the third gate line 2G2 on the substrate can overlap the orthographic projection of the second active portion 82 on the substrate, and a portion of the third gate line 2G2 can be used to form the bottom gate of the second transistor T2. The orthographic projection of the third reset signal line 2Re1 on the substrate can overlap the orthographic projection of the first active portion 81 on the substrate, and a portion of the third reset signal line 2Re1 can be used to form the bottom gate of the first transistor T1.

[0156] As shown in Figures 34, 40, 48, 51, 57, and 65, the third gate layer may include a first reset signal line 3Re1 and a second gate line 3G2. The orthographic projection of the first reset signal line 3Re1 on the base substrate and the orthographic projection of the second gate line 3G2 on the base substrate may both extend along the first direction X. The first reset signal line 3Re1 may be used to provide the first reset signal terminal shown in Figure 32. The orthographic projection of the first reset signal line 3Re1 on the base substrate may cover the orthographic projection of the first active portion 81 on the base substrate. Part of the structure of the first reset signal line 3Re1 may be used to form the top gate of the first transistor T1. At the same time, the first reset signal line 3Re1 may be connected to the third reset signal line 2Re1 through a via located in the border area of ​​the display panel. The second gate line 3G2 can be used to provide the second gate drive signal terminal shown in FIG32 . The orthographic projection of the second gate line 3G2 on the substrate can overlap the orthographic projection of the second active portion 82 on the substrate. Part of the structure of the second gate line 3G2 can be used to form the top gate of the second transistor T2. At the same time, the second gate line 3G2 can be connected to the third gate line 2G2 through a via located in the border area of ​​the display panel. As shown in FIG40 , in adjacent repeating units in the second direction Y, the minimum distance between the orthographic projections of adjacent second gate lines 3G2 and first reset signal line 3Re1 on the substrate in the second direction Y is L14. In adjacent sub-repeating units located in the same repeating unit in the second direction Y, the minimum distance between the orthographic projections of adjacent second gate lines 3G2 and first reset signal line 3Re1 on the substrate in the second direction Y is L13, and L14 is greater than L13. In addition, the display panel can use the third gate layer as a mask to conduct conductor processing on the second active layer, that is, the area of ​​the second active layer covered by the third gate layer can form the channel region of the transistor, and the area of ​​the second active layer not covered by the third gate layer forms a conductor structure.

[0157] As shown in Figures 34, 41, 49, 51, 58, and 66, the first source-drain layer may include: the aforementioned first signal line H1, the second initial signal line Vinit2, the first bridge portion 41, the second bridge portion 42, the third bridge portion 43, the fourth bridge portion 44, the fifth bridge portion 45, and the sixth bridge portion 46. The first bridge portion 41 is connected to the connecting portion 23 and the ninth active portion 79 through vias, respectively, to connect the first electrode of the fifth transistor and the second electrode of the capacitor C. Adjacent sub-repeating units in the first direction X share the same first bridge portion 41. The second bridge portion 42 may be connected to the tenth active portion 710 through vias to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The third bridge portion 43 may be connected to the eleventh active portion 711 and the sixteenth active portion 816 through vias, respectively, to connect the second electrode of the second transistor T2, the first electrode of the sixth transistor T6, and the second electrode of the driving transistor T3. The fourth bridge portion 44 can be connected to the fifteenth active portion 815 and the first conductive portion 11 through vias, respectively, to connect the first electrode of the second transistor T2 and the gate of the driving transistor. An opening 221 is formed on the second conductive portion 22, and the orthographic projection of the via connected between the first conductive portion 11 and the fourth bridge portion 44 on the substrate is located within the orthographic projection of the opening 221 on the substrate, so that the via and the second conductive portion 22 are insulated from each other. The fifth bridge portion 45 can be connected to the twelfth active portion 712 through a via to connect the first electrode of the fourth transistor. The sixth bridge portion 46 can be connected to the fourteenth active portion 814 and the first initial signal line Vinit1 through vias, respectively, to connect the first electrode of the first transistor and the first initial signal end. In the same repeating unit, two adjacent pixel driving circuits can share the same sixth bridge portion 46. The second initial signal line Vinit2 can be used to provide the second initial signal terminal in Figure 32. The orthographic projection of the second initial signal line Vinit2 on the substrate can extend along the first direction X. The second initial signal line Vinit2 can be connected to the thirteenth active portion 713 through a via to connect the first electrode and the second initial signal terminal of the seventh transistor. A plurality of the repeating units distributed in the first direction X form a repeating unit row, and each repeating unit row corresponds to a first signal line H1. The orthographic projection of the first signal line H1 on the substrate is located between the orthographic projection of the enable signal line EM in the first pixel driving circuit row Ph1 and the orthographic projection of the second reset signal line Re2 in the first pixel driving circuit row Ph1.The orthographic projection of the first signal line H1 on the substrate does not overlap with the orthographic projections of the first gate layer and the third gate layer on the substrate. Instead, the orthographic projection of the first signal line H1 on the substrate only overlaps with the orthographic projections of a portion of the first active layer and the first initial signal line located in the second gate layer on the substrate. This configuration can reduce the parasitic capacitance of the first signal line and the coupling between the first signal line and other signal lines. In adjacent columns of repeating units in the first direction X, the orthographic projection of the first bridging portion 41 shared by adjacent sub-repeating units in the substrate has a maximum dimension L15 in the first direction X. In the same repeating unit, the orthographic projection of the first bridging portion 41 shared by adjacent sub-repeating units in the first direction X on the substrate has a maximum dimension L16 in the first direction X, with L15 being greater than L16. The maximum distance in the second direction Y between the orthographic projection of the first bridge portion 41 in the first pixel driving circuit row Ph1 and the orthographic projection of the second initial signal line Vinit2 on the substrate is L26, and the maximum distance in the second direction Y between the orthographic projection of the first bridge portion 41 in the second pixel driving circuit row Ph2 and the orthographic projection of the second initial signal line Vinit2 on the substrate is L25, and L26 is greater than L25.

[0158] As shown in Figures 34, 42, 50, 51, 59, and 67, the second source-drain layer may include: the aforementioned second signal line V2, multiple power lines VDD, multiple data lines Da, and a seventh bridge portion 57. A corresponding second signal line V2 is provided between adjacent repeating units in the first direction X. The orthographic projections of the power line VDD and the data line Da on the substrate can both extend along the second direction Y. The power line VDD can be used to provide the first power supply terminal shown in Figure 32, and the data line Da can be used to provide the data signal terminal shown in Figure 32. A power line VDD can be provided for each column of pixel driving circuits. The power line VDD can be connected to the first bridge portion 41 via a via to connect the first electrode of the fifth transistor to the first power supply terminal. The data line Da can be connected to the fifth bridge portion 45 via a via to connect the first electrode of the fourth transistor to the data signal terminal. The seventh bridge portion 57 can be connected to the second bridge portion 42 via a via to connect the second electrode of the seventh transistor. In the same sub-repeating unit, adjacent power lines VDD are connected to each other, so that the power lines VDD and the second conductive portion 22 can form a grid structure. The power lines of the grid structure can reduce the voltage drop of the power signal thereon.

[0159] As shown in Figures 34, 42, 50, 51, 59, and 67, the power line VDD may include a first power line segment VDD1, a second power line segment VDD2, and a third power line segment VDD3. The second power line segment VDD2 is connected between the first power line segment VDD1 and the third power line segment VDD3. The orthographic projection of the second power line segment VDD2 on the substrate in the first direction X may be larger than the orthographic projection of the first power line segment VDD1 on the substrate in the first direction X, and the orthographic projection of the second power line segment VDD2 on the substrate in the first direction X may be larger than the orthographic projection of the third power line segment VDD3 on the substrate in the first direction X. Furthermore, the orthographic projection of the second power line segment VDD2 on the substrate may also cover the orthographic projections of the first active portion 81 and the second active portion 82 on the substrate. The second power line segment VDD2 can reduce the effects of light on the characteristics of the first transistor T1 and the second transistor T2. Furthermore, the orthographic projection of the power line VDD on the base substrate may at least partially overlap with the orthographic projection of the fourth bridge portion 44 on the base substrate. The power line VDD can be used to shield the fourth bridge portion 44 from noise interference from other signals, thereby improving the stability of the gate voltage of the driving transistor T3. As shown in FIG42 , in adjacent columns of repeating units in the first direction X, the minimum distance between the orthographic projections of two adjacent data lines Da on the base substrate in the first direction X is L1. In two adjacent sub-repeating units in the same repeating unit in the first direction X, the distance between the orthographic projections of two adjacent data lines Da on the base substrate in the first direction X is L2, where L1 is greater than L2.

[0160] As shown in Figures 34, 43, 51, and 60, the pixel electrode layer may include multiple electrode portions: a first electrode portion R, a second electrode portion B, and a third electrode portion G. In the same electrode row, the first electrode portion R, the third electrode portion G, the second electrode portion B, and the third electrode portion G are alternately arranged in sequence in the first direction X. The multiple electrode portions form multiple electrode columns, and the multiple electrode columns include a first electrode column ROW1, a second electrode column ROW2, a third electrode column ROW3, ​​and a fourth electrode column ROW4 that are adjacent to each other in sequence. The first electrode column ROW1 includes the first electrode portion R and the second electrode portion B that are alternately arranged in sequence in the second direction Y; the second electrode column ROW2 includes multiple third electrode portions G distributed in the second direction Y; the third electrode column ROW3 includes the second electrode portion B and the first electrode portion R that are alternately arranged in sequence in the second direction Y; and the fourth electrode column ROW4 includes multiple third electrode portions G distributed in the second direction Y. The minimum distance S5 between the orthogonal projections of two third electrode portions G located in adjacent electrode rows of the same electrode column on the substrate in the second direction Y is greater than the dimension S6 of the orthogonal projection of the first electrode portion R on the substrate in the second direction Y, or greater than the dimension S7 of the orthogonal projection of the second electrode portion B on the substrate in the second direction Y. The orthogonal projection of the first electrode portion R on the substrate coincides with the orthogonal projection of its corresponding pixel opening on the pixel definition layer on the substrate, the orthogonal projection of the third electrode portion G on the substrate coincides with the orthogonal projection of its corresponding pixel opening on the pixel definition layer on the substrate, and the orthogonal projection of the second electrode portion B on the substrate coincides with the orthogonal projection of its corresponding opening on the pixel definition layer on the substrate. In the same repeating unit, two second power line segments VDD2 of adjacent power lines VDD are connected.

[0161] As shown in Figure 34 , in two adjacent sub-repeating units in the first direction, the orthographic projections of two adjacent data lines Da on the base substrate intersect with the orthographic projection of the same third electrode portion G on the base substrate, and are located on either side of the orthographic projection of the second signal line V2 on the base substrate. The orthographic projection of the second signal line V2 on the base substrate intersects with the third electrode portion. This arrangement can improve the flatness of the electrode portion, thereby enhancing the uniformity of the display panel.

[0162] It should be noted that, as shown in Figures 34, 49, 50, 51, 66, and 67, the black squares drawn on the side of the first source / drain layer facing away from the substrate represent vias connecting the first source / drain layer to other layers facing the substrate; the black squares drawn on the side of the second source / drain layer facing away from the substrate represent vias connecting the second source / drain layer to other layers facing the substrate; and the black squares drawn on the side of the electrode layer facing away from the substrate represent vias connecting the electrode layer to other layers facing the substrate. The black squares merely indicate the locations of the vias; different vias represented by black squares in different locations can penetrate different insulating layers.

[0163] In this exemplary embodiment, a second signal line V2 is provided between two adjacent columns of repeating units in the first direction, and a first signal line H1 is provided in the same repeating unit row. In this exemplary embodiment, the repeating unit includes two rows and two columns of sub-repeating units. It should be understood that in other exemplary embodiments, the repeating unit may also include sub-repeating units with other numbers of rows and columns.

[0164] FIG68 is a partial cross-sectional view of the display panel shown in FIG51 taken along dotted line EE. The display panel may further include a first insulating layer 91, a second insulating layer 92, a third insulating layer 93, a fourth insulating layer 94, a fifth insulating layer 95, a first dielectric layer 96, a passivation layer 97, a first planarization layer 98, and a second planarization layer 99, wherein the base substrate 90, the shielding layer, the first insulating layer 91, the first active layer, the second insulating layer 92, the first gate layer, the third insulating layer 93, the second gate layer, the fourth insulating layer 94, the second active layer, the fifth insulating layer 95, the third gate layer, the first dielectric layer 96, the first source and drain layer, the passivation layer 97, the first planarization layer 98, the second source and drain layer, and the second planarization layer 99 are stacked in sequence. The first insulating layer 91, the second insulating layer 92, the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 can be single-layer or multi-layer structures, and the material of the first insulating layer 91, the second insulating layer 92, the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride. The first dielectric layer 96 can be a silicon nitride layer. The materials of the first planarizing layer 98 and the second planarizing layer 99 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding (SOG), etc. The passivation layer 97 can be a silicon oxide layer. The base substrate 90 can include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence. The barrier layer can be an inorganic material. The materials of the first, second, and third gate layers can be molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked conductive layer. The first and second source / drain layers may be made of metal materials, such as molybdenum, aluminum, copper, titanium, or niobium, or alloys thereof, or molybdenum / titanium alloys or stacks, or conductive layers such as titanium / aluminum / titanium stacks. The sheet resistance of either the first or second source / drain layer can be lower than the sheet resistance of either the first, second, or third gate layers. Consequently, in this exemplary embodiment, the first and second data fan-out lines have lower resistances.

[0165] It should be noted that the proportions of the drawings in this disclosure can be used as a reference in actual processes, but are not limited to this. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematics. In addition, qualifiers such as first and second are only used to limit different structural names, and they do not have a specific order of meaning. The same structural layer can be formed by the same composition process. In this exemplary embodiment, the orthographic projection of a certain structure on the base substrate extends in a certain direction, which can be understood as the orthographic projection of the structure on the base substrate extending in a straight line or bending along that direction.

[0166] In this exemplary embodiment, the display panel may be a flexible display panel or a non-flexible display panel.

[0167] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a mobile phone, a tablet computer, a television, or other display device.

[0168] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0169] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display panel, wherein: The display panel includes a display area and a fan-out area located in the display area, and the display panel further includes: substrate; a plurality of data lines located in the display area, wherein orthographic projections of the data lines on the base substrate are spaced apart along a first direction and extend along a second direction, wherein the first direction and the second direction intersect; a plurality of first data fan-out lines located in the fan-out area, wherein the orthographic projections of the first data fan-out lines on the substrate are spaced apart along the second direction and extend along the first direction, the first data fan-out lines are arranged corresponding to the data lines, and the first data fan-out lines are connected to the corresponding data lines; A plurality of second data fan-out lines are located in the fan-out area, the orthographic projections of the second data fan-out lines on the substrate are spaced apart along the first direction and extend along the second direction, the second data fan-out lines are arranged corresponding to the first data fan-out lines, and the second data fan-out lines are connected to the corresponding first data fan-out lines.

2. The display panel according to claim 1, wherein The display panel further includes: a plurality of first signal lines located in the display area, wherein orthographic projections of the first signal lines on the base substrate extend along the first direction and are spaced apart along the second direction, the plurality of first signal lines including first sub-signal lines, at least a portion of which is configured to form the first data fan-out lines; A plurality of second signal lines are located in the display area and are located in a different conductive layer from the first signal lines. The orthographic projections of the second signal lines on the base substrate extend along the second direction and are spaced apart along the first direction. The plurality of second signal lines include second sub-signal lines. At least a portion of the structure of the second sub-signal lines is used to form the second data fan-out lines.

3. The display panel according to claim 2, wherein: The minimum distance between the orthographic projections of two adjacent first signal lines on the substrate in the second direction is S1, and the maximum distance between the orthographic projections of two adjacent first signal lines on the substrate in the second direction is S2, where (S2-S1) / S1 is greater than or equal to 0 and less than or equal to 0.2; And / or, the minimum distance between the orthographic projections of two adjacent second signal lines on the substrate in the first direction is S3, and the orthographic projections of two adjacent second signal lines on the substrate are S3. The maximum distance of the projection in the first direction is S4, where (S4-S3) / S3 is greater than or equal to 0 and less than or equal to 0.

2.

4. The display panel according to claim 2, wherein: The first sub-signal line further includes a first analog line spaced apart from the first data fan-out line, and the second sub-signal line further includes a second analog line spaced apart from the second data fan-out line; The fan-out area includes a first fan-out area and a second fan-out area, the first data fan-out line is located in the first fan-out area, and the second data fan-out line is located in the second fan-out area; The plurality of first signal lines further include a third analog line, and the third analog line is located in a display area outside the first fan-out area; The plurality of second signal lines further include a fourth analog line, and the fourth analog line is located in a display area outside the second fan-out area.

5. The display panel according to claim 4, wherein: The display panel further includes a pixel driving circuit and a light emitting unit, wherein the pixel driving circuit is connected to the first electrode of the light emitting unit; The display panel further includes: a common electrode layer, the common electrode layer being used to form a second electrode of the light-emitting unit; The first analog line, the second analog line, the third analog line, and the fourth analog line are connected to the common electrode layer. The display panel according to claim 4 , wherein: The first simulation line is connected to a fourth simulation line intersecting with its orthographic projection on the substrate through a via; The third simulation line is connected to the second simulation line and the fourth simulation line intersecting with its orthographic projection on the base substrate through a via hole.

7. The display panel according to claim 5, wherein: The display panel further includes a frame area located around the display area, the frame area including a first frame area and a second frame area that are oppositely arranged, and the fan-out area is located on a side close to the second frame area; The display panel further includes: an electrode ring, the electrode ring being located in the border area and connected to the common electrode layer, wherein at least a portion of the electrode ring located in the first border area is connected to the second analog line and the fourth analog line; A power supply circuit is bound to the second border area, the power supply circuit is connected to at least a portion of the structure of the electrode ring located in the second border area, and the power supply circuit is used to provide power to the electrode ring. Power signal.

8. The display panel according to claim 4, wherein: The first fan-out area includes a first sub-fan-out area and a second sub-fan-out area, and the first sub-fan-out area and the second sub-fan-out area are located on both sides of the second fan-out area in the first direction; The plurality of second signal lines also include at least one fifth analog line, a partial structure of the fifth analog line is located in the second fan-out area, and the fifth analog line is connected to the first analog line and the third analog line whose orthographic projections intersect with it on the substrate through vias.

9. The display panel according to claim 2, wherein: A plurality of the first signal lines are located in the same conductive layer, and a plurality of the second signal lines are located in the same conductive layer; The conductive layer where the second signal line is located is located on a side of the conductive layer where the first signal line is located away from the base substrate.

10. The display panel according to claim 9, wherein: The display panel further includes: a first source / drain layer, located on one side of the base substrate, wherein the first source / drain layer includes the first signal line; a second source-drain layer, located on a side of the first source-drain layer away from the base substrate, the second source-drain layer including the second signal line and the data line; The orthographic projection of the second signal line on the base substrate is located between the orthographic projections of two adjacent data lines on the base substrate.

11. The display panel according to claim 2, wherein: The first signal line includes a plurality of first via contact portions and a first extension portion, wherein the orthographic projections of the plurality of first via contact portions on the base substrate are spaced apart along the first direction, the first extension portion is connected to the first via contact portion, and the orthographic projection of the first via contact portion on the base substrate in the second direction is larger than the orthographic projection of the first extension portion on the base substrate in the second direction; The second signal line includes a plurality of second via contact portions and a second extension portion, wherein the orthographic projections of the plurality of second via contact portions on the base substrate are spaced apart along the second direction, the second extension portion is connected to the second via contact portion, and the orthographic projection of the second via contact portion on the base substrate in the first direction is larger than the orthographic projection of the second extension portion on the base substrate in the first direction; Wherein, the first via contact portion and the second via contact portion are correspondingly arranged, An orthographic projection of a via contact portion on the base substrate and an orthographic projection of the corresponding second via contact portion on the base substrate at least partially overlap, and at least a portion of the first via contact portion is connected to the corresponding second via contact portion through a via.

12. The display panel according to claim 11, wherein: The minimum distance between the orthographic projections of adjacent first via contact portions on the base substrate in the first direction is S5, and the maximum distance between the orthographic projections of adjacent first via contact portions on the base substrate in the first direction is S6, where (S6-S5) / S5 is greater than or equal to 0 and less than or equal to 0.2; And / or, the minimum distance between the orthographic projections of adjacent second via contact portions on the base substrate in the second direction is S7, and the maximum distance between the orthographic projections of adjacent second via contact portions on the base substrate in the second direction is S8, wherein (S8-S7) / S7 is greater than or equal to 0 and less than or equal to 0.

2.

13. The display panel according to claim 11, wherein: The plurality of first via contact portions include a first solid hole contact portion, and the plurality of second via contact portions include a second solid hole contact portion and a second virtual hole contact portion; The first real hole contact portion and the corresponding second real hole contact portion are connected through a via hole, and the second virtual hole contact portion is insulated from the first signal line intersecting with its orthographic projection on the base substrate.

14. The display panel according to claim 13, wherein: The plurality of first via contact portions further include a first dummy hole contact portion, and the first dummy hole contact portion and the corresponding second dummy hole contact portion are insulated from each other.

15. The display panel according to claim 10, wherein: The display panel includes: The first planar layer is located between the first source / drain layer and the second source / drain layer, and the thickness of the first planar layer is less than or equal to 1.6 μm.

16. The display panel according to claim 13, wherein: The display panel further includes: a passivation layer located between the conductive layer where the first signal line is located and the conductive layer where the second signal line is located; a first planar layer, located between the passivation layer and the conductive layer where the second signal line is located; A first opening is formed on the first flat layer, and an orthographic projection of the first opening on the base substrate at least partially overlaps with an orthographic projection of the second virtual hole contact portion on the base substrate.

17. The display panel according to claim 13, wherein: The display panel further includes: a passivation layer located between the conductive layer where the first signal line is located and the conductive layer where the second signal line is located; a first planar layer, located between the passivation layer and the conductive layer where the second signal line is located; A second opening is formed on the passivation layer, and an orthographic projection of the second opening on the base substrate at least partially overlaps with an orthographic projection of the second virtual hole contact portion on the base substrate.

18. The display panel according to claim 4, wherein: The size of the orthographic projection of the break between the first data fan-out line and the first analog line on the substrate in the first direction is 1.5 μm to 3.5 μm; And / or, a size of an orthographic projection of a break between the second data fan-out line and the second analog line on the substrate in the second direction is 1.5 um to 3.5 um.

19. The display panel according to claim 11, wherein: The data line whose orthographic projection on the base substrate is located on two adjacent sides of the second signal line includes a third extending portion, a fourth extending portion, and a fifth extending portion, and the fourth extending portion is connected between the third extending portion and the fifth extending portion; At least part of the structure of the second via contact portion and the fourth extension portion is arranged relative to each other in the first direction, and the size of the orthographic projection of the fourth extension portion on the substrate and the orthographic projection of the second extension portion on the substrate in the first direction is larger than the size of the orthographic projection of the third extension portion on the substrate and the orthographic projection of the second extension portion on the substrate in the first direction, and the size of the orthographic projection of the fourth extension portion on the substrate and the orthographic projection of the second extension portion on the substrate in the first direction is larger than the size of the orthographic projection of the fifth extension portion on the substrate and the orthographic projection of the second extension portion on the substrate in the first direction.

20. The display panel according to claim 4, wherein The display panel further includes a pixel driving circuit and a light-emitting unit, wherein the pixel driving circuit is connected to the first electrode of the light-emitting unit, and the display panel further includes: an electrode layer, located on one side of the base substrate, the electrode layer including a plurality of electrode portions, the electrode portions being used to form a first electrode of the light-emitting unit; The break between the first data fan-out line and the first analog line is on the substrate The orthographic projection of the electrode portion on the substrate does not overlap with the orthographic projection of the electrode portion on the substrate; And / or, an orthographic projection of a break between the second data fan-out line and the second analog line on the base substrate does not overlap with an orthographic projection of the electrode portion on the base substrate.

21. The display panel according to claim 11, wherein: The display panel further includes a pixel driving circuit and a light-emitting unit, wherein the pixel driving circuit is connected to the first electrode of the light-emitting unit, and the display panel further includes: an electrode layer, located on one side of the base substrate, the electrode layer including a plurality of electrode portions, the electrode portions being used to form a first electrode of the light-emitting unit; The orthographic projection of the first via contact portion on the base substrate and the orthographic projection of the electrode portion on the base substrate do not overlap; An orthographic projection of the second via contact portion on the base substrate does not overlap with an orthographic projection of the electrode portion on the base substrate.

22. The display panel according to claim 2, wherein: The display panel further includes a plurality of pixel driving circuits and a plurality of light-emitting units, wherein the plurality of pixel driving circuits are distributed in an array along the first direction and the second direction, and the pixel driving circuits are connected to the first electrodes of the light-emitting units; The pixel driving circuit includes a driving transistor, a sixth transistor, and a seventh transistor, wherein a first electrode of the sixth transistor is connected to a second electrode of the driving transistor, a second electrode of the sixth transistor is connected to a first electrode of the light-emitting unit, a first electrode of the seventh transistor is connected to a second initial signal line, and a second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit; The display panel further includes: a first active layer located on one side of the base substrate, the first active layer comprising a sixth active portion and a seventh active portion, the sixth active portion being used to form a channel region of the sixth transistor, and the seventh active portion being used to form a channel region of the seventh transistor; a first gate layer located on a side of the first active layer facing away from the base substrate, the first gate layer comprising an enable signal line and a second reset signal line, an orthographic projection of the enable signal line on the base substrate extending along the first direction and covering an orthographic projection of the sixth active portion on the base substrate, and an orthographic projection of the second reset signal line on the base substrate extending along the first direction and covering an orthographic projection of the seventh active portion on the base substrate; The first direction is the row direction, and the first signal line is on the substrate. The orthographic projection is located between the orthographic projection of the enable signal line on the base substrate and the orthographic projection of the second reset signal line on the base substrate in the same row of pixel driving circuits.

23. The display panel according to claim 11, wherein The display panel further includes a plurality of pixel driving circuits and a plurality of light-emitting units, wherein the plurality of pixel driving circuits are distributed in an array along the first direction and the second direction, and the pixel driving circuits are connected to the first electrodes of the light-emitting units; The pixel driving circuit includes a driving transistor, a sixth transistor, and a first transistor, wherein a first electrode of the sixth transistor is connected to a second electrode of the driving transistor, a second electrode of the sixth transistor is connected to a first electrode of the light-emitting unit, a first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a gate of the driving transistor; The display panel further includes: a first gate layer, located on one side of the base substrate, the first gate layer comprising an enable signal line, a portion of the enable signal line being used to form a gate of the sixth transistor; a second gate layer, located on a side of the first gate layer away from the base substrate, the second gate layer including the first initial signal line; The orthographic projection of the first extension portion of the first signal line on the base substrate is located between the orthographic projection of the first initial signal line in the pixel driving circuit of the current row on the base substrate and the orthographic projection of the enable signal line in the pixel driving circuit of the next adjacent row on the base substrate.

24. The display panel according to claim 2, wherein: The display panel includes a plurality of repeating units arrayed in the first direction and the second direction, the repeating unit includes n rows and m columns of sub-repeating units, where n and m are positive integers greater than or equal to 1; The sub-repeating unit includes two pixel driving circuits adjacently distributed in the first direction, and the two pixel driving circuits in the same sub-repeating unit are arranged in a mirror-symmetrical manner; A plurality of the repeating units distributed in the second direction form a repeating unit column, and a second signal line is correspondingly provided between two adjacent repeating unit columns in the first direction; A plurality of the repeating units distributed in the first direction form a repeating unit row, and each of the repeating unit rows is correspondingly provided with one first signal line.

25. The display panel according to claim 24, wherein: The display panel further includes a light emitting unit, and the pixel driving circuit is connected to the light emitting unit. The display panel further comprises: an electrode layer, comprising a plurality of electrode portions, wherein the electrode portions are used to form a first electrode of the light-emitting unit; Among them, in two adjacent sub-repeating units in the first direction, the orthographic projections of two adjacent data lines on the base substrate intersect with the orthographic projection of the same electrode portion on the base substrate, and are located on both sides of the orthographic projection of the second signal line on the base substrate.

26. The display panel according to claim 25, wherein: m is a positive integer greater than or equal to 2; In the adjacent repeating unit columns in the first direction, the minimum distance between the orthographic projections of two adjacent data lines on the substrate in the first direction is L1; In two sub-repeating units located in the same repeating unit and adjacent to each other in the first direction, a minimum distance in the first direction between orthographic projections of two adjacent data lines on the base substrate is L2; Among them, L1 is greater than L2.

27. The display panel according to claim 24, wherein: n is a positive integer greater than or equal to 2; The display panel further includes a light-emitting unit, and the pixel driving circuit includes a driving transistor, a sixth transistor, and a seventh transistor, wherein a first electrode of the sixth transistor is connected to a second electrode of the driving transistor, a second electrode of the sixth transistor is connected to a first electrode of the light-emitting unit, a gate of the sixth transistor is connected to an enable signal line, a first electrode of the seventh transistor is connected to a second initial signal line, a second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit, and a gate of the seventh transistor is connected to a second reset signal line; The same repeating unit row includes a first pixel driving circuit row and a second pixel driving circuit row, the first pixel driving circuit row includes a plurality of pixel driving circuits distributed along the first direction, and the second pixel driving circuit row includes a plurality of pixel driving circuits distributed along the first direction; The orthographic projection of the first signal line on the substrate is located between the orthographic projection of the enable signal line in the first pixel driving circuit row on the substrate and the orthographic projection of the second reset signal line in the first pixel driving circuit row on the substrate; In the first pixel driving circuit row, the enable signal line is on the substrate. The minimum distance between the orthographic projection and the orthographic projection of the second reset signal line on the base substrate in the second direction is L3; In the second pixel driving circuit row, a minimum distance in the second direction between an orthographic projection of the enable signal line on the base substrate and an orthographic projection of the second reset signal line on the base substrate is L4; Among them, L3 is greater than L4.

28. The display panel according to claim 1, wherein The display panel includes a pixel driving circuit and a light emitting unit, wherein the pixel driving circuit includes a driving transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a capacitor; A first electrode of the first transistor is connected to a first initial signal line, and a second electrode is connected to a gate of the driving transistor; A first electrode of the second transistor is connected to the gate of the driving transistor, and a second electrode of the second transistor is connected to the second electrode of the driving transistor; A first electrode of the fourth transistor is connected to the data line, and a second electrode is connected to the first electrode of the driving transistor; A first electrode of the fifth transistor is connected to a power line, and a second electrode is connected to the first electrode of the driving transistor; The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light emitting unit; A first electrode of the seventh transistor is connected to the second initial signal line, and a second electrode is connected to the first electrode of the light emitting unit; A first electrode of the capacitor is connected to the gate of the driving transistor, and a second electrode of the capacitor is connected to the power line.

29. The display panel according to claim 28, wherein: The display panel further includes: a first active layer located on one side of the substrate base, the first active layer comprising a third active portion, a fourth active portion, a fifth active portion, a sixth active portion, and a seventh active portion, the third active portion being used to form a channel region of the driving transistor, the fourth active portion being used to form a channel region of the fourth transistor, the fifth active portion being used to form a channel region of the fifth transistor, the sixth active portion being used to form a channel region of the sixth transistor, and the seventh active portion being used to form a channel region of the seventh transistor; a first gate layer located on a side of the first active layer facing away from the base substrate, the first gate layer comprising a first gate line, an enable signal line, a second reset signal line, and a first conductive portion, wherein an orthographic projection of the first gate line on the base substrate extends along the first direction and covers an orthographic projection of the fourth active portion on the base substrate, an orthographic projection of the enable signal line on the base substrate extends along the first direction and covers an orthographic projection of the fifth active portion and an orthographic projection of the sixth active portion on the base substrate, an orthographic projection of the second reset signal line on the base substrate extends along the first direction and covers an orthographic projection of the seventh active portion on the base substrate, and an orthographic projection of the first conductive portion on the base substrate covers an orthographic projection of the third active portion on the base substrate; a second active layer, located on a side of the first gate layer facing away from the base substrate, the second active layer comprising a first active portion and a second active portion, the first active portion being used to form a channel region of the first transistor, and the second active portion being used to form a channel region of the second transistor; a third gate layer, located on a side of the second active layer facing away from the base substrate, the third gate layer comprising a second gate line and a first reset signal line, wherein an orthographic projection of the second gate line on the base substrate extends along the first direction and covers an orthographic projection of the second active portion on the base substrate, and an orthographic projection of the first reset signal line on the base substrate extends along the first direction and covers an orthographic projection of the first active portion on the base substrate; Among them, the orthographic projection of the second reset signal line on the base substrate, the orthographic projection of the enable signal line on the base substrate, the orthographic projection of the first conductive part on the base substrate, the orthographic projection of the second gate line on the base substrate, the orthographic projection of the first gate line on the base substrate, and the orthographic projection of the first reset signal line on the base substrate are distributed in sequence along the second direction.

30. The display panel according to claim 29, wherein The first direction is a row direction, the second direction is a column direction, and the first gate line in the pixel driving circuit of a current row is multiplexed as a second reset signal line in the pixel driving circuit of the next adjacent row.

31. The display panel according to claim 28, wherein The driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are P-type transistors, and the first transistor and the second transistor are N-type transistors.

32. The display panel according to claim 4, wherein: The second signal line includes a plurality of second via contact portions, and the orthographic projections of the plurality of second via contact portions on the base substrate are spaced apart along the second direction; In the same second signal line, the distance between the orthographic projections of two adjacent second via contact portions on the base substrate in the second direction is A1, and the size of the orthographic projection of the break between the second data fan-out line and the second analog line on the base substrate in the second direction is A2; A1 / A2 is greater than or equal to 27 and less than or equal to 68.

33. A display device, wherein: The display device comprises the display panel according to any one of claims 1 to 32.

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