TESTING THE FUNCTIONAL SAFETY OF PHASE SHIFTERS

Abstract

An integrated circuit is described that performs testing of a circuit subblock. This integrated circuit may include the circuit subblock performing a function, wherein the circuit subblock is implemented in an analog domain with analog components and in a digital domain with digital components. Furthermore, the integrated circuit may perform testing of the circuit subblock by independently testing individual components in the circuit subblock, rather than testing the function of the circuit subblock as a whole. Note that the individual components include the analog and digital components. In some embodiments, the testing may also include functional safety testing.

Description

FIELD

[0001] The present disclosure relates to techniques for performing tests of a circuit subblock comprising multiple components in an integrated circuit, such as a phase shifter. BACKGROUND

[0002] To increase safety and provide more convenient transportation options, many automakers are incorporating additional sensors and / or features into their vehicles. For example, self-driving cars typically incorporate a variety of sensors, such as acoustic and / or electromagnetic sensors, that monitor the environment to detect other vehicles, people, animals, or obstacles. In addition, many vehicles include sensors that monitor vehicle operation (e.g., parking sensors or seat adjustment sensors) and, more generally, components that provide features or functions (e.g., interior lighting).

[0003] To ensure the safe operation of vehicles, the automotive industry typically provides safety features that test functional safety (e.g., functional tests according to ISO 26262 of the International Organization for Standardization in Geneva, Switzerland) to detect or report problems in circuits, such as those that use sensors (e.g., radar sensors) to monitor a vehicle's environment. For example, a power detector in a radar device can inject an electrical test signal into a receiver to test its proper operation.

[0004] However, radar transceivers often contain complex circuit subblocks implemented in both analog and digital domains, typically comprising multiple components. Accurately testing the numerous components within a circuit subblock during vehicle operation can be challenging, and the test structures can occupy a large area on a silicon chip, increasing the cost of the transceiver. SUMMARY

[0005] Embodiments of an integrated circuit are described. This integrated circuit includes a circuit subblock that performs a function, wherein the circuit subblock is implemented in an analog domain using analog components and in a digital domain using digital components. Furthermore, the integrated circuit performs tests of the circuit subblock by independently testing individual components within the circuit subblock, rather than testing the function of the circuit subblock as a whole. Note that the individual components include the analog and digital components.

[0006] In some embodiments, the circuit subblock may include a phase shifter, and the function may include providing an output signal having a phase shift relative to an input signal, and the input signal and the output signal may be in a non-zero frequency band.

[0007] In addition, testing of analog components may include testing for the presence of current and exclude testing of high-frequency functionality.

[0008] Furthermore, testing the digital components may include performing measurements on the digital components and a replica of the digital components. For example, testing the digital components may include comparing the measurements on the digital components and the replica of the digital components; and, if the comparison indicates a difference between the measurements on the digital components and the replica of the digital components, activating a flag.In some embodiments, the circuit subblock may include the phase shifter, the digital component may include a look-up table (LUT) decoder, testing the LUT decoder may include inputting phase shift values ​​to the LUT decoder and a replica LUT decoder, and the comparison may be performed by performing a logical XOR operation on measured outputs of the LUT decoder and measured outputs of the replica LUT decoder for the phase shift values.

[0009] Note that testing may also include functional safety testing.

[0010] Furthermore, the integrated circuit may evaluate the circuit sub-block based at least in part on the test results and the ratio between the detectable potential defects in the component in question and the total number of potential defects in the component in question.

[0011] Furthermore, the analog components may include a variable-gain amplifier, which may include a Gilbert cell, and testing may involve performing measurements at different gain values ​​of the variable-gain amplifier using a simulator circuit that includes a second Gilbert cell. During testing at a specific gain value, a differential DC input signal may be applied to the second Gilbert cell, and two measurements are performed. For example, the voltage at each of the outputs is measured to determine the differential DC output signal.

[0012] Alternatively or additionally, the analog components may include the variable-gain amplifier, the variable-gain amplifier may include the Gilbert cell, and testing may include performing measurements at different gain values ​​of the variable-gain amplifier using a emulation circuit including a third Gilbert cell in which the drain nodes are not cross-coupled. During testing at a particular gain value, a differential DC input signal may not be applied to the third Gilbert cell, and a number of measurements may be performed that corresponds to a number of drain nodes in the second Gilbert cell.

[0013] In some embodiments, the circuit subblock may include the phase shifter, the phase shifter may include a variable gain amplifier, and the testing may include high-frequency testing for the presence of variable gain amplifier performance over a range of variable gain amplifier gain values. Furthermore, the phase shifter may include an in-phase input signal and an out-of-phase input signal orthogonal to the in-phase input signal, and the testing for the presence of variable gain amplifier performance over the range of variable gain amplifier gain values ​​may be performed for the in-phase input signal and the out-of-phase input signal.It should be noted that testing for the presence of variable-gain amplifier performance across the variable-gain amplifier's range of gain values ​​may include a subset of gain values ​​within the range of gain values. Furthermore, testing may include confirming an expected difference in power levels at extreme gain values ​​across the range of gain values ​​relative to the power levels at an origin within the range of gain values.

[0014] Another embodiment provides an electronic device containing the integrated circuit.

[0015] Another embodiment provides a system that includes the integrated circuit.

[0016] Another embodiment provides a method for performing tests of the circuit subblock. This method includes at least some of the operations performed by the integrated circuit.

[0017] This summary is intended to illustrate some exemplary embodiments to provide a basic understanding of some aspects of the subject matter described herein. Accordingly, it is to be understood that the features described above are examples and should not be construed to limit the scope or spirit of the subject matter described herein in any way. Other features, aspects, and advantages of the subject matter described herein will become apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a drawing showing an example of a vehicle equipped with radar sensors according to some embodiments of the present disclosure. Fig. 2 is a block diagram illustrating an example of a driver assistance system according to some embodiments of the present disclosure. Fig. 3 is a block diagram illustrating an example of a radar system according to some embodiments of the present disclosure. Fig. 4 is a block diagram illustrating an example of a radar system according to some embodiments of the present disclosure. Fig. 5 is a block diagram showing an example of a phase shifter sub-block according to some embodiments of the present disclosure. Fig. 6 is a drawing showing an example of the number of components per circuit subblock in a Cartesian phase shifter according to some embodiments of the present disclosure. Fig. 7 is a drawing showing an example of a look-up table (LUT) coverage according to some embodiments of the present disclosure. Fig. 8 is a drawing showing an example of analog sub-block coverage according to some embodiments of the present disclosure. Fig. 9 is a drawing showing an example of the input phases of a phase shifter sub-block according to some embodiments of the present disclosure. Fig. 10 is a flowchart illustrating an example method for performing tests of a circuit subblock according to some embodiments of the present disclosure.

[0018] Please note that like reference numerals refer to corresponding parts in the drawings. Furthermore, multiple instances of the same part are designated by a common prefix separated from the instance number by a hyphen. DETAILED DESCRIPTION

[0019] An integrated circuit is described that performs testing of a circuit subblock. This integrated circuit may include the circuit subblock performing a function, wherein the circuit subblock is implemented in an analog domain with analog components and in a digital domain with digital components. Furthermore, the integrated circuit may perform testing of the circuit subblock by independently testing individual components in the circuit subblock, rather than testing the function of the circuit subblock as a whole. Note that the individual components include the analog and digital components. In some embodiments, the testing may also include functional safety testing.

[0020] By performing independent tests of individual components instead of testing the functionality of the circuit subblock as a whole, these circuit techniques can enable more accurate testing of the circuit subblocks. In particular, by covering a sufficient number of subcomponents within the circuit subblock, the circuit techniques can achieve a much higher safety rating than by testing the functionality of the circuit subblock as a whole. Furthermore, the required silicon area and the development time of the integrated circuit can be reduced. Consequently, these circuit techniques can improve the performance and reliability of the circuit subblock.

[0021] In the following discussion, a vehicle can be an automobile, a sports car, a truck, a motorcycle, a train, an airplane, a boat, or another type of transportation. However, in the following remarks, an automobile will be used as an illustrative example of a vehicle.

[0022] In addition, a vehicle may use one or more types of sensors to make measurements related to objects in the environment. Although a variety of sensor types may be used, the following discussion uses radar sensors as an illustrative example. The radar sensors may make measurements using at least one of several operating modes (e.g., pulsed or continuous wave) and use one or more modulation types (e.g., amplitude, frequency, and / or phase modulation). In the following discussions, frequency-modulated continuous wave (FMCW) radar is used for illustration. In addition, transmitted and received radar signals (e.g., with carrier frequencies in a radar frequency band, e.g., between 3 MHz and 100 GHz) may be generated and / or processed in the analog domain and / or the digital domain.

[0023] We now describe embodiments of the circuit techniques. Fig. Figure 1 shows a drawing illustrating an example of a vehicle 110 equipped with an array of radar antennas, including: antennas 112 for near-range detection (e.g., for parking assistance), antennas 114 for medium-range detection (e.g., for monitoring stop-and-go traffic and merges), and antennas 116 for long-range detection (e.g., for adaptive cruise control and forward collision warning), each of which may be located behind the front bumper cover. Antennas 118 for near-range detection (e.g., for reverse assist) and antennas 120 for medium-range detection (e.g., for rear collision warning) may be mounted behind the rear bumper cover. In addition, antennas 122 for short-range detection (e.g., for blind spot monitoring and lateral obstacle detection) can be mounted behind the vehicle's fenders.Each antenna and antenna set can be grouped into one or more arrays. Furthermore, each array can be controlled by a radar array controller 205 (. Fig. 2). In some embodiments, a particular set of antennas can perform multiple-input, multiple-output (MIMO) radar sensing. The type, number, and configuration of sensors in the sensor array vary for vehicles with driver assistance and self-driving features. The vehicle can use the sensor array to detect and measure distances / directions to objects in the various detection zones, allowing the vehicle to navigate while avoiding other vehicles and obstacles. While the preceding discussion shows the vehicle 110 with radar sensors, in other embodiments, the vehicle 110 can include additional types of sensors, such as LiDAR, an ultrasonic sensor, a camera, etc.

[0024] Fig. Figure 2 shows a block diagram illustrating an example of a driver assistance system. This driver assistance system may include an electronic control unit (ECU) 210 connected to various sensors 212 and a radar array controller 214 as the center of a star topology. However, other topologies such as serial, parallel, and hierarchical (tree) topologies are also possible. The radar array controller 214 may be coupled to the transmit and receive antennas (e.g., in antennas 114) to transmit electromagnetic waves, receive reflections, and determine a spatial relationship of the vehicle to its surroundings. Furthermore, the radar array controller 214 may be coupled to carrier signal generators. In some embodiments, the radar array controller 214 may control the timing and order of activation of a plurality of carrier signal generators.

[0025] To provide automatic parking assistance, the ECU 210 may be coupled to a number of actuators, such as: a turn signal actuator 216, a steering actuator 218, a brake actuator 220, and / or a throttle actuator 222. In addition, the control unit 210 may be connected to an interactive user interface 224 to accept user inputs and display various measurements and system status.

[0026] Using the user interface 224, the sensors, and the actuators, the ECU 210 can provide the following functions: automatic parking, assisted parking, lane change assistance, obstacle and blind spot detection, autonomous driving, and / or other desirable functions. During operation of the vehicle 110 ( Fig. 1) Sensor measurements may be collected by the ECU 210 and used by the ECU 210 to determine a status of the vehicle 110. Furthermore, the ECU 210 may respond to the status and incoming information to actuate signaling and control transducers to adjust and maintain operation of the vehicle 110. Functions that may be provided by the ECU 210 include, for example, driver-assistance features such as automatic parking, lane following, automatic braking, autonomous driving, etc.

[0027] In addition, the ECU 210 may use a MIMO radar system to obtain the measurements. In radar systems, electromagnetic waves are emitted, which propagate from a transmitting antenna before being reflected to a receiving antenna. The reflector may be any moderately reflective object located in the path of the emitted electromagnetic waves. By measuring the travel time of the electromagnetic waves from the transmitting antenna to the reflector and back to the receiving antenna, the radar system can determine the distance to the reflector. In addition, by measuring the Doppler shift of the electromagnetic waves, the radar system can determine the speed of the reflector relative to the vehicle 110 ( Fig. 1). If multiple transmitting or receiving antennas are used, or if multiple measurements are taken at different positions, the radar system can determine the direction to the reflector and thus track the position of the reflector relative to the vehicle 110 ( Fig. 1). With more sophisticated processing, multiple reflectors can also be tracked. In some embodiments, the radar system can use array processing to "scan" a directed beam of electromagnetic waves and create an image of the surroundings of the vehicle 110 ( Fig. 1). In general, pulsed and / or continuous wave radar systems can be implemented.

[0028] Fig. 3 shows a block diagram illustrating an example of a radar system 310 with a MIMO configuration in which J transmitters are collectively coupled to M transmit antennas 312 to transmit transmit signals 316, where J and M are non-zero integers. The M possible transmit signals 316 may be reflected by one or more reflectors or targets 314 to be received as receive signals 318 via N receive antennas 320 coupled to P receivers, where N and P are non-zero integers. Each receiver can extract the amplitude and phase or propagation delay associated with each of the M transmit signals 316, enabling the system to obtain N x M measurements (although only J x P of the measurements may be obtained at one time).The processing requirements associated with each receiver extracting J measurements can be reduced by using time-division multiplexing and / or orthogonal coding. Furthermore, the available antennas can be systematically multiplexed with the available transmitters and receivers to capture all measurements for radar imaging.

[0029] Fig. Figure 4 shows a block diagram illustrating an example of a radar transmit / receive circuit 410 (e.g., in radar system 310 in Fig. 3). In some embodiments, the radar transceiver circuit 410 is implemented as an integrated circuit in a packaged chip. The radar transceiver circuit 410 may include a carrier signal (chirp) generator 412, a phase shifter 414, an amplifier 416, and / or transmit antennas 312 that can transmit signals 316 based at least in part on the output signal of the carrier signal generator 412. Furthermore, the radar transceiver circuit 410 may include receiver antennas 320, a low-noise amplifier (LNA) 418, and / or a mixer 420. The mixer 420 may mix the receive signals 318 detected by the receive antennas 312 with the signal from the carrier signal generator 412. In addition, the low-noise amplifier 418 can be used to amplify the receive signals 318 detected by the receive antennas 320.In some embodiments, radar transmit / receive circuitry 410 may include a sensitivity timing regulator and equalizer (not shown), a wideband filter 422, an analog-to-digital converter 424, and / or a processor 426 (e.g., ECU 210 and / or radar array controller 214 in FIG. Fig. 2), which can further process the received signals (e.g., a Fourier transform). In some embodiments, the processor 426 and the low-noise amplifier 418 can be coupled for bidirectional communication.

[0030] Furthermore, in some embodiments, the carrier signal generator 412 may be coupled to the radar array controller 214 ( Fig. 2). The carrier signal generator 412 may include a chirp generator to generate an FMCW signal. The chip rate of the carrier signal generator 412 may be controlled by the radar array controller 214 ( Fig. 2). In some embodiments, the carrier signal generator 412 may be controlled by the radar array controller 214 ( Fig. 2) can be deactivated to generate an unmodulated carrier signal. Furthermore, the carrier signal generator 412 can be implemented as a local oscillation (LO) signal generator, a fractional-N phase-locked loop (PLL) with ΣΔ control, or as a direct digital synthesis generator.

[0031] In addition, the carrier signal generator 412 can be coupled to the transmit antennas 312 via the phase shifter 414 and the amplifier 416. The carrier signal generator 412 can be coupled to the receive antennas 312 via the mixer 420 and the low-noise amplifier 418. In addition, the carrier signal generator 412 can generate a transmit signal (e.g., a chirp signal). The amplifier 416 can receive the transmit signal from the carrier signal generator 412, and the transmit signals 316 corresponding to the transmit signal from the carrier signal generator 412 can be transmitted via the transmit antennas 312.

[0032] In some embodiments, a radar transmitter may include a phase rotator, a biphase modulator, a variable gain amplifier, a switch, a power amplifier driver, a power amplifier, and / or a digital signal processor (DSP). In some embodiments, a radar transmitter may also include a digital controller. This digital controller may be included within the DSP or be a separate component. Furthermore, the phase rotator may be used for digital phase modulation. Furthermore, the radar transmitter may use a wave-modulated power amplifier in a digital envelope modulation scheme.

[0033] As previously mentioned, circuits used in vehicles can be difficult to accurately test while the vehicles are in operation. For example, a phased array circuit in a transceiver may include a phase-shifter subblock (sometimes referred to as a "phase shifter"). In particular, a 6-bit phase shifter may be used in a phased array to provide 64 phase states. The phase shifter may split an input signal into quadrature or orthogonal I and Q components, which are amplified or attenuated based at least in part on weights and then combined to produce a weighted output signal to obtain a different phase than the input signal.A safety test circuit for a phase shifter may include a mmWave phase detector based on an I / Q downconverter and a mixer, whose RF and local oscillator inputs are coupled to the power amplifier input signals of two adjacent transmitters. However, this phase detector can require a large amount of silicon area and may be difficult to implement. For example, the phase detector may exhibit poor integral nonlinearity (INL) due to the transmitters' high RF leakage, which typically cannot be completely eliminated by calibration or by shutting down the power amplifiers.

[0034] In the disclosed circuit techniques, these problems can be addressed by independently evaluating the functionality of the individual components in the phase shifter, rather than evaluating the functionality of the phase shifter through direct phase measurement (e.g., at 80 GHz). In particular, the functionality of the individual components in the phase shifter can be evaluated using the following methods: Coverage=Number of detectable potential errorsNumber of potential errors.

[0035] By covering a sufficient number of subcomponents in the phase shifter, the circuit techniques can achieve a significantly higher safety rating than using a mmWave phase detector. For example, the disclosed circuit techniques can provide 98% safety coverage in the phase shifter. Furthermore, the required silicon area can be negligible, and the development time can be significantly shorter than that required for the phase detector.

[0036] The presented circuit techniques can be used to test a variety of circuits and circuit subblocks in an integrated circuit. For example, the circuit techniques can be used to test an active Cartesian phase shifter with Gilbert cell-based variable-gain amplifiers. However, in some embodiments, the disclosed circuit techniques can also be adapted to other Cartesian phase shifters.

[0037] Fig. Figure 5 shows a block diagram illustrating an example of a phase-shifter sub-block. The phase shifter may, in particular, include: high-frequency sub-blocks (e.g., a passive quadrature hybrid and an input matching network, a Gilbert cell-based variable-gain I and Q amplifier (VGAs), and / or a current-combining output matching network); digital sub-blocks (e.g., a hard-coded 6-bit to 12-bit LUT that translates an input phase setting into I and Q gain settings); and / or analog sub-blocks (e.g., I and Q pseudo-differential digital-to-analog converters or IDACs controlled by the LUT, differential diode-connected FETs that convert the IDAC differential currents into differential common-gate or CG bias voltages). VI+, VI−, VQ+, VQ−, and / or a common-source or CS bias circuit).

[0038] Fig. Figure 6 shows a drawing illustrating an example of the number of components per circuit subblock in a Cartesian phase shifter. Specifically, the common base (CB) or common gate bias voltage may comprise 12% (or 144 components) of the components in the circuit subblock, the components in the common base or common gate bias voltage for the variable gain amplifiers may comprise 1.1% of the components in the circuit subblock, the components in the common emitter (CE) or common source bias voltage may comprise 3.4% of the components in the circuit subblock, and a LUT decoder may comprise 82% (or 944 components) of the components in the circuit subblock. Thus, in the Cartesian phase shifter, the highest failure probability exists for the digital subblock containing the LUT decoder. (Note that the LUT decoder may contain 64 rows of gain values ​​for different values ​​of I and Q.)Due to the differential signals, the phase of the signals to the cell-based Gilbert amplifiers with variable gain in a Cartesian phase shifter can be inverted by changing the polarity of the local oscillator signal.

[0039] Regarding circuit techniques, it is important to note that failures can be detected primarily through low-frequency measurements. High-frequency measurements can perform basic performance detection (e.g., no leakage, etc.).

[0040] Fig. Figure 7 shows a drawing illustrating an example of the coverage of a LUT decoder. The input of the LUT decoder can be an N-bit word (where N is an integer) that contains the 2 NPhase shifter states (or the phase value of the phase shifter output signal), and its output may be two N-bit words representing the I and Q amplifier gain settings. In some embodiments, an identical replica of the LUT decoder may be used to perform bit-by-bit comparisons of the output bits of the real and replicated LUT decoders. For example, during testing, for each 2 NPhase shifter adjustment input: read the 2N output bits of the real LUT decoder and the emulated LUT decoder; perform a bit-by-bit comparison (e.g., using an XOR operation and, more generally, determine if there is a difference between the output of the real LUT decoder and the emulated LUT decoder) and sum the results; set a flag if the result is greater than zero. Note that any error would have to occur in exactly the same place in the emulated LUT decoder to avoid detection.

[0041] Fig. Figure 8 shows a drawing illustrating an example of the coverage of an analog sub-block. The analog sub-block includes two bias circuits with a current mirror that generates voltage drops across diodes or resistors. In addition, the analog sub-block can bias the common gate of a Gilbert cell with a DC local oscillator signal at the inputs. (Note that in a Gilbert cell, each common-source component sets the predefined total current of the two common-gate components above it. The differential common-gate bias sets the differential current through the common-gate components. Consequently, the analog sub-block can bias the differential common-gate components of a Gilbert cell.) Thus, the analog sub-block sets the gain of the Gilbert cell, providing a variable-gain amplifier. When the current I + high and the current I -is low, the analog sub-block is a differential cascode stage. If the current I + low and the current I - is high, the analog subblock reverses the phase. If I + equal to I - The analog subblock also ensures complete cancellation. Therefore, the local oscillator input signal and the differential voltage in the analog subblock can cause amplification and / or phase reversal.

[0042] During testing of the analog subblock, the differential bias of the variable-gain amplifier can be applied to a DC replica of the variable-gain amplifier, which in turn can be converted to output voltages. In some embodiments, one or more types of replicas can be used for testing. For example, replica A can include a Gilbert cell with two load resistors (instead of input / output matching networks), while replica B can have four non-cross-coupled drain nodes and four outputs.

[0043] Additionally, the DC gain can be measured during testing (e.g., using an analog-to-digital converter). For example, a specific measurement might capture the I / Q amplitudes immediately before the high-frequency conversion in a radar transceiver. Note that for Replica A, two voltage measurements per bias setting may be required, but for Replica A, a differential DC input signal may be required. Because the four drain nodes cannot be cross-coupled, a differential DC input signal may not be required for Replica B. However, four voltage measurements for each bias setting may be required. (VD1, VD2, VD3, VD4). For simulation A, it should be noted that the outputs can be the same if the gate voltages are the same. For simulation B, it should be noted that there can be a difference between two outputs if the gate voltages are the same.

[0044] It should also be noted that it is not necessary to use every 2 N states for each variable-gain amplifier. The number of required states can be on the order of N per variable-gain amplifier (where N is a non-zero integer), since each IDAC can contain N elements. Similarly, the common source bias can be tested by generating a DC current through a current mirror and converting it to a voltage across a resistor. However, as described below, high-frequency measurement can make this test unnecessary.

[0045] In some embodiments, for sub-block coverage in the high-frequency range, a transmit power detector can be used to derive information about the gain of the variable-gain amplifier. Since the amplitude of vector-summed signals is a function of the input phases (e.g., constructive / destructive interference), information can be derived via the quadrature hybrid and the current combiner. During these measurements, the transmit gain (via the variable-gain amplifier and the power amplifier bias) should be reduced to avoid compression (e.g., by using a bias voltage).B, a minimum gain may be used so that little or no output power is expected); then sweep the gain of the variable gain amplifier I and Q over the values ​​{-G, 0, +G}, where G is the maximum gain of the variable gain amplifier, and read the output of the power detector (as in . Fig. 9, which shows a drawing illustrating an example of input phases to a phase shifter sub-block, this may include a total of nine measurements); confirm that the power levels ±G ±iG are equal or approximately equal (e.g., within a tolerance of 1, 3, 5, or 10%); confirm that the ±G ±i0 power levels are equal or approximately equal (e.g., within a tolerance of 1, 3, 5, or 10%) and are, for example, 3 dB lower than the power levels at ±G ±iG (e.g., within a tolerance of 1, 3, 5, or 10%); and confirm that the power level 0 ±i0 is much lower than the other measured power levels. In some embodiments, more variable gain gain values ​​may be used in the testing, or continuous variable gain gain values ​​may be used over the ranges specified in Fig. 9 can be used. In general, variable gain gain values ​​can be based, at least in part, on the resolution and dynamic range of the transmit power detector. While the aforementioned measurements may not be accurate enough to detect aging-related mismatches, they may be able to detect hard component faults (such as opens and shorts). It should also be noted that the high-frequency components in the phase-shifter subblock must only constitute approximately 1% of the total components.

[0046] Embodiments of a method are described below. Fig.10 shows a flowchart illustrating an example of a method 1000 for testing a circuit subblock that may be performed by an integrated circuit. During operation, the integrated circuit may perform the testing of the circuit subblock (step 1010) using independent tests of individual components within the circuit subblock, rather than testing the function of the circuit subblock as a whole, wherein the circuit subblock performs a function and is implemented in an analog domain using analog components and in a digital domain using digital components, and the individual components include the analog components and the digital components.The integrated circuit may then evaluate the circuit subblock (step 1012) based at least in part on the test results and the ratio between the detectable potential faults in the given component and the total number of potential faults in the given component. The evaluation may include, for example, whether the circuit subblock is capable of performing the function (or not). Note that testing may also include functional safety testing.

[0047] In some embodiments of method 1000, there may be additional or fewer operations. Furthermore, the order of operations may be changed and / or two or more operations may be combined into a single operation.

[0048] The disclosed integrated circuit and circuit techniques may be (or be included in) any electronic device or system. The electronic device may include, for example, a mobile phone or smartphone, a tablet computer, a laptop computer, a notebook computer, a personal or desktop computer, a netbook computer, a media player device, an e-book device, a MiFi® device, a smartwatch, a wearable computing device, a consumer electronic device, an access point, a router, a switch, communications equipment, test equipment, a vehicle, a ship, an aircraft, a car, a truck, a bus, a motorcycle, manufacturing equipment, agricultural equipment, construction equipment, or any other type of electronic device.

[0049] Although specific components are used to describe embodiments of the integrated circuit and / or the integrated circuit containing the integrated circuit, in alternative embodiments, various components and / or subsystems may be present in the integrated circuit and / or the integrated circuit containing the integrated circuit. Thus, embodiments of the integrated circuit and / or the integrated circuit containing the integrated circuit may include fewer components, additional components, different components, two or more components that can be combined into a single component, a single component that can be split into two or more components, one or more positions of one or more components that can be changed, and / or different types of components.

[0050] Furthermore, the circuits and components in the embodiments of the integrated circuit and / or the integrated circuit containing the integrated circuit may be implemented using any combination of analog and / or digital circuits, including: bipolar, PMOS, and / or NMOS gates or transistors. Furthermore, the signals in these embodiments may include digital signals with approximately discrete values ​​and / or analog signals with continuous values. Furthermore, the components and circuits may be single-ended or differential, and the power supplies may be unipolar or bipolar. Note that the electrical coupling or connection in the preceding embodiments may be direct or indirect. In the preceding embodiments, a single line corresponding to a track may refer to one or more individual lines or tracks.

[0051] As mentioned above, an integrated circuit can implement some or all of the functions of the circuit techniques. This integrated circuit can contain hardware and / or software mechanisms used to implement the functions associated with the circuit techniques.

[0052] In some embodiments, the output of a process for designing the integrated circuit or a portion of the integrated circuit that includes one or more of the circuits described herein may be a computer-readable medium, such as magnetic tape or an optical or magnetic disk. The computer-readable medium may be encoded with data structures or other information that describe a circuit that can be physically instantiated as the integrated circuit or portion of the integrated circuit. Although various formats may be used for such encoding, these data structures are typically written in the following formats: Caltech Intermediate Format (CIF), Calma GDS II Stream Format (GDSII), Electronic Design Interchange Format (EDIF), OpenAccess (OA), or Open Artwork System Interchange Standard (OASIS).Those skilled in the art of integrated circuit design can develop such data structures from schematic diagrams of the type described above and the corresponding descriptions and encode the data structures on the computer-readable medium. Those skilled in the art of integrated circuit fabrication can use such encoded data to fabricate integrated circuits incorporating one or more of the circuits described herein.

[0053] While some of the operations in the preceding embodiments have been implemented in hardware or software, the operations in the preceding embodiments may generally be implemented in a variety of configurations and architectures. Therefore, some or all of the operations described in the preceding embodiments may be performed in hardware, in software, or both. For example, at least some of the operations in the circuit techniques may be implemented using program instructions executed by a processor or in firmware in an integrated circuit.

[0054] While examples of numerical values ​​have been provided in the foregoing, other embodiments use different numerical values. Therefore, the numerical values ​​provided are not intended to be limiting.

[0055] In the preceding description, we refer to "some embodiments." Note that "some embodiments" describes a subset of all possible embodiments, but does not always specify the same subset of embodiments.

[0056] The foregoing description is intended to enable any person skilled in the art to make and use the disclosure and is presented in the context of a particular application and its requirements. Furthermore, the foregoing descriptions of embodiments of the present disclosure have been presented for purposes of illustration and description only. They are not intended to be exhaustive or to limit the present disclosure to the forms shown. Accordingly, many modifications and variations will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. Furthermore, the discussion of the foregoing embodiments is not intended to limit the present disclosure.Therefore, the present disclosure is not intended to be limited to the embodiments shown, but is intended to have the widest possible application consistent with the principles and features disclosed herein. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited non-patent literature

[0000] ISO 26262

[0003]

Claims

[1] An integrated circuit comprising: a circuit subblock configured to perform a function, the circuit subblock being implemented in an analog domain using analog components and in a digital domain using digital components; wherein the integrated circuit is configured to perform testing of the circuit subblock using independent tests of individual components in the circuit subblock instead of testing the function of the circuit subblock as a whole; and where the individual components include the analog components and the digital components. [2] The integrated circuit of claim 1, wherein the circuit subblock comprises a phase shifter and the function comprises providing an output signal having a phase shift relative to an input signal, and the input signal and the output signal are in a non-zero frequency band. [3] The integrated circuit of claim 1, wherein testing the analog components includes testing for the presence of power and excludes testing of radio frequency functionality. [4] The integrated circuit of claim 1, wherein testing the digital components comprises performing measurements on the digital components and a replica of the digital components. [5] The integrated circuit of claim 4, wherein testing the digital components comprises: Comparing the measurements on the digital components and the emulation of the digital components; and If the comparison shows a difference between the measurements on the digital components and the emulation of the digital components, a flag is set. [6] The integrated circuit of claim 5, wherein the circuit subblock comprises a phase shifter and the function comprises providing an output signal having a phase shift relative to an input signal; wherein the digital component comprises a look-up table detector (LUT), testing the LUT decoder comprises inputting values ​​of the phase shift to the LUT decoder and a replica LUT decoder, and comparing is performed by performing a logical XOR operation on measured outputs of the LUT decoder and measured outputs of the replica LUT decoder for the values ​​of the phase shift. [7] The integrated circuit of claim 1, wherein testing comprises functional safety testing. [8] The integrated circuit of claim 1, wherein the integrated circuit is configured to evaluate the circuit subblock based at least in part on test results and a ratio of detectable potential failures in a given component in the circuit subblock to a total number of potential failures in the given component. [9] The integrated circuit of claim 1, wherein the analog components comprise a variable gain amplifier and the variable gain amplifier comprises a Gilbert cell; wherein testing comprises performing measurements at different gain values ​​of the variable gain amplifier using a replication circuit comprising a second Gilbert cell; and During testing, at a specific gain value, a differential DC input signal is applied to the second Gilbert cell and two measurements are taken. [10] The integrated circuit of claim 1, wherein the analog components comprise a variable gain amplifier and the variable gain amplifier comprises a Gilbert cell; wherein testing comprises performing measurements at different gain values ​​of the variable gain amplifier using a emulation circuit comprising a second Gilbert cell in which drain nodes are not cross-coupled; and wherein during testing at a given gain value, a differential DC input signal is not applied to the second Gilbert cell and a number of measurements are taken equal to the number of drain nodes in the second Gilbert cell. [11] The integrated circuit of claim 1, wherein the circuit subblock comprises a phase shifter and the function comprises providing an output signal having a phase shift relative to an input signal; wherein the phase shifter comprises a variable gain amplifier and the testing comprises high frequency testing for the presence of power of the variable gain amplifier over a range of gain values ​​of the variable gain amplifier. [12] The integrated circuit of claim 12, wherein the phase shifter comprises an in-phase input signal and a phase-shifted input signal orthogonal to the in-phase input signal; and wherein testing for the presence of performance of the variable gain amplifier is performed over the range of gain values ​​of the variable gain amplifier for the in-phase input signal and the phase-shifted input signal. [13] The integrated circuit of claim 12, wherein testing for the presence of performance of the variable gain amplifier over the range of gain values ​​of the variable gain amplifier comprises a subset of gain values ​​in the range of gain values. [14] The integrated circuit of claim 13, wherein testing comprises confirming an expected difference in power levels at extreme gain values ​​over the range of gain values ​​relative to power levels at an origin in the range of gain values. [15] An electronic device comprising: an integrated circuit, the integrated circuit comprising: a circuit subblock configured to perform a function, the circuit subblock being implemented in an analog domain using analog components and in a digital domain using digital components; wherein the integrated circuit is configured to perform testing of the circuit subblock using independent tests of individual components in the circuit subblock instead of testing the function of the circuit subblock as a whole; and where the individual components include the analog components and the digital components. [16] The electronic device of claim 15, wherein the electronic device comprises a vehicle. [17] A method for testing a circuit subblock, comprising: by an integrated circuit Performing testing of a circuit subblock in the integrated circuit using independent testing of individual components in the circuit subblock instead of testing the function of the circuit subblock as a whole, wherein the circuit subblock performs a function and is implemented in an analog domain using analog components and in a digital domain using digital components; and wherein the individual components comprise the analog components and the digital components; and Evaluating the circuit subblock based at least in part on the test results and the ratio between the detectable potential failures in a particular component of the circuit subblock and the total number of potential failures in the particular component. [18] The method of claim 17, wherein the circuit subblock comprises a phase shifter and the function comprises providing an output signal having a phase shift relative to an input signal, and the input signal and the output signal are in a non-zero frequency band. [19] The method of claim 17, wherein testing the analog components includes testing for the presence of power and excludes testing of radio frequency functionality. [20] The method of claim 17, wherein testing the digital components comprises performing measurements on the digital components and simulating the digital components.

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