Stacked field-effect transistor structure with independent gate control of an upper and a lower gate

Abstract

A semiconductor device comprises a first transistor and a first gate electrically connected to the first transistor. A second transistor is arranged on the first transistor. A second gate is electrically connected to the second transistor. A dielectric insulation layer is arranged between the first gate and the second gate. A first conductive contact is electrically connected to the first gate. A second conductive contact is electrically connected to the second gate. Control of the first gate by the first conductive contact is independent of control of the second gate by the second conductive contact.

Description

BACKGROUNDTechnical field

[0001] The present disclosure relates generally to electrical devices and, more particularly, to a stacked FET structure that enables independent gate control of an upper and lower gate. Description of the state of the art

[0002] In stacked nanosheet transistor structures, the gate control of individual transistors can often be handled by the same gate element. Fig. Figure 1A shows a conventional stacked transistor device. As can be seen in the figure, the upper and lower transistors share the same gate. In some devices, the upper and lower transistors may be different device types (for example, a pFET and an nFET). In I / O circuit design, not all gates of nFET / pFET structures are connected. By sharing the same gate, an nFET can introduce noise in a circuit connected to the pFET.

[0003] Although noise is undesirable, current manufacturing processes are typically limited by a standard procedure in which a dummy gate region is formed for all channels in a stacked nanosheet structure. Nanosheets of semiconductor channels are formed with sacrificial layers that ultimately define insulators between the individual channel layers. A dummy gate material is deposited around the nanosheet stacks until the signal channels are defined. Once the dummy gate material is removed, there are dummy gate cavities around all signal channels. The gate material completely fills the cavities around the channels so that each transistor is in contact with the same gate metal. Therefore, when a signal is passed through the gate of one transistor, the other transistor in contact with the same gate material can introduce a parasitic element such as noise. SUMMARY

[0004] In general, embodiments provide a semiconductor device and a manufacturing method that enables independent gate control of an upper and lower gate in a stacked transistor device. Stacked transistors no longer need to share the same gate element. By separating the gate control, the device avoids parasitic elements such as noise from a transistor that is not part of a signal-generating circuit but shares its gate with a transistor used in another signal-generating circuit.

[0005] According to one embodiment of the present disclosure, a chip semiconductor device is provided. The semiconductor device includes a first transistor and a first gate electrically connected to the first transistor. A dielectric isolation layer is disposed on at least a portion of the first transistor. A second transistor is disposed on at least a portion of the dielectric isolation layer. A second gate is electrically connected to the second transistor. The dielectric isolation layer is arranged to isolate the first gate from the second gate. A first conductive contact is electrically connected to the first gate. The first conductive contact is disposed within a first lateral boundary of the first transistor and outside a second lateral boundary of the second transistor.

[0006] In one embodiment, a second conductive contact is electrically connected to the second gate. The second conductive contact is located within the first lateral boundary and within the second lateral boundary. As can be seen, the structure defines separate access to the respective gates by offsetting the edges of each of the gates. In a stacked structure, the gates typically share the same contact because the lower gate is blocked from accessing the top surface by the upper gate. However, by offsetting the gate boundaries, a path is opened that allows the lower gate to be accessed independently of the upper gate.

[0007] According to one embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device comprises a first transistor and a first gate electrically connected to the first transistor. A second transistor is arranged on the first transistor. A second gate is electrically connected to the second transistor. A dielectric insulation layer is arranged between the first gate and the second gate. A first conductive contact is electrically connected to the first gate. A second conductive contact is electrically connected to the second gate. Control of the first gate by the first conductive contact is independent of control of the second gate by the second conductive contact.

[0008] In one embodiment that can be combined with the previous embodiments, the semiconductor device comprises a third conductive contact electrically connected to a first source / drain of the first transistor. The third conductive contact is connected to a front side of the first transistor. A fourth conductive contact is electrically connected to a second source / drain of the first transistor. The fourth conductive contact is connected to the front side of the first transistor. A fifth conductive contact is electrically connected to a first source / drain of the second transistor. The fifth conductive contact is connected to the front side of the second transistor. A sixth conductive contact is electrically connected to a second source / drain of the second transistor. The sixth conductive contact is connected to the front side of the second transistor.Together with independent gate access, access to the lower transistor elements can be performed simultaneously with access to the upper transistor elements from the front of the device. The manufacturing process can be simplified by accessing the stacked transistors entirely from the front of the device.

[0009] According to one embodiment of the present disclosure, a method of fabricating a semiconductor device is provided. The method includes forming a first stack of nanosheets on a substrate. A second stack of nanosheets is formed on the first stack of nanosheets. A first dummy gate is formed adjacent to the first stack of nanosheets and below a bottom nanosheet of the second stack of nanosheets. A dielectric isolation layer is formed on the first dummy gate and between the first stack of nanosheets and the second stack of nanosheets. A second dummy gate is formed on the dielectric isolation layer and adjacent to the second stack of nanosheets. The first dummy gate is replaced by a bottom gate electrically connected to the first stack of nanosheets.The first stack of nanosheets, in conjunction with gate material of the lower gate, forms a first transistor. The second dummy gate is replaced by an upper gate that is electrically connected to the second stack of nanosheets. The second stack of nanosheets, in conjunction with gate material of the upper gate, forms a second transistor. A first conductive contact is formed such that it is electrically connected to the lower gate. A second conductive contact is formed such that it is electrically connected to the upper gate. Control of the lower gate by the first conductive contact is independent of control of the upper gate by the second conductive contact.

[0010] In one embodiment that can be combined with the previous embodiments, the method comprises forming a third conductive contact electrically connected to a first source / drain of the first transistor. The third conductive contact is connected to a backside of the first transistor. A fourth conductive contact is formed to be electrically connected to a second source / drain of the first transistor. The fourth conductive contact is connected to the backside of the first transistor. A fifth conductive contact is formed to be electrically connected to a first source / drain of the second transistor. The fifth conductive contact is connected to the frontside of the second transistor. A sixth conductive contact is formed to be electrically connected to a second source / drain of the second transistor.The sixth conductive contact is connected to the front side of the second transistor. This embodiment provides rear access to the lower transistor elements, which can be useful in applications that include backside layers. For example, some applications include a back-end-of-line layer and / or a wafer carrier on the backside of the device. Connections to the lower transistor become available from the backside, saving space on the topside for additional circuit elements.

[0011] The techniques described herein can be implemented in a variety of ways. Example implementations are provided below with reference to the following figures. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The drawings illustrate exemplary embodiments. They do not illustrate all embodiments. Other embodiments may be used in addition to or instead of the invention. Details that are obvious or unnecessary may be omitted for space or clarity of illustration. Some embodiments may be practiced with additional components or steps and / or without all of the components or steps shown. When the same reference number appears in different drawings, it refers to the same or similar components or steps. Fig. Figure 1A is a cross-sectional view of a conventional shared gate field effect transistor. Fig. 1B is a cross-sectional view of a field effect transistor with independent control of a top gate and a bottom gate according to embodiments of the present disclosure. Fig. 2 is a key showing the sight lines for the views in Fig. 3A, 3B, 3C to 18A, 18B and 18C, in accordance with embodiments of the present disclosure. The Fig. 3A to 3C show views of an initial starting arrangement for a method of manufacturing a semiconductor with independent gate control according to embodiments. The Fig. 4A to 4C show views of deposition of a hard mask and an organic planarization layer according to one embodiment. The Fig. 5A to 5C show views of etching down the hard mask and a portion of the dummy gate material according to one embodiment. The Fig. 6A to 6C show views of removing the organic planarization layer according to an embodiment. The Fig. 7A to 7C show views of deposition of a dielectric isolation layer according to an embodiment. The Fig. 8A to 8C show views of removing a portion of the dielectric isolation layer from the top stack of nanosheets according to one embodiment. The Fig. 9A to 9C show views of depositing an upper portion of dummy gate material around the upper stack of nanosheets according to one embodiment. The Fig. 10A to 10C show views of patterning the upper portion of the dummy gate material according to an embodiment. The Fig. 11A to 11C show views of a recess downward through the upper stack of nanosheets according to one embodiment. The Fig. 12A to 12C show views of selectively removing sacrificial layer material from the upper stack of nanosheets and from a portion of the lower stack of nanosheets according to one embodiment. The Fig. 13A to 13C show views of deposition of fill material in cavities formed by selectively removing sacrificial layer material, according to one embodiment. The Fig. 14A to 14C show views of removing a portion of the lower gate material according to one embodiment. The Fig. 15A to 15C show views of removing a portion of the upper gate material according to one embodiment. The Fig. 16A to 16C show views of replacing the upper dummy gate material with a metal gate material according to an embodiment. The Fig. 17A to 17C show views of removing an interlayer dielectric material from a top surface above the bottom dummy gate material according to an embodiment. The Fig. 18A to 18C show views of replacing the lower dummy gate material with a metal gate material according to an embodiment. Fig. 19A is a key similar to Fig. 2, but including a fourth axis M, in accordance with embodiments. The Fig. 19B to 19E show views of forming metal contacts according to an embodiment. The Fig. 20A to 20D show views of bonding a back-end-of-line layer and a carrier wafer to the bottom of the substrate according to one embodiment. DETAILED DESCRIPTIONOverview

[0013] In conventional stacked transistor devices, the transistor structures generally must share the same gate element and utilize a common metal contact. Shared gate control leads to various signaling problems, including unwanted noise from a neighboring transistor that is not part of a circuit. In general, embodiments of the disclosure provide a semiconductor device that enables independent gate control between a top and bottom gate all-around structure in a transistor. In one example, the device is a field-effect transistor (FET) with a stacked nanosheet structure.

[0014] In the following detailed description, numerous specific details are described by way of example in order to provide a thorough understanding of the relevant teachings. It should be understood, however, that the present teachings may be practiced without such details. In other instances, well-known methods, operations, components, and / or circuits have been described at a relatively high level and without detail in order not to unnecessarily obscure aspects of the present teachings.

[0015] In one embodiment, spatially related terminology such as "front," "back," "top," "bottom," "beneath," "under," "lower," "above," "upper," "side," "left," "right," and the like is used with respect to the direction of the described figures. Because components of embodiments of the disclosure may be arranged in a number of different directions, the directional terminology is used for illustrative purposes and is in no way limiting. Therefore, it is to be understood that the terminology relating to spatial relationships is intended to cover other directions of the device in use or operation in addition to the direction shown in the figures. For example, if the device is turned over in the figures, elements described as being "below" or "below" other elements or structures would then be arranged "above" the other elements or structures.For example, the term "below" can cover both an upper and a lower arrangement. The component may be oriented differently (rotated 90 degrees or viewed or described from other directions), and the spatial terms used herein should be interpreted accordingly.

[0016] As used herein, the terms "lateral," "planar," and "horizontal" describe an orientation parallel to a first surface of a chip or substrate. In the description herein, a "first surface" may be the topmost layer of a semiconductor device, in which individual circuit components are patterned in the semiconductor material.

[0017] As used herein, the term “vertical” describes an orientation that is perpendicular to the first surface of a chip, chip carrier, chip substrate, or semiconductor body.

[0018] The terms "connected" and / or "electrically connected" as used herein are not intended to imply that the elements must be directly connected to one another - intermediate elements may be provided between the "connected" or "electrically connected" elements. On the other hand, when an element is described as being "directly connected" or "directly coupled" to another element, no intervening elements are present. The term "electrically connected" refers to a low-resistance electrical connection between the electrically connected elements. The term "electrically connected" does not necessarily mean that the elements must be in direct physical contact with one another - intermediate elements may be provided between the "connected" or "electrically connected" elements.

[0019] Although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element could be referred to as a second element, and a second element could similarly be referred to as a first element without departing from the scope of the exemplary embodiments. Likewise, describing an element as "first" or "second," etc., does not necessarily imply that the elements have a particular order or priority. As used herein, the term "and / or" covers any and all combinations of one or more of the respective listed elements.

[0020] Example embodiments are described herein with reference to cross-sectional views, which are schematic representations of idealized or simplified embodiments (and intermediate structures). Therefore, variations from the shapes of the illustrations are to be expected, for example, due to manufacturing techniques and / or tolerances. Thus, the portions shown in the figures are schematic in nature, and their shapes do not necessarily reflect the actual shape of any portion of a device or are limiting in scope. It should be noted that the figures and / or drawings accompanying this disclosure are exemplary and not restrictive and are not necessarily drawn to scale.

[0021] It is understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims. The description of the embodiments is not limiting. In particular, elements of the embodiments described below may be combined with elements of other embodiments. Example component structure

[0022] With reference to Fig. 1B is a cross-sectional view of a semiconductor device 100 (generally referred to as "device 100") in accordance with embodiments of the disclosure. Device 100 includes a first transistor structure 110 and a second transistor structure 120. The area for each of transistor structures 110 and 120 is indicated by a dashed line. Both transistor structures 110 and 120 may include a plurality of stacked nanosheet semiconductor channels (115 and 125, respectively). Transistor structures 110 and 120 may be pFETs, nFETs, or each a pFET and an nFET transistor. In the embodiment shown, transistor structure 110 is stacked on top of transistor structure 120. Accordingly, transistor structure 110 is sometimes referred to as "top transistor 110" and transistor structure 120 as "bottom transistor 120."Embodiments may also include a gate element 340 associated with the upper transistor 110 and a gate element 350 that is independent of the gate element 340 and associated with the lower transistor 120. The gate element 340 is sometimes referred to as an "upper gate 340" in accordance with embodiments that refer to the "upper transistor 100." The gate element 350 may sometimes be referred to as a "lower gate 350" in accordance with embodiments that refer to the "lower transistor 120." The device 100 includes a dielectric isolation layer 235 separating or demarcating the gate element 340 from the gate element 350. The transistor structures 110 and 120, the gate element 340, and the gate element 350 may be supported by a substrate 150. Embodiments generally also include a metal contact 135 in electrical communication with the first transistor structure 110.Embodiments may include separate metal contacts for the upper and lower gates 340 and 350. A metal contact 135 may be electrically connected to the gate element 340 from a top surface of the device 100. A metal contact 145 may be electrically connected to and associated with the gate element 350. Although not shown in this figure, embodiments may include a separate metal contact electrically connected to the transistor 120. Example manufacturing process

[0023] The following describes a general method for manufacturing a semiconductor device that has independent gate control for multiple transistors in the same device. Fig. Figure 2 shows a key showing the various views of the semiconductor device during the manufacturing process. The "X" axis is an edge view of a stack of nanosheets, showing the bottom and top gates. The "Y" axis shows a side view along the top of the nanosheet stack. The "M" axis shows a view below the center of the bottom stack of nanosheets.

[0024] It will now initially focus on the Fig. 3A to 3C to describe, by way of example, a method for manufacturing a semiconductor device 100 with independent gate control of the upper and lower transistors. Fig. 3A to 20D show a manufacturing method that includes additive and subtractive processes for forming some circuit elements in the finished device. The additive and subtractive processes involved (e.g., masking, deposition, etching, lithography, etc.) may be known to those skilled in the art and are not necessarily described in every process shown. The fabrication of the devices described herein may include multi-step sequences of, for example, photolithographic and / or chemical processing steps that enable the step-by-step fabrication of electronics-based systems, devices, components, and / or circuits in a semiconducting and / or superconducting device (e.g., an integrated circuit). For example, a device may be formed on one or more substrates (e.g.,a silicon substrate (Si) and / or another substrate) using techniques including, but not limited to: photolithography, microlithography, nanolithography, nanoimprint lithography, photomasking techniques, patterning techniques, photoresist techniques (e.g., positive resist, negative resist, hybrid resist and / or other photoresist techniques), etching techniques (e.g., reactive ion etching (RIE), dry etching, wet etching, ion beam etching, plasma etching, laser ablation and / or other etching techniques), evaporation techniques, sputtering techniques, plasma ashing techniques, heat treatments (e.g.,rapid thermal annealing, furnace annealing, thermal oxidation, and / or other heat treatments), chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), chemical mechanical planarization (CMP), grind-back techniques, and / or other integrated circuit fabrication techniques. In some figures, some reference numerals may not be repeated for elements not affected by a step.

[0025] With reference to the Fig. 3A to 3C, the process is shown in an initial state in which a first stack of nanosheets is provided, formed beneath a second stack of nanosheets on a substrate 150. Those skilled in the art will know the process leading to this initial structure without needing to describe the formation of the nanosheets on the substrate 150. References to "first" structures may generally refer to the lower gate and lower transistor elements. References to "second" structures may generally refer to the upper gate and upper transistor elements.

[0026] The first stack of nanosheets comprises alternating layers of a sacrificial material 240 (e.g., silicon germanium with a germanium concentration of 30% (SiGe30)) and semiconductor layers 125 (e.g., consisting of silicon). The second stack of nanosheets is similar to the first stack, except that the semiconductor layers are labeled 115. Furthermore, the first stack of nanosheets may be formed laterally longer than the width of the second stack, as shown in Fig. 3A. Some embodiments include a sacrificial layer 250 (e.g., made of SiGe 60) formed between the first stack of nanosheets and the second stack of nanosheets. As a precursor to the final product, the second stack of nanosheets is used to define the second (or upper) transistor structure 110, while the first stack of nanosheets is used to define the first (or lower) transistor structure 120 (both in Fig. 1B shown)).

[0027] An oxide layer 230 may be formed on both the upper and lower stacks of nanosheets. A first dummy gate material 220 is formed on the oxide layer 230. The first dummy gate material 220 surrounds both the upper and lower stacks of nanosheets at this stage. A hard mask 210 may be added on top of the structure, defining areas for recesses.

[0028] The Fig. 4A to 4C show deposition of an organic planarization layer (OPL) 260 in the recesses formed in the Fig. 3B and Fig. 3C were trained.

[0029] In the Fig. 5A to 5C, the hard mask 210 was removed. The dummy gate material 220 was etched away around the second stack of nanosheets (for example, using reactive ion etching (RIE)). In the vertical direction, the dummy gate material 220 can be removed from the top until the top is below the bottom semiconductor layer 115. In the embodiment shown, the removal is down to the level of the sacrificial layer 250, but some dummy gate material 220 remains on the oxide layer 230 above and on the sides of the first stack of nanosheets. Fig. 6A to 6C, the OPL 260 can be removed, exposing the oxide layer 230 surrounding the second stack of nanosheets. As a precursor, the remaining dummy gate material 220 defines the gate region for the lower transistor 120.

[0030] In the Fig. 7A to 7C, a layer of a dielectric 235 (e.g., silicon nitride or any non-EG oxide) is deposited on the oxide layer 230 and the dummy gate material 220, for example, using an atomic layer deposition (ALD) process. Fig. 8A to 8C illustrate deposition of an OPL 245 over the dielectric 235, which is disposed over the dummy gate material 220. A portion of the OPL 245 may cover the vertical portions of the dielectric 235 extending laterally upward at the base of the upper stack of nanosheets. The dielectric 235 surrounding the upper stack of nanosheets above the OPL 245 may be removed, exposing the oxide layer 230.

[0031] In the Fig. 9A to 9C, a second dummy gate material 280 may be deposited on the dielectric 235 and the exposed portions of the oxide 230 surrounding the upper stack of nanosheets. The second dummy gate material 280 may be the same as or different from the dummy gate material 220. A portion of the second dummy gate material 280 is deposited in areas designated for the formation of the upper gate element. As can be seen, the location of the dielectric 235 isolates the upper gate region from the lower gate region (outside the region where the upper transistor transitions to the lower transistor), ultimately leading to the formation of interconnects that enable independent control of the upper gate element and the lower gate element. Fig. 10A to 10C show patterning of recesses in the dummy gate material 280 using a gate hard mask 290.

[0032] The Fig. 11A to 11C illustrate performing a recess into the upper stack of nanosheets. The extent of the recess may extend beyond the sacrificial layer 250 into the uppermost sacrificial layer 240 of the lower stack of nanosheets. In some embodiments, deposition of a spacer layer 225 on the sides of the recessed walls may be provided. In some embodiments, deposition of a dielectric layer 265 is provided on portions of the oxide layer 230 covering the lower stack of nanosheets, for example, using a spin-on-glass (SOG) process.

[0033] In the Fig. 12A to 12C, material in the sacrificial layers 240 in the upper stack of nanosheets can be selectively removed to form recesses that are recessed inward from the sides of the semiconductor channels 115 (See Fig. 12B). The material removal can be performed up to the top sacrificial layer 240 of the lower nanosheet stack. Furthermore, the same process for removing the sacrificial layers 240 can completely remove the sacrificial layer 250 between the upper nanosheet stack and the lower nanosheet stack, creating a gap 250 e remains behind. In the Fig. 13A to 13C, the cavities containing the indentations and the space 250 e and left over from the removal of the sacrificial layer material are filled with an insulating spacer material 270. The insulating spacer material 270 provides a charge barrier between the upper transistor structure 110 and the lower transistor structure 120. At this stage, the insulating spacer material 270 cooperates with the dielectric layer 235 to form an insulation barrier between the upper gate region and the lower gate region.

[0034] The Fig. 14A to 14C show a process of removing a portion of the dummy gate materials 220 and 280 (exposing an oxide 275 in the process) using a hard mask 290. The left and right edges of the dummy gate material 220 define the lateral boundaries of the lower gate region. In Fig. 14B shows the source-drain material 310 (which is horizontally aligned) for the upper transistor. Fig. 14B and Fig. Figure 14C shows the source-drain material 320 (which is oriented horizontally) for the lower transistor. An insulator 330 is disposed between the source / drain 310 of the upper transistor and the source / drain 320 of the lower transistor.

[0035] In the Fig. 15A to 15C, a cutting process for removing the dummy gate material 280 for the upper gate element is shown. As shown in Fig. 15A, a portion of the dummy gate material 280 is removed. In one embodiment, the left lateral edge boundary of the dummy gate material 280 is aligned with the lateral edge boundary of the left side of the dummy gate material 220. The right side of the dummy gate material 280 may be removed laterally inward beyond the outer right lateral edge boundary of the dummy material 220. By offsetting the gate regions, space is freed up to add a separate metal contact for the bottom gate, which can be accessed from the top side (see Fig. 19B).

[0036] In the Fig. 16A to 16C, the process removes the sacrificial layers 240 of the upper stack of nanosheets and the upper dummy gate material 280. The upper dummy gate material 280 is replaced with a metal gate 340. Those skilled in the art will be aware of the available techniques for replacing the dummy gate material 280 with the metal gate 340. Removing the sacrificial layers 240 may also form cavities between the semiconductor channels 115. Deposition of the metal gate 340 may fill the channel cavities, forming a mandrel around the channels. In some embodiments, the upper transistor 110 may be a gate-all-around structure.

[0037] In the Fig. 17A to 17C, a portion of the oxide 275 above the dummy gate material 220 may be punctured. In the illustrated embodiment, the punctured portion lies above the portion of the lower nanosheet stack extending laterally to the right of the upper transistor 110. The puncture may remove both the oxide 275 and a portion of the dielectric 235, thereby exposing the dummy gate material 220 to the top surface of the device 100. Fig. 18A through 18C show the result of removing and replacing dummy gate material 220 with a metal gate 350. Metal gate 350 may be made of the same metal as gate 340 or a different metal. Similar to the upper transistor 110, metal gate 350 may enclose channels 125, completing the fabrication of transistor 120.

[0038] The Fig. 19A to 19E show an example of a resulting structure for the device 100 after metal contacts 130, 135, and 145 have been added that connect the top gate 340 and the bottom gate 350 to the top of the device 100. Fig. 19A is a key to symbols that corresponds to the key to symbols in Fig. 2, except that a fourth axis H has been added, showing a cross-sectional view along a lower gate contact. Processes showing the material recess for forming the openings for metal contacts 130, 135, and 145 are omitted.

[0039] In Fig. 19B, a metal contact 130 electrically connects the source-drain of the upper transistor 110 to the top surface via the top surface of the transistor 110. A metal contact 140 electrically connects the source-drain of the lower transistor 120 to the top surface via the top surface of the transistor 120. The metal contact 135 electrically connects the gate 340 of the upper transistor 110 to the top surface. The metal contact 145 electrically connects the lower gate 350 of the lower transistor 120 to the top surface. An additional view along the H axis is added (in Fig. 19E), taken from a cross-sectional view along the device structure and including a plurality of the metal contacts 145.

[0040] The Fig. 20A to 20D show an embodiment of the device 100 which is similar to the one shown in Fig. 19B to 19E, except that the device 100 is configured for rear access to the lower transistor 120. Metal contacts 165 may be formed on the backside of the substrate 150 (see Fig. 20C). The metal contacts 165 may be electrically connected to the source-drain regions 320 of the lower transistor 120. In some embodiments, a back-end-of-line layer 370 may be formed beneath the substrate 150. Some embodiments may include a carrier wafer 380 formed beneath the back-end-of-line layer 370. Concluding remark

[0041] The descriptions of the various embodiments of the present teachings have been provided for purposes of illustration, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been chosen to best describe the principles of the embodiments, practical application, or technical improvement over existing technologies in the marketplace, or to enable others skilled in the art to understand the disclosed embodiments.

[0042] While the foregoing has described the best mode contemplated and / or other examples, it should be understood that various changes may be made therein, the subject matter disclosed herein may be embodied in various forms and examples, and the teachings may be applied in numerous applications, only a few of which have been described herein. The following claims are intended to claim all applications, modifications, and variations that fall within the true scope of the present teachings.

[0043] The components, steps, features, tasks, benefits, and advantages described herein are for illustrative purposes only. None of them, nor any discussions thereof, are intended to limit the scope of protection. While various advantages have been described herein, it should be understood that not all embodiments necessarily include all advantages. Unless otherwise indicated, all measurements, values, ratings, positions, magnitudes, sizes, and other particulars presented in this application, including the following claims, are approximate and not exact. They are intended to have a reasonable range consistent with the functions to which they relate and with what is customary in the relevant art.

[0044] Numerous other embodiments are also contemplated. These include embodiments having fewer, additional, and / or different components, steps, features, objects, benefits, and advantages. These also include embodiments in which the components and / or steps are arranged and / or ordered differently.

[0045] Although the foregoing has been described in connection with exemplary embodiments, it is to be understood that the term "exemplary" is intended to be understood merely as an example and not as the best or optimum. Unless stated immediately above, nothing described or shown is intended or should be interpreted as dedicating any component, step, feature, task, benefit, advantage, or equivalent to the public, whether or not recited in the claims.

[0046] It is understood that the terms and expressions used herein have the ordinary meanings assigned to such terms and expressions with respect to the respective fields of study and research, unless a specific meaning is specified herein. Relational terms such as "first" and "second" and the like may be used solely to distinguish one entity or act from another, without necessarily requiring or implying any actual relationship or sequence between such entities or acts.The terms "comprises," "comprising," or any other variation thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a list of elements does not comprise only those elements, but may include other elements not expressly listed or inherent in such process, method, article, or device. An element preceded by "a" does not preclude, without further limitation, the existence of additional identical elements in the process, method, article, or device comprising the element.

[0047] The Summary of Disclosure is intended to enable the reader to quickly appreciate the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Moreover, it will be apparent from the foregoing Detailed Description that various features are grouped together in various embodiments to simplify the disclosure. This method of disclosure should not be interpreted to reflect an intent that the claimed embodiments include more features than are expressly recited in each claim. Rather, as will be apparent from the following claims, inventive subject matter lies in fewer than all of the features of a single disclosed embodiment.Therefore, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.

Claims

[1] Semiconductor device, comprising: a first transistor; a first gate electrically connected to the first transistor; a dielectric insulation layer on at least a portion of the first transistor; a second transistor on at least a portion of the dielectric insulation layer; a second gate electrically connected to the second transistor, wherein the dielectric insulation layer is arranged to insulate the first gate from the second gate; and a first conductive contact electrically connected to the first gate, the first conductive contact being located within a first lateral boundary of the first transistor and outside a second lateral boundary of the second transistor. [2] The semiconductor device of claim 1, further comprising a second conductive contact electrically connected to the second gate, the second conductive contact being within the first lateral boundary and within the second lateral boundary. [3] A semiconductor device according to claim 1, further comprising: a second conductive contact electrically connected to a first source or a first drain of the first transistor, the second conductive contact being connected to a front side of the first transistor; and a third conductive contact electrically connected to a second source or a second drain of the first transistor, the third conductive contact being connected to the front side of the first transistor. [4] A semiconductor device according to claim 3, further comprising: a fourth conductive contact electrically connected to a first source or a first drain of the second transistor, the fourth conductive contact being connected to the front side of the second transistor; and a fifth conductive contact electrically connected to a second source or a second drain of the second transistor, the fifth conductive contact being connected to the front side of the second transistor. [5] A semiconductor device according to claim 1, further comprising: a second conductive contact electrically connected to a first source or a first drain of the first transistor, the second conductive contact being connected to a backside of the first transistor; a third conductive contact electrically connected to a second source or a second drain of the first transistor, the third conductive contact being connected to the back of the first transistor; a fourth conductive contact electrically connected to a first source or a first drain of the second transistor, the fourth conductive contact being connected to the front side of the second transistor; and a fifth conductive contact electrically connected to a second source or a second drain of the second transistor, the fifth conductive contact being connected to the front side of the second transistor. [6] The semiconductor device of claim 1, further comprising stacks of nanosheets in the first transistor and in the second transistor. [7] Semiconductor device, comprising: a first transistor; a first gate electrically connected to the first transistor; a second transistor arranged on the first transistor; a second gate electrically connected to the second transistor; a dielectric insulation layer disposed between the first gate and the second gate; a first conductive contact electrically connected to the first gate; and a second conductive contact electrically connected to the second gate, wherein control of the first gate by the first conductive contact is independent of control of the second gate by the second conductive contact. [8] A semiconductor device according to claim 7, wherein the second gate is arranged on at least a part of the first gate. [9] The semiconductor device of claim 7, further comprising stacks of nanosheets in the first transistor and in the second transistor. [10] The semiconductor device of claim 9, further comprising a gate material of the first and second gates, wherein the gate material encloses the stacks of nanosheets. [11] A semiconductor device according to claim 7, further comprising: a third conductive contact electrically connected to a first source or a first drain of the first transistor, the third conductive contact being connected to a front side of the first transistor; a fourth conductive contact electrically connected to a second source or a second drain of the first transistor, the fourth conductive contact being connected to the front side of the first transistor; a fifth conductive contact electrically connected to a first source or a first drain of the second transistor, the fifth conductive contact being connected to the front side of the second transistor; and a sixth conductive contact electrically connected to a second source or a second drain of the second transistor, the sixth conductive contact being connected to the front side of the second transistor. [12] A semiconductor device according to claim 7, further comprising: a third conductive contact electrically connected to a first source or a first drain of the first transistor, the third conductive contact being connected to a backside of the first transistor; a fourth conductive contact electrically connected to a second source or a second drain of the first transistor, the fourth conductive contact being connected to the back of the first transistor; a fifth conductive contact electrically connected to a first source or a first drain of the second transistor, the fifth conductive contact being connected to the front side of the second transistor; and a sixth conductive contact electrically connected to a second source or a second drain of the second transistor, the sixth conductive contact being connected to the front side of the second transistor. [13] A semiconductor device according to claim 7, wherein the first transistor is an nFET and the second transistor is a pFET. [14] A semiconductor device according to claim 7, wherein the first transistor is a pFET and the second transistor is an nFET. [15] A method for producing a semiconductor device, comprising: Forming a first stack of nanosheets on a substrate; Forming a second stack of nanosheets on the first stack of nanosheets; Forming a first dummy gate adjacent to the first stack of nanosheets and below a bottom nanosheet of the second stack of nanosheets; Forming a dielectric insulation layer on the first dummy gate and between the first stack of nanosheets and the second stack of nanosheets; Forming a second dummy gate on the dielectric isolation layer and adjacent to the second stack of nanosheets; Replacing the first dummy gate with a bottom gate electrically connected to the first stack of nanosheets, wherein the first stack of nanosheets, in cooperation with a gate material of the bottom gate, forms a first transistor; Replacing the second dummy gate with a top gate electrically connected to the second stack of nanosheets, wherein the second stack of nanosheets, in cooperation with a gate material of the top gate, forms a second transistor; Forming a first conductive contact electrically connected to the lower gate; and Forming a second conductive contact electrically connected to the upper gate, wherein control of the lower gate by the first conductive contact is independent of control of the upper gate by the second conductive contact. [16] The method of claim 15, further comprising forming the first stack of nanosheets to have a greater width than a width of the second stack of nanosheets. [17] The method of claim 16, further comprising: Deepening a lateral boundary of the second dummy gate inwardly, wherein the lateral boundary of the second dummy gate lies within a lateral boundary of the first dummy gate; and Arranging the first conductive contact outside a lateral boundary of the upper gate and within a lateral boundary of the lower gate. [18] The method of claim 15, further comprising: Forming a third conductive contact electrically connected to a first source or a first drain of the first transistor, the third conductive contact being connected to a front side of the first transistor; Forming a fourth conductive contact electrically connected to a second source or a second drain of the first transistor, the fourth conductive contact being connected to the front side of the first transistor; Forming a fifth conductive contact electrically connected to a first source or a first drain of the second transistor, wherein the fifth conductive contact is connected to the front side of the second transistor; and Forming a sixth conductive contact electrically connected to a second source or a second drain of the second transistor, wherein the sixth conductive contact is connected to the front side of the second transistor. [19] The method of claim 15, further comprising: Forming a third conductive contact electrically connected to a first source or a first drain of the first transistor, the third conductive contact being connected to a backside of the first transistor; Forming a fourth conductive contact electrically connected to a second source or a second drain of the first transistor, the fourth conductive contact being connected to the backside of the first transistor; Forming a fifth conductive contact electrically connected to a first source or a first drain of the second transistor, wherein the fifth conductive contact is connected to the front side of the second transistor; and Forming a sixth conductive contact electrically connected to a second source or a second drain of the second transistor, wherein the sixth conductive contact is connected to the front side of the second transistor. [20] The method of claim 19, further comprising: Forming a back-end-of-line layer on a back side of the substrate; and Forming a wafer carrier on a backside of the back-end-of-line layer.

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