SHIFT CONTROL DEVICE AND MOTOR SYSTEM

Abstract

A switching control device includes: a PWM duty ratio conversion unit configured to convert voltage command signals of three phases into PWM duty ratios; a PWM duty ratio setting unit configured to simultaneously set the PWM duty ratios of the three phases using the same setting value; a pulse generation unit configured to generate pulse signals from the PWM duty ratios set by the PWM duty ratio setting unit; and an inverter circuit configured to include a plurality of switching elements driven by the pulse signals generated by the pulse generation unit.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This non-provisional application is based on International Patent Application No. PCT / JP2023 / 037163, filed on October 13, 2023, which claims priority from Japanese Patent Application No. 2022-199763, filed on December 14, 2022, the entire contents of which are hereby incorporated by reference. Technical area

[0002] The invention disclosed in the present specification relates to a shift control device and an engine system using a shift control device. State of the art

[0003] Conventionally, among the motor driving devices that drive a brushless DC motor, there is a motor driving device that drives a motor by PWM (Pulse Width Modulation) based on a speed command signal (for example, Patent Document 1). Prior art documentPatent publication

[0004] Patent Document 1: Japanese Patent Application Laid-Open No. 2022-104708 Summary of the inventionProblems to be solved by the invention

[0005] The demand for a switching control device and a motor system that drives a brushless DC motor that operates stably over a long period of time is increasing. Means of solving the problem

[0006] To achieve the above-described object, the present disclosure provides a switching control device comprising: a PWM duty conversion unit configured to convert voltage command signals of three phases into PWM duty ratios; a PWM duty setting unit configured to simultaneously set the PWM duty ratios of the three phases using the same setting value; a pulse generation unit configured to generate pulse signals from the PWM duty ratios set by the PWM duty setting unit; and an inverter circuit configured to include a plurality of switching elements driven by the pulse signals generated by the pulse generation unit. Advantages of the invention

[0007] According to the present disclosure, it is possible to provide a switching control device and a motor system that can drive a brushless DC motor that can operate stably for a long period of time. Short description of the drawings Fig. 1 is a schematic view of the configuration of an engine system; Fig. Figure 2 is a view illustrating ideal voltage signals and PWM waveforms when driving a motor; Fig. 3 is a view illustrating the waveforms of the PWM duty cycles; Fig. 4 is a flowchart illustrating a method for adjusting PWM duty cycles; Fig. 5 is an enlarged view of the PWM duty cycle waveforms illustrating the method for setting the PWM duty cycles; Fig. 6 is a view illustrating the waveforms of the PWM duty cycles after adjustment; Fig. 7 is a view illustrating the waveforms of the line voltages of a brushless DC motor; Fig. 8 is a view illustrating the waveforms of the PWM duty cycles; Fig. 9 is a flowchart illustrating a method for performing line modulation on voltage command signals; Fig. 10 is an enlarged view of the PWM duty cycle waveforms illustrating a method for adjusting the PWM duty cycles; Fig. 11 is a view illustrating the waveforms of the PWM duty cycles after adjustment; Fig. Fig. 12 is a view illustrating the waveforms of the line voltages of the motor; Fig. 13 is a schematic view of the configuration of an engine system in a second variant; Fig. 14 is a view illustrating an example of a dead time insertion operation; Fig. 15 is a view illustrating the waveforms of PWM duty cycles on which line modulation and dead time compensation were performed; Fig. 16 is an enlarged view of the PWM duty cycle waveforms illustrating a method for adjusting the PWM duty cycles; Fig. 17 is a view illustrating the waveforms of the PWM duty cycles after adjustment; Fig. Fig. 18 is a view illustrating the waveforms of line voltages of a motor; Fig. 19 is a flowchart illustrating a method for setting PWM duty cycles in a third variant; and Fig. 20 is an enlarged view of the waveforms in the method of adjusting the PWM duty cycles using the Fig. 19 shown flowchart. Description of the embodiments

[0008] In this specification, a MOS (metal oxide semiconductor) field-effect transistor refers to a transistor whose gate structure comprises at least three layers, namely "a layer of a conductor or a semiconductor such as polysilicon with a low resistance value," "an insulating layer," and "a P-channel, N-channel, or intrinsic semiconductor layer." In other words, the gate structure of the MOS field-effect transistor is not limited to a three-layer structure consisting of a metal, an oxide, and a semiconductor.

[0009] The embodiments will be described below with reference to the drawings. In the present description, a case where elements are connected to each other includes not only a case where they are mechanically connected, but also a case where they are electrically connected, that is, a case where current flows. Therefore, the case where "they are connected" includes the case where "they are electrically connected." <Motorsystem 100>

[0010] Fig. 1 is a schematic view of the configuration of an engine system 100; Fig. Figure 2 is a view illustrating ideal voltage wavelengths and PWM waveforms when driving a motor. Fig. The motor system 100 illustrated in Figure 1 includes a motor 200 and a switching control device 300. The motor 200 is a brushless DC motor. The motor 200 includes a U-phase coil 201, a V-phase coil 202, and a W-phase coil 203. A voltage of appropriate magnitude is applied to each of the U-phase coil 201, the V-phase coil 202, and the W-phase coil 203 at an appropriate time, so that the motor 200 rotates at a desired speed.

[0011] The shift control device 300 receives a speed command signal for the motor 200 from an external drive controller unit (not shown). The speed command signal includes information indicating the speed of the motor 200 and information for starting and stopping the motor 200. In other words, the shift control device 300 receives the speed command signal to drive the motor 200 at a speed specified by the speed command signal.

[0012] The switching control device 300 includes a voltage command calculation unit 1, a PWM duty cycle conversion unit 2, a PWM duty cycle adjustment unit 3, a pulse generation unit 4, and an inverter circuit 5. In the switching control device 300 according to the present embodiment, the voltage command calculation unit 1, the PWM duty cycle conversion unit 2, the PWM duty cycle adjustment unit 3, and the pulse generation unit 4 are digital processing units that perform digital processing. However, the present disclosure is not limited to this configuration, and the voltage command calculation unit 1, the PWM duty cycle conversion unit 2, the PWM duty cycle adjustment unit 3, and the pulse generation unit 4 may be analog processing units.These processing units can be configured with a single processing circuit or a combination of different processing circuits. They can be provided as programs that can perform the processing with a computing circuit.

[0013] The voltage command calculation unit 1 receives a speed control command from the drive controller unit described above. Based on the speed control command, the voltage command calculation unit 1 calculates the frequency and amplitude of a voltage applied to each of the coils 201 to 203 of the phases in the motor 200. The voltage command calculation unit 1 transmits the voltage command signals for the phases to the PWM duty cycle conversion unit 2. The voltage command signals contain digital information corresponding to the Fig. 2. The voltage command signals are assumed to be the U-phase voltage command signal VL_U, the V-phase voltage command signal VL_V, and the W-phase voltage command signal VL_W. The amplitude of the voltage command signal is represented by Vd.

[0014] The PWM duty cycle conversion unit 2 receives the voltage command signals from the voltage command calculation unit 1 and PWM periods to convert them into PWM signals. The PWM periods correspond to the PWM carrier signals, as shown in Fig. 2. In other words, the PWM periods are reference periods when the PWM signals are generated.

[0015] As in Fig. 2, the PWM duty cycle conversion unit 2 compares the voltage command signal and the PWM carrier signal to determine a PWM duty cycle. As shown in Fig. For example, as illustrated in Figure 2, the PWM duty cycle is generated by setting it to "on" when the voltage command signal is greater than the PWM carrier signal and setting it to "off" when the PWM carrier signal is greater than the voltage command signal. The PWM duty cycle can be determined using another method.

[0016] The PWM duty cycle conversion unit 2 generates the PWM signal based on the voltage command signal and the PWM period and transmits the PWM signal to the PWM duty cycle setting unit 3. The PWM signals are generated for the voltage command signals VL_U, VL_V and VL_W of the three phases.

[0017] The PWM duty cycle setting unit 3 acquires the PWM duty cycles of the three phases based on the PWM signals transmitted from the PWM duty cycle conversion unit 2. The PWM duty cycle setting unit 3 includes a minimum duty cycle determination unit 31. The minimum duty cycle determination unit 31 determines, based on the PWM duty cycle, whether the width of the on-period or the off-period of the PWM signal is greater than a predetermined width.

[0018] The PWM duty ratio setting unit 3 sets the PWM duty ratio to be converted based on the determination made by the minimum duty ratio determination unit 31. The details of the PWM duty ratio setting will be described later. The PWM duty ratio setting unit 3 generates the PWM duty ratio and transmits the PWM duty ratio to the pulse generation unit 4.

[0019] The pulse generation unit 4 generates pulse signals of the three phases based on the PWM duty cycles of the PWM duty cycle setting unit 3. The pulse signals generated in the pulse generation unit 4 are voltage signals for driving the inverter circuit 5 and are analog signals.

[0020] The inverter circuit 5 is a circuit that applies a voltage to the U-phase coil 201, the V-phase coil 202, and the W-phase coil 203 of the motor 200. As shown in Fig. 1, the inverter circuit 5 includes an inverter main circuit 51 and a switch driver circuit 52.

[0021] The inverter main circuit 51 is a three-phase full-bridge circuit comprising a U-phase arm, a V-phase arm, and a W-phase arm. In each of the phase arms, the first end of an upper arm is configured to receive a voltage. The second end of the upper arm and the first end of a lower arm are connected in series. The second end of the lower arm is configured to be connected to a ground potential.

[0022] The U-phase coil 201 is connected to a part where the upper arm and lower arm of the U-phase branch are connected. The V-phase coil 202 is connected to a part where the upper arm and lower arm of the V-phase branch are connected. Furthermore, the W-phase coil 203 is connected to a part where the upper arm and lower arm of the W-phase branch are connected.

[0023] The upper arm and the lower arm contain switching elements 511 to 516 such as bipolar transistors, MOS field-effect transistors, or IGBTs (Insulated Gate Bipolar Transistors), and freewheeling diodes 501 to 506 connected in parallel with the switching elements. In the inverter circuit 5 of the present embodiment, the IGBTs are used as switching elements 511 to 516.

[0024] When MOS field-effect transistors are used as switching elements 511 to 516, body diodes added to the MOS field-effect transistors can also be used as freewheeling diodes. This eliminates the need for freewheeling diodes.

[0025] The pulse signals generated in the pulse generation unit 4 are input to the switch driver circuit 52. As described above, the pulse signals are voltage signals, and the switch driver circuit 52 amplifies, for example, the input voltage signals to generate switching signals and outputs the switching signals to the control nodes of the switching elements 511 to 516 (in the present embodiment, the gates of the IGBTs). In this way, the switching elements 511 to 516 are controlled to be turned on.

[0026] The pulse generating unit 4 may supply the voltage signals indicating the voltages of the U-phase, the V-phase, and the W-phase, or it may supply six pulse signals for driving the switching elements 511 to 516. <Betrieb der Wechselrichter-Schaltung 5>

[0027] The operation of the inverter circuit 5 is described with reference to the figures. Fig. 2 illustrates the waveforms of the voltages applied by the inverter circuit 5 to the motor 200, as well as the PWM signals for controlling the switching elements 511 to 516.

[0028] As in Fig. As illustrated in Figure 2, the waveforms of the U-phase voltage Vu, the V-phase voltage Vv, and the W-phase voltage Vw are sinusoidal waves whose phases are shifted by 120 degrees. These voltage waveforms and the waveforms of the carrier signals, which are formed with triangular waves, are compared, and thus the PWM signals are generated. Fig. 2, switching elements 511, 512, and 513 in the upper arms of the U-phase branch, the V-phase branch, and the W-phase branch are turned on when the voltage waveforms are larger than the carrier signals. Switching elements 514, 515, and 516 in the lower arms of the U-phase branch, the V-phase branch, and the W-phase branch are respectively operated complementarily to switching elements 511, 512, and 513 in the upper arms. "Complementary" here refers to a state in which the switching elements in the upper arms of the branches and the switching elements in the lower arms of the branches are alternately turned on and off.

[0029] In other words, the voltage signals in the form of sinusoidal waves are subjected to PWM modulation using the carrier signals of the triangular waves, and thus the PWM signals are generated. Fig. 2, the PWM duty cycle is changed significantly over time, i.e., in a stepped manner. The frequency of the carrier signal is increased, thus achieving a finer change in the PWM duty cycle over time, so that the PWM duty cycle is closer to a sinusoidal wave. Therefore, the change in the PWM duty cycle over time is illustrated here as a sinusoidal wave with an amplitude of 1, as shown in Fig. 3 shown. Fig. Figure 3 is a view illustrating the PWM duty cycle waveforms.

[0030] If the PWM duty cycle waveforms in Fig. 3 When the PWM duty cycles have positive values, the on-periods of the switching elements 511 to 513 in the upper arms of the phase branches are long, and the on-periods of the switching elements 514 to 516 in the lower arms are short. When the PWM duty cycles are "0," the on-periods of the switching elements 511 to 513 in the upper arms of the phase branches are 50%, and the on-periods of the switching elements 514 to 516 in the lower arms are 50%. When the PWM duty cycles are "1," the switching elements in the upper arms are controlled to be constantly on (the on-periods are 100%), and when the PWM duty cycles are "-1," the switching elements in the upper arms are controlled to be constantly off (the on-periods are 0%).

[0031] When current is supplied to the motor, the inverter circuit 5 switches the switching elements 511 to 516 on and off to output a voltage with an AC component (in the form of sinusoidal waves). The frequency of switching on / off of the switching elements 511 to 516 increases, thus increasing switching loss. When the switching elements 511 to 516 are switched on / off briefly, a surge current several times larger than the current flowing through the inverter circuit 5 flows through the phase coils 201 to 203 of the motor 200, causing a severe stress on the insulation of the motor 200.

[0032] Therefore, the inverter circuit 5 performs control to turn on and off the switching elements 511 to 516 for a longer time than a predetermined limit time, so that the switching loss described above is suppressed and a large load on the insulation of the motor 200 is prevented.

[0033] In the inverter circuit 5, the PWM duty cycle setting unit 3 sets the PWM duty cycles so that the on / off switching time of the switching elements 511 to 516 is not shorter than the limit time described above. The PWM duty cycles are set as described above so that the switching control device 300 can operate the motor 200 stably over a long period.

[0034] The following describes the PWM duty cycles and the on / off switching time. Increasing the PWM duty cycle reduces the off period of the switching elements. Likewise, decreasing the PWM duty cycle reduces the on period of the switching elements. In other words, the on / off switching time is shortened.

[0035] Therefore, the PWM duty setting unit 3 sets an allowable range of PWM duty cycles so that the on / off switching width is not less than a predetermined width so that the motor 200 can rotate stably for a long period of time. The minimum duty determination unit 31 sets the upper limit of the allowable range to an allowable upper limit D_UL. The minimum duty determination unit 31 sets the lower limit of the allowable range to an allowable lower limit D_LL. If the PWM duty cycle is equal to or less than the allowable lower limit D_LL or equal to or greater than the allowable upper limit D_UL, the minimum duty determination unit 31 determines that adjustment is required.

[0036] Here, a method for setting the PWM duty cycles is described with reference to the figures. Fig. Figure 4 is a flowchart illustrating the method for setting the PWM duty cycles. A voltage having a different phase and the same waveform is applied to each of the phase coils 201 to 203 in the motor 200. Therefore, a U-phase duty cycle Du_U, a V-phase duty cycle Du_V, and a W-phase duty cycle Du_W only have different phases but the same waveform (see Fig. 3).

[0037] The PWM duty cycle setting unit 3 and the minimum duty cycle determination unit 31 have acquired the U-phase duty cycle Du_U, the V-phase duty cycle Du_V, and the W-phase duty cycle Du_W. Then, the minimum duty cycle determination unit 31 determines, as shown in Fig. 4 illustrates whether at least one of the U-phase duty ratios Du_U, the V-phase duty ratios Du_V and the W-phase duty ratios Du_W is greater than the allowable upper limit D_UL and less than “1” or whether at least one of the U-phase duty ratios Du_U, the V-phase duty ratios Du_V and the W-phase duty ratios Du_W is less than the allowable lower limit D_LL and greater than “-1” (step S101).

[0038] In step S101, it is determined whether at least one of the U-phase duty ratios Du_U, the V-phase duty ratios Du_V, and the W-phase duty ratios Du_W is outside the above-described allowable range, and whether at least one of the U-phase duty ratios Du_U, the V-phase duty ratios Du_V, and the W-phase duty ratios Du_W is less than "1" or greater than "-1." It can also be said that it is determined whether all of the U-phase duty ratios Du_U, the V-phase duty ratios Du_V, and the W-phase duty ratios Du_W are within the allowable range.

[0039] If the minimum duty ratio determination unit 31 determines that all of the U-phase duty ratios Du_U, the V-phase duty ratios Du_V, and the W-phase duty ratios Du_W are within the allowable range (No in step S101), the PWM duty ratio setting unit 3 outputs the U-phase duty ratios Du_U, the V-phase duty ratios Du_V, and the W-phase duty ratios Du_W, which are the current duty ratios, to the pulse generation unit 4 (step S105). After the PWM duty ratios of the phases are output, the processing returns to step S101, and the processing is thus repeated. In other words, if the U-phase duty ratios Du_U, the V-phase duty ratios Du_V, and the W-phase duty ratios Du_W are within the allowable range, the PWM duty ratios are not adjusted.

[0040] If at least one of the U-phase duty cycles Du_U, the V-phase duty cycles Du_V and the W-phase duty cycles Du_W is outside the allowable range, the PWM duty cycle setting unit 3 adjusts the PWM duty cycles.

[0041] Therefore, when it is determined by the minimum duty ratio determining unit 31 that at least one of the U-phase duty ratios Du_U, the V-phase duty ratio Du_V, and the W-phase duty ratio Du_W is larger than the allowable upper limit D_UL and smaller than “1,” or at least one of the U-phase duty ratios Du_U, the V-phase duty ratio Du_V, and the W-phase duty ratio Du_W is smaller than the allowable lower limit D_LL and larger than “-1” (Yes in step S101), the processing proceeds to step S102.

[0042] In step S102, the minimum duty ratio determination unit 31 determines whether a difference value between the maximum value D_max and the minimum value D_min of the U-phase duty ratio Du_U, the V-phase duty ratio Du_V, and the W-phase duty ratio Du_W is smaller than a difference value between the allowable upper limit D_UL and the allowable lower limit D_LL. This determination is performed, and thus it is determined whether the duty ratios of the phases after adjustment are outside the allowable range. Further description will be given. In the present method, when the duty ratios of all phases after adjustment are within the allowable range, feedback control is performed to adjust the duty ratios of all phases.If the duty cycles are outside the allowable range after adjustment, only a part that is currently outside the allowable range will be adjusted in the current processing.

[0043] When the minimum duty ratio determining unit 31 determines that the difference value between the maximum value D_max and the minimum value D_min is smaller than the difference value between the allowable upper limit D_UL and the allowable lower limit D_LL (Yes in step S102), the processing proceeds to step S103.

[0044] In step S103, if the maximum value D_max is greater than the allowable upper limit D_UL, the PWM duty ratio setting unit 3 sets a shift amount D_Sh to a value obtained by subtracting the allowable upper limit D_UL from the maximum value D_max. If the minimum value D_min is less than the allowable lower limit D_LL, the shift amount D_Sh is set to a value obtained by subtracting the allowable lower limit D_LL from the minimum value D_min. After that, the processing proceeds to step S104.

[0045] In step S104, the PWM duty ratio setting unit 3 sets values ​​obtained by subtracting the shift amount D_Sh from each of the current duty ratios U-phase duty ratio Du_U, V-phase duty ratio Du_V, and W-phase duty ratio Du_W, which are the new duty ratios, to the U-phase duty ratio Du_U, the V-phase duty ratio Du_V, and the W-phase duty ratio Du_W. After that, the processing proceeds to step S105.

[0046] When the difference value between the maximum value D_max and the minimum value D_min is smaller than the difference value between the allowable upper limit D_UL and the allowable lower limit D_LL, as shown in step S104, the U-phase duty ratio Du_U, the V-phase duty ratio Du_V, and the W-phase duty ratio Du_W are within the allowable range after adjustment.

[0047] In step S105, the PWM duty ratio setting unit 3 outputs the U-phase duty ratio Du_U, the V-phase duty ratio Du_V, and the W-phase duty ratio Du_W to the pulse generation unit 4.

[0048] When the minimum duty ratio determining unit 31 determines that the difference value between the maximum value D_max and the minimum value D_min is equal to or greater than the difference value between the allowable upper limit D_UL and the allowable lower limit D_LL (No in step S102), the processing proceeds to step S106.

[0049] When the difference value between the maximum value D_max and the minimum value D_min is equal to or larger than the difference value between the allowable upper limit D_UL and the allowable lower limit D_LL, when the setting is performed as shown in step S104, at least one of the U-phase duty ratios Du_U, the V-phase duty ratios Du_V, and the W-phase duty ratios Du_W is out of the allowable range.

[0050] Therefore, in step S106, among the U-phase duty ratio Du_U, the V-phase duty ratio Du_V, and the W-phase duty ratio Du_W, the duty ratio that is greater than the allowable upper limit D_UL and less than "1" is set as the allowable upper limit D_UL. Moreover, among the U-phase duty ratio Du_U, the V-phase duty ratio Du_V, and the W-phase duty ratio Du_W, the duty ratio that is less than the allowable lower limit D_LL and greater than "-1" is set as the allowable lower limit D_LL. In step S105, the duty ratio that is within the allowable range is not set. Thereafter, the processing proceeds to step S105. The processing in step S105 is performed as described above.

[0051] In the inverter circuit 5, the duty cycles are set as described above, so that it is possible to suppress the on / off switching of the switching elements 511 to 516 for a shorter time than the limit time. In this way, it is possible to stably control the rotation of the motor 200 over a long period.

[0052] The setting of the PWM duty cycles is described in more detail below with reference to the figures. Fig. 5 is an enlarged view of the PWM duty cycle waveforms illustrating the method for adjusting the PWM duty cycles. Fig. Figure 6 is a view illustrating the waveforms of the PWM duty cycles after adjustment. Fig. 7 is a view illustrating the waveforms of the line voltages of the brushless DC motor 200.

[0053] In the inverter circuit 5, the PWM duty cycles of the Fig. 3 are output from the PWM duty cycle conversion unit 2. Here, a part (between time t1 and time t2 in Fig. 5), in which the U-phase duty cycle Du_U is greater than the permissible upper limit, and a part (between time t3 and time t4 in Fig. 5), where the W-phase duty cycle Du_W is smaller than the allowable lower limit, is described as an example. Since the U-phase duty cycle Du_U, the V-phase duty cycle Du_V, and the W-phase duty cycle Du_W repeat periodically, they are adjusted using the same process.

[0054] The PWM duty cycle setting unit 3 determines that the maximum value D_max is the U-phase duty cycle Du_U and the minimum value D_min is the V-phase duty cycle Du_V between time t1 and time t2 (see Fig. 3).

[0055] As in Fig. As illustrated in Figure 5, the minimum duty cycle determination unit 31 determines that the U-phase duty cycle Du_U is greater than the allowable upper limit D_UL and less than "1" between time t1 and time t2 (Yes in step S101). Then, the minimum duty cycle determination unit 31 determines that the difference value between the maximum value D_max and the minimum value D_min is less than the difference value between the allowable upper limit D_UL and the allowable lower limit D_LL between time t1 and time t2 (Yes in step S102).

[0056] As in Fig. As illustrated in Figure 5, the difference between the maximum value D_max and the minimum value D_min between time t1 and time t2 is smaller than the difference between the allowable upper limit D_UL and the allowable lower limit D_LL. Therefore, the shift amount D_Sh is set to the value obtained by subtracting the allowable upper limit D_UL from the maximum value D_max (Du_U) (step S103). Subsequently, the PWM duty setting unit 3 outputs the U-phase duty ratio Du_U, the V-phase duty ratio Du_V, and the W-phase duty ratio Du_W after being set (step S105).

[0057] The U-phase duty cycle Du_U, the V-phase duty cycle Du_V and the W-phase duty cycle Du_W are set as described above so that the PWM duty cycles between time t1 and time t2 reach the values ​​shown in Fig. 5 and Fig. 6. In other words, the U-phase duty cycle Du_U is fixed to the allowable upper limit D_UL, and the V-phase duty cycle Du_V and the W-phase duty cycle Du_W have the waveforms shifted downward by the shift amount D_Sh.

[0058] Between time t2 and time t3, the U-phase duty cycle Du_U, the V-phase duty cycle Du_V, and the W-phase duty cycle Du_W are within the allowable range (No in step S101). Therefore, the U-phase duty cycle Du_U, the V-phase duty cycle Du_V, and the W-phase duty cycle Du_W are used as is, and the Fig. 5 and Fig. The PWM duty cycle waveforms illustrated in Figure 6 are the same as the waveforms of the Fig. 3 illustrated PWM duty cycles.

[0059] Then, the W-phase duty cycle Du_W between time t3 and time t4 is greater than "-1" and greater than the allowable lower limit D_LL. Then, the difference between the maximum value D_max and the minimum value D_min is smaller than the difference between the allowable upper limit D_UL and the allowable lower limit D_LL. Therefore, the shift amount D_Sh is set to a value resulting from subtracting the allowable lower limit D_LL from the minimum value D_min (Du_W) (step S103 in Fig. 4). Subsequently, the values ​​obtained by subtracting the shift amount D_Sh from each of the U-phase duty ratios Du_U, V-phase duty ratios Du_V, and W-phase duty ratios Du_W are set to the U-phase duty ratio Du_U, the V-phase duty ratio Du_V, and the W-phase duty ratio Du_W after being adjusted (step S104).

[0060] Between time t3 and time t4, the shift amount D_Sh is a negative value. Therefore, between time t3 and time t4, the W-phase duty cycle Du_W is fixed to the allowable lower limit D_LL, and the U-phase duty cycle Du_U and the V-phase duty cycle Du_V have the waveforms shifted upward by the shift amount D_Sh (see Fig. 5 and Fig. 6).

[0061] When the PWM duty cycles are set as in Fig. 5 and Fig. As illustrated in Figure 6, the difference between the PWM duty cycles, such as the difference between the U-phase duty cycle Du_U and the V-phase duty cycle Du_V, is unchanged before and after adjustment. The waveforms of the PWM signals correspond to the voltage waveforms of the voltages applied from the switching control device 300 to the motor 200. Therefore, the waveforms of the U-phase, V-phase, and W-phase voltages are the same as the waveforms of the PWM signals.

[0062] A line voltage (hereinafter referred to as U_V line voltage Vu_v) between the U-phase voltage and the V-phase voltage, a line voltage (hereinafter referred to as V_W line voltage Vv_w) between the V-phase voltage and the W-phase voltage, and a line voltage (hereinafter referred to as W_U line voltage Vw_u) between the W-phase voltage and the U-phase voltage output from the inverter circuit 5 are controlled by the U-phase duty cycle Du_U, the V-phase duty cycle Du_V and the W-phase duty cycle Du_W are the same as before setting the PWM duty cycles (see Fig. 7). In this way, the PWM duty cycles are adjusted, suppressing momentary on / off switching without changing the line voltages, thus suppressing current surges. Consequently, it is possible to operate the motor 200 stably over a long period of time.

[0063] When the PWM duty cycle adjustment unit 3 performs the adjustment in step S106, a surge current can be suppressed even though the line voltages change. Therefore, it is possible to operate the motor 200 stably for a long period of time, even though the rotation accuracy of the motor 200 may be reduced. <erste Variante>

[0064] A first variant of the motor system is described with reference to the figures. In the present variant, the motor system 100 has the same configuration as in Fig. 1. Therefore, the description of the configuration of the motor system 100 is omitted. Fig. Figure 8 is a view illustrating the PWM duty cycle waveforms.

[0065] In the above description, the PWM duty cycles may be outside the permissible range. If, as in Fig. As illustrated in Figure 8, when the U-phase duty cycle Du_U, the V-phase duty cycle Du_V, and the W-phase duty cycle Du_W are small, a surge current is easily generated. Even if the PWM duty cycles of the phases are changed, the line voltages do not change as long as the difference between the phase duty cycles remains the same.

[0066] Therefore, the voltage command calculation unit 1 in the motor system 100 performs conduction modulation to increase or decrease the voltage command signals VL_U, VL_V, and VL_W to generate the voltage command signals that have undergone conduction modulation. Subsequently, the PWM duty cycle conversion unit 2 generates the PWM duty cycles from the voltage command signals that have undergone conduction modulation, thereby suppressing the occurrence of a current surge in the motor system 100.

[0067] The voltage command signals of the modulated phases are referred to as a modulation U-phase voltage command signal Mv_U, a modulation V-phase voltage command signal Mv_V and a modulation W-phase voltage command signal Mv_W.

[0068] First, line modulation is described. Fig. 9 is a flowchart illustrating a method for performing line modulation on the voltage command signals. The voltage command calculation unit 1 first acquires the maximum value V_max and the minimum value V_min from the voltage command signals VL_U, VL_V, and VL_W of the phases at a certain time (step S201). It is determined whether the absolute value Va_max of the maximum value is greater than the absolute value Va_min of the minimum value (step S202). If the absolute value Va_max of the maximum value is greater than the absolute value Va_min of the minimum value (Yes in step S202), the voltage command calculation unit 1 sets the maximum value of the voltage to be supplied to the shift amount V_Sh, which in this case is a value obtained by subtracting the maximum value V_max from the amplitude "Vd" of the voltage command signal (step S203).

[0069] Thereafter, the voltage command calculation unit 1 adds the shift amount V_Sh to each of the U-phase voltage command signal VL_U, the V-phase voltage command signal VL_V, and the W-phase voltage command signal VL_W to generate the modulated U-phase voltage command signal Mv_U, the modulated V-phase voltage command signal Mv_V, and the modulated W-phase voltage command signal Mv_W (step S204).

[0070] Then, the voltage command calculation unit 1 outputs the modulated U-phase voltage command signal Mv_U, the modulated V-phase voltage command signal Mv_V, and the modulated W-phase voltage command signal Mv_W to the PWM duty conversion unit 2 (step S205).

[0071] If the absolute value Va_min of the minimum voltage value is greater than the absolute value Va_max of the maximum value (No in step S202), the voltage command calculation unit 1 sets the minimum voltage value that can be supplied to the shift amount V_Sh, which in this case is a value obtained by subtracting the minimum value V_min from "-Vd" (step S206). After that, the processing proceeds to step S204. The processing in step S204 is the same as that described above.

[0072] The PWM duty cycle conversion unit 2 determines the PWM duty cycles according to the method described above based on the voltage command signals subjected to line modulation. The PWM duty cycles of the modulated phases are referred to as a modulated U-phase duty cycle Md_U, a modulated V-phase duty cycle Md_V, and a modulated W-phase duty cycle Md_W.

[0073] The waveforms of the PWM duty cycles obtained by converting the voltage command signals subjected to line modulation are shown in Fig. 8. In the PWM duty ratios obtained by converting the voltage command signals subjected to line modulation, the PWM duty ratio of a part of the maximum value (Vd) or the minimum value (-Vd) of the voltage that can be supplied by the voltage command signal is "1" or "-1".

[0074] The PWM duty cycle setting unit 3 sets the modulated U-phase duty cycle Md_U, the modulated V-phase duty cycle Md_V, and the modulated W-phase duty cycle Md_W. The setting of the modulated U-phase duty cycle Md_U, the modulated V-phase duty cycle Md_V, and the modulated W-phase duty cycle Md_W will be described below with reference to the figures.

[0075] Fig. 10 is an enlarged view of the PWM duty cycle waveforms illustrating a method for adjusting the PWM duty cycles. Fig. Figure 11 is a view illustrating the waveforms of the PWM duty cycles after adjustment. Fig. 12 is a view illustrating the waveforms of the line voltages of the motor 200.

[0076] The setting of the duty cycles is carried out according to the Fig. 4. Therefore, a description is given according to the flow chart shown in Fig. 4 illustrated flowchart with reference to the Fig. 10 illustrated waveforms of the PWM duty cycles are given. The case of a change in the waveforms of the Fig. 10 illustrates the PWM duty cycles from time s1 to time s7. In Fig. 4, the U-phase duty cycle Du_U, the V-phase duty cycle Du_V and the W-phase duty cycle Du_W are respectively replaced by the modulated U-phase duty cycle Md_U, the modulated V-phase duty cycle Md_V and the modulated W-phase duty cycle Md_W.

[0077] As in Fig. As illustrated in FIG. 10, the minimum duty cycle determination unit 31 determines that the modulated U-phase duty cycle Md_U has the maximum value D_max between time s1 and time s2 and between time s3 and time s4, and here, the maximum value D_max is "1." The minimum duty cycle determination unit 31 determines that the minimum value D_min is the modulated V-phase duty cycle Md_V (between time s1 and time s2) and the modulated W-phase duty cycle Md_W (between time s3 and time s4). Then, the minimum duty ratio determining unit 31 determines that the modulated W-phase duty ratio Md_W (between time s1 and time s2) or the modulated V-phase duty ratio Md_V (between time s3 and time s4) is larger than the allowable upper limit D_UL and smaller than “1” (Yes in step S101).

[0078] The minimum duty cycle determination unit 31 determines that the difference between the maximum value D_max and the minimum value D_min is smaller than the difference between the allowable upper limit D_UL and the allowable lower limit D_LL (Yes in step S102). Processing proceeds to step S103.

[0079] Since the maximum value D_max is greater than the allowable upper limit D_UL, the PWM duty ratio setting unit 3 sets a value obtained by subtracting the allowable upper limit D_UL from the maximum value D_max to the shift amount D_Sh (step S103). Then, the PWM duty ratio setting unit 3 sets values ​​obtained by subtracting the shift amount D_Sh from each of the modulated U-phase duty ratio Md_U, the modulated V-phase duty ratio Md_V, and the modulated W-phase duty ratio Md_W, which are the current duty ratios, to the modulated U-phase duty ratio Md_U, the modulated V-phase duty ratio Md_V, and the modulated W-phase duty ratio Md_W, which are new duty ratios (step S104).Then, the PWM duty ratio setting unit 3 outputs to the pulse generation unit 4 the modulated U-phase duty ratio Md_U, the modulated V-phase duty ratio Md_V, and the modulated W-phase duty ratio Md_W, which are new duty ratios (step S105).

[0080] As described above, when the PWM duty cycles are "1," the on-periods of the switching elements in the upper arms are 100% (the on-periods of the switching elements in the lower arms are 0%). In other words, the switching elements are not switched on and off, and thus the switching elements are not affected by momentary switching. Therefore, when the PWM duty cycles are "1," the PWM duty cycles can be used without adjustment. Between time s2 and time s3, the modulated V-phase duty cycle Md_V and the modulated W-phase duty cycle Md_W are smaller than the allowable upper limit D_UL. Therefore, the PWM duty ratio setting unit 3 determines that no adjustment is required and outputs to the pulse generation unit 4 the modulated U-phase duty ratio Md_U, the modulated V-phase duty ratio Md_V, and the modulated W-phase duty ratio Md_W, which are the current duty ratios (step S105).

[0081] As in Fig. As illustrated in FIG. 10, the minimum duty cycle determination unit 31 determines that the modulated W-phase duty cycle Md_W is the minimum value D_min between time s4 and time s5 and between time s6 and time s7, and here, the minimum value D_min is "1." The minimum duty cycle determination unit 31 determines the modulated U-phase duty cycle Md_U (between time s4 and time s5) and the modulated V-phase duty cycle Md_V (between time s6 and time s7). Then, the minimum duty ratio determining unit 31 determines that the modulated V-phase duty ratio Md_V (between time s4 and time s5) or the modulated U-phase duty ratio Md_U (between time s6 and time s7) is smaller than the allowable lower limit D_LL and larger than “-1” (Yes in step S101).

[0082] The minimum duty cycle determination unit 31 determines that the difference between the maximum value D_max and the minimum value D_min is smaller than the difference between the allowable upper limit D_UL and the allowable lower limit D_LL (Yes in step S102). Processing proceeds to step S103.

[0083] Since the minimum value D_min is below the allowable lower limit D_LL, the PWM duty setting unit 3 sets a value obtained by subtracting the allowable upper limit D_UL from the minimum value D_min to the shift amount D_Sh (step S103). Then, the PWM duty setting unit 3 sets values ​​obtained by subtracting the shift amount D_Sh from each of the modulated U-phase duty ratios Md_U, the modulated V-phase duty ratio Md_V, and the modulated W-phase duty ratio Md_W, which are the current duty ratios, to the modulated U-phase duty ratio Md_U, the modulated V-phase duty ratio Md_V, and the modulated W-phase duty ratio Md_W, which are new duty ratios (step S104).Then, the PWM duty ratio setting unit 3 outputs to the pulse generation unit 4 the modulated U-phase duty ratio Md_U, the modulated V-phase duty ratio Md_V, and the modulated W-phase duty ratio Md_W, which are new duty ratios (step S105).

[0084] As described earlier, the on-periods of the switching elements in the upper arms are 0% when the PWM duty cycles are "-1" (the on-periods of the switching elements in the lower arms are 100%). In other words, the switching elements are not switched on and off, and thus the switching elements are not affected by momentary switching. Therefore, the PWM duty cycles can be used without adjustment when the PWM duty cycles are "-1". Between time s5 and time s6, the modulated V-phase duty cycle Md_V and the modulated W-phase duty cycle Md_W are smaller than the allowable upper limit D_UL.Therefore, the PWM duty ratio setting unit 3 determines that no adjustment is required and outputs to the pulse generation unit 4 the modulated U-phase duty ratio Md_U, the modulated V-phase duty ratio Md_V, and the modulated W-phase duty ratio Md_W, which are the current duty ratios (step S105).

[0085] As described above, the PWM duty ratio setting unit 3 sets the duty ratios, and thus the modulated U-phase duty ratio Md_U, the modulated V-phase duty ratio Md_V and the modulated W-phase duty ratio Md_W have the Fig. 11 illustrated waveforms.

[0086] As described above, the PWM duty cycles of the phases are adjusted and thus the short-term on / off switching is suppressed without changing the line voltages (see Fig. 12), so that a current surge can be suppressed. Consequently, it is possible to operate the motor 200 stably over a long period. <zweite Variante>

[0087] A second variant of the motor system is described with reference to the figures. Fig. 13 is a schematic view of the configuration of a motor system 100A in the second variant. Fig. 14 is a view illustrating an example of a dead time insertion operation. Fig. Figure 15 is a view illustrating the waveforms of PWM duty cycles where line modulation and dead time compensation were performed.

[0088] The Fig. The motor system 100A shown in Figure 13 differs from the one shown in Fig. 1 in that the PWM duty ratio adjusting unit 3A of a switching control device 300A includes a dead time compensation unit 32. Parts other than the PWM duty ratio adjusting unit 3A of the motor system 100A have the same configurations as those in the motor system 100. Therefore, in the motor system 100A, substantially the same parts as those in the motor system 100 are denoted by the same symbols, and the detailed description of the same parts is omitted.

[0089] As in Fig. As illustrated in Figure 2, the PWM duty cycle conversion unit 2 generates the PWM duty cycles so that the switching element 511 (512 and 513) in the upper arm and the switching element 514 (515 and 516) in the lower arm are complementarily turned on and off. However, after receiving the PWM signals, the actual switching elements 511 and 514 are turned on or off with a delay. When such a delay occurs and the actual switching elements 511 and 514 are complementarily turned on and off, the switching element 511 (512 and 513) and the switching element 514 (515 and 516) are turned on simultaneously, so a short circuit may occur.

[0090] Therefore, the PWM duty cycle conversion unit 2 adjusts the PWM signals so that periods in which the switching elements in the upper arms and the lower arms of the branches of the phases are simultaneously turned off occur at locations where the functions of the switching elements are switched. Fig. Figure 14 illustrates the PWM signals for the switching element 511 in the upper arm and the switching element 514 in the lower arm of the U phase in a certain period. To simplify the description, Fig. 14 shows a steady-state control state in which the switching element 511 is switched between the PWM duty cycle of "1" and the PWM duty cycle of "0". In fact, the PWM duty cycles fluctuate, as shown in Fig. 2 illustrates, over time.

[0091] In the Fig. 14, when the switching element 514 is turned on, the timing at which the switching element 514 is turned on is shifted to the timing at which the switching element 511 is completely turned off. When the switching element 511 is controlled in the on state, the timing at which the switching element 511 is turned on is shifted to the timing at which the switching element 514 is completely turned off.

[0092] In this way, a dead time is inserted into the PWM signals, during which the switching elements in the upper arm and the switching elements in the lower arm are simultaneously turned off. Inserting the dead time prevents the switching elements in the upper arm and the switching elements in the lower arm from being turned on simultaneously in the phase branches, thus preventing short-circuit current from flowing. The dead time is also inserted in the V-phase branch and the W-phase branch.

[0093] Although in the Fig. While the timing at which each of the switching elements enters the on-state is shifted backward in the waveforms illustrated in FIG. 14, the present disclosure is not limited to this configuration. The timing at which each of the switching elements enters the off-state may be shifted forward to insert the dead time. Alternatively, the timing at which each of the switching elements enters the off-state may be shifted forward, and the timing at which each of the switching elements enters the on-state may be shifted backward, allowing the dead time to be inserted.

[0094] The dead time is inserted, resulting in an error between the voltages actually output to the motor 200 and the voltage command signals. In the PWM duty cycle adjustment unit 3A of the motor system 100A, the dead time compensation unit 32 adjusts the PWM duty cycles to correct the error between the voltages output to the motor 200 and the voltage command signals.

[0095] In the motor system 100A, the voltage command calculation unit 1 performs conduction modulation on the voltage command signals, and the PWM duty cycle conversion unit 2 generates the PWM duty cycles based on the conduction modulated voltage command signals. Then, the dead time compensation unit 32 of the PWM duty cycle setting unit 3A performs dead time compensation on the PWM duty cycles supplied from the PWM duty cycle conversion unit 2.

[0096] Fig. Figure 15 illustrates the waveforms of the PWM duty cycles on which line modulation and dead-time compensation have been performed. In the PWM duty cycles for which dead-time compensation has been performed, a part may be generated in which "1" or "-1" does not persist in the parts where the PWM duty cycles are modulated to "1" or "-1" by line modulation (see Fig. 15).

[0097] As in Fig. As illustrated in Figure 15, as a result of the line modulation and the dead time compensation performed, a portion may be generated in which the maximum PWM duty cycle exceeds "-1" and a portion in which the minimum PWM duty cycle falls below "1." In the motor system 100A, when the PWM duty cycle exceeds "1," the same operation as when the PWM duty cycle is "1" is performed, that is, the switching element is controlled to be constantly on. When the PWM duty cycle falls below "-1," the same operation as when the PWM duty cycle is "-1" is performed, that is, the switching element is controlled to be constantly off.

[0098] The PWM duty ratio setting unit 3A of the motor system 100A in the present variant further performs the setting by the Fig. 4 illustrated procedures on the PWM duty cycles, which are shown in Fig. 15 and on which the line modulation and dead-time compensation were performed. The method for adjusting the PWM duty cycles at which the line modulation and dead-time compensation were performed is described below with reference to the figures. Fig. 16 is an enlarged view of the PWM duty cycle waveforms illustrating the method for adjusting the PWM duty cycle. Fig. Figure 17 is a view illustrating the waveforms of the PWM duty cycles after adjustment.

[0099] As in Fig. As illustrated in Figure 16, the PWM duty cycles between time m1 and time m5 are described. Between time m1 and time m2, the minimum duty cycle determination unit 31 determines that the modulated U-phase duty cycle Md_U is the maximum value D_max. The minimum duty cycle determination unit 31 determines that the minimum value D_min corresponds to the modulated V-phase duty cycle Md_V. Then, the minimum duty cycle determination unit 31 determines that the modulated U-phase duty cycle Md_U (maximum value D_max) is greater than the allowable upper limit D_UL and less than "1" (Yes in step S101).

[0100] The minimum duty cycle determination unit 31 determines that the difference between the maximum value D_max and the minimum value D_min is smaller than the difference between the allowable upper limit D_UL and the allowable lower limit D_LL (Yes in step S102). Processing proceeds to step S103.

[0101] Since the maximum value D_max is greater than the allowable upper limit D_UL, the PWM duty ratio setting unit 3 sets a value obtained by subtracting the allowable upper limit D_UL from the maximum value D_max to the shift amount D_Sh (step S103). Then, the PWM duty ratio setting unit 3A sets values ​​obtained by subtracting the shift amount D_Sh from each of the modulated U-phase duty ratio Md_U, the modulated V-phase duty ratio Md_V, and the modulated W-phase duty ratio Md_W, which are the current duty ratios, to the modulated U-phase duty ratio Md_U, the modulated V-phase duty ratio Md_V, and the modulated W-phase duty ratio Md_W, which are new duty ratios (step S104).Then, the PWM duty ratio setting unit 3A outputs to the pulse generation unit 4 the modulated U-phase duty ratio Md_U, the modulated V-phase duty ratio Md_V, and the modulated W-phase duty ratio Md_W, which are new duty ratios (step S105).

[0102] Between time m2 and time m3, the minimum duty ratio determination unit 31 determines that the maximum value D_max is greater than "1" (No in step S101). The PWM duty ratio setting unit 3A outputs the modulated U-phase duty ratio Md_U, the modulated V-phase duty ratio Md_V, and the modulated W-phase duty ratio Md_W, which are the current duty ratios, to the pulse generation unit 4 (step S105). When outputting the duty ratios of the phases, they can be output after setting the modulated U-phase duty ratio Md_U, which is the maximum value D_max, to "1."

[0103] As in Fig. As illustrated in FIG. 16, between time m3 and time m4, the minimum duty ratio determination unit 31 determines that the modulated W-phase duty ratio Md_W is the minimum value D_min. The minimum duty ratio determination unit 31 determines that the modulated U-phase duty ratio Md_U is the maximum value D_max. Then, the minimum duty ratio determination unit 31 determines that the minimum value D_min (= the modulated W-phase duty ratio Md_W) is less than the allowable lower limit D_LL and greater than "-1" (Yes in step S101).

[0104] The minimum duty cycle determination unit 31 determines that the difference between the maximum value D_max and the minimum value D_min is smaller than the difference between the allowable upper limit D_UL and the allowable lower limit D_LL (Yes in step S102). Processing proceeds to step S103.

[0105] Since the minimum value D_min is less than the allowable lower limit D_LL, the PWM duty setting unit 3A sets a value obtained by subtracting the allowable lower limit D_LL from the minimum value D_min to the shift amount D_Sh (step S103). Then, the PWM duty setting unit 3A sets the values ​​obtained by subtracting the shift amount D_Sh from each of the modulated U-phase duty ratios Md_U, the modulated V-phase duty ratio Md_V, and the modulated W-phase duty ratio Md_W, which are the current duty ratios, to the modulated U-phase duty ratio Md_U, the modulated V-phase duty ratio Md_V, and the modulated W-phase duty ratio Md_W, which are new duty ratios (step S104).Then, the PWM duty ratio setting unit 3 outputs to the pulse generation unit 4 the modulated U-phase duty ratio Md_U, the modulated V-phase duty ratio Md_V, and the modulated W-phase duty ratio Md_W, which are new duty ratios (step S105).

[0106] Between time m4 and time m5, the minimum duty ratio determination unit 31 determines that the minimum value D_min is less than "-1" (No in step S101). Then, the PWM duty ratio setting unit 3A outputs the modulated U-phase duty ratio Md_U, the modulated V-phase duty ratio Md_V, and the modulated W-phase duty ratio Md_W, which are the current duty ratios, to the pulse generation unit 4 (step S105). When outputting the duty ratios of the phases, they can be output after setting the modulated W-phase duty ratio Md_W, which is the minimum value D_min, to "-1."

[0107] The modulated U-phase duty cycle Md_U, the modulated V-phase duty cycle Md_V, and the modulated W-phase duty cycle Md_W have the same waveforms whose phases are shifted, and so the PWM duty cycle adjusting unit 3A can adjust the duty cycles according to the same method.

[0108] The PWM duty cycles of the phases are set as described above, and so the PWM duty cycles of the waveforms are set as shown in Fig. 17. The line voltages of the motor 200 when the inverter main circuit 51 is operated using the Fig. 17 is operated based on the PWM signals of the pulse generating unit 4, the Fig. 18 illustrated waveforms. Fig. Fig. 18 is a view illustrating the waveforms of the line voltages of the motor 200. Although in Fig. 18, an error in the waveforms caused by dead-time compensation partially occurs, the line voltages have essentially the same waveforms as before adjustment. Short circuits in the switching elements in the upper arm and the switching elements in the lower arm, as well as momentary on / off switching, are suppressed, so that a current surge can be suppressed. Consequently, the performance degradation of the motor 200 is suppressed, and it is possible to rotate the motor 200 stably for a long period of time. <dritte Variante>

[0109] A third variant of the motor system is described with reference to the figures. Fig. 19 is a flowchart illustrating a method for setting PWM duty cycles in the third variant. Fig. 20 is an enlarged view of the waveforms in the method of adjusting the PWM duty cycles using the Fig. 19. The flow chart shown in Fig. 19 illustrated flowchart branches from a state in which in step S101 of the Fig. 4, a determination of Yes is made.

[0110] It is believed that the Fig. 19, parallel to steps S102 to S104 or steps S102 and S106 in the flowchart shown in Fig. 4 shown flowchart. The Fig. The PWM duty cycles illustrated in Figure 20 show a case where the Fig. 16 illustrated PWM duty cycles according to the processing in the Fig. 19 shown flowchart. In Fig. 19, as in the second embodiment, the U-phase duty cycle Du_U, the V-phase duty cycle Du_V and the W-phase duty cycle Du_W may be replaced by the modulated U-phase duty cycle Md_U, the modulated V-phase duty cycle Md_V and the modulated W-phase duty cycle Md_W.

[0111] During processing in Fig. 19, the PWM duty setting unit 3A sets a value obtained by subtracting the maximum value D_max from "1" to a shift amount D_Sh2 when the maximum value D_max is greater than the allowable upper limit D_UL. When the minimum value D_min is less than the allowable lower limit D_LL, the PWM duty setting unit 3A sets a value obtained by subtracting the minimum value D_min from "-1" to the shift amount D_Sh2 (step S301).

[0112] Thereafter, the PWM duty ratio setting unit 3A adds the shift amount D_Sh2 to the U-phase duty ratio Du_U, the V-phase duty ratio Du_V, and the W-phase duty ratio Du_W, which are the current duty ratios, to generate a provisional U-phase duty ratio Du_U2, a provisional V-phase duty ratio Du_V2, and a provisional W-phase duty ratio Du_W2 (step S302).

[0113] Subsequently, the minimum duty ratio determination unit 31 determines whether at least one of the provisional U-phase duty ratios Du_U2, the provisional V-phase duty ratio Du_V2, and the provisional W-phase duty ratio Du_W2 is greater than the allowable upper limit D_UL and less than “1” or less than the allowable lower limit D_LL and greater than “-1” (step S303).

[0114] If at least one of the temporary U-phase duty ratio Du_U2, the temporary V-phase duty ratio Du_V2, and the temporary W-phase duty ratio Du_W2 satisfies the above-described condition in step S303 (Yes in step S303), the minimum duty ratio determination unit 31 determines that at least one of the temporary U-phase duty ratio Du_U2, the temporary V-phase duty ratio Du_V2, and the temporary W-phase duty ratio Du_W2 is outside the allowable range or is not “1” or “-1”.

[0115] Then, the PWM duty ratio setting unit 3A discards the preliminary U-phase duty ratio Du_U2, the preliminary V-phase duty ratio Du_V2 and the preliminary W-phase duty ratio Du_W2 calculated by the processing in steps S301 to S303, and outputs the U-phase duty ratio Du_U, the V-phase duty ratio Du_V and the W-phase duty ratio Du_W calculated in steps S102 to S104 or steps S102 and S106 in Fig. 4 were calculated (step S105).

[0116] When the preliminary U-phase duty ratio Du_U2, the preliminary V-phase duty ratio Du_V2, and the preliminary W-phase duty ratio Du_W2 do not satisfy the condition in step S303 (No in step S303), the minimum duty ratio determination unit 31 determines that the preliminary U-phase duty ratio Du_U2, the preliminary V-phase duty ratio Du_V2, and the preliminary W-phase duty ratio Du_W2 are within the allowable range or are “1” or “-1”.

[0117] Then, the PWM duty ratio setting unit 3A sets the provisional U-phase duty ratio Du_U2, the provisional V-phase duty ratio Du_V2, and the provisional W-phase duty ratio Du_W2 to the U-phase duty ratio Du_U, the V-phase duty ratio Du_V, and the W-phase duty ratio Du_W, which are new duty ratios (step S304), and outputs them to the pulse generation unit 4 (step S105). When the U-phase duty ratio Du_U, the V-phase duty ratio Du_V, and the W-phase duty ratio Du_W, which are new duty ratios, are generated in step S304, the U-phase duty ratio Du_U, the V-phase duty ratio Du_V, and the W-phase duty ratio Du_W generated in steps S102 to S104 or step S106 are discarded.

[0118] The PWM duty cycles are set as described above, and thus the maximum value D_max can be set to "1" or the minimum value D_min can be set to -1. In this way, switching loss is suppressed and short circuits in the switching elements in the upper arm and the switching elements in the lower arm, as well as momentary on / off switching, are suppressed, so that a current surge can be suppressed. Consequently, the lowering of the operation of the motor 200 is suppressed, and thus it is possible to rotate the motor 200 stably for a long period.

[0119] The Fig. The processing for setting the PWM duty cycles illustrated in Figure 19 is described using Fig. 20. As explained in Fig. 20 illustrates the PWM duty cycles between time m1 and time m5 are described.

[0120] Between time m1 and time m2, the minimum duty cycle determination unit 31 determines that the modulated U-phase duty cycle Md_U has the maximum value D_max. The minimum duty cycle determination unit 31 determines that the minimum value D_min corresponds to the modulated V-phase duty cycle Md_V. Then, the minimum duty cycle determination unit 31 determines that the modulated U-phase duty cycle Md_U (maximum value D_max) is greater than the allowable upper limit D_UL and less than "1" (Yes in step S101).

[0121] Since the maximum value D_max exceeds the allowable upper limit D_UL, the PWM duty setting unit 3A sets a value obtained by subtracting the maximum value D_max from "1" to the shift amount D_Sh2 (step S301). Then, the PWM duty setting unit 3A sets values ​​obtained by adding the shift amount D_Sh2 to each of the U-phase duty ratio Du_U, the V-phase duty ratio Du_V, and the W-phase duty ratio Du_W, which are the current duty ratios, to the provisional U-phase duty ratio Du_U2, the provisional V-phase duty ratio Du_V2, and the provisional W-phase duty ratio Du_W2 (step S302).

[0122] Then, the minimum duty ratio determination unit 31 determines that each of the temporary U-phase duty ratios Du_U2, the temporary V-phase duty ratios Du_V2, and the temporary W-phase duty ratios Du_W2 does not satisfy the condition where the duty ratio is greater than the allowable upper limit D_UL and less than “1” or the duty ratios are less than the allowable lower limit D_LL and greater than “-1” (No in step S303).

[0123] Then, in step S304, the PWM duty setting unit 3A sets the provisional U-phase duty ratio Du_U2, the provisional V-phase duty ratio Du_V2, and the provisional W-phase duty ratio Du_W2 to the U-phase duty ratio Du_U, the V-phase duty ratio Du_V, and the W-phase duty ratio Du_W (step S304) and outputs them to the pulse generation unit 4 (step S105).

[0124] Between time m2 and time m3, the minimum duty ratio determination unit 31 determines that the maximum value D_max is greater than "1" (No in step S101). The PWM duty ratio setting unit 3A outputs the modulated U-phase duty ratio Md_U, the modulated V-phase duty ratio Md_V, and the modulated W-phase duty ratio Md_W, which are the current duty ratios, to the pulse generation unit 4 (step S105). When outputting the duty ratios of the phases, they can be output after the modulated U-phase duty ratio Md_U, which is the maximum value D_max, is set to "1."

[0125] As in Fig. As illustrated in FIG. 20, between time m3 and time m4, the minimum duty ratio determination unit 31 determines that the modulated W-phase duty ratio Md_W is the minimum value D_min. The minimum duty ratio determination unit 31 determines that the modulated U-phase duty ratio Md_U is the maximum value D_max. Then, the minimum duty ratio determination unit 31 determines that the minimum value D_min (= the modulated W-phase duty ratio Md_W) is less than the allowable lower limit D_LL and greater than "-1" (Yes in step S101).

[0126] Since the minimum value D_min is below the allowable lower limit D_LL, the PWM duty setting unit 3 sets a value obtained by subtracting the minimum value D_min from "-1" to the shift amount D_Sh2 (step S301). Then, the PWM duty setting unit 3 sets values ​​obtained by adding the shift amount D_Sh2 to each of the U-phase duty ratio Du_U, the V-phase duty ratio Du_V, and the W-phase duty ratio Du_W, which are the current duty ratios, to the provisional U-phase duty ratio Du_U2, the provisional V-phase duty ratio Du_V2, and the provisional W-phase duty ratio Du_W2 (step S302).

[0127] Then, the minimum duty ratio determination unit 31 determines that each of the temporary U-phase duty ratios Du_U2, the temporary V-phase duty ratios Du_V2, and the temporary W-phase duty ratios Du_W2 does not satisfy the condition where the duty ratio is greater than the allowable upper limit D_UL and less than “1” or the duty ratios are less than the allowable lower limit D_LL and greater than “-1” (No in step S303).

[0128] Then, in step S304, the PWM duty setting unit 3A sets the provisional U-phase duty ratio Du_U2, the provisional V-phase duty ratio Du_V2, and the provisional W-phase duty ratio Du_W2 to the U-phase duty ratio Du_U, the V-phase duty ratio Du_V, and the W-phase duty ratio Du_W (step S304) and outputs them to the pulse generation unit 4 (step S105).

[0129] Between time m4 and time m5, the minimum duty ratio determination unit 31 determines that the minimum value D_min is less than "-1" (No in step S101). Therefore, the PWM duty ratio setting unit 3A outputs the U-phase duty ratio Du_U, the V-phase duty ratio Du_V, and the W-phase duty ratio Du_W, which are the current duty ratios, to the pulse generation unit 4 (step S105). When outputting the duty ratios of the phases, they can be output after setting the modulated W-phase duty ratio Md_W, which is the maximum value D_max, to "-1."

[0130] The modulated U-phase duty cycle Md_U, the modulated V-phase duty cycle Md_V, and the modulated W-phase duty cycle Md_W have the same waveforms whose phases are shifted, and so the PWM duty cycle adjusting unit 3A can adjust the duty cycles according to the same method.

[0131] The PWM duty cycles are set as described above, and thus the maximum value D_max can be set to "1" or the minimum value D_min can be set to -1. In this way, switching loss is suppressed and short circuits in the switching elements in the upper arm and the switching elements in the lower arm, as well as momentary on / off switching, are suppressed, so that a current surge can be suppressed. Consequently, the lowering of the operation of the motor 200 is suppressed, and thus it is possible to rotate the motor 200 stably for a long period of time.

[0132] Although the Fig. 19 parallel to the steps S102 to S104 and S106 in the flow chart shown in Fig. 4, the present disclosure is not limited to this configuration. For example, if in the flowchart shown in Fig. 19, a No is determined in step S303, the processing may be transferred to step S102. In this way, the processing in Fig. 19 so that parallel processing can be reduced. Steps S102 to S104 in Fig. 14 can be prioritized. In this case, an additional step is preferably provided to determine whether the Fig. 4 is appropriate. A determination may be made using a different criterion before and after step S102 to select the processing. <sonstige>

[0133] In the embodiments of the present disclosure, various changes can be made as needed without departing from the technical ideas within the scope of the claims. The various embodiments described above can be combined as needed as long as there are no contradictions. The embodiments described above are merely examples of the embodiment of the present disclosure, and the meanings of the terms in the present disclosure and the constituent elements are not limited to those described in the above embodiments.

[0134] Although the switching control device has been described in the above-described embodiments using the configurations in which the switching control device 300 is used to drive the brushless DC motor 200 as an example, the present disclosure is not limited to these configurations. The present disclosure can generally be used for controlling an inverter circuit with switching elements.

[0135] The switching control device (300) described above may include: a PWM duty ratio conversion unit (2) configured to convert voltage command signals of three phases (U, V, and W) into PWM duty ratios; a PWM duty ratio setting unit (3) configured to simultaneously set the PWM duty ratios of the three phases using the same setting value; a pulse generation unit (4) configured to generate pulse signals from the PWM duty ratios set by the PWM duty ratio setting unit (3); and an inverter circuit (6) configured to include a plurality of switching elements (501 to 506) controlled by the pulse signals generated by the pulse generation unit (4) (first configuration).

[0136] In the switching control device of the first configuration, the PWM duty setting unit (3) may set the setting value so that a line voltage has a sinusoidal wave fluctuating in a predetermined period (second configuration).

[0137] In the switching control device of the first or second configuration, when at least one of the PWM duty ratios exceeds an upper limit (D_UL) of an allowable range, the PWM duty ratio setting unit (3) may set a difference value between the maximum PWM duty ratio of the PWM duty ratios exceeding the upper limit (D_UL) and the upper limit (D_UL) of the allowable range to the setting value (third configuration).

[0138] In the switching control device of any of the first to third configurations, when at least one of the PWM duty ratios falls below a lower limit (D_LL) of an allowable range, the PWM duty ratio setting unit (3) may set a difference value between the minimum PWM duty ratio of the PWM duty ratios falling below the lower limit (D_LL) and the lower limit (D_LL) of the allowable range to the setting value (fourth configuration).

[0139] The switching control device of the first or second configuration further comprises: a voltage command calculation unit (1) configured to perform line modulation to set the voltage command signal of the maximum phase to the maximum value (Vd) of a supplyable voltage within a predetermined period. The PWM duty conversion unit (2) can generate a PWM duty such that the PWM duty is "1" when the voltage command signal is the maximum value (Vd) of the supplyable voltage, and when the PWM duty of a phase other than "1" exceeds an upper limit (D_UL) of an allowable range, the PWM duty setting unit (3) can set a difference value between the PWM duty exceeding the upper limit of the allowable range and "1" to the setting value (fifth configuration).

[0140] The switching control device of any of the first, second, and fifth configurations further comprises: a voltage command calculation unit (1) configured to perform line modulation to set the voltage command signal of the minimum phase to the minimum value (-Vd) of a supply voltage within a predetermined period. The PWM duty ratio conversion unit (2) may generate a PWM duty ratio such that the PWM duty ratio is "-1" when the voltage command signal is the minimum value (-Vd) of the supply voltage. When the PWM duty ratio of a phase other than "-1" falls below a lower limit (D_LL) of an allowable range, the PWM duty ratio conversion unit (3) may set a difference value between the PWM duty ratio falling below the lower limit (D_LL) of the allowable range and "-1" to the setting value (sixth configuration).

[0141] In the switching control device of any of the first to sixth configurations, the PWM duty ratio setting unit (3) can set only a PWM duty ratio of an adjustable phase in an adjustable range (seventh configuration).

[0142] The switching control device of any one of the first to fifth configurations may further comprise: a dead time compensation unit (32) configured to perform processing that compensates for a dead time for the PWM duty ratio before it is set by the PWM duty ratio setting unit (3) (eighth configuration).

[0143] In the switching control device of any of the first to eighth configurations, the inverter circuit (5) may include, for each of the three phases, a branch including a switching element (501 to 503) in an upper arm and a switching element (504 to 506) in a lower arm (ninth configuration).

[0144] The above-described engine system (100) may include: the shift control device (300) of the ninth configuration; and a motor (200) configured to be controlled by the shift control device (300) (tenth configuration). List of reference symbols 1 voltage command calculation unit 2 PWM duty cycle conversion unit 3.3A PWM duty cycle adjustment unit 4 Pulse generation unit 5 Inverter circuit 31 Minimum duty cycle determination unit 32 Dead time compensation unit 51 Inverter main circuit 52 switch driver circuit 100, 100A motor system 200 brushless DC motor 201 U-phase coil 202 V-phase coil 203 W phase coil 300 switching control device 501 to 506 free-running diode 511 to 516 switching element QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] PCT / JP2023 / 037163

[0001] JP 2022-199763

[0001] JP 2022-104708

[0004] < / sonstige>

Claims

[1] A switching control device comprising: a PWM duty cycle conversion unit configured to convert voltage command signals of three phases into PWM duty cycles; a PWM duty cycle setting unit configured to simultaneously set the PWM duty cycles of the three phases using the same setting value; a pulse generating unit configured to generate pulse signals from the PWM duty cycles set by the PWM duty cycle setting unit; and an inverter circuit configured to include a plurality of switching elements controlled by the pulse signals generated by the pulse generating unit. [2] The switching control device according to claim 1, wherein the PWM duty setting unit sets the setting value such that a line voltage has a sinusoidal wave fluctuating in a predetermined period. [3] The switching control device according to claim 1 or 2, wherein the PWM duty setting unit, when at least one of the PWM duty ratios exceeds an upper limit of an allowable range, sets a difference value between a maximum PWM duty ratio of the PWM duty ratios exceeding the upper limit and the upper limit of the allowable range to the setting value. [4] The switching control device according to any one of claims 1 to 3, wherein the PWM duty setting unit, when at least one of the PWM duty ratios falls below a lower limit of an allowable range, sets a difference value between a minimum PWM duty ratio of the PWM duty ratios falling below the lower limit and the lower limit of the allowable range to the setting value. [5] A shift control device according to claim 1 or 2, further comprising: a voltage command calculation unit configured to perform line modulation to set the voltage command signal of a maximum phase to a maximum value of a supplyable voltage within a predetermined period, wherein the PWM duty cycle conversion unit generates a PWM duty cycle such that the PWM duty cycle is “1” when the voltage command signal is the maximum value of the voltage that can be supplied, and When a PWM duty cycle of a phase other than "1" exceeds an upper limit of an allowable range, the PWM duty cycle setting unit sets to the setting value a difference value between the PWM duty cycle exceeding the upper limit of the allowable range and "1". [6] A shift control device according to any one of claims 1, 2 and 5, further comprising: a voltage command calculation unit configured to perform line modulation to set the voltage command signal of a minimum phase within a predetermined period to a minimum value of a voltage to be supplied, and wherein the PWM duty cycle conversion unit generates a PWM duty cycle such that the PWM duty cycle is “-1” when the voltage command signal is the minimum value of the voltage to be supplied, and When a PWM duty cycle of a phase other than "-1" falls below a lower limit of an allowable range, the PWM duty cycle setting unit sets to the setting value a difference value between the PWM duty cycle falling below the lower limit of the allowable range and "-1". [7] The switching control device according to any one of claims 1 to 6, wherein the PWM duty ratio setting unit sets only a PWM duty ratio of an adjustable phase in an adjustable range. [8] A shift control device according to any one of claims 1 to 7, further comprising: a dead time compensation unit configured to perform processing that compensates for a dead time for the PWM duty cycle before it is set by the PWM duty cycle setting unit. [9] The switching control device according to any one of claims 1 to 8, wherein the inverter circuit comprises, for each of the three phases, a branch including a switching element in an upper arm and a switching element in a lower arm. [10] Engine system comprising: the shift control device according to claim 9; and a motor which is adapted to be controlled by the switching control device.

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