DEVICE WITH A DIGITAL / ANALOGUE CONVERTER CIRCUIT

Abstract

A device 1 containing a digital-to-analog converter (DAC) circuit comprises at least: a processor 10P that outputs a DAC target value, a pre-stage circuit 10FNT that receives the DAC target value from the processor 10P, corrects the DAC target value according to correction data, and outputs the corrected DAC target value, a main circuit 10BDY that contains one or more correction target DAC elements and performs a DAC conversion on the corrected DAC target value, and an analog-to-digital converter 10AD. The correction target DAC element is a hybrid DAC element that outputs an analog value from an output terminal. This analog value is obtained by adding an analog value output by a circuit segment of the first type SEG1, which is responsible for a higher order, and an analog value output by a circuit segment of the second type SEG2, which is responsible for a lower order.Additionally, as a calibration test for creating or updating correction data, the Processor 10P acquires: (A) a plurality of test pairs, each of which is a pair consisting of a test input value and a test result value with the following properties: (A1) the test input value is a value that is input to the main circuit as a D / A conversion target value, with or without correction; (A2) the test result value is a value obtained by performing an A / D conversion by the A / D converter on an analog value output by inputting the test input value to the main circuit; and (B) updates the correction data based on the plurality of test pairs in (A). The number of test pairs acquired during a calibration test period is less than 2. N , and N is the number of bits that specify a resolution of the correction target DA converter element.

Description

Technical field

[0001] The present invention relates to a device with a digital / analog converter circuit (hereinafter also referred to as DA converter circuit or DA converter element), for example a device with a DA converter circuit that can achieve high accuracy. State of the art

[0002] A technique for providing a high-accuracy digital-to-analog converter (DAC) circuit is described, for example, in PTL 1. PTL 1 discloses a technique for improving the accuracy of a DAC circuit using an R-2R resistance DAC (digital-to-analog converter) element, an interpolation DAC element, and a sigma-delta modulator element. In PTL 1, a calibration process (corresponding to a calibration test in an embodiment to be described later) is performed to achieve high accuracy. List of citations from patent literature

[0003] PTL 1: JP 2022-003830 A Summary of the invention: Technical problem

[0004] As a result of studies by the present inventor, it was found that the technology disclosed in PTL 1 has at least one of the following improvements.

[0005] The conversion characteristics of a digital-to-analog converter (DAC) are expected to change due to dynamic temperature variations (ambient temperature) of a device containing a DAC element (hereinafter also referred to simply as the DAC). Therefore, repeated calibration testing is necessary, whereas the technique disclosed in PTL 1 allows for improvements in the calibration test time.

[0006] A destination device, to which an analog value output by the digital-to-analog converter (DAC) is delivered, includes a device that requires a high voltage or a high current. With such a device, it is difficult to deliver the DAC output to the destination device unchanged, and an amplifier circuit is generally connected between the DAC and the destination device. In the amplifier circuit, an input and output characteristic, represented, for example, by a gain factor, fluctuates due to, for example, a temperature change (ambient temperature), and thus varies over time. Consequently, the analog value delivered to the destination device also fluctuates over time. The technique described in PTL 1 offers room for improvement in this respect.

[0007] One objective of the invention is to provide a device that solves one or more of the problems.

[0008] Other objectives and new features of the invention will become apparent from the description in this document and the accompanying drawings. Solution to the problem

[0009] An overview of a representative embodiment disclosed in the present application is briefly described below.

[0010] That is, a device according to the embodiment comprises at least: a processor configured to output a D / A conversion target value; a pre-stage circuit configured to receive the D / A conversion target value from the processor, correct the D / A conversion target value according to correction data, and output the corrected D / A conversion target value; a main circuit containing one or more correction target D / A converter elements that performs D / A conversion on the corrected D / A conversion target value; and an analog-to-digital converter. The correction target D / A converter element is a hybrid D / A converter element that outputs an analog value from an output terminal. This analog value is obtained by adding an analog value output by a circuit segment of the first type, responsible for a higher order, and an analog value output by a circuit segment of the second type, responsible for a lower order.Additionally, as a calibration test for creating or updating correction data, the processor acquires: (A) a plurality of test pairs, each of which is a pair consisting of a test input value and a test result value with the following properties: (A1) the test input value is a value that is input to the main circuit as a D / A conversion target value, with or without correction; (A2) the test result value is a value obtained by performing an A / D conversion by the A / D converter on an analog value output by inputting the test input value to the main circuit; and (B) updates the correction data based on the plurality of test pairs in (A). The number of test pairs acquired during a calibration test period is less than 2. N , and N is the number of bits that specify a resolution of the correction target DA converter element.

[0011] A device according to another embodiment comprises at least one main circuit containing one or more digital-to-analog converter (DAC) elements configured to convert a main input bit sequence, which is a received bit sequence, into a main output analog value and output the main output analog value; a processor configured to output a processor output bit sequence; a preamplifier circuit configured to receive the processor output bit sequence and output the main input bit sequence; and an analog-to-digital converter (ADC). The preamplifier circuit corrects the processor output bit sequence based on correction data and outputs the main input bit sequence. The main circuit includes an amplifier circuit that amplifies an analog value output by the DAC element and outputs the amplified analog value as the main output analog value.The processor (A) acquires a plurality of pairs consisting of a test bit sequence and a test result bit sequence with the following properties: (A1) the test bit sequence is the processor output bit sequence or the main input bit sequence for a calibration test, (A2) the test result bit sequence is acquired by converting the main output analog value through the A / D converter, and (B) updates the correction data based on the plurality of pairs in (A). Advantageous effects of the invention

[0012] In order to briefly describe the effects achieved by the typical embodiments of the inventions disclosed in the present application, it is possible to provide a device that includes a high-precision DA converter circuit. Brief description of the drawings [ Fig. 1] Fig. Figure 1 shows a block diagram illustrating a configuration of a device with a DA converter according to embodiment 1. [ Fig. 2] Fig. Figure 2 shows a block diagram illustrating a configuration of the DA converter according to embodiment 1. [ Fig. 3] Fig. Figure 3 shows a circuit diagram illustrating the configuration of the DA converter according to embodiment 1. [ Fig. 4] Fig. Figure 4 shows a flowchart when the DA converter is operated according to embodiment 1. [ Fig. 5] Fig. Figure 5 shows a flowchart illustrating a calibration test according to embodiment 1. [ Fig. 6] Fig. Figure 6 shows a diagram illustrating the calibration test according to embodiment 1. [ Fig. 7] Fig. Figure 7 shows a diagram illustrating a correction amount according to embodiment 1. [ Fig. 8] Fig. Figure 8 shows a block diagram illustrating a configuration of a bit sequence correction circuit according to embodiment 1. [ Fig. 9] Fig. Figure 9 shows a block diagram illustrating a configuration of a DA converter according to embodiment 2. [ Fig. 10] Fig. Figure 10 shows a diagram illustrating a bit sequence correction circuit according to embodiment 2. [ Fig. 11] Fig. Figure 11 shows a block diagram illustrating a configuration of a charged particle beam device according to embodiment 4. [ Fig. 12] Fig. Figure 12 shows a diagram illustrating equations for the embodiment. [ Fig. 13] Fig. Figure 13 shows a block diagram illustrating a configuration of a DA converter according to a modification of embodiment 2. Description of the embodiments

[0013] Embodiments are described with reference to the drawings. The embodiments described below do not limit the invention to the scope of the claims, and it is not necessary that all elements and combinations described in the embodiments be essential for the solution of the invention. (Version 1)<Konfiguration der Vorrichtung>

[0014] Fig. Figure 1 shows a block diagram illustrating a configuration of a device according to embodiment 1. Fig. Reference numeral 1 denotes a device. The device 1 comprises a processor 10P, a pre-stage circuit 10FNT, a main circuit 10BDY and an analog-to-digital converter (hereinafter referred to as the ADC) 10AD.

[0015] In Fig. 1 denotes OBJ as a target device, and an analog value is output from device 1 to target device OBJ. Here, a case is described in which target device OBJ is located outside of device 1, and of course, target device OBJ can also be contained within device 1. Target device OBJ is a device that is operated by receiving an analog value from device 1. An example of target device OBJ is described later, and the invention is not limited to such an example. In a broader sense, target device OBJ can be considered a control target device whose operation is controlled by an analog value from device 1, and target device OBJ can be considered an amplifier circuit such as an operational amplifier.In this description, a value specified by an analogous method (specifying at least one value by means of a continuously changing (or allowing) physical quantity such as a voltage or current) is referred to as an analog value. The processing, such as the generation, output, input, transmission, and reception of an analog value of a physical entity (an element, circuit, or device), actually means at least the modification of a physical quantity that continuously changes (or can be changed), such as a current or voltage.

[0016] The following description details the Fig. The pre-stage circuit 10FNT and the main circuit 10BDY shown together are referred to as a DA converter circuit. < <prozessor>>

[0017] The 10P processor is a device that performs predetermined processing (control processing in Fig. 1) performs a process to generate and transmit a value (hereinafter referred to as the DA conversion target value) that is to be given to the target device OBJ as a digital value (bit sequence) after DA conversion via a circuit to be described later. In the following description, the bit sequence generated and transmitted by processor 10P as a result of the control processing is referred to as the processor output bit sequence and in Fig. 1 is shown as an example of LOBTP.

[0018] The processor 10P, for example, is a device that performs predetermined processing by executing a program, similar to a CPU or GPU. However, the processor 10P can be an FPGA or another IC, as long as the digital value (bit sequence) can be generated by performing the predetermined processing. The processor 10P can be part of a component 10C, such as a motherboard or controller, along with volatile memory VOLMEM or non-volatile memory NVMEM (a flash memory or HDD is an example), or it can be a computer. Furthermore, the device 1 itself can be a computer. A program (group) for implementing the test and control processing performed by the processor 10P is stored in the non-volatile memory NVMEM. <<Hauptschaltung und Vorstufenschaltung> >

[0019] The main circuit 10BDY is a circuit containing one or more digital-to-analog converters (DACs) 10DACs that convert a main input bit sequence 10BTB into a main output analog value 10ANG(A), which is an analog value, and output the main output analog value 10ANG(A). One can say that the value of the main input bit sequence 10BTB, which is output according to the processor output bit sequence 10BTP with the DAC target value, has a "corrected DAC target value".

[0020] The pre-stage circuit 10FNT is a circuit that receives the processor output bit sequence 10BTP and outputs the main input bit sequence 10BTB. The pre-stage circuit 10FNT includes a bit sequence correction circuit 10BCT, which corrects the processor output bit sequence 10BTP based on correction data (correction D in Fig. 1) corrects and outputs the main input bit sequence 10BTB. The correction data is stored in a memory (not shown) in a preamplifier circuit. The correction does not always need to be performed. For example, the correction is performed after a calibration test described later. < <ad-wandler>>

[0021] The 10AD analog-to-digital converter (ADC) is a component used in the calibration test described later. During the calibration test, the 10AD converts the main analog output value 10ANG into a bit sequence 10BTTR. For clarity, the bit sequence 10BTTR will be referred to as the test result bit sequence 10BTTR in the following description. The calibration test can simply be called the test in the following description. Of course, the 10AD can also be used for applications other than testing. <<Testobjekt und Korrekturzweck> >

[0022] The calibration test processing is performed by the processor 10P, and the calibration test is carried out to determine a conversion relationship (primarily a D / A conversion relationship) between an input and an output of the main circuit 10BDY due to a characteristic change (for example, an environmental factor such as temperature) of the main circuit 10BDY. Correction data to be used in the preamplifier circuit 10FNT is generated based on the result of the test processing. Although a characteristic change of interest in embodiment 1 is the D / A converter 10DAC(A), characteristic changes in other elements can also be considered. For example, a characteristic change in the amplifier circuit AMP, described later, can also be considered.

[0023] A typical purpose of correction, performed by capturing the conversion relationship, is to improve digital and analog linearity. A 3-bit sequence (an offset binary format or an uncoded binary format) is described as an example. If the current output for a bit sequence (1, 0, 0) represented in the order MSB, intermediate bit, LSB is 4 mA, then, in the case of a highly linear digital-to-analog converter, taking into account the significance of each bit, the analog value output for the bit sequence (0, 1, 0) would ideally be 2 mA, and the analog value output for the bit sequence (0, 0, 1) would ideally be 1 mA.

[0024] However, if the characteristic change in the circuit responsible for the intermediate bit in the DAC is significant, and 3 mA is output only for the bit sequence (0, 1, 0) while other outputs remain unchanged, the linearity described above decreases. The correction performed by the 10FNT preamplifier circuit improves this reduced linearity by actually modifying the bit sequence input to the 10DAC DAC. A target line for this improvement is not necessarily a straight line connecting the analog values ​​of the bit sequence (1, 0, 0) and the analog values ​​of the bit sequence (0, 0, 1). It could be a straight line interpolation using the analog values ​​of the other two bit sequences, or a straight line obtained through regression analysis.

[0025] In embodiment 1, during the calibration test, the processor 10P acquires a plurality of pairs (hereinafter also referred to as test pairs) consisting of a test bit sequence (sometimes abstracted and referred to as the test input value) and a test result bit sequence (sometimes abstracted and referred to as the test result value) with the following properties (A1) and (A2): (A1) The test bit sequence is the processor output bit sequence or the main input bit sequence for a calibration test. It should be noted that the test bit sequence can also be viewed from another perspective as a value that is input into the main circuit, with or without correction, as the DA conversion target value. (A2) The test result bit sequence is acquired by converting the main output analog value through the ADC. From another perspective, the test result bit sequence can be viewed as a value obtained by the ADC, which performs an A / D conversion on an analog signal output by inputting the test input value into the main circuit.

[0026] Here, the conversion relationship described above between the digital value (bit sequence) and the analog value of the DA converter 10DAC(A) is obtained by collecting the multitude of test pairs or processing the collection.

[0027] Although a variety of embodiments are described below, in each embodiment, to reduce test processing time, an internal structure of the DA converter 10DAC(A) is taken into account, thereby reducing the number of pairs associated with the test described above. More precisely, as in Fig. As shown in Figure 1, the DA converter 10DAC(A) reduces the number of test pairs taking into account the structure of the DA converter (hereinafter also referred to as hybrid DA converter), which generates an analog value as a converter by adding an analog value output by a circuit segment of the first type SEG1 and an analog value output by a circuit segment of the second type SEG2.

[0028] In the case of a hybrid digital-to-analog converter (DAC) that supports high-precision multi-bit input while reducing the DAC's circuit size, a high-precision circuit segment (typically responsible for the MSB and bits (group) up to a predetermined number lower than the MSB) and a low-circuit-size circuit segment (typically responsible for the LSB and bits (group) up to a predetermined number higher than the LSB) are used together. Examples of such segments (first-type circuit segment SEG1 and second-type circuit segment SEG2) include a thermometer-type, suitable for high-precision applications, and a weighted binary (ladder)-type, suitable for low-circuit-size applications.As an example of a 3-bit hybrid D / A converter (offset binary or uncoded binary), a high-precision circuit segment (hereinafter referred to as the high-precision circuit segment) is responsible for the MSB, and a low-gain circuit segment (hereinafter referred to as the low-gain circuit segment) is responsible for the LSB and an intermediate bit. The above example is not intended to limit the technique described here to a D / A converter that processes an input in offset binary or uncoded binary. The technique described here can also be applied to other binary formats (for example, two's complement binary).

[0029] In the low-scale circuit segment, a common element is often used to output an analog value of one bit sequence and an analog value of another bit sequence. For example, in the case of 3-bit, a common element is used in both the bit sequence (x, 0, 1) and the bit sequence (x, 1, 1). Since the MSB is assumed to be responsible for a high-density segment, it is omitted by x.

[0030] In each of the following embodiments, the "other test pair" is omitted by exploiting the fact that the test result bit sequence of the other test pair can be favorably estimated by acquiring one or more test pairs based on a relationship between each of the bits in the bit sequence and the element used in the circuit segment. Consequently, the number of test pairs in a calibration test is less than the "number of bits in the test bit sequence" squared. From another perspective, the number of test pairs acquired during the calibration test period can be said to be less than 2 N is (N is the number of bits that specify the resolution of the correction target DA converter element), which is a result. <<Optionen der Hauptschaltung> >

[0031] The main circuit 10BDY according to embodiment 1 can include the following options. <<<Verstärkerschaltung AMP> >>

[0032] The amplifier circuit AMP amplifies the output of the digital-to-analog converter 10DAC(A) when the output (output current or output voltage) of the DAC 10DAC(A) is insufficient for the operation of the target device OBJ. An example of the amplifier circuit AMP is an operational amplifier, an amplifier circuit using an operational amplifier, or an amplifier circuit using a transistor (including a FET). The amplifier circuit AMP may use a circuit element (for example, a resistor) that can be affected by an operating environment (for example, temperature). To correct for such fluctuations in the amplifier circuit, the output of the amplifier circuit AMP, 10ANG(B), can be used as a conversion target for the analog-to-digital converter 10AD instead of the main output analog circuit 10ANG(A).When the 10DAC(A) digital-to-analog converter (DAC) converts the current value to an analog value and outputs the current value, the AMP amplifier circuit can amplify either the current value or the voltage value. Similarly, when the 10DAC(A) digital-to-analog converter converts the voltage value to an analog value and outputs the analog value, the AMP amplifier circuit can amplify either the voltage value or the current value. <<<Dämpfungsglied> >>

[0033] The output of the DA converter 10DAC(A) or the output of the amplifier circuit AMP can be fed into the ADC 10AD via an attenuator (not shown). Since the attenuator limits the voltage or current input to the ADC 10AD, it prevents damage to the ADC 10AD from excessive voltage or current. Even if the components of the attenuator are affected by the operating environment, the resulting fluctuations can be corrected. <<<DA-Wandler DAC(B)> >>

[0034] The main circuit 10BDY can include an additional digital-to-analog converter (DAC) 10DAC(B). The DAC 10DAC(B) is used, for example, to convert the number of bits exceeding the number of bits that can be input to the DAC 10DAC(A) into an analog value. Components required to add the DAC 10DAC(B) include a divider circuit 10SPT and a weighted addition circuit 10ADDW. Each role is described later. The DAC 10DAC(B) need not be a hybrid DAC, nor need it be a correction target for calibration testing. Conversely, the DAC 10DAC(B) can be a hybrid DAC or a correction target for calibration testing. <<<Schalter 10SW> >>

[0035] A switch 10SW toggles whether the output of the DA converter 10DAC(A) is supplied to a target device side OBJ or an AD converter side 10AD. Fig. 1. The state of switch 10SW during a test described later is indicated by a solid line. In this state, the output of the DA converter 10DAC(A) is supplied to the AD converter 10AD. Switch 10SW is used when the main analog output value 10ANG is not preferred for the target device OBJ during the test described later.

[0036] The preamplifier circuit 10FNT may include optional components described in the main circuit 10BDY instead of the main circuit 10BDY. For example, the preamplifier circuit 10FNT may include a divider circuit 10SPT(B) instead of a divider circuit 10SPT(A), which is an option in the main circuit 10BDY. Such an example occurs when the correction, which is a role of at least one part of the preamplifier circuit 10FNT, is improved by closer cooperation with the DA converter circuit.

[0037] The addition function is not limited to the 10DAC(A) digital-to-analog converter, and a component such as an operational amplifier is not necessarily required. For example, in the case of adding current values, lines from two current sources can be combined into one, and in the case of adding voltage values, two voltage sources can be directly connected. In the following description, such a structure for addition can be referred to as an "addition circuit." That is, the addition circuit can be just a wiring diagram. Furthermore, the "circuit" can simply be a wiring diagram that contains no other component.

[0038] The connection between the "wiring"—the processor 10P, the pre-stage circuit 10FNT, the main circuit 10BDY, and the A / D converter 10AD—can be wiring formed on a substrate, a cable such as a coaxial cable, an optical cable, or a communication cable, an in-chip wiring pattern in an IC, or wiring defined virtually in an FPGA. For example, a communication cable (such as a network communication cable) can be used as part or all of the connection between the processor 10P and the pre-stage circuit 10FNT. Therefore, the processor output bit sequence 10BTP can be transmitted in parallel through a variety of wiring connections or in a serialized manner, as in a general communication protocol.The connection between the processor 10P, the preamplifier circuit 10FNT, the main circuit 10BDY, and the analog-to-digital converter 10AD need not be directly connected by wiring alone and may include several components. Examples of these components include a photodiode for optical communication, a communication chip for communication using a network communication protocol (such as USB, PCI, or Ethernet), a timing circuit, a hold circuit, and a bandpass filter circuit, which are generally used in digital and analog circuits.When the output, input, transmission, and reception of a bit sequence are described in the present description, it is only necessary to output, input, transmit, and receive a bit sequence as a result, and it is not necessary to perform a transmission while maintaining a "column" as in serial communication.

[0039] The components that make up device 1 do not necessarily have to be integrated into a housing, a fixture, or a substrate. In other words, each of the components can be implemented by a separate housing, a separate fixture, or a separate substrate. <Konfigurationsbeispiel des DA-Wandlers 10DAC(A)>

[0040] Fig. Figure 2 shows a block diagram illustrating a configuration of a digital-to-analog converter according to embodiment 1. As shown in Fig. 2 shown, contains the Fig. Figure 1 shows a DA converter 10DAC(A) comprising a main DA converter M_DAC, a sub-DA converter S_DAC, a weighted addition circuit MS_ADDW, hold circuits M_HL and S_HL, and the divider circuit 10SPT(B). An example is described here in which the divider circuit 10SPT(B) is included in the main circuit 10BDY of the DA converter 10DAC(A), and the divider circuit 10SPT(B) can also be included in the preamplifier circuit 10FNT, as shown in Figure 1. Fig. Figure 1 shows that a digital-to-analog converter (DAC) processing an input in an offset binary format or an uncoded binary format is used as an example in the following description. However, the technique described here can also be applied to a two's complement binary format (for example, a decoder circuit performing binary format conversion can be included in the DAC 10DAC(A)).

[0041] Fig. Figure 2 shows a case where the number of bits in the processor output bit sequence (input bit sequence) 10BTP, supplied by the processor 10P to the pre-stage circuit 10FNT and the main circuit 10BDY, is N. The input bit sequence 10BTP of N bits is divided by the divider circuit 10SPT(B) into an upper input bit sequence Inp_U and a lower input bit sequence Inp_L. Here, describing the relationship between the input bit sequence 10BTP and the upper input bit sequence Inp_U and the lower input bit sequence Inp_L, the number of bits K of the upper input bit sequence Inp_U + the number of bits M of the lower input bit sequence Inp_L = the number of bits N of the input bit sequence 10BTP. Furthermore, in the input bit sequence 10BTP M-1 bits from a lowest bit LSB are extracted as the lower input bit sequence Inp_L by the divider circuit 10SPT(B).Furthermore, in the input bit sequence 10BTP, K bits from the M bits up to a topmost bit MSB are extracted as the upper input bit sequence Inp_U by the divider circuit 10SPT(B).

[0042] The upper input bit sequence Inp_U is held in the holding circuit M_HL according to the main DAC M_DAC and supplied to its input. The lower input bit sequence Inp_L is held in the holding circuit S_HL according to the sub-DAC S_DAC and supplied to its input. The upper input bit sequence Inp_U is converted into a corresponding analog value by the main DAC M_DAC, and the lower input bit sequence Inp_L is converted into a corresponding analog value by the sub-DAC S_DAC. The analog value received by the main DAC M_DAC and the analog value received by the sub-DAC S_DAC are added by the addition circuit MS_ADDW and output as the analog value 10ANG(A) corresponding to the input bit sequence 10BTP.

[0043] Since the upper input bit sequence Inp_U is formed from bits on a topmost bit side of the MSB, the analog value output by the main DAC M-DAC changes significantly (grossly) when the bits forming the upper input bit sequence Inp_U change. Conversely, since the lower input bit sequence Inp_L is formed from bits on a lowest bit side of the LSB, the analog value output by the sub-DAC S_DAC changes slightly (finely) when the bits forming the lower input bit sequence Inp_L change. <<Konfigurationen der DA-Wandler M_DAC und S_DAC und der Additionsschaltung MS_ADDW> >

[0044] Next, a specific example of the main DAC M_DAC, the sub-DAC S_DAC, and the addition circuit MS_ADDW, which are in Fig. 2 are shown, described. Fig. Figure 3 shows a circuit diagram illustrating the configuration of the DA converter according to embodiment 1.

[0045] In embodiment 1, the main DAC M_DAC is implemented by a thermometer DAC (hereinafter referred to as M_DAC), and the sub-DAC S_DAC is implemented by a weighted binary DAC (hereinafter referred to as S_DAC). The thermometer DAC M_DAC corresponds to the one in Fig. The circuit segment shown is of the first type SEG1, and the weighted binary DAC S_DAC corresponds to the circuit segment of the second type SEG2. Therefore, the DAC 10DAC(A) is a segment DAC in which the thermometer DAC (circuit segment of the first type) M_DAC and the weighted binary DAC (circuit segment of the second type) S_DAC are combined.

[0046] The input bit sequence from the divider circuit 10SPT(B) is supplied to control circuits (hereinafter also referred to as decoders) M_DEC and S_DEC. That is, the upper input bit sequence Inp_U from the divider circuit 10SPT(B) is supplied to decoder M_DEC. Decoder M_DEC outputs a number of complementary signals Ul+ and UI- according to the code of the supplied upper input bit sequence Inp_U. Specifically, the UI+ signal is set to a high level by the number corresponding to the number represented by the code of the upper input bit sequence Inp_U, and the remaining UI+ signal is set to a low level. The Ul- signal is in a complementary (inverting) relationship to the paired UI+ signal and is at a low level when the paired Ul+ signal is at a high level.

[0047] The lower input bit sequence Inp_L from the divider circuit 10SPT(B) is supplied to the decoder S_DEC. The decoder S_DEC outputs complementary signals UB_0+, UB_0- to UB_M-1+, UB_M-1- according to the code of the supplied lower input bit sequence Inp_L. The complementary signals UB_0+, UB_0- to UB_M-1+ and UB_M-1- correspond to bits 0 (lowest bit LSB) to M-1, which form the lower input bit sequence Inp_L. For example, if bit 0 has a logical value "1", the signal UB_0+ is at the high level (UB_0- is at the low level), and if bit 0 has a logical value "0", the signal UB_0+ is at the low level (UB_0- is at the high level). Similarly, the remaining complementary signals UB_1+, UB_1- to UB_M-1+ and UB_M-1- are set to a high level or a low level according to the logical value of the corresponding bit in the lower input bit sequence Inp_L. <<<Gewichteter Binär-DA-Wandler> >>

[0048] The weighted binary DAC S_DAC contains a number of binary unit circuits (binary circuits, circuits of the second type) UB_0 to UB_M-1 corresponding to the number M of bit sequences that form the lower input bit sequence Inp_L. The binary unit circuit UB_0 corresponds to the lowest bit (LSB) of the lower input bit sequence Inp_L, and the binary unit circuits UB_1 to UB_M-1 correspond to bits 1 to M-1 in the lower input bit sequence Inp_L.

[0049] Each of the binary unit circuits UB_0 to UB_M-1 has a similar configuration. As an example, binary unit circuit UB_0, corresponding to the lowest bit (LSB), contains transistors Q2 and Q3, whose drains are connected to the output lines Lo+ and Lo-, and transistor Q4, which is connected between a common source of transistors Q2 and Q3 and the ground line Ls. Transistors Q2 and Q3 are switched on and off by corresponding signals UB_0+ and UB_0- from the decoder S_DEC. A reference voltage Vref is supplied to a gate of transistor Q4. Transistor Q4 acts as a constant current source, generating a predetermined constant current 2011sb when the reference voltage Vref is supplied. For example, a parameter or similar setting of transistor Q4 in binary unit circuit UB_0 is configured to generate a constant current corresponding to the lowest bit (LSB).Therefore, for example, when the signal UB_0+ is at the high level, transistor Q2 is switched on, and the predetermined constant current 20llsb flows from the output line Lo+ to a ground line Ls via transistor Q2.

[0050] The binary unit circuits UB_1 to UB_M-1 differ from the binary unit circuit UB_0 in that the value of transistor Q4 is set such that a value of the constant current to be generated corresponds to bit 1 to bit M-1 of the lower input bit sequence Inp_L. For example, transistor Q4 of the binary unit circuit UB_M-1 is set such that a constant current 2 (M-1)llSb The signal flows according to bit M-1 of the lower input bit sequence Inp_L.

[0051] Accordingly, in the weighted binary D / A converter S_DAC, the constant current corresponding to the bit flows from the output line Lo+ to the ground line Ls via the binary unit circuit that corresponds to the bit with the logical value "1" in the lower input bit sequence Inp_L. As a result, the lower input bit sequence Inp_L is converted into a corresponding current value. << <thermometer-da-wandler>>>

[0052] The thermometer-to-digital converter M_DAC contains the number of thermo-unit circuits (thermometer circuits, circuits of the first type) Ul according to the number of bits K of the upper input bit sequence Inp_U. That is, the thermometer-to-digital converter M_DAC contains the thermo-unit circuits Ul whose number is 2 to the power of K (2 K ) with the number of bits K as the exponent. The thermoelectric unit circuits UI are connected in parallel between the output lines Lo+ and Lo- and the ground line Ls.

[0053] These thermo unit circuits have the same UI configuration. As in Fig. As shown in Figure 3, each of the thermo unit circuits Ul contains a transistor Q1, to which the reference voltage Vref is supplied, and transistors Q2 and Q3, which operate complementarily to each other.

[0054] Transistor Q1 acts as a constant current source, generating a predetermined constant current when the reference voltage Vref is applied to the gate. The value of the generated constant current is a current 2. M*llsb , which corresponds to the lowest bit M in the upper input bit sequence Inp_U.

[0055] In the thermometer-based digital-to-analog converter (DAC), because transistors Q2 are switched on in the number of thermo-unit circuits Ul represented by the code of the upper input bit sequence Inp_U, a current flows from the output line Lo+ to the ground line Ls according to the number represented by the upper input bit sequence Inp_U. Consequently, the upper input bit sequence Inp_U is also converted into a corresponding current value.

[0056] As in Fig. As shown in Figure 3, the output lines Lo+ and Lo- are connected to a voltage Vd via a load resistor RL. This means that the load resistor RL is common to both the thermometer DAC M_DAC and the binary DAC S_DAC. Accordingly, the output of the thermometer DAC M_DAC and the output of the binary DAC S_DAC are added together. That is, the outputs shown in Figure 3 are... Fig. 1 and Fig. The addition circuit MS_ADDW shown in Figure 2 is implemented by the common output lines Lo+ and Lo- and the load resistor RL. <<<Entsprechung zur Eingabe in verschiedenen Binärformaten> >>

[0057] The hybrid DAC 10DAC(A), which accepts offset binary or uncoded binary format, is described above. When processing two's complement binary input, a decoder circuit for converting the two's complement binary input to offset binary can be placed between the divider circuit 10SPT(B) and an input terminal within the converter. Other implementation examples are also conceivable. For example, the divider circuit 10SPT(B) can receive a bit sequence in two's complement binary format and divide the bit sequence into the upper input bit sequence Inp_U and the lower input bit sequence Inp_L, also in two's complement binary format, and output the bit sequences. In this case, the decoder of each segment processes the two's complement binary format.With regard to the above implementation example, the divider circuit can be viewed as a circuit that outputs an internal upper bit sequence of K bits and an internal lower bit sequence of M bits based on the input value from the input terminal and the binary format assumed by the element. <Kalibrierungstest des DA-Wandlers>

[0058] As described above, linearity (INL) is known as the accuracy of the digital-to-analog converter. The linearity of the in Fig. The accuracy of the DA converter 10DAC(A) shown in Figure 1 fluctuates, for example, depending on changes in ambient temperature. In embodiment 1, to improve the accuracy of the DA converter 10DAC(A), the calibration test is performed by the DA converter 10DAC(A) before any actual conversion process takes place, and the input bit sequence of the DA converter 10DAC(A) is modified by the parameters shown in Figure 1. Fig. 1 Preamplifier circuit 10FNT shown corrected based on a correction amount obtained through the calibration test.

[0059] Fig. Figure 4 shows a flowchart when the DA converter 10DAC(A) is operated according to embodiment 1. In step S0, the DA converter 10DAC(A) starts operating. Then the processor 10P ( Fig. 1) During a calibration period CAL, the processor 10P executes steps S0 to S3 to perform the calibration test of the digital-to-analog converter 10DAC(A). In step S1, the processor 10P reads a test bit sequence from test data, inputs this test bit sequence into the digital-to-analog converter 10DAC(A), and measures an output of the converter. In step S2, the processor 10P generates a correction value using the output of the digital-to-analog converter 10DAC(A) measured in step S1 and the test bit sequence. Then, in step S3, the processor 10P determines whether the measurement and generation of the correction value are complete for all test bit sequences. If step S3 determines that the processing is not complete for all test bit sequences, the processor 10P returns to step S1. Thus, during the calibration period CAL, the processor 10P repeatedly executes steps S1 to S3.

[0060] After completion of the calibration test, the DA converter 10DAC(A) performs an actual DA conversion process in step S4.

[0061] To reduce the fluctuation in the accuracy of the digital-to-analog converter (DAC) circuit due to ambient temperature changes and to improve accuracy, it is conceivable to increase the frequency of calibration tests. However, if the calibration period (CAL) is long, the frequency of the actual DAC operation decreases. If the calibration period (CAL) is long, it is conceivable to divide it into multiple periods and perform the calibration test in a distributed manner, but in this case, the time until the correction is finally completed is delayed, and the accuracy decreases until the correction is finished.

[0062] The test bit sequence has the same number of bits as the actual input bit sequence 10BTP fed into the DA converter 10DAC(A), and in general, the test bit sequences corresponding to all combinations of codes of the input bit sequence 10BTP are prepared as test data. That is, as described above, in the case of the input bit sequence 10BTP with the number of bits N (the number of bits of the upper input bit sequence: K bits + the number of bits of the lower input bit sequence: M bits) 2 to the power of N (2 N Test bit sequences with the number of bits N as the exponent were prepared as test data. To increase the resolution of the 10DAC(A) digital-to-analog converter, it is necessary to increase the number of bits in the input bit sequence, which causes a problem in that the calibration period CAL becomes long. <testdaten>

[0063] In embodiment 1, to shorten the calibration period CAL, a test bit sequence is used that takes into account the structure of the DA converter 10DAC(A). Here, as with reference to Fig. 2 and Fig. 3 describes a case in which the DA converter 10DAC(A) is implemented by the thermometer DA converter M_DAC and the weighted binary DA converter S_DAC, as an example. <<Test-Bitfolge des gewichteten Binär-DA-Wandlers> >

[0064] The relationship between the lower input bit sequence Inp_L, which is in the Fig. The 3-shown weighted binary DAC S_DAC is input, and the output of the DAC is determined by formula (1) in Fig. Figure 12 is shown. In formula (1), D0 to DM-1 represent a bit that forms the lower input bit sequence Inp_L. That is, bit D0 corresponds to the lowest bit (LSB) of the lower input bit sequence Inp_L, and bit DM-1 corresponds to the highest bit of the lower input bit sequence Inp_L. The in Fig. The decoder S_DEC shown here outputs the signals UB_0+ and UB_0- according to a logical value of bit D0. For example, if the logical value of bit D0 is "1", decoder S_DEC outputs a high-level signal UB_0+. D1 to DM-1 are equal to bit D0, and decoder S_DEC sets the corresponding signals UB_1+ to UB_M-1+ to a high level if the logical value of bit D0 is "1".

[0065] Furthermore, in formula (1), WO to WM-1 specify a value of the constant current generated by the constant current source (transistor Q4) in the binary unit circuits UB_0 to UB_M-1. For example, the current value W0 specifies the value of the constant current generated by transistor Q4 of the binary unit circuit UB_0.

[0066] As can be seen from formula (1), a current value S_DA output by the weighted binary D / A converter S_DAC is a constant current value when the desired bit has a logical value "1", by setting the desired bit to the logical value "1" and setting all other bits to the logical value "0" in the lower input bit sequence Inp_L. This indicates that, for example, if the logical value of bit D0 is set to "1" and all logical values ​​of bits D1 to DM-1 are set to "0", the value of the constant current corresponding to bit D0 can be measured as the current value S_DA output by the weighted binary D / A converter S_DAC.

[0067] If a large number of bits in the lower input bit sequence Inp_L have the logical value "1", the value of the constant current output by the DAC S_DAC can be calculated by combining (adding) the previously measured current value S_DA with the bit containing the logical value "1". For example, if in the lower input bit sequence Inp_L both bit D0 and bit D1 have the logical value "1" and all remaining bits have the logical value "0", the current value S_DA output by the weighted binary DAC S_DAC can be calculated by adding the previously measured current value S_DA for bit D0 and the previously measured current value S_DA for bit D1.

[0068] This means that if the output of the weighted binary DAC is measured when only one bit has the logical value “1” in the lower input bit sequence Inp_L, the output of the weighted binary DAC can also be calculated using the measured value when a large number of bits simultaneously have the logical value “1” in the lower input bit sequence Inp_L.

[0069] Taking into account the structure of the weighted binary DAC, in the weighted binary DAC according to embodiment 1, M bit sequences are used as a test bit sequence corresponding to the lower input bit sequence Inp_L, in which one of the bits D0 to DM-1 has the logical value “1” and all other bits have the logical value “0”.

[0070] The weighted binary DAC S_DAC can have a DC offset DC_Offset. Therefore, in embodiment 1, a test bit sequence is also used in which all logical values ​​from D0 to DM-1 are set to "0". Therefore, the number of test bit sequences for the weighted binary DAC S_DAC according to embodiment 1 is M+1. <<Test-Bitfolge des Thermometer-DA-Wandlers> >

[0071] In the thermometer DA converter M_DAC, the constant currents of the number of thermo unit circuits UI, corresponding to the number represented by the code of the input bit sequence, are added to obtain the current value output by the thermometer DA converter M_DAC.

[0072] In embodiment 1, the same bit sequence as all codes that can be entered into the thermometer-DA converter M_DAC is defined as the test bit sequence. That is, the number of test bit sequences for the thermometer-DA converter M_DAC is 2 to the power of K (2 K ) with the number of bits K of the upper input bit sequence Inp_U as the exponent.

[0073] As a result, during the calibration period CAL, the number of devices connected to the DA converter 10DAC(A) ( Fig. 2) the sum (M + 1 + 2) of the test bit sequences supplied according to embodiment 1 K ) the number M+1 of test bit sequences for the weighted binary DAC S_DAC and the number 2 K of test bit sequences for the thermometer DA converter M_DAC and can be compared to the number (2 N The number of test bit sequences corresponding to all codes represented by the input bit sequence is reduced. For example, if the number of bits K of the upper input bit sequence Inp_U is 7, the number of bits M of the lower input bit sequence Inp_L is 7, and the number of bits N (= K + M) of the input bit sequence 10BTP is 14 (in the case of N bit resolution), then the number of test bit sequences corresponding to all codes is 2 14 = 16384. On the other hand, according to embodiment 1, the number of test bit sequences is 7 + 1 + 2 7 = 136. This means that during the calibration period CAL, the number of deliveries of the test bit sequence to the DA converter 10DCA (A) and the measurement of its output can be significantly reduced to 136.

[0074] The test data for the thermometer DAC M_DAC and the test data for the weighted binary DAC S_DAC, determined as described above, are stored in non-volatile memory NVMEM or volatile memory VOLMEM, which are located in Fig. The images shown in 1 are saved before the calibration test is performed. <Betrieb des Kalibrierungstests>

[0075] Fig. Figure 5 shows a flowchart illustrating the calibration test according to embodiment 1. Fig. Figure 6 shows a diagram illustrating the calibration test according to embodiment 1. The operation of the calibration test is described below with reference to Fig. 1, Fig. 2, Fig. 5 and Fig. 6 described.

[0076] In Fig. In step 5, processor 10P starts a calibration test in step SC0. An example is described here in which the calibration test of the thermometer DAC (hereinafter also referred to simply as DAC M_DAC) is performed before the weighted binary DAC (hereinafter also referred to simply as DAC S_DAC), and the invention is not limited thereto. That is, the DAC S_DAC can be subjected to the calibration test first.

[0077] In step SC1, processor 10P reads the test bit sequence from the test data stored in non-volatile memory NVMEM or volatile memory VOLMEM and inputs the test bit sequence as the upper input bit sequence Inp_U into the DAC M_DAC, which forms the DAC 10DAC(A) via the preamplifier circuit 10FNT. At this point, processor 10P inputs a bit sequence in which all logical values ​​are "0" (lower input bit sequence of a predetermined value) as the lower input bit sequence Inp_L into the DAC S_DAC, which forms the DAC 10DAC(A). Processor 10P controls the switch 10SW ( Fig. 1) such that the output of the DA converter 10DAC(A) is supplied to the AD converter 10AD.

[0078] Accordingly, the analog value corresponding to the test bit sequence converted by the DA converter M_DAC is supplied to the AD converter 10AD, converted by the AD converter 10AD into a digital sequence corresponding to the supplied analog value, and sent to the processor 10P as the test result bit sequence 10BTTR ( Fig. 1) delivered.

[0079] In step SC2, the processor 10P compares the test bit sequence delivered to the DAC M_DAC in step SC1 with the delivered test result bit sequence and generates input and output characteristics of the DAC M_DAC based on the test bit sequence. Based on the generated input and output characteristics, the processor 10P generates a correction amount so that the test result bit sequence matches the test bit sequence and stores the correction amount in the memory of the preamplifier circuit 10FNT as correction data (correction D in Fig. 1) At this point, the processor 10P stores the generated correction amount in such a way that it is paired with the supplied test bit sequence.

[0080] Next, in step SC3, processor 10P determines whether the test of the digital-to-analog converter M_DAC is complete using all test bit sequences. This is achieved, for example, by processor 10P determining whether all parts of the test data to be delivered to the digital-to-analog converter M_DAC are read from the non-volatile memory NVMEM or the volatile memory VOLMEMTHM. If processor 10P determines that the test is not complete using all test bit sequences, it returns to step SC1, reads the unread test bit sequence, and repeats steps SC1 through SC3.

[0081] An output voltage range represented by the input bit sequence Input entered into the DA converter 10DAC(A) is subdivided into a plurality of blocks 1 to 128 by the code of the upper input bit sequence Inp_U entered into the DA converter M_DAC, as shown in the table on the left side of Fig. Figure 6 shows that the code of the upper input bit sequence Inp_U specifies a unique base voltage value for each block, and the code of the lower input bit sequence Inp_L specifies a common voltage value for each block. For example, if the upper input bit sequence Inp_U has a logical value of "0x8000", block 1 is identified, and the upper input bit sequence Inp_U specifies a base voltage VB1B for block 1. Similarly, if the upper input bit sequence Inp_U has a logical value of "0x0000", block 65 is identified, and the upper input bit sequence Inp_U specifies a base voltage VB65B for block 65.

[0082] The analog value 10ANG(A) output by the DA converter 10DAC(A) by converting the input bit sequence is converted by formula (2) into Fig. Figure 12 is shown. In formula (2), VB(i) specifies a base voltage indicated by the upper input bit sequence Inp_U. As can be seen from formula (2), the analog value 10ANG(A) corresponding to the input bit sequence 10BTP is obtained by adding the common voltage value specified by the code of the lower input bit sequence Inp_L to the base voltage value identified by the code of the upper input bit sequence Inp_U. Therefore, in step SC1, by inputting a predetermined value (all logical values ​​are "0") into the DA converter S_DAC, the lower input bit sequence Inp_L and the upper input bit sequence Inp_U specify the base voltage VB(i) of the block specified by the upper input bit sequence.

[0083] In Fig. Figure 6 shows the relationship between the block number and the base voltage on the right-hand side of the graph. In the graph, a horizontal axis represents the block number, and a vertical axis represents the base voltage. Although not particularly restricted, the DA converter 10DAC(A) according to embodiment 1, as can be seen from the graph, converts the input bit sequence 10BTP into a positive voltage side and a negative voltage side with respect to a ground voltage (0 V). The DC offset used is the value of the base voltage at the time of block number 65, which corresponds to the ground voltage (0 V) where the output noise is small. That is, an output value of the DA converter 10DAC(A) when the test bit sequence corresponding to the logical value "0x000" is supplied to the DA converter 10DAC(A) is the DC offset DC_Offset.In other words, the lower input bit sequence Inp_L is set to a predetermined value (all logical values ​​are "0"), the upper input bit sequence Inp_U is also set to a predetermined value (all logical values ​​are "0"), and the DC offset DC_Offset is acquired.

[0084] Next, the calibration test of the DA converter S_DAC will be described.

[0085] Processor 10P executes step SC4 after step SC3. In step SC4, processor 10P reads the test bit sequence stored in non-volatile memory NVMEM or volatile memory VOLMEM related to the digital-to-analog converter S_DAC and inputs the test bit sequence as the lower input bit sequence Inp_L into the digital-to-analog converter S_DAC. At this point, processor 10P inputs a bit sequence in which all logical values ​​are "0" (upper input bit sequence of a predetermined value) as the upper input bit sequence Inp_U into the digital-to-analog converter M_DAC. Additionally, processor 10P controls switch 10SW so that the output of the digital-to-analog converter 10DAC(A) is supplied to the analog-to-digital converter 10AD.

[0086] Accordingly, the analog value corresponding to the test bit sequence converted by the DA converter S_DAC is supplied to the AD converter 10AD, converted into the corresponding digital sequence by the AD converter 10AD and supplied to the processor 10P as the test result bit sequence 10BTTR.

[0087] In step SC5, the processor 10P compares the test bit sequence delivered to the DAC S_DAC in step SC3 with the delivered test result bit sequence and generates the input and output characteristics of the DAC S_DAC based on the test bit sequence. Based on the generated input and output characteristics, the processor 10P generates a correction amount so that the test result bit sequence matches the test bit sequence and stores the correction amount in the memory of the preamplifier circuit 10FNT as correction data (correction D in Fig. 1) At this point, the processor 10P stores the generated correction amount in such a way that it is paired with the supplied test bit sequence.

[0088] Next, in step SC6, processor 10P determines whether the test of the digital-to-analog converter S_DAC using all test bit sequences is complete. This can be determined, for example, using the same procedure as described in step SC3 above. In step SC6, if processor 10P determines that not all test bit sequences have been read, it returns to step SC4, reads the unread test bit sequence, and then repeats steps SC4 through SC6.

[0089] When step SC6 ends, processor 10P terminates the calibration test operation in step SC7.

[0090] Fig. Figure 7 shows a diagram illustrating the correction amount according to embodiment 1. Fig. Figure 7 shows an example of the process by the 10P processor by executing the command in Fig. The correction amount was generated by the 6 calibration tests described and stored as correction data (correction D) in the pre-stage circuit 10FNT.

[0091] In Fig. 7 specifies THM_D as a region corresponding to the DA converter M_DAC, which stores a multitude of correction amounts generated by executing steps SC1 to SC3, and BW_D as a region corresponding to the DA converter S_DAC, which stores a multitude of correction amounts generated by executing steps SC4 to SC6. As in Fig. As shown in Figure 7, the correction amount of the DC offset DC_Offset is stored in the area BW_D.

[0092] In the THM_D area, a column of M_DAC_Code specifies an area in which a test bit sequence corresponding to the upper input bit sequence Inp_U is stored, and a column of THM_C specifies an area in which a correction amount is stored. Fig. 7 is the correction amount of the block number corresponding to the test bit sequence, stored in the area THM_C. In the area TMH_D, a test bit sequence and a correction amount are stored in pairs so that they correspond to each other. For example, the correction amount for block number 1 is stored in such a way that it is paired with the test bit sequence "0×8000", which indicates block number 1.

[0093] Furthermore, in the BW_D area, the S_DAC_Code column specifies a range in which the test bit sequence corresponding to the lower input bit sequence Inp_L is stored, and BW_C specifies a range in which the correction amount corresponding to the test bit sequence is stored. For example, the correction amount of bit 1 is stored such that it is paired with the test bit sequence "0x0001", in which only bit 1 has the logical value "1". The DC offset DC_Offset is stored as a pair of correction data corresponding to the test bit sequence "0x0000". <korrektur>

[0094] Next, the correction carried out in the pre-stage circuit 10FNT will be described with reference to the drawings. Fig. Figure 8 shows a block diagram illustrating a configuration of the bit sequence correction circuit according to embodiment 1.

[0095] The bit sequence correction circuit 10BCT contains a table THM_T corresponding to the upper input bit sequence Inp_U, a table BW_T corresponding to the lower input bit sequence Inp_L, and adders ADD1 and ADD2.

[0096] The 10P processor transmits the correction amount in the THM_D area ( Fig. 7) stored test bit sequence and block number to table THM_T and transfers the correction amount of the data in area BW_D ( Fig. 7) stored test bit sequence and the bit to the table BW_T. Accordingly, as in Fig. Figure 8 shows that the test bit sequence corresponding to the upper input bit sequence Inp_U and the corresponding correction amount are registered as a pair in the table THM_T, and the test bit sequence corresponding to the lower input bit sequence Inp_L and the corresponding correction amount are registered as a pair in the table BW_T.

[0097] The table THM_T is searched using the upper input bit sequence Inp_U of the input bit sequence 10BTP, and the table THM_T outputs the correction amount corresponding to the test bit sequence matching the upper input bit sequence Inp_U. The output correction amount is then passed to the adder ADD1.

[0098] The table BW_T is searched using the lower input bit sequence Inp_L of the input bit sequence 10BTP. During the search, a test bit sequence is sought in the lower input bit sequence Inp_L where the same bit number as the bit number whose logical value is "1" also has the logical value "1". The correction amount corresponding to this test bit sequence, where the logical value of the same bit number is "1", is then output from the table BW_T. In the lower input bit sequence Inp_L of the input bit sequence 10BTP, a multitude of different bit numbers can simultaneously have the logical value "1". In this case, a multitude of correction amounts are output from the table BW_T. To handle this, a sum of the correction amounts output from the table BW_T is digitally generated. This sum of correction amounts is then sent to the adder ADD1.

[0099] The adder ADD1 adds the correction amounts from table THM_T and the correction amounts (sum of correction amounts) from table BW_T and sends the correction amounts to the adder ADD2. The adder ADD2 adds the input bit sequence 10BTP and the correction amount from adder ADD1 and sends the result to the input of the DA converter 10DAC(A).

[0100] Accordingly, the main input bit sequence 10BTB supplied to the DA converter 10DAC(A) is corrected by the preamplifier circuit 10FNT based on the correction amount obtained in the calibration test. That is, the input bit sequence fed into the DA converter 10DAC(A) is corrected based on the input and output characteristics of the DA converter 10DAC(A), and the accuracy is improved.

[0101] Since the number of test bit sequences used in the calibration test can be reduced, the calibration period (CAL) can be shortened. Therefore, it is possible to shorten the execution interval of the calibration test to accommodate fluctuations in ambient temperature.

[0102] Furthermore, it is possible to prevent the table BW_T and the area BW_D of memory 100 from becoming large, since the number of correction amounts corresponding to the lower input bit sequence Inp_L is the number of bits M+1 that make up the lower input bit sequence Inp_L.

[0103] In embodiment 1, the bit sequence correction circuit 10BCT of the pre-stage circuit 10FNT contains the adders, as for example in Fig. Figure 8 shows that the adder can be omitted. This can be achieved, for example, by registering not only the correction amount, but also a value obtained by adding a value specified by the original processor output bit sequence 10BTP to the correction amount in tables THM_T and BW_T, and by outputting a value obtained by correcting the processor output bit sequence from the bit sequence correction circuit 10BCT.

[0104] The DA converter 10DAC(A) can contain a variety of DA converters, a variety of divider circuits and a variety of weighting addition circuits.

[0105] Although Fig. 4 and Fig. Figure 5 shows an example in which the steps of measuring the test result bit sequence corresponding to the test bit sequence and generating the correction amount are repeated. However, the procedure for generating the correction amount is not limited to this. For example, the correction amount can be generated by creating a target DA conversion relationship through regression analysis (linear regression). That is, all measurements can be performed, and then the correction amount can be generated.

[0106] In embodiment 1, the example is described in which the correction data is generated by the calibration test, and the invention is not limited thereto. That is, for example, the correction data already generated can be updated by the calibration test. In this case, the upstream circuit performs the correction based on the updated correction data. In the following description, both the generation and the updating of the correction data can be referred to as updating the correction data.

[0107] In embodiment 1, the updating of the correction data or the generation of the test input value is performed based on the relationship between the bit group contained in the bit sequence input into the DA converter 10DAC(A) and the circuit segment of the first type SEG1 and the circuit segment of the second type SEG2.

[0108] In embodiment 1, an example is described in which an uncorrected value is used as a test input value, which is a test pair, and the invention is not limited thereto. That is to say, for example, the calibration test can be performed using a corrected value as the test input value.

[0109] As in Fig. As shown in Figure 2, the divider circuit 10SPT(B) outputs the internal upper bit (Inp_U) of K bits to the circuit segment of the first type (M_DAC) and outputs the internal lower bit (Inp_L) of M bits to the circuit segment of the second type (S_DAC). The calibration test includes a test focused on the first type to capture the DA conversion characteristics of the circuit segment of the first type (M_DAC) and a test focused on the second type for the DA conversion characteristics of the circuit segment of the second type (S_DAC). In this case, as shown in Fig. Figure 5 shows a test input value to be used in the first-type targeted test, a value adapted so that the internal lower bit sequence becomes the second fixed bit sequence (predetermined value input in step SC1). As shown in Fig. As shown in Figure 5, the test input value to be used in the second-type-oriented test is a value adapted so that the internal upper bit sequence becomes the first fixed bit sequence (predetermined value entered in step SC4). Accordingly, it is possible to reduce the influence of the second-type circuit segment during the first-type-oriented test and vice versa.

[0110] In the calibration test, as in Fig. As shown in Figure 6, an offset measurement test is performed to obtain an analog value that is independent of the values ​​of the internal upper bit sequence and the internal lower bit sequence. In this case, as shown in Fig. Figure 6 shows the first fixed bit sequence and the second fixed bit sequence “0x0000” being entered into the circuit segment of the first type (M_DAC) and the circuit segment of the second type (S_DAC).

[0111] The calibration test according to embodiment 1 can be viewed as omitting the first reduction target test using a first reduction target test input value. Here, the first reduction target test input value has an internal upper bit sequence that is different from the first fixed bit sequence (M_DAC in Fig. 5: predetermined input value), and an internal lower bit sequence that is a different value than the second fixed bit sequence (S_DAC in Fig. 5: predetermined entered value).

[0112] The calibration test according to embodiment 1 can be considered to include the first reduction target test using the first reduction target test input value. Here, the first reduction target test input value has an internal upper bit sequence that is different from the first fixed bit sequence, and an internal lower bit sequence that is different from the second fixed bit sequence, and the number of test pairs to be used in the first reduction target test is 2. N - (2 K +2 M+1 ).

[0113] In Fig. 3. The decoder M_DEC can be considered a selector that chooses a circuit of the first type from the multitude of circuits of the first type UI. In this case, the selector supplies an active signal (signal Ul+ at a high level) to a selected circuit of the first type and supplies an inactive signal (signal UI- at a high level) to an unselected circuit of the first type. Taking into account the active / inactive states of the in Fig. In the circuit of the first type and the circuit of the second type shown in Figure 3, the correction data is updated or the test input value is generated based on the relationship between the bit group contained in the bit sequence input into the DA converter 10DAC(A) and the active / inactive states of the circuit of the first type and the circuit of the second type.

[0114] The number of test pairs acquired in the calibration test is equal to or greater than the total number in Fig. 3 described circuits of the first type and circuits of the second type.

[0115] In Fig. 8. The table THM_T can be considered as a first table for managing the correction amount derived from the circuit segment of the first type, and the table BW_T can be considered as a table for managing the correction amount derived from the circuit segment of the second type.

[0116] Although an example is described in which the processor output bit sequence 10BTP is used as the test bit sequence, the main input bit sequence 10BTB can also be used as the test bit sequence. (Version 2)

[0117] In embodiment 1, a device using a digital-to-analog converter (DAC) 10DAC(A) is described. In embodiment 2, a device using a plurality of DACs is described. That is, a case in which the main circuit 10BDY includes an additional DAC 10DAC(B) besides the DAC 10DAC(A) is described as embodiment 2. By adding the DAC 10DAC(B), the number of bits that can be input to the DAC can be increased. In this case, the main circuit 10BDY, as described above, also includes the divider circuit 10SPT(A) and the weighted addition circuits 10ADDW.

[0118] Fig. Figure 9 shows a block diagram illustrating a configuration of the device according to embodiment 2. Fig. Figure 9 shows the main circuit 10BDY and the pre-stage circuit 10FNT according to embodiment 2. <hauptschaltung>

[0119] In Fig. 9 contains the main circuit 10BDY, the DA converter 10DAC(A), the DA converter 10DAC(B), and the weighted addition circuits 10ADDW. As in Fig. As shown in Figure 2, the DA converter DAC(A) includes the divider circuit, the hold circuits M_HL and S_HL, the main DA converter M_DAC, the sub-DA converter S_DAC, and the addition circuit MS_ADDW. In the DA converter DAC(A) according to embodiment 2, the divider circuit 10SPT(B) provided in the main circuit 10BDY is used as a divider circuit.

[0120] The output of the DA converter 10DAC(A) and the output of the DA converter 10DAC(B) are added by the addition circuit 10ADDW and sent as an analog value to the amplifier circuit AMP or the AD converter 10AD via the switch 10SW ( Fig. 1) supplied. In embodiment 2, the addition circuit 10ADDW, although not particularly limited, includes a gain amplifier 10M_GP, to which an output from the DA converter 10DAC(A) is supplied, a gain amplifier 10S_GP, to which an output from the DA converter 10DAC(B) is supplied, and an adder ADDW, which adds the output of the gain amplifier 10M_GP and the output of the gain amplifier 10S_GP and outputs the result. <vorstufenschaltung>

[0121] As in Fig. As shown in Figure 9, the pre-stage circuit 10FNT includes the bit sequence correction circuit 10BCT, the divider circuit 10SPT(B), a hold circuit 10M_HL and 10S_HL, and an adder ADD4. In embodiment 1, the bit sequence correction circuit 10BCT mainly adds and outputs the processor output bit sequence 10BTP using the adder ADD2. Fig. 8. On the other hand, in embodiment 2, such an addition as the bit sequence correction circuit 10BCT is not performed, as in Fig. 9 is shown. This is because the adder ADD4 plays a similar role.

[0122] The processor output bit sequence 10BTP from processor 10P is delivered to the divider circuit 10SPT(B). Here, although not particularly restrictive, a case where the processor output bit sequence 10BTP consists of 32 bits is described as an example. That is, it is assumed that 32 bits are set in parallel in time as a single bit sequence, and that the bit sequence is delivered from processor 10P to the pre-stage circuit 10FNT.

[0123] The divider circuit 10SPT(B) divides the supplied 32-bit processor output bit sequence 10BTP into an upper bit sequence U_Input and a lower bit sequence L_Input. Here, it is assumed that the upper bit sequence U_Input contains 16 bits on the top-most bit (MSB) side of the processor output bit sequence 10BTP, and the lower bit sequence L_Input contains 16 bits on the lowest-most bit (LSB) side of the processor output bit sequence 10BTP. Of course, 32 bits and 16 bits are examples, and the invention is not limited to them.

[0124] The upper bit sequence U_Input is held by the holding circuit 10M_HL and fed into the DAC 10DAC(A). Conversely, the lower bit sequence L_Input is held by the holding circuit 10S_HL and fed to the adder ADD4. The output of the adder ADD4 is fed into the DAC 10DAC(B). The output of the DAC 10DAC(A) and the output of the 10DAC(B) are added by the weighted addition circuit 10ADDW and output, for example, as the analog value 10ANG(A).

[0125] The 10BCT bit sequence correction circuit contains tables THM_T and BW_T and an adder ADD3. The upper bit sequence U_Input searches the first table THM_T and the second table BW_T, and the correction amount found is added by the adder ADD3. The result of this addition by the adder ADD3 is then passed to the adder ADD4. Therefore, the adder ADD4 adds the correction amount from the 10BCT bit sequence correction circuit to the lower bit sequence L_Input. In other words, the lower bit sequence L_Input is corrected by the correction amount from the 10BCT bit sequence correction circuit.

[0126] The DA converter 10DAC(A) according to embodiment 2 is described by reference to Fig. 2 and Fig. The 3 described segment DACs are implemented. That is, the DAC 10DAC(A) contains the thermometer DAC M_DAC and the weighted binary DAC S_DAC.

[0127] In embodiment 2, the correction of the DA converter 10DAC(A), whose voltage changes significantly depending on the value of the input bit sequence, is performed. Therefore, during the calibration period CAL, a test bit sequence suitable for the configurations of the thermometer DA converter M_DAC and the weighted binary DA converter S_DAC, which form the DA converter 10DAC(A), is generated by the processor 10P ( Fig. 1) supplied to the DA converter 10DAC(A) as the upper bit sequence U_Input.

[0128] That is, in the same way as described in embodiment 1, test data formed from a test bit sequence derived from the structure of the thermometer DA converter M_DAC forming the DA converter 10DAC(A) and test data formed from a test bit sequence derived from the structure of the weighted binary DA converter S_DAC forming the DA converter 10DAC(A) are prepared in advance.

[0129] As described in embodiment 1, the processor 10P supplies the test bit sequence to the DA converter 10DAC(A) via the pre-stage circuit 10FNT using the prepared test data and generates the correction amount based on the test result bit sequence and the test bit sequence from the AD converter 10AD ( Fig. 1) The processor 10P then registers the correction data related to the thermometer-based DAC M_DAC under the generated correction amounts in table THM_T and registers the correction data related to the weighted binary DAC S_DAC in table BW_T. Accordingly, the test bit sequence and the correction amount are stored in tables THM_T and BW_T of the... Fig. The bit sequence correction circuit 10BCT shown in 9 is registered, similar to the one in Fig. Table 7 shown.

[0130] The upper bit sequence U_Input is divided into the upper input bit sequence Inp_U for the thermometer DA converter M_DAC forming the DA converter 10DAC(A) and the lower input bit sequence Inp_L for the weighted binary DA converter S_DAC forming the DA converter 10DAC(A).

[0131] Table THM_T is searched using the split upper input bit sequence Inp_U, and table THM_T is searched using the split lower input bit sequence Inp_L. The correction amount found by searching each table is added by adder ADD3 and passed to adder ADD4.

[0132] Fig. Figure 10 shows a correction table according to embodiment 2. Fig. 10 is similar to Fig. 8. One difference is that the upper bit sequence U_Input, which is to be input into the DA converter to be corrected, DA converter 10DAC(A), is used to search the tables THM_T and BW_T. Furthermore, it differs Fig. 9 also from Fig. 8 in that the correction amount found by the search is added by the adder ADD3 and then output to the adder ADD4.

[0133] As in Fig. As shown in Figure 9, the adder ADD4 adds the lower bit sequence L_Input and the correction amount output by the bit sequence correction circuit 10BCT, so that the lower bit sequence corrected for the DA converter 10DAC(A) is input into the DA converter 10DAC(B). As a result, as in embodiment 1, it is possible to reduce the number of test bit sequences, increase the calibration frequency, and mitigate large fluctuations in accuracy due to variations in ambient temperature or the like. Furthermore, it is possible to prevent an increase in the size of the bit sequence correction circuit 10BCT, since the number of test bit sequences is reduced.

[0134] In Fig. 9. The DA converter 10DAC(B) is also implemented by the segment DA converter. However, the DA converter 10DAC(B) does not have to be the segment DA converter. (Version 3)

[0135] In embodiment 3, the input path of the Fig. The A / D converter 10AD shown in section 1 has been modified. That is to say, in Fig. 1. The output of amplifier circuit AMP passes through the attenuator. The output is supplied to the A / D converter 10AD. Accordingly, the analog value, at a high voltage, is attenuated by an attenuator 1100 through amplifier circuit 1403 and supplied to an A / D converter 1406, thus preventing the A / D converter 1406 from being destroyed by the high voltage.

[0136] In embodiment 3, during the calibration period CAL, a correction amount is generated based on the test bit sequence by integrating the input and output characteristics of the DA converter DAC(A) and the input and output characteristics of the amplifier circuit AMP, and the generated correction amount is registered as a table in the bit sequence correction circuit 10BCT.

[0137] Accordingly, the bit sequence correction circuit 10BCT corrects the bit sequence input to the DAC(A) by the correction amount, taking into account the input and output characteristics of both the DAC(A) and the amplifier circuit AMP. As a result, the accuracy of the analog value output by the amplifier circuit AMP can be improved. Of course, when using both DACs 10DAC(A) and 10DAC(B), as in embodiment 2, the input and output characteristics of the amplifier circuit AMP can be taken into account in the same way. (Version 4)

[0138] In embodiment 4, a charged particle beam device is described as an example of a device with a DA converter.

[0139] Fig. Figure 11 shows a schematic diagram illustrating a configuration of the charged particle beam device according to embodiment 4. In embodiment 4, a case in which the charged particle beam device is an electron microscope device using an electron beam is taken as an example, and the charged particle beam device is not limited thereto and can, for example, be an ion microscope device using an ion beam.

[0140] In Fig. Reference numeral 1100 denotes a charged particle beam device. The charged particle beam device 1100 schematically irradiates a sample 1117 with an electron beam (a charged particle beam) B1 emitted by an electron gun (a charged particle gun) 1106, and detects a quantity of electrons (in particular secondary electrons or reflected electrons) B2 emitted by the sample 1117 by means of a detector 1114.

[0141] The in Fig. Figure 11 shows a charged particle beam device 1100 comprising a main unit 1101, a control unit 1119, a variety of power supply circuits 1103a, 1103b, 1103c, and 1103d, and an image processing unit 1118. The main unit 1101 includes a housing 1104 and a sample chamber 1105. The housing 1104 contains the electron gun (charged particle gun) 1106, a condenser lens 1110, a reflection plate 1111, a deflector 1112, an objective lens 1113, the detector 1114, and an accelerator electrode 1115. The electron gun 1106 contains an electron source (charged particle source) 1107, an extraction electrode 1108, and an accelerator electrode 1109. The sample chamber 1105 contains a table. 1116, on which sample 1117 is placed.

[0142] The housing 1104 is made of a metal part and connected to a ground power supply Vs. The power supply circuit 1103a generates a negative accelerating voltage VO and supplies this voltage to the electron source 1107. The power supply circuit 1103b generates a positive extraction voltage based on the voltage (V0) of the electron source 1107 and supplies this extraction voltage to the extraction electrode 1108. The electron source 1107 emits the electron beam (charged particle beam) B1 through the extraction voltage. The accelerating electrode 1109 is connected to the ground power supply Vs. Accordingly, the positive accelerating voltage V0 is applied to the accelerating electrode 1109 with respect to the electron source 1107. The electron beam B1 emitted by the electron source 1107 is accelerated by the accelerating voltage VO.

[0143] The condenser lens 1110 focuses the electron beam B1 emitted by the electron gun 1106. The objective lens 1113 focuses the electron beam B1 so that it becomes a tiny spot on the sample 1117. At this point, the power supply circuit 1103d generates a positive accelerating voltage Vb and supplies it to the accelerating electrode 1115, which is installed near the condenser lens 1110. Consequently, the electron beam B1, already accelerated by the accelerating voltage VO, is further accelerated by the accelerating voltage Vb. This allows for a further increase in the resolution of the electron beam B1.

[0144] The deflector 1112 is a magnetic field deflector or an electrostatic deflector and deflects the electron beam B1 focused by the objective lens 1113 in order to scan the electron beam B1 emitted on the sample 1117 (i.e., a tiny spot). The power supply circuit 1103c generates a negative delay voltage Vr and supplies this voltage to the stage 1116. Consequently, the electron beam B1 passing through the objective lens 1113 is slowed down by the delay voltage Vr. This reduces the risk of damage to the sample 1117.

[0145] Energy of, for example, several tens of kV is applied to the electron beam B1 by the accelerating voltage VO and the accelerating voltage Vb. The deceleration voltage Vr reduces the energy of the electron beam B1 to, for example, 1 kV or less. As described above, the energy of the electron beam B1 is determined accordingly by the power supply circuits 1103a to 1103d. However, the power supply circuit 1103d and the accelerating electrode 1115 are not required.

[0146] Sample 1117 emits electrons (especially secondary electrons or reflected electrons) B2 according to the irradiation of the electron beam B1. The emitted electrons B2 are accelerated towards the electron source 1107 by the retarding voltage Vr and the accelerating voltage Vb and collide with the reflection plate 1111. The reflection plate 1111 then emits secondary electrons. The detector 1114 detects a quantity of these secondary electrons.

[0147] The control unit 1119, for example, contains a wiring substrate (control substrate) on which various integrated circuits (ICs), including a processor, are mounted. The control unit 1119 controls the voltage levels of the power supply circuits 1103a to 1103d. The control unit 1119 controls the deflector 1112, the objective lens 1113, and the like. Furthermore, the control unit 1119 processes an output signal from the detector 1114 using a predetermined signal processing circuit. At this point, the control unit 1119 synchronizes a control signal to the deflector 1112 and an output signal from the detector 1114 to generate the original data for producing a secondary electron image of a sampled area. The control unit 1119 does not necessarily have to be completely mounted on a substrate.The control unit 1119 can contain components found in a computer, such as volatile memory or non-volatile memory.

[0148] The image processing unit 1118 contains, for example, a computer such as a personal computer (PC) that includes various integrated circuits (ICs), including a processor. The image processing unit 1118 acquires the original secondary electron image data from the control unit 1119 and creates the secondary electron image based on this data. The image processing unit 1118 then displays the created secondary electron image on a screen or similar device. The secondary electron image is an image in which the luminance varies depending on the emission quantity of secondary electrons at each position within the scanned area.

[0149] In the charged particle beam device 1100 according to embodiment 4, the control unit 1119 includes the pre-stage circuit 10FNT described in embodiments 1 to 3, the main circuit 10BDY, the analog-to-digital converter 10AD, and the like. An example is described here in which the main circuit 10BDY described in embodiment 2 is used to control the deflector 1112. The invention is not limited to this, and the analog-to-digital converter can be used to control various parts in the charged particle beam device 1100. It is understood that the analog-to-digital converter used can be the one described in embodiment 1 or 3.

[0150] In Fig. Reference numeral 1120 denotes a digital-to-analog converter (DAC) circuit. The DAC circuit 1120 contains the components described in... Fig. 9 shown preamplifier circuit 10FNT, the main circuit 10BDY and the amplifier circuit AMP (corresponding to the amplifier circuit AMP in Fig. 1) which amplifies an output of the main circuit 10BDY. A deflection signal Scn is input as an input bit sequence to the DA converter circuit 1120, the deflection signal Scn is converted into an analog value by the DA converter circuit 1120, and the analog value is amplified by the amplifier circuit. The amplified deflection signal Scn with an analog value is applied to the deflector 1112. The DA converter circuit 1120 can control the AD converter 10AD and the processor 10P used for calibration ( Fig. 1) included. In this case, the processor 10P can also be included in the control device 1119.

[0151] By linearly increasing (decreasing) the value of the deflection signal Scn over time, the analog value applied to the deflector 1112 also increases (decreases) linearly. Accordingly, a magnetic or electric field generated by the deflector 1112 also changes, and the electron beam B1 moves on the sample 1117.

[0152] If the linearity of the DA converter fluctuates, for example due to variations in ambient temperature, the magnetic or electric field generated by the deflector 1112 also fluctuates due to these temperature variations. As a result, the distance traveled by the electron beam B1 on the sample 1117 changes, causing the image in the generated secondary electron image to expand or contract. This expansion and contraction of the image, which depends on the ambient temperature variation, becomes particularly noticeable when an observation area is expanded at low resolution.

[0153] As described above, performing the calibration generates the correction factor for the DA converter circuit, including the amplifier circuit. This corrects the bit sequence input to the DA converter circuit and improves linearity. Furthermore, according to the embodiment, it is possible to shorten the calibration period (CAL), thus reducing the observation time of the sample by the charged particle beam device 1100, even when the calibration frequency is increased to compensate for fluctuations in ambient temperature. Naturally, the calibration can be performed multiple times without generating all the correction factors at once.

[0154] In Fig. Figure 11 shows only one pair of deflectors 1112, as the housing 1104 is viewed from a side angle. However, two pairs of deflectors 1112 are provided in the housing 1104 to move the electron beam B1 on the sample 1117 in the X and Y directions (two essentially orthogonal directions). Since the DA converter circuit 1120 provides an analog signal to the pair of deflectors 1112 according to the deflection signal Scn, the control unit 1119 is equipped with two pairs of DA converter circuits 1119, corresponding to the two pairs of deflectors. In this case, it is possible to prevent a test time from becoming too long by performing the calibration test on both pairs of DA converter circuits simultaneously. Since it is not necessarily assumed that the two pairs of DA-Waridler circuits have the same properties, it is difficult for the two pairs of DA converter circuits to share the correction data.

[0155] In embodiment 4, the charged particle beam device is described as an example of the device with the DA converter, and the device 1 is not limited to it.

[0156] In embodiments 1 and 2, an example is described in which two tables THM_T and BW_T are used as a bit sequence correction circuit 10BCT, and the invention is not limited thereto. For example, the bit sequence correction circuit 10BCT can contain one table (for simplicity, U_TB). With reference to Fig. 9 and Fig. As an example, the bit sequence correction circuit 10BCT contains a table that is searched for the upper bit sequence U_Input. During the calibration period CAL, a multitude of test bit sequences corresponding to all codes of the upper bit sequence U_Input are supplied to the DA converter 10DAC(A). That is, 2 N Test bit sequences are pre-prepared with the number of bits N (= 16 bits) of the upper bit sequence U_Input as the exponent. During the calibration period CAL, processor 10P successively delivers the test bit sequence to the digital-to-analog converter 10DAC(A). Processor 10P compares the test bit sequence with a test result bit from the analog-to-digital converter 10AD and generates a correction amount corresponding to the test bit sequence. Processor 10P records the generated correction amount in the table U_TB. Accordingly, the table U_TB, which contains the upper bit sequence U_Input corresponding to the test bit sequence and the correction amount, is created.

[0157] If the DA converter 10DAC(A) is actually used, the upper bit sequence U_Input is converted into an analog value by the DA converter 10DAC(A) and supplied to the bit sequence correction circuit 10BCT. The table U_TB is searched by the upper bit sequence U_Input supplied to the bit sequence correction circuit 10BCT, converted into a correction amount, the correction amount is added to the lower bit sequence L_Input, converted into an analog value by the DA converter 10DAC(B), and added to the analog value from the DA converter 10DAC(A).

[0158] In this way, by implementing the bit sequence correction circuit 10BCT 2 N Correction amounts based on the 2 N Test bit sequences are generated during the calibration period CAL, but the input bit sequence of the DA converter 10DAC(B) can be corrected taking into account the input and output characteristics of the DA converter 10DAC(A), without considering the configuration of the DA converter 10DAC(A).

[0159] Fig. Figure 13 shows a diagram illustrating a modification of embodiment 2, which is shown in Fig. Figure 9 shows the modification, which includes a table described above. Hereinafter, the modification will be referred to as a modification of embodiment 2. In the configuration of Fig. 13 can use the bit sequence correction circuit 10BCT, which contains two tables, as in Fig. As shown in Figure 8, the bit sequence correction circuit 10BCT is applied. In embodiment 1, the bit sequence correction circuit 10BCT mainly adds and outputs the processor output bit sequence 10BTP using the adder ADD2. Fig. 8. On the other hand, in embodiment 2, such an addition as the bit sequence correction circuit 10BCT is not performed, as in Fig. Figure 9 shows this. This is because the adder ADD4 plays a similar role. The description of embodiment 2 can also be applied to the modification.

[0160] In embodiments 1 to 4, the example described in the segment D / A converter is that the main D / A converter M_DAC, which converts the upper input bit sequence Inp_U, is implemented by the thermometer D / A converter, and the sub-D / A converter S_DAC, which converts the lower input bit sequence Inp_L, is implemented by the weighted binary D / A converter. The invention is not limited to this. That is to say, the main D / A converter M_DAC, which converts the upper input bit sequence Inp_U, can be implemented by a weighted binary D / A converter, and the sub-D / A converter S_DAC, which converts the lower input bit sequence Inp_L, can be implemented by a thermometer D / A converter.

[0161] From the perspective of binary format, endianity, and communication encoding, the bit sequence generated by the processor, the bit sequence output by the processor, the bit sequence input and output by the preamplifier circuitry, the bit sequence input to the main circuitry, the bit sequence input to the digital-to-analog converter (DAC), and the bit sequence within the DAC can be the same or different. For example, the DAC target value generated in the processor, the DAC target value output by processor 10P as the processor output bit sequence 10BTP, the DAC target value corrected by the preamplifier circuitry, and the DAC target value input to the main circuitry 10BDY or the DAC 10DAC(A) can all be different (from the perspective of binary format, endianity, and communication encoding).

[0162] Although the invention made by the present inventors has been specifically described based on the embodiment, the invention is not limited to the embodiment, and it is self-evident that various modifications can be made without deviating from the core of the invention.

[0163] The following is described above in the present description.

[0164] A device comprises: a processor configured to output a DA conversion target value; a pre-stage circuit configured to receive the DA conversion target value from the processor, correct the DA conversion target value according to correction data, and output the corrected DA conversion target value; a main circuit containing one or more correction target DA converter elements and configured to perform DA conversion at the corrected DA conversion target value; and an AD converter, The correction target DA converter element is a hybrid DA converter element that outputs an analog value from an output terminal, which is obtained by adding an analog value output from a circuit segment of the first type, responsible for a higher order, and an analog value output from a circuit segment of the second type, responsible for a lower order. as a calibration test to create or update the correction data of the processor (A) acquires a plurality of test pairs, each of which is a pair consisting of a test input value and a test result value with the following properties: (A1) The test input value is a value that is entered into the main circuit as a DA conversion target value, with or without correction, and (A2) The test result value is a value obtained by performing an A / D conversion by the A / D converter to an analog value that is output by inputting the test input value into the main circuit, and (B) the correction data is updated based on the multitude of test pairs in (A), where the number of test pairs acquired during a calibration test period is less than 2 N is, N is the number of bits that specify a resolution of the correction target DA converter element.

[0165] Furthermore, it is described that the device can be as follows.

[0166] In the device, the update of the correction data in (B) or the generation of the test input value is performed based on the following for an input terminal bit sequence, which is a bit sequence to which the correction target DA converter element is input at an input terminal: a relationship between 0 and 1 of a bit group contained in the input terminal bit sequence and the circuit segment of the first type and the circuit segment of the second type.

[0167] Furthermore, it is described that the device can be as follows.

[0168] In the device, The correction target DA converter element has a divider circuit that outputs an internal upper bit sequence of K bits and an internal lower bit sequence of M bits, based on an input value from an input terminal and a binary format assumed by the element, The calibration test includes a test focused on the first type to capture a DA conversion characteristic of the circuit segment of the first type and a test focused on the second type to capture a DA conversion characteristic of the circuit segment of the second type. A test input value to be used in the first-type targeted test is a value adapted such that the internal lower bit sequence is a second fixed bit sequence after passing through the divider circuit, and A test input value to be used in the second-type targeted test is a value that is adjusted so that the internal upper bit sequence is a first fixed bit sequence after passing through the divider circuit.

[0169] Furthermore, it is described that the device can be as follows.

[0170] The calibration test in the device further includes an offset measurement test for outputting an analog value that is independent of a value of the internal upper bit sequence and a value of the internal lower bit sequence, and A test input value to be used in the offset measurement test is a value that is adjusted so that the internal lower bit sequence is the second fixed bit sequence and the internal upper bit sequence is the first fixed bit sequence after passing through the divider circuit.

[0171] Furthermore, it is described that the device can be as follows.

[0172] In the device, The calibration test does not include an initial reduction target test using an initial reduction target test input value, and The first reduction target test input value is a value that is adjusted so that after passing through the divider circuit it has the following properties: The internal upper bit sequence is a different value than the first fixed bit sequence, and The internal lower bit sequence has a different value than the second fixed bit sequence.

[0173] Furthermore, it is described that the device can be as follows.

[0174] In the device, The calibration test includes an initial reduction target test using an initial reduction target test input value, and The first reduction target test input value is a value that is adjusted so that after passing through the divider circuit it has the following properties: The internal upper bit sequence is a different value than the first fixed bit sequence. The internal lower bit sequence has a different value than the second fixed bit sequence, and The number of test pairs to be used in the first reduction target test is 2. N - (2 K +2 M+1 ).

[0175] Furthermore, it is described that the device can be as follows.

[0176] In the device, The correction target DA converter element has a divider circuit that outputs an internal upper bit sequence of K bits and an internal lower bit sequence of M bits, based on an input value from an input terminal and a binary format assumed by the element. The internal upper bit sequence is entered into the circuit segment of the first type; the internal lower bit sequence is entered into the circuit segment of the second type; the circuit segment of the first type comprises a plurality of circuits of the first type and a selector circuit. The selector circuit is a circuit that selects one of the circuits of the first type according to the internal upper bit sequence, outputs an active signal to the selected circuit of the first type, and outputs an inactive signal to the unselected circuit of the first type. Each of the circuits of the first type contains a circuit element for outputting an analog value according to a weight of the internal upper bit sequence and the active signal or the inactive signal, The circuit segment of the second type is a segment that has a circuit of the second type corresponding to each of the bits of the internal lower bit sequence, and adds Analog values ​​output by each of the circuits of the second type to obtain an output value as a segment, and The circuit of the first type contains a circuit element for outputting the analog value according to the weight of the bit and an active / inactive state specified by the bit.

[0177] Furthermore, it is described that the device can be as follows.

[0178] In the device, the update of the correction data in (B) or the generation of the test input value is performed based on the following for an input terminal bit sequence, which is a bit sequence to which the correction DA converter element is input at an input terminal: a relationship between 0 / 1 of a bit group contained in the input terminal bit sequence and the active / inactive state of the plurality of circuits of the first type and the plurality of circuits of the second type.

[0179] Furthermore, it is described that the device can be as follows.

[0180] In the device, the number of test pairs acquired during the calibration test period is equal to or greater than the sum of the number of circuits of the first type and the number of circuits of the second type.

[0181] Furthermore, it is described that the device can be as follows.

[0182] In the device, the circuit segment of the first type is a thermometer circuit segment, and The circuit segment of the second type is a binary or ladder circuit segment.

[0183] Furthermore, it is described that the device can be as follows.

[0184] In the device, the pre-stage circuit stores as correction data a first table for managing a correction amount derived from the circuit segment of the first type and a second table for managing a correction amount derived from the circuit segment of the second type.

[0185] Furthermore, it is described that the device can be as follows: In the device, the main circuit is a circuit that performs a DA conversion of N+1 bits or more by jointly using a sub-DA converter element. which is responsible for a lower order, in addition to the correction target DA converter element, which is responsible for a higher order, The pre-stage circuit includes a divider circuit or divider wiring that receives the DA conversion target value and divides and outputs an upper DA conversion target value and a lower DA conversion target value, a correction circuit that outputs a correction amount obtained based on the upper DA conversion target value and the correction data, and an addition circuit that adds the correction amount and the lower DA conversion target value and outputs the corrected lower DA conversion target value, The correction target DA converter element sets the upper DA conversion target value as the conversion target. The sub-DA converter element sets the corrected lower DA conversion target value as the conversion target, and The main circuit includes a weighted addition circuit that performs a weighted addition of an analog value output by the correction target DA converter element and an analog value output by the sub-DA converter element to output an analog value.

[0186] Furthermore, it is described that the device can be as follows.

[0187] The main circuit in the device contains wiring that outputs the analog value output by the weighted addition circuit as the main output analog value.

[0188] Furthermore, it is described that the device can be as follows.

[0189] The device contains the main circuit. an amplifier circuit that amplifies the analog value output by the weighted addition circuit, and A wiring configuration that outputs an analog value amplified by the amplifier circuit as the main output analog value.

[0190] Furthermore, it is described that the device can be as follows.

[0191] The device contains the pre-stage circuit. a correction circuit that receives the processor output bit sequence and outputs a correction amount bit sequence based on the correction data, and an addition circuit that adds the correction amount bit sequence and the processor output bit sequence and outputs the main input bit sequence.

[0192] Furthermore, it is described that the device can be configured as follows. In the device, the pre-stage circuitry includes a correction circuitry that receives the processor output bit sequence and outputs the main input bit sequence based on the correction data.

[0193] Furthermore, it is described that the device can be as follows.

[0194] A charged particle beam device includes: a charged particle source configured to produce a charged particle beam; a deflector configured to deflect the charged particle beam; and the device described above as a controller configured to control the deflector.

[0195] The following is described in the present description.

[0196] A device comprises at least: a main circuit containing one or more DA converter elements and configured to convert a main input bit sequence, which is a received bit sequence, into a main output analog value, which is an analog value, and output the main output analog value; a processor configured to output a processor output bit sequence; a pre-stage circuit configured to receive the processor output bit sequence and output the main input bit sequence; and an AD converter, The pre-stage circuit corrects the processor output bit sequence based on correction data and outputs the main input bit sequence. The main circuit contains an amplifier circuit that amplifies an analog value output by the DA converter element and outputs the amplified analog value as the main output analog value, and the processor (A) acquires a plurality of pairs consisting of a test bit sequence and a test result bit sequence with the following properties: (A1) The test bit sequence is the processor output bit sequence or the main input bit sequence for a calibration test, (A2) The test result bit sequence is acquired by converting the main output analog value through the A / D converter, and (B) updates the correction data based on the multitude of pairs in (A). Reference symbol list 1 Device 10AD AD converter 10ADDW weighted addition circuit 10BCT bit sequence correction circuit 10BDY Main Circuit 10DAC(A), 10DAC(B) DA converter 10FNT preamplifier circuit 10P processor 10SPT(A), 10SPT(B) divider circuit 1100 charged particle beam device Inp_L lower input bit sequence Inp_U upper input bit sequence L_Input lower bit sequence M_DAC Main DA Converter S_DAC Sub-DA Converter U_Input upper bit sequence QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2022-003830 A

[0003] < / vorstufenschaltung> < / hauptschaltung> < / korrektur> < / testdaten> < / prozessor>

Claims

[1] Device comprising at least: a processor configured to output a DA conversion target value; a pre-stage circuit configured to receive the DA conversion target value from the processor, correct the DA conversion target value according to correction data, and output the corrected DA conversion target value; a main circuit containing one or more correction target DA converter elements and configured to perform DA conversion at the corrected DA conversion target value; and an AD converter, whereby The correction target DA converter element is a hybrid DA converter element that outputs an analog value from an output terminal, which is obtained by adding an analog value output from a circuit segment of the first type, responsible for a higher order, and an analog value output from a circuit segment of the second type, responsible for a lower order. as a calibration test to create or update the processor's correction data (A) acquires a plurality of test pairs, each of which is a pair consisting of a test input value and a test result value with the following properties: (A1) The test input value is a value that is entered into the main circuit as a DA conversion target value, with or without correction, and (A2) The test result value is a value obtained by performing an A / D conversion by the A / D converter to an analog value that is output by inputting the test input value into the main circuit, and (B) the correction data based on the multitude of test pairs in (A) is updated, wherein the number of test pairs acquired during a calibration test period is less than 2 N is, N is the number of bits that specify a resolution of the correction target DA converter element. [2] Device according to claim 1, wherein the updating of the correction data in (B) or the generation of the test input value is performed based on the following for an input terminal bit sequence, which is a bit sequence to which the correction target DA converter element is input at an input terminal: a relationship between 0 and 1 of a bit group contained in the input terminal bit sequence and the circuit segment of the first type and the circuit segment of the second type. [3] Device according to claim 1, wherein The correction target DA converter element has a divider circuit that outputs an internal upper bit sequence of K bits and an internal lower bit sequence of M bits, based on an input value from an input terminal and a binary format assumed by the element. the internal upper bit sequence is entered into the circuit segment of the first type, the internal lower bit sequence is entered into the circuit segment of the second type, the calibration test includes a test focused on the first type to capture a DA conversion characteristic of the circuit segment of the first type and a test focused on the second type to capture a DA conversion characteristic of the circuit segment of the second type, A test input value to be used in the first-type targeted test is a value adapted so that the internal lower bit sequence is a second fixed bit sequence after passing through the divider circuit, and A test input value to be used in the second-type targeted test is a value that is adjusted so that the internal upper bit sequence is a first fixed bit sequence after passing through the divider circuit. [4] Device according to claim 3, wherein The calibration test further includes an offset measurement test to output an analog value that is independent of a value of the internal upper bit sequence and a value of the internal lower bit sequence, and A test input value to be used in the offset measurement test is a value that is adjusted so that the internal lower bit sequence is the second fixed bit sequence and the internal upper bit sequence is the first fixed bit sequence after passing through the divider circuit. [5] Device according to claim 4, wherein the calibration test does not include an initial reduction target test using an initial reduction target test input value, and The first reduction target test input value is a value that is adjusted so that after passing through the divider circuit it has the following properties: The internal upper bit sequence is a different value than the first fixed bit sequence, and The internal lower bit sequence has a different value than the second fixed bit sequence. [6] Device according to claim 4, wherein the calibration test includes an initial reduction target test using an initial reduction target test input value, and The first reduction target test input value is a value that is adjusted so that after passing through the divider circuit it has the following properties: The internal upper bit sequence is a different value than the first fixed bit sequence. The internal lower bit sequence is a different value than the second fixed bit sequence, and the number of test pairs to be used in the first reduction target test is 2. N - (2 K +2 M+1 ) amounts. [7] Device according to claim 1, wherein The correction target DA converter element has a divider circuit that outputs an internal upper bit sequence of K bits and an internal lower bit sequence of M bits, based on an input value from an input terminal and a binary format assumed by the element. the internal upper bit sequence is entered into the circuit segment of the first type, the internal lower bit sequence is entered into the circuit segment of the second type, The circuit segment of the first type comprises a multitude of circuits of the first type and a selector circuit. The selector circuit is a circuit that selects one of the circuits of the first type according to the internal upper bit sequence, outputs an active signal to the selected circuit of the first type, and outputs an inactive signal to the unselected circuit of the first type. Each of the circuits of the first type contains a circuit element for outputting an analog value according to a weight of the internal upper bit sequence and the active signal or the inactive signal, The circuit segment of the second type is a segment that has a circuit of the second type corresponding to each of the bits of the internal lower bit sequence, and adds analog values ​​output by each of the circuits of the second type to obtain an output value as a segment, and The circuit of the first type contains a circuit element for outputting the analog value according to the weight of the bit and an active / inactive state specified by the bit. [8] Device according to claim 7, wherein the updating of the correction data in (B) or the generation of the test input value is performed based on the following for an input terminal bit sequence, which is a bit sequence to which the correction DA converter element is input at an input terminal: a relationship between 0 / 1 of a bit group contained in the input terminal bit sequence and the active / inactive state of the plurality of circuits of the first type and the plurality of circuits of the second type. [9] Device according to claim 8, wherein the number of test pairs acquired during the calibration test period is equal to or greater than the sum of the number of circuits of the first type and the number of circuits of the second type. [10] Device according to claim 1, wherein the circuit segment of the first type is a thermometer circuit segment, and The circuit segment of the second type is a binary or ladder circuit segment. [11] Device according to claim 1, wherein the pre-stage circuit stores as correction data a first table for managing a correction amount derived from the circuit segment of the first type and a second table for managing a correction amount derived from the circuit segment of the second type. [12] Device according to claim 1, wherein The main circuit is a circuit that performs a DA conversion of N+1 bits or more by using a sub-DA converter element responsible for a lower order, in addition to the correction target DA converter element responsible for a higher order. the pre-stage circuit includes a divider circuit or divider wiring that receives the DA conversion target value and divides and outputs an upper DA conversion target value and a lower DA conversion target value, a correction circuit that outputs a correction amount obtained based on the upper DA conversion target value and the correction data, and an addition circuit that adds the correction amount and the lower DA conversion target value and outputs the corrected lower DA conversion target value, The correction target DA converter element sets the upper DA conversion target value as the conversion target. the sub-DA converter element sets the corrected lower DA conversion target value as the conversion target, and The main circuit includes a weighted addition circuit that performs a weighted addition of an analog value output by the correction target DA converter element and an analog value output by the sub DA converter element to output an analog value. [13] Device according to claim 9, wherein the main circuit includes wiring that outputs the analog value output by the weighted addition circuit as the main output analog value. [14] Device according to claim 9, wherein the main circuit includes an amplifier circuit that amplifies the analog value output by the weighted addition circuit, and A wiring configuration that outputs an analog value amplified by the amplifier circuit as the main output analog value. [15] Device according to claim 1, wherein the pre-stage circuit includes a correction circuit that receives the processor output bit sequence and outputs a correction amount bit sequence based on the correction data, and an addition circuit that adds the correction amount bit sequence and the processor output bit sequence and outputs the main input bit sequence. [16] Device according to claim 1, wherein the pre-stage circuit includes a correction circuit which receives the processor output bit sequence and outputs the main input bit sequence based on the correction data. [17] Charged particle beam device comprising: a charged particle source configured to produce a charged particle beam; a deflector configured to deflect the charged particle beam; and the device according to claims 1 to 16 as a controller configured to control the deflector. [18] Device comprising at least: a main circuit containing one or more DA converter elements and configured to convert a main input bit sequence, which is a received bit sequence, into a main output analog value, which is an analog value, and output the main output analog value; a processor configured to output a processor output bit sequence; a pre-stage circuit configured to receive the processor output bit sequence and output the main input bit sequence; and an AD converter, whereby The pre-stage circuit corrects the processor output bit sequence based on correction data and outputs the main input bit sequence. the main circuit contains an amplifier circuit that amplifies an analog value output by the DA converter element and outputs the amplified analog value as the main output analog value, and the processor (A) acquires a plurality of pairs consisting of a test bit sequence and a test result bit sequence with the following properties: (A1) The test bit sequence is the processor output bit sequence or the main input bit sequence for a calibration test, (A2) The test result bit sequence is acquired by converting the main output analog value through the A / D converter, and (B) the correction data is updated based on the multitude of pairs in (A).

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