METHOD FOR UNITING MICROELCONY COMPONENT PACKAGES BY ATTACHING MICROELCONY CHIPS TO A CONDUCTOR BOARD AND ASSOCIATED STRUCTURES

Abstract

The methods can involve mounting a plurality of microelectronic chips onto a printed circuit board (PCB). The individual microelectronic chips within the plurality of chips can be electrically connected via at least one via on the PCB. Microelectronic component packages can be isolated from the PCB, each package comprising at least one microelectronic chip from the plurality of chips and a section of the PCB. The structures can include multiple microelectronic chips mounted on a PCB. The PCB can include vias, with subsets of the vias positioned for electrical connection to a specific microelectronic chip within the plurality of chips.

Description

PRIORITY CLAIM

[0001] This application claims the benefit of the filing date of the preliminary US patent application No. 63 / 497,134, filed on April 19, 2023, for “Methods of Packaging Microelectronic Devices Utilizing Panels and Related Temporary Structures”, the disclosure of which is hereby incorporated in its entirety by this reference. TECHNICAL AREA

[0002] This disclosure relates generally to methods for packaging microelectronic components using boards and associated temporary structures. More specifically, the disclosed examples relate to packaging techniques for microelectronic components that reduce costs and waste, increase reliability and yield, and require fewer process steps compared to board-level packaging techniques known to the inventor. BACKGROUND

[0003] The inventor is aware of several attempts to package microelectronic components at the wafer level. Generally, these techniques involve singulating microelectronic components from wafers, arranging the components in an array within a rectangular or square frame, and encapsulating the components in a dielectric material to form a wafer. The wafer containing the components can be mounted on a rigid substrate, such as stainless steel or glass. After wafer formation, additional processing steps, such as signal routing (e.g., fan-out processes), can be performed on the components. The substrate can be removed from the wafer prior to singulating individual component packages. REVELATION

[0004] In some examples, the methods may involve mounting a plurality of microelectronic chips onto a printed circuit board (PCB). The individual microelectronic chips within the plurality of chips may be electronically connected via at least one via on the PCB. Microelectronic component packages may be isolated from the PCB, each package comprising at least one microelectronic chip from the plurality of chips and a section of the PCB.

[0005] In other examples, temporary structures can enclose a multitude of microelectronic chips mounted on a printed circuit board. The circuit board can include vias, with subsets of the vias positioned for electrical connection to each of the multitude of microelectronic chips.

[0006] In other examples, the methods may involve the formation of a rewiring layer on a printed circuit board (PCB) in conjunction with vias on the PCB. A multitude of microelectronic chips may be mounted on the rewiring layer. The individual microelectronic chips within this multitude may be electronically connected to the rewiring layer. Microelectronic component packages may be isolated from the PCB, with each package comprising at least one microelectronic chip from the multitude and a section of the PCB. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] While this disclosure concludes with claims that particularly highlight and explicitly claim certain examples, various features and advantages of examples within the scope of this disclosure can be more readily derived from the following description when read in conjunction with the accompanying drawings. In the drawings: Fig. Figure 1 is a flowchart of a process for packaging microelectronic components; Fig. Figure 2 is a flowchart of another method for packaging microelectronic components; Fig. 3 is a surface view of a printed circuit board; Fig. Figure 4 is a perspective side view of a section of the printed circuit board. Fig. 3; Fig. Figure 5 is a cross-sectional side view of a temporary structure in a first phase of one of the procedures of Fig. 1 or Fig. 2; Fig. Figure 6 is a cross-sectional side view of a microelectronics chip; Fig. Figure 7 is a cross-sectional side view of another temporary structure in a second phase of the procedure of Fig. 1 or Fig. 2; Fig. Figure 8 is a cross-sectional side view of another temporary structure in a third phase of the process of Fig. 1 or Fig. 2; Fig. Figure 9 is a cross-sectional side view of a microelectronic component package; Fig. Figure 10 is a flowchart of another method for packaging microelectronic components; Fig. Figure 11 is a cross-sectional side view of a temporary structure in a first phase of the procedure of Fig. 1 or Fig. 10; Fig. Figure 12 is a cross-sectional side view of another microelectronics chip; Fig. Figure 13 is a cross-sectional side view of another temporary structure in a second phase of the procedure of Fig. 1 or Fig. 10; Fig. Figure 14 is a cross-sectional side view of another temporary structure in a third phase of the procedure of Fig. 1 or Fig. 10; Fig. Figure 15 is a cross-sectional side view of another temporary structure in a fourth phase of the procedure of Fig. 1 or Fig. 10; Fig. Figure 16 is a cross-sectional side view of another temporary structure in a fifth phase of the procedure of Fig. 1 or Fig. 10; Fig. Figure 17 is a flowchart of another method for packaging microelectronic components; Fig. Figure 18 is a surface view of another microelectronics component package; Fig. Figure 19 is a cross-sectional view of a section of another printed circuit board; Fig. 20 is a cross-sectional side view of a temporary structure in a first phase of the process of Fig. 1 or Fig. 17; Fig. Figure 21 is a cross-sectional side view of another temporary structure in a second phase of the procedure of Fig. 1 or Fig. 17; and Fig. Figure 22 is a flowchart of another method for packaging microelectronic components. FORMS OF THE INVENTION

[0008] The illustrations presented in this disclosure are not intended to be actual views of any particular printed circuit board, microelectronic device, microelectronic device package, temporary structure in a method for manufacturing a microelectronic device package, or any component thereof, but are merely idealized representations used to describe the illustrative examples. Therefore, the drawings are not necessarily to scale.

[0009] The disclosed examples generally relate to techniques for packaging microelectronic components using printed circuit boards (PCBs). Such techniques can reduce costs and waste, increase reliability and yield, and require fewer process steps compared to board-level packaging techniques known to the inventor. More specifically, examples of PCBs and methods for using PCBs to fabricate multiple microelectronic component packages are disclosed. For example, methods for fabricating microelectronic component packages according to this disclosure may involve mounting a plurality of microelectronic chips onto a PCB. The individual microelectronic chips of the plurality of microelectronic chips may be electrically connected via at least one via on the PCB.Microelectronic component packages can be separated from the printed circuit board, with each microelectronic component package including at least one microelectronic chip of the plurality of microelectronic chips and a section of the printed circuit board.

[0010] In some examples, the packaging techniques may involve forming a rewiring layer on the printed circuit board (PCB) in conjunction with the vias before the multitude of microelectronic chips are placed on the PCB. In such examples, placing the multitude of microelectronic chips on the PCB may involve placing them on the rewiring layer. Forming the rewiring layer can be achieved, for example, by positioning electrically conductive rewiring material on areas of the PCB between the vias.Electrically connecting the individual microelectronic chips of the multitude of microelectronic chips to the at least one via on the printed circuit board (PCB) can, for example, involve melting electrically conductive material extending from the individual microelectronic chips to the over-wiring layer. More precisely, the melting of the electrically conductive material can be achieved, for example, by directing the energy emitted by a laser onto the electrically conductive material to melt it. In some examples consistent with the above, the multitude of microelectronic chips can be placed in flip-chip orientations when mounted on the PCB.

[0011] In other examples, active surfaces of the microelectronic chip array can be positioned on the sides of the array facing away from the printed circuit board (PCB) when the array is mounted on the PCB. A first rewiring layer can be formed on the PCB and electrically connected to the vias before the array of microelectronic chips is mounted. This first rewiring layer can contain studs of electrically conductive material, with the studs having a height above the PCB that is at least equal to the greatest thickness of any microelectronic chip in the array. The microelectronic chips can be mounted on sections of the rewiring layer between the studs.In some examples, a molding material can be placed around the multitude of microelectronic components and around at least sections of the studs. A second wiring layer can be formed on the molding material, which is electrically connected to the studs and to the multitude of microelectronic components. A passivation material can cover the second wiring layer.

[0012] In some examples, the isolation of the microelectronic component packages from the printed circuit board may involve isolating the microelectronic component packages such that at least some of the microelectronic component packages include bond pads located on a side of at least some of the microelectronic component packages facing away from the microelectronic component, and along the respective sides of the periphery of at least some of the microelectronic component packages. In other examples, the isolation of the microelectronic component packages from the printed circuit board may involve isolating the microelectronic component packages such that at least some of the microelectronic component packages include bond pads arranged in a grid.

[0013] Some exemplary processes may not require wire bonding, steel or glass substrates, or substrate debonding processes, or any combination or subcombination of these processes may be omitted. Some exemplary processes may not require processes involving wire bonding, steel or glass substrates, or substrate debonding, nor any combination or subcombination of these processes. Some other exemplary processes may use steel or glass substrates, substrate debonding processes, or steel or glass substrates and substrate debonding processes.

[0014] Temporary structures formed during board-level microelectronic component packaging processes can enclose a multitude of microelectronic chips mounted on a printed circuit board (PCB). The PCB may include vias, and subsets of these vias can be positioned for electrical connection to a specific microelectronic chip within the multitude of microelectronic chips. For example, the subset of vias themselves, or electrically conductive material electrically connected to the vias, can be positioned, sized, shaped, and oriented to align with the corresponding electrically conductive elements of the microelectronic components to be mounted on the PCB, thus facilitating electrical connection.

[0015] In some examples, the footprints of the microelectronic chips cover at least some of the vias on the printed circuit board (PCB). In other examples, the vias may be located outside the footprints of the microelectronic chips. At least some of the vias may be covered and at least partially hollow. The spacing of the PCB vias can range from 0.65 mm to 1 mm. The PCB dimensions can be, for example, 300 mm x 300 mm, 510 mm x 510 mm, 510 mm x 515 mm, 515 mm x 515 mm, or 600 mm x 600 mm.

[0016] In this context, the term "printed circuit board" refers to and encompasses a circuit board that is dimensioned, shaped, and configured to support a multitude of microelectronic components, is permanently electrically connected to these components, is isolated into package substrates when forming microelectronic component packages, and features vias for connection to the microelectronic components. For example, printed circuit boards can have a polygonal shape when viewed from the surface (e.g.,rectangular, square, without restriction), can define package positions with vias located therein, can accommodate at least one microelectronic component within a respective package location, can have the vias of the respective package position connected to the microelectronic component(s) and can be separated to form resulting microelectronic component packages.

[0017] As used herein, the terms “essentially” and “approximately” with respect to a given parameter, property, or condition mean that the given parameter, property, or condition is satisfied to a degree of variance, such as within acceptable manufacturing tolerances, and include this to an extent that would be understood by those skilled in the art. For example, a parameter that is essentially or approximately a specified value may be at least approximately 90% of the specified value, at least approximately 95% of the specified value, at least approximately 99% of the specified value, or even at least approximately 99.9% of the specified value.

[0018] Fig. Figure 1 is a flowchart of a process 100 for packaging microelectronic components. The process 200 may, for example, involve mounting a plurality of microelectronic chips onto a printed circuit board, as described in process 102. The individual microelectronic chips of the plurality of microelectronic chips may be electrically connected by at least one via on the printed circuit board, as described in process 104. Microelectronic component packages may be separated from the printed circuit board, wherein the individual microelectronic component packages include at least one microelectronic chip of the plurality of microelectronic chips and a section of the printed circuit board, as described in process 106.

[0019] By processing at the plate level, as in Fig. As shown in Figure 1, costs can be saved because disk-level processing can involve the simultaneous and / or sequential execution of repeated processing operations to produce many microelectronic component packages. Unlike wafer-level processing, disk-level processing can utilize microelectronic chips that have already been isolated from the wafer of the material from which these microelectronic chips were manufactured. Optionally, the microelectronic chips can be tested so that further processing and packaging can be performed only on microelectronic chips that function according to specifications and are sometimes referred to as "known good chips."The microelectronic chips can be mounted on a molded material or otherwise arranged and interconnected to form a plate whose dimensions are larger than the dimensions of the wafer(s) from which the microelectronic chips were isolated. This allows a larger number of microelectronic chips to be packaged.

[0020] Unlike certain plate-level packaging techniques known to the inventor, in which microelectronic chips are glued to a substrate, the microelectronic chips are joined together in a molding material to form a plate, and the plate is subsequently removed from the substrate, the method involves 100 of Fig. 1. A printed circuit board. Printed circuit boards according to this disclosure can reduce or eliminate the number of process steps performed when using other substrates and can be designed to make permanent connections with the microelectronic chips mounted thereon and electrically connected to them. The printed circuit boards can also be singulated during the singulation of the microelectronic component packages, so that the respective microelectronic component packages can enclose a section of the printed circuit board that is used in their packaging process.

[0021] Fig. Figure 2 is a flowchart of another, more specific procedure 200 for packaging microelectronic components. As in Fig. As set out in section 2, procedure 200 encompasses those related to procedure 100. Fig. 1. The processes performed, as well as several other optional processes indicated by dashed lines. Similar to procedure 100 of Fig. 1. The procedure can be 200 of Fig. 2 involves attaching a large number of microelectronic chips to a printed circuit board, as shown in Procedure 202.

[0022] Fig. Figure 3 is a surface view of a printed circuit board 300, which can illustrate an example of a printed circuit board 300 produced in method 200 of Fig. 2 can be used, such as in the execution of process 202 and other processes involving a printed circuit board 300. The printed circuit board 300 can include materials and be manufactured using techniques known to those skilled in the art for use with printed circuit boards. For example, the printed circuit board 300 can include selectively positioned electrically conductive and dielectric materials for making and / or routing electrical connections. In some examples, such as the one in Fig. As shown in Figure 3, the printed circuit board 300 can include at least one mass (e.g., a layer, without limitation) of dielectric material 302 and a plurality of vias 304 extending through the dielectric material 302. At least some of the vias 304 can be exposed or have exposed pads 306 to establish and conduct electrical connections between opposing main surfaces 308 of the printed circuit board 300. In some examples, the printed circuit boards 300 according to this disclosure may lack conductive traces for routing electrical connections. The printed circuit board 300 and its vias 304 can define a plurality of packaging positions, respective packaging positions for receiving one or more microelectronic chips and forming a respective microelectronic component package.

[0023] In other examples, printed circuit boards according to this disclosure can include conductive traces for making electrical connections. More specifically, the printed circuit boards can, for example, include traces of electrically conductive material (e.g., etched foil of copper, gold, aluminum, alloys with one or more of these materials, without limitation) on one or more major surfaces of the printed circuit boards and / or laminated between layers of the dielectric material. In some examples where the printed circuit boards include conductive traces, the printed circuit boards may lack vias that would extend completely through the thickness of the printed circuit boards, and they may have partial vias that connect from a major surface 308 to a conductive trace on an intermediate layer of dielectric material and / or pads associated with the conductive traces.In other examples, the vias 304 of the printed circuit boards can be through-hole connections.

[0024] The main surface 308 of the printed circuit board 300 can have a larger surface area than the surface area of ​​a wafer from which the microelectronic chips mounted on the printed circuit board 300 can be isolated. For example, the surface area of ​​the main surface 308 of the printed circuit board 300 can be between approximately 90,000 mm². 2 and approximately 360,000 mm 2 exhibit. More precisely, the surface area of ​​the main surface 308 of the printed circuit board 300 can be between approximately 260,100 mm². 2 and approximately 360,000 mm 2 exhibit. As a specific, non-restrictive example, the surface area of ​​the main area 308 of the printed circuit board 300 can be between approximately 262,650 mm². 2 and approximately 360,000 mm 2 (e.g., approximately 265,225 mm) 2 , without restriction).

[0025] When viewed in a surface view, as in Fig. 3. The perimeter of the main surface 308 of the printed circuit board 300 can have a different shape than the shape of a wafer from which microelectronic chips to be mounted on the printed circuit board 300 can be separated. For example, wafers from which microelectronic chips are cut can generally have a circular shape when viewed in a surface view, whereas the printed circuit board 300 can have a polygonal shape with at least four sides and four interior angles when viewed in a surface view. More precisely, the perimeter of the main surface 308 of the printed circuit board 300 can form a rectangle, a square, or another polygon when viewed in a surface view.

[0026] In examples where the printed circuit board 300 is rectangular or square when viewed in a surface view, the dimensions of the printed circuit board 300 can, for example, range from approximately 300 mm x 300 mm to approximately 600 mm x 600 mm. More precisely, the dimensions of the printed circuit board 300 can, for example, range from approximately 510 mm x 510 mm to approximately 515 mm x 515 mm. As a specific, non-restrictive example, the dimensions of the printed circuit board 300 can be approximately 510 mm x 515 mm.

[0027] In some examples, such as the one in Fig. As shown in Figure 3, the vias 304 can be arranged in an array or other repeating pattern distributed across the main surface 308 of the printed circuit board 300. For example, the vias 304 can form a grid that includes rows and columns of vias 304 arranged in repeating patterns. In some of these examples, the printed circuit board 300 can conform to a standardized spacing and distribution of the vias 304, forming a pattern that can be used with a wide variety of microelectronic chips to be packaged, requiring little or no custom layout or signal routing. In other examples, the vias can be positioned in a custom layout to facilitate the packaging of specific microelectronic chips.

[0028] The spacing of the vias 304 on the printed circuit board 300, measured by calculating the average of the shortest distances between the centers of adjacent vias 304 in the respective rows and columns, can, for example, be between approximately 0.65 mm and approximately 1 mm. More precisely, the spacing of the vias 304 can, for example, be between approximately 0.7 mm and approximately 0.95 mm. As a specific, non-restrictive example, the spacing of the vias 304 can be between approximately 0.75 mm and approximately 0.9 mm (e.g., approximately 0.8 mm, approximately 0.85 mm, without restriction). Therefore, the number and size of the vias 304 are relative to the size of the Fig. The circuit board 300 shown in the diagram may not be to scale.

[0029] Fig. Figure 4 is a cross-sectional side view of a section of the printed circuit board 300. Fig. 3. The one in Fig. Section 4 shown can correspond to a package position 400 of the printed circuit board 300, and the printed circuit board 300 can include a plurality of such package positions 400. For example, the package positions 400 can be distributed in a grid or other arrangement on the main surface 308 of the printed circuit board 300, thereby enabling the simultaneous packaging of multiple microelectronic component packages, with each microelectronic component package located at its own package position 400.

[0030] In some examples, the printed circuit board 300 may include fixed vias 304, which have a solid mass of electrically conductive material located in holes 402 that extend partially or completely through the printed circuit board 300. As in Fig. As shown in Figure 4, there can be a single mass (e.g., layer, without limitation) of dielectric material 302 having a plurality of holes 402 extending completely through the dielectric material 302 of the printed circuit board 300. In other examples, the vias can be hollow and have electrically conductive material lining the surfaces of the dielectric material 302 defining the holes 402, as well as volumes within the electrically conductive material that can be filled with ambient fluid (e.g., air, an inert gas, without limitation) or filled with a filler material (e.g., flux, without limitation).In some of these examples, the hollow vias can be covered by, for example, at least temporarily applying a covering material over the hollow section of the vias, thereby blocking the passage of liquid through the hollow section of the vias, which can facilitate the application of pressure in certain packaging and handling techniques (e.g., vacuum handling, without restriction).

[0031] Back to Fig. 2: Method 200 may involve forming a rewiring layer on the printed circuit board (PCB), wherein the rewiring layer is electrically connected to the at least one via of the PCB before any microelectronic chips are placed on the PCB, as described in Procedure 204. Forming the rewiring layer may involve positioning electrically conductive rewiring layer material on areas of the PCB between vias of the PCB, including the at least one via, as described in Procedure 206. For example, a cover material (e.g., a photoresist material, without limitation) may be positioned on the main surface of the PCB, and sections of the cover material may be selectively removed (e.g.,Electrically conductive material can be positioned on the main surface in areas exposed by selectively removing sections of the covering material (e.g., by a plating process, without limitation) and the remaining covering material can be removed (e.g., by exposure to a solvent, without limitation).

[0032] Fig. Figure 5 is a cross-sectional side view of a temporary structure 500 in a first phase of one of the procedures 100 of Fig. 1 or of procedure 200 of Fig. 2. In particular, the temporary structure shows 500 of Fig. 5 the package position 400 of the circuit board 300 after carrying out operation 204 and operation 206 of procedure 200 of Fig. 2. The temporary structure 500 can include a rewiring layer 502 positioned on the main surface 308 of the printed circuit board 300. The rewiring layer 502 can consist of or include conductor tracks 504 made of an electrically conductive material, which are applied to the main surface 308 of the printed circuit board 300. The conductor tracks 504 of the rewiring layer 502 can be located mainly between and below the vias 304. For example, the conductor tracks 504 can be applied mainly to the dielectric material 302 of the printed circuit board 300 and be electrically connected to the vias 304. In examples where the vias 304 include pads 306, sections of the electrically conductive material of the rewiring layer 502 can extend between the pads 306 (e.g.,from surfaces of the pads 306, which are distal to the dielectric material 302 of the circuit board 300, to the main surface 308 of the circuit board 300, without restriction) and the conductor tracks 504 can be positioned to electrically connect the pads 306 to one or more corresponding microelectronic components.

[0033] Fig. Figure 6 is a cross-sectional side view of a microelectronic chip 600. The microelectronic chip 600 can carry an integrated circuit that is mounted on and / or embedded in a material of the microelectronic chip 600. For example, the microelectronic chip 600 can include a semiconductor material that can be doped to form at least part of the integrated circuit of the microelectronic chip 600. The microelectronic chip 600 can include electrically conductive elements 602 in electrical connection with the integrated circuit, which are mounted on a major surface 604 of the microelectronic chip 600 and positioned to connect the integrated circuit of the microelectronic chip 600 to a higher-level packaging. For example, the electrically conductive elements 602 can be columns, posts, pillars, beads, spheres, or other masses of electrically conductive material (e.g.,Electrically conductive elements may include copper, gold, aluminium, tin, silver, alloys including the foregoing, solder (without limitation), at least one section of which may be remeltable. As specific, non-restrictive examples, electrically conductive elements 602 may include copper columns covered with and / or tipped with a solder material, which may be referred to in technical terms as a ‘copper column bead’, or may include solder beads.

[0034] Back to Fig. 2: Procedure 200 may involve placing the plurality of microelectronic chips in flip-chip orientations when the plurality of microelectronic chips are mounted on the printed circuit board, as specified in Procedure 202 and Procedure 208. For example, a placement operation may be performed to remove microelectronic chips 600 (e.g.,one after the other or one after the other per handling mechanism of a placement machine, without restriction), to align the microelectronic chips 600 such that electrically conductive elements of the microelectronic chips 600 point towards the circuit board 300 and the rewiring layer 502 applied thereto, to align the electrically conductive elements 602 with sections of the rewiring layer 502 which are positioned for electrical connection with the microelectronic chips 600, and to position at least one microelectronic chip 600 at the respective package positions on the circuit board 300.

[0035] Fig. Figure 7 is a cross-sectional side view of another temporary structure 700 in a second phase of the procedure 100 of Fig. 1 or of procedure 200 of Fig. 2. The temporary structure 700 of Fig. Figure 7 shows the package position 400 of the circuit board 300 after performing at least operation 202 and operation 208 of procedure 200. Fig. 2. The temporary structure 700 can enclose the microelectronic chip 600, which is placed on the same side of the circuit board 300 as the rewiring layer 502.

[0036] More precisely, the electrically conductive elements 602 of the microelectronic chip 600 can, for example, be located on one side of the microelectronic chip 600 near the circuit board 300, and the electrically conductive elements 602 can be in contact with and attached to the conductor tracks 504 of the rewiring layer 502, the pads 306 of the vias 304 or other electrically conductive structures of the rewiring layer 502 or the vias 304 or both.

[0037] In some examples where the electrically conductive elements 602 of the microelectronic chip 600 include a flowable material (e.g., solder, without limitation), the electrical connection of the microelectronic chip 600 to at least one via 304 of the printed circuit board 300, as described in Procedure 210, may involve the melting of electrically conductive material extending from the microelectronic chip 600 to the rewiring layer 502.Since processing at the plate level can be considered, the process in which the flowable material is brought into contact with or at least near the rewiring layer 502 and / or the vias 304, the flowable material is remelted, and the flowable material electrically connects the electrically conductive elements 602 of the microelectronic chip 600, can be carried out for a large number of such microelectronic chips 600, as in process 212 in . Fig. 2 indicated.

[0038] Melting the flowable material can generally involve exposing the flowable material of the electrically conductive elements 602 to one or more heat sources. As an example, the energy emitted by a laser 702 can be directed onto the flowable, electrically conductive material of the electrically conductive elements 602, as in process 214 in Fig. 2. To reduce the risk of damage to the integrated circuit of the microelectronic chip 600, the energy emitted by the laser 702 can have a certain intensity, and the duration of exposure to the energy emitted by the laser 702 can be sufficiently short so that the temperatures in the material of the microelectronic chip 600 can remain below a defined threshold. The energy emitted by the laser 702 can be directed onto different areas of the printed circuit board 300, enabling the laser 702 to melt corresponding amounts of the flowable, electrically conductive material of the electrically conductive elements 602. For example, the laser 702 can be mounted on a movable frame and follow a grid pattern when melting the flowable, electrically conductive material of the electrically conductive elements 602.In other examples of the methods, in which the flowable, electrically conductive material of the electrically conductive elements 602 is exposed to one or more heat sources, the printed circuit board 300 and the associated electrically conductive elements 602 can be placed in an oven. In other examples of the methods for melting flowable, electrically conductive material, the flowable, electrically conductive material of the electrically conductive elements 602 can be exposed to vibrational energy, such that the friction between the electrically conductive elements 602 and any contact material can heat the electrically conductive elements 602 to melt the flowable, electrically conductive material of the electrically conductive elements 602.

[0039] In examples where a multitude of microelectronic chips 600 are mounted on the printed circuit board 300, subsets of the vias 304 can be positioned for electrical connection with each of the multitude of microelectronic chips 600. For example, the respective package positions 400 of the printed circuit board 300 can include some vias 304 within the footprint of the package position 400, with at least one via 304 being positioned for electrical connection with one or more microelectronic chips 600 to form a microelectronic component that is to be isolated from the printed circuit board 300. In other words, the package positions 400 can subdivide and define the subsets of the vias 304.

[0040] In some examples, the footprints of the microelectronic chips 600 of the plurality of microelectronic chips 600 can cover at least some of the vias 304 of the printed circuit board 300. As an example, the spacing of the vias 304, measured and defined by the shortest distance between the centers of adjacent vias 304 in a direction that is at least substantially parallel to the main surface 308 of the printed circuit board 300, can be smaller than the footprint of a microelectronic chip 600, and the vias 304 can be distributed such that at least some of the vias 304 lie under an associated microelectronic chip 600.More precisely, the vias 304 can be distributed in a pattern resembling the nodes of a grid, and placing the microelectronic chip 600 over the main surface 308 of the circuit board 300 can cause the microelectronic chip 600 to cover at least some of the vias 304 within the package position 400.

[0041] Fig. Figure 8 is a cross-sectional side view of another temporary structure 800 in a third phase of the procedure 100 of Fig. 1 or of procedure 200 of Fig. 2. In some examples, such as the one in Fig. As shown in Figure 8, an underfill material 802 can be placed between the microelectronic chip 600 and the printed circuit board 300. For example, the underfill material 802 can initially be in a flowable state and be distributed or otherwise positioned so that it flows under the microelectronic chip 600 and around sections of the main surface 308 of the printed circuit board 300, the rewiring layer 502, and the electrically conductive elements 602. The underfill material 802 can enclose a curable polymer material that can subsequently be cured. In some examples, the heat from curing the underfill material 802 can be sufficient to remelt the flowable, electrically conductive material of the electrically conductive elements 602. The underfill material 802 can, for example, enclose any underfill material 802 known in the art.As with other processes, the process of positioning the underfill material 802 between the microelectronic chip 600 and the circuit board 300 can be repeated for at least some and up to all of the microelectronic chips 600 mounted on the circuit board 300. In other examples, no underfill material 802 may be positioned between one or more of the microelectronic chips 600 and the circuit board 300.

[0042] To reiterate Fig. Returning to point 2: Method 200 may involve separating microelectronic component packages from the printed circuit board, as specified in Procedure 216. The respective microelectronic component packages may include at least one microelectronic chip of the plurality of microelectronic chips and a section of the printed circuit board, as further specified in Procedure 216. More specifically, Method 200 may, for example, involve separating the microelectronic component packages such that at least some of the microelectronic component packages include bond pads arranged in a grid, as specified in Procedure 218. As a specific, non-limiting example, a saw or saws may be used to cut the printed circuit board along lines between selected rows and columns of the grid of vias, thus separating individual package positions 400 from one another to form microelectronic component packages.

[0043] Fig. Figure 9 is a cross-sectional side view of a 900 series microelectronic component package. The 900 series microelectronic component package from Fig. Figure 9 shows the package position 400 of the printed circuit board after performing at least steps 216 and 218 of procedure 200. Fig. 2. The microelectronic component package 900 can, for example, include at least one microelectronic chip 600, which is mounted on a package position 400 defined by a section of the printed circuit board 300 and is electrically connected to it. The package position 400 can include vias 304, a rewiring layer 502 electrically connected to the vias 304, and electrically conductive elements 602 that electrically connect the microelectronic chip 600 to the rewiring layer 502. An underfill material 802 can be inserted between the microelectronic chip 600 and the section of the printed circuit board 300.In some examples, the microelectronic component package 900 can include an encapsulation material that encapsulates the respective microelectronic chips 600 and at least a section of the rewiring layer 502 and the main surface 308 of the section of the printed circuit board 300 located outside the footprint of the respective microelectronic chip 600. In some examples, the microelectronic component package 900 can include a thermal management structure, such as a heat spreader, a heat sink, or another thermal management structure known in the art, arranged on the microelectronic component package 900 (e.g., in contact with the microelectronic chip 600, without limitation).

[0044] The microelectronic component package 900 can include conductive elements 902 positioned to connect the microelectronic component package 900 to a higher-level package. For example, the conductive elements 902 of the microelectronic component package 900 can include masses of electrically conductive material electrically connected to and attached to sections of the vias 304 on one side of the printed circuit board section 300 facing away from the microelectronic chip 600. More specifically, the conductive elements 902 can include beads, spheres, columns, columns, or other known shapes and configurations containing electrically conductive material (e.g., solder, without limitation).

[0045] Fig. 10 is similar to Fig. 2, a flowchart of another, more specific procedure 1000 for packaging microelectronic components. As in Fig. As set out in section 10, procedure 1000 includes those related to procedure 100 of Fig. 1. The processes performed, as well as several other optional processes indicated by dashed lines. Similar to procedure 100 of Fig. 1. The procedure can be 1000 of Fig. 10. Method 1000 includes the placement of a plurality of microelectronic chips on a printed circuit board, as shown in Process 1002. Method 1000 may further include the formation of a first rewiring layer on the printed circuit board and in electrical connection with the vias before the plurality of microelectronic chips is placed on the printed circuit board, as described in Process 1004. The first rewiring layer may include distribution layer studs made of electrically conductive material, the studs having a height above the printed circuit board that is at least as great as the greatest thickness of any microelectronic chip from the plurality of microelectronic chips, as described in Process 1004.Forming the rewiring layer may involve performing all the actions previously described in connection with Operation 206 and may further involve building up sections of electrically conductive material to form the bolts or positioning preformed bolts enclosing electrically conductive material on sections of the rewiring layer.

[0046] Fig. Figure 11 is a cross-sectional side view of a temporary structure 1100 in a first phase of the procedure 100 of Fig. 1 or of the procedure 1000 of Fig. 10. More precisely, the temporary structure represents 1100 of Fig. 11 a package position 1102 of the circuit board 300 after execution of operation 1004 of procedure 1000 of Fig. Figure 10. The temporary structure 1100 can include a first rewiring layer 1104 positioned on the main surface 308 of the printed circuit board 300. The first rewiring layer 1104 can include conductor tracks 1106 made of an electrically conductive material, or such a material can be attached to the main surface 308 of the printed circuit board 300. The first rewiring layer 1104 can further include distribution layer studs 1108 that enclose electrically conductive material. The distribution layer studs 1108 can have a height 1110 above the printed circuit board 300, measured in a direction that is at least substantially perpendicular to the main surface 308 of the printed circuit board 300 and that is at least as great as the greatest thickness of any microelectronic chip of the plurality of microelectronic chips. The bolts 1108 of the distribution layer can be attached to and extend from the conductor tracks 1106.

[0047] The conductor tracks 1106 and the distribution layer studs 1108 of the first rewiring layer 1104 can be located mainly between and below the vias 304. For example, the conductor tracks 1106 can be mainly attached to the dielectric material 302 of the printed circuit board 300 and electrically connected to the vias 304. In examples where the vias 304 enclose pads 306, sections of the electrically conductive material of the first rewiring layer 1104 can extend to the pads 306 (e.g., to surfaces of the pads 306 distal to the dielectric material 302 of the printed circuit board 300, without limitation) to electrically connect the conductor tracks 1106 and the distribution layer studs 1108 to the pads 306 and thereby to the vias 304.

[0048] Fig. Figure 12 is a cross-sectional side view of another microelectronics chip 1200; the microelectronics chip 1200 can carry integrated circuits mounted on and / or embedded in a material of the microelectronics chip 1200, as previously described in connection with the microelectronics chip 600. Fig. 6. The microelectronics chip 1200 can include microelectronic chip studs 1202 in electrical connection with the integrated circuit, which are mounted on a main surface 1204 of the microelectronics chip 1200 and are positioned to connect the integrated circuit of the microelectronics chip 1200 to a higher-level package. For example, the microelectronic chip studs 1202 can be taller, measured in a direction that is at least substantially perpendicular to the main surface 1204, than they are wide, measured in a direction that is at least substantially parallel to the main surface 1204.In some examples, the microelectronic chip studs 1202 can be at least substantially free of flowable, electrically conductive material, wherein the electrically conductive material of the microelectronic chip studs 1202 is configured such that it does not remelt after being positioned on the main surface 1204 of the microelectronic chip 1200.

[0049] Back to Fig. 10: Method 1000 may involve positioning the active surfaces of the plurality of microelectronic chips so that they face away from the printed circuit board when the plurality of microelectronic chips is mounted on the printed circuit board, as described in Method 1006. The positioning may, for example, be performed using one of the methods previously described in connection with Fig. The two discussed techniques will be used.

[0050] Fig. Figure 13 is a cross-sectional side view of another temporary structure 1300 in a second phase of procedure 100 of Fig. 1 or of the procedure 1000 of Fig. 10. The temporary structure 1300 of Fig. Figure 13 shows the package position 1102 of the circuit board 300 after performing at least operation 1006 of procedure 1000. Fig. 10. The temporary structure 1300 can enclose the microelectronic chip 1200, which is mounted on the same side of the printed circuit board 300 as the first rewiring layer 1104. The microelectronic chip studs 1202 of the microelectronic chip 1200 can be located on a side of the microelectronic chip 1200 facing away from the printed circuit board 300. The studs 1108 of the distribution layer and the studs 1202 of the microelectronic chip can terminate at least substantially at the same height above the main surface 308 of the printed circuit board 300, measured in a direction that is at least substantially perpendicular to the main surface 308.

[0051] The microelectronic chip 1200 can be mounted on the printed circuit board 300 on sections of the first rewiring layer 1104 between the distribution layer studs 1108. For example, the distribution layer studs 1108 can be located outside the base area of ​​the microelectronic chip 1200, can be located near one or more sides of the microelectronic chip 1200, and can extend to heights above the main surface 308 of the printed circuit board 300 that are higher than the main surface 1204 of the microelectronic chip 1200.The distribution layer bolts 1108 can be located next to the microelectronic chip 1200 on two opposite sides, on two adjacent sides, on any three sides, on all four sides (in examples where the microelectronic chip 1200 has at least a substantially rectangular shape when viewed in a surface view), or on respective sides regardless of the number (in examples where the microelectronic chip 1200 has fewer or more than four sides).

[0052] Back to Fig. 10: Method 1000, as part of the process for electrically connecting individual microelectronic chips of the plurality of microelectronic chips with at least one via of the printed circuit board, as specified in Method 1008, may involve placing a molding material around the plurality of microelectronic components and around at least sections of the studs, as specified in Method 1010. For example, the molding material may initially be in a flowable state and be distributed or otherwise positioned under, around, and over the microelectronic chip 1200, covering sections of the main surface of the printed circuit board and the first re-wiring layer. The molding material may further be arranged at least laterally around sections of the studs of the distribution layer and the studs of the microelectronic chips, completely covering them in some examples.The molding material can enclose a curable polymer material that can then be cured.

[0053] Fig. Figure 14 is a cross-sectional side view of another temporary structure 1400 in a third phase of procedure 100 of Fig. 1 or of the procedure 1000 of Fig. 10. The temporary structure of 1400 by Fig. Figure 14 shows the package position 1102 of the circuit board 300 after performing at least operation 1010 of procedure 1000. Fig. 10. The temporary structure 1400 can enclose the formwork material 1402, which can connect the respective microelectronic chips 1200, the distribution layer studs 1108, and the microelectronic chip studs 1202 within the formwork material 1402. More precisely, the formwork material 1402 can contact and at least partially cover the main surface 308 of the printed circuit board 300, the first rewiring layer 1104, the microelectronic chip 1200, the distribution layer studs 1108, and the microelectronic chip studs 1202 at their respective enclosure locations 1102. In some examples, sections of the distribution layer studs 1108 and the microelectronic chip studs 1202 can be exposed above the formwork material 1402.In other examples, the molding material 1402 can completely cover the studs 1108 of the distribution layer and the studs 1202 of the microelectronic chips, and a section of the molding material 1402 can be removed to expose the studs 1108 of the distribution layer and the studs 1202 of the microelectronic chips (e.g., by back-grinding, without restriction). Regardless, a planarization process can be performed to make the molding material 1402, the studs 1108 of the distribution layer, and the studs 1202 of the microelectronic chip at least substantially flush with each other.

[0054] Back to Fig. 10: Method 1000, as part of the process for electrically connecting individual microelectronic chips to the plurality of microelectronic chips with at least one via on the printed circuit board, may further include forming a second rewiring layer on the mold material, in electrical connection with the studs and in electrical connection with the plurality of microelectronic components, as specified in Process 1012. For example, the second rewiring layer may be formed using one of the previously described methods associated with Fig. 5 and Fig. 11 techniques and structures are discussed, and how they are applied to the mold material and the bolts.

[0055] Fig. Figure 15 is a cross-sectional side view of another temporary structure 1500 in a fourth phase of procedure 100 of Fig. 1 or of the procedure 1000 of Fig. 10. More precisely, the temporary structure represents 1500 of Fig. 15 a package position 1102 of the circuit board 300 after carrying out operation 1012 of procedure 1000 of Fig. Figure 10. The temporary structure 1500 can include a second rewiring layer 1502, which is positioned on the mold material 1402 on one side of the mold material 1402 facing away from the printed circuit board 300. The second rewiring layer 1502 can include conductor tracks 1504 made of an electrically conductive material or such a material that is attached to the mold material 1402. The conductor tracks 1504 of the second rewiring layer 1502 can be electrically connected to the distribution layer studs 1108 of the first rewiring layer 1104 and to the studs of the microelectronic chip 1202 of the microelectronic chip 1200.Thus, the microelectronic chip 1200 can be electrically connected to the vias 304 by the microelectronic chip studs 1202 extending from the microelectronic chip 1200, the second rewiring layer 1502 being connected to the microelectronic chip studs 1202, the studs 1108 of the distribution layer being connected to the second rewiring layer 1502, and the first rewiring layer 1104 being connected to the studs 1108 of the distribution layer and the vias 304.

[0056] Back to Fig. 10: Method 1000 may further include the application of a passivation material to cover the second rewiring layer, as specified in Method 1014. For example, the second rewiring layer may be covered with a passivation material that includes a further amount of molding material that can flow and harden, as previously described in conjunction with Fig. 14 discussed.

[0057] Fig. Figure 16 is a cross-sectional side view of another temporary structure 1600 in a fifth phase of procedure 100 of Fig. 1 or of the procedure 1000 of Fig. 10. More precisely, the temporary structure represents 1500 of Fig. 15 a package position 1102 of the circuit board 300 after execution of operation 1014 of procedure 1000 of Fig. Figure 10. The temporary structure 1500 can include a passivation material 1602, which is positioned to protect the second rewiring layer 1502. For example, the passivation material 1602 can cover the second rewiring layer 1502 and sections of the molding material 1402 on the sides of the second rewiring layer 1502 and the molding material 1402 facing away from the printed circuit board 300. The passivation material 1602 can, for example, include a dielectric material. More specifically, the passivation material 1602 can, for example, include a curable polymer material.

[0058] To reiterate Fig. Returning to step 10: Procedure 1000 may involve singulating microelectronic component packages from the printed circuit board, as described in Procedure 1016. The respective microelectronic component packages may include at least one microelectronic chip of the plurality of microelectronic chips and a section of the printed circuit board, as also described in Procedure 1016. For example, the singulation process and any further actions performed to complete the microelectronic component packages or to configure them for connection with a higher-level package may be carried out by performing one of the procedures described above in conjunction with Fig. 2 and Fig. The 9 described actions will take place.

[0059] Fig. Figure 17 is a flowchart of another process, 1700, for packaging microelectronic components. As in Fig. As set out in 17, the procedure 1700 can be used in connection with the procedure 100 of Fig. The process comprises the operations performed and an additional optional operation indicated by dashed lines. For example, process 1700 may involve placing a plurality of microelectronic chips onto a printed circuit board, as shown in process 1702. The individual microelectronic chips of the plurality of microelectronic chips may be electrically connected to at least one via in the printed circuit board, as shown in process 1704. Microelectronic component packages may be separated from the printed circuit board, each microelectronic component package comprising at least one microelectronic chip of the plurality of microelectronic chips and a section of the printed circuit board, as shown in process 1706.As further specified in Procedure 1708, the microelectronic component packages can be isolated such that at least some of the microelectronic component packages include bond pads located on one side of the at least some microelectronic component packages facing away from the microelectronic component, arranged along corresponding sides of the periphery of the at least one microelectronic component package, and electrically connected to corresponding vias of the printed circuit board enclosing the at least one via.

[0060] Fig. Figure 18 is a surface view of another microelectronics component package, the 1800. The dashed lines in Fig. Figure 18 shows illustrative outlines of microelectronic chips, including size, shape, and orientation, that are incorporated into the 1800 microelectronic component package from Fig. 18 can be included. The microelectronic component package 1800 can include bond pads 1802 located along the respective sides of a periphery of the microelectronic component package 1800. For example, the bond pads 1802 can be distributed around a perimeter of the microelectronic component package 1800 and can be positioned to facilitate connection to higher-level packaging. The respective bond pads 1802 can be electrically connected to internal components of the microelectronic component package 1800, such as one or more microelectronic chips, using the respective conductor tracks 1804. The conductor tracks 1804 in Fig. For simplicity, 18 are represented by solid lines, and the conductor tracks 1804 may be exposed on an outer surface of the microelectronic component package 1800 or be located within the microelectronic component package 1800 to reduce the risk of damage to the conductor tracks 1804. In general, the Fig. The configuration shown in Figure 18 resembles what is known in engineering as a "Quad-Flat, No Lead" (QFN) package, since the microelectronic component package includes 1800 bond pads 1802 distributed around all four sides, exposed for connection, and located at least substantially in the same plane. Furthermore, it lacks leads in the form of dangling fingers for insertion into a receptacle, such as might be found on a lead frame.

[0061] Fig. 19 a cross-sectional view of a section of another printed circuit board 1904. Similar to the one in Fig. Section 4 shown can be found in Fig. The section shown in Figure 19 corresponds to a package position 1900 of the printed circuit board 1904, and the printed circuit board 1904 can include a plurality of such package positions 1900. For example, the package positions 1900 can be distributed in a grid or other arrangement on a major surface 1902 of the printed circuit board 1904, thereby enabling the simultaneous packaging of multiple microelectronic component packages, with each microelectronic component package located at its own package position 1900.

[0062] The vias 1906 of the respective package positions 1900 can be located near the periphery of the package position 1900 and distal to the geometric center of the package position 1900. For example, the vias 1906 of the printed circuit board 1904 can be distributed in repeating patterns of peripherally distributed circumferences around the respective package positions 1900, with roads between the package positions 1900. The conductor tracks 1804 can extend from the vias 1906 closer to the geometric center of the package position 1900 to provide an electrical connection to one or more microelectronic chips. In some examples, at least one package position 1900, and optionally each package position 1900, can include a thermal pad 1914 located on one side of the printed circuit board 1904 opposite the main surface 1902, on which a rewiring layer 2002 (see Fig. 20) can be formed. The thermal pad 1914 can, for example, enclose a mass of thermally conductive material (e.g., a metal or metal alloy) that adheres to the printed circuit board 1904 in the associated package position 1900 or is otherwise attached to it. The thermal pad 1914 can facilitate the dissipation (e.g., distribution) of the heat generated by a microelectronic component package to be formed from the package position 1900.

[0063] As already mentioned in connection with Fig. As discussed in section 3, the circuit board can be made from 1904. Fig. 19 materials and can be manufactured using techniques known to a person skilled in the art for use with printed circuit boards. For example, printed circuit board 1904 can include any materials and configurations and be manufactured using any of the previously mentioned techniques in connection with Fig. The three discussed techniques can be used to manufacture them. In some examples, the printed circuit board 1904 can include vias 1906, which may be covered and at least partially hollow. For example, instead of a solid mass of electrically conductive material occupying the entire space defined by the side walls 1908 of the dielectric material 1910 that defines the vias 1906, electrically conductive material of the at least partially hollow vias 1906 may be positioned mainly on the side walls 1908 and define a gap (e.g., at least substantially cylindrical, without restriction) that is filled by surrounding fluid (e.g., air, without restriction).

[0064] The vias 1906 can be covered by enclosing a covering material 1912 that at least partially seals the at least partially hollow vias 1906. Such occlusion can inhibit or prevent ambient fluid (e.g., air, without limitation) from passing through the at least partially hollow vias 1906, which can facilitate handling using pressure-based manipulators (e.g., vacuum chucks, without limitation). The covering material 1912 can then be removed, allowing connection to a higher-level package using through-hole soldering techniques and providing the associated opportunity to visually inspect and verify the quality of all electrical connections thereby made.The at least partially hollow vias 1906 and the associated cover material 1912 can be formed using any techniques and materials known in the prior art for such structures. In some examples, separating individual package positions 1900 of the printed circuit board 1904 from one another may involve cutting through the previously covered, at least partially hollow vias 1906, causing the vias 1906 to form an incomplete, generally circular shape (e.g., semicircles), sometimes referred to as "crenellations".

[0065] Fig. Figure 20 is a cross-sectional side view of a temporary structure 2000 in a first phase of the procedure 100 of Fig. 1 or of the procedure 1700 of Fig. 17. More precisely, the temporary structure represents 2000 of Fig. 20 a package position 1900 of the circuit board 1904 in preparation for the execution of operation 1702 of procedure 1700 of Fig. 17. The temporary structure 2000 can include a rewiring layer 2002 positioned on the main surface 1902 of the printed circuit board 1904. The rewiring layer 2002 can include any structures and materials and can be constructed using any of the previously described methods. Fig. 5 and Fig. 11 techniques discussed. For example, the rewiring layer 2002 can include conductor tracks that are electrically connected to the vias 1906.

[0066] Back to Fig. 17: Method 1700 may involve mounting a plurality of microelectronic chips onto a printed circuit board, as described in Method 1702. Method 1700 may further involve electrically connecting individual microelectronic chips of the plurality of microelectronic chips to at least one via in the printed circuit board, as described in Method 1704. Such tasks may be accomplished by performing one of the steps described above in conjunction with Fig. 7 and Fig. 13 to Fig. The 15 described actions must be completed.

[0067] Fig. Figure 21 is a cross-sectional side view of another temporary structure 2100 in a second phase of procedure 100 of Fig. 1 or of the procedure 1700 of Fig. 17. In particular, the temporary structure 2100 shows Fig. 21 a package position 1900 of the circuit board 1904 after carrying out operation 1702 and operation 1704 of procedure 1700 of Fig. 17. Since the package position 1900 includes vias 1906 near the periphery of the package position 1900, at least the majority of the vias 1906 may be located outside the footprint of the microelectronic chip 2102. For example, the vias 1906 of the printed circuit board 1904 may be located outside the footprint of the microelectronic chip 2102 of the plurality of microelectronic chips 2102.

[0068] To reiterate Fig. Returning to point 17: Method 1700 can further involve singulating microelectronic component packages from the printed circuit board, wherein the respective microelectronic component packages comprise at least one microelectronic chip of the plurality of microelectronic chips and a section of the printed circuit board, as described in process 1706. More specifically, the singulation can result in at least some of the microelectronic component packages having bond pads of the printed circuit board located on one side of the at least one microelectronic component package facing away from the microelectronic component, arranged along corresponding sides of the periphery of the at least one microelectronic component package, and electrically connected to the vias, as described in process 1708. The singulation process and other packaging and processing tasks can be carried out by performing one of the previously described steps in conjunction with Fig. 9 and Fig. The 16 described actions will be carried out.

[0069] Fig. Figure 22 is a flowchart of another, more specific method 2200 for packaging microelectronic components. Method 2200 may, for example, involve forming a rewiring layer on a printed circuit board and electrically connecting the formed rewiring layer to vias on the printed circuit board, as described in Procedure 2202. Several microelectronic chips may be placed on the rewiring layer, as shown in Procedure 2204. The individual microelectronic chips of the plurality of microelectronic chips may be electrically connected to the rewiring layer, as described in Procedure 2206. Finally, microelectronic component packages may be separated from the printed circuit board, each microelectronic component package comprising at least one microelectronic chip of the plurality of microelectronic chips and a section of the printed circuit board, as described in Procedure 2208.

[0070] Fig.Figure 22 shows an illustrative combination of operations that can be carried out when performing methods according to this disclosure. Additional methods within the scope of this disclosure may involve carrying out any combination or subcombination of the operations previously described in this disclosure, provided that this is logically possible and has been expressly considered by the inventor.

[0071] Additional, non-restrictive examples within the scope of protection of this disclosure include: Example 1: A method comprising: placing a plurality of microelectronic chips on a printed circuit board; electrically connecting respective microelectronic chips of the plurality of microelectronic chips to at least one via of the printed circuit board; and separating microelectronic component packages from the printed circuit board, wherein the respective microelectronic component packages comprise at least one microelectronic chip from the plurality of microelectronic chips and a section of the printed circuit board. Example 2: The method from Example 1 comprises forming a rewiring layer on the printed circuit board, wherein the rewiring layer is electrically connected to the at least one via before the plurality of microelectronic chips is placed on the printed circuit board, and wherein placing the plurality of microelectronic chips on the printed circuit board comprises placing the plurality of microelectronic chips on the rewiring layer. Example 3: The method from Example 2, wherein forming the rewiring layer comprises positioning electrically conductive material of the rewiring layer on areas of the printed circuit board between vias of the printed circuit board, including the at least one via. Example 4: The method from Example 2 or Example 3, wherein the electrical connection of respective microelectronic chips of the plurality of microelectronic chips to the at least one via of the printed circuit board comprises the melting of electrically conductive material extending from the respective microelectronic chip of the plurality of microelectronic chips to the rewiring layer. Example 5: The method from Example 4, wherein the melting of the electrically conductive material comprises directing energy emitted by a laser onto the electrically conductive material in order to melt the electrically conductive material. Example 6: The method according to one of Examples 1 to 5 includes placing the plurality of microelectronic chips in flip-chip orientations when the plurality of microelectronic chips is mounted on the printed circuit board. Example 7: The method from Example 1 comprises positioning the active surfaces of the plurality of microelectronic chip sides of the plurality of microelectronic chips such that they are facing away from the printed circuit board when the plurality of microelectronic chips is placed on the printed circuit board. Example 8: The method from Example 7 comprises forming a first rewiring layer on the printed circuit board, wherein the first rewiring layer is in electrical contact with the at least one via before the plurality of microelectronic chips is placed on the printed circuit board, wherein the first rewiring layer comprises distribution layer studs made of electrically conductive material, wherein the studs have a height above the printed circuit board that is at least as great as the greatest thickness of any microelectronic chip of the plurality of microelectronic chips, and wherein placing the plurality of microelectronic chips on the printed circuit board comprises placing the plurality of microelectronic chips on sections of the rewiring layer between the studs. Example 9: The method from Example 8 involves placing a molding material around the multitude of microelectronic components and around at least sections of the bolts. Example 10: The method from Example 9 comprises forming a second rewiring layer on the mold material, wherein the second rewiring layer is electrically connected to the studs of the distribution layer and electrically to the plurality of microelectronic components. Example 11: The method from Example 10 involves placing a passivation material to cover the second rewiring layer. Example 12: The method according to one of Examples 1 and 7 to 11, wherein the singulation of the microelectronic component packages from the printed circuit board comprises singulation of the microelectronic component packages such that at least some of the microelectronic component packages comprise bond pads of the printed circuit board which are located on a side of at least some of the microelectronic component packages that is facing away from the microelectronic component, are arranged along respective sides of the periphery of at least some of the microelectronic component packages and are electrically connected to the vias. Example 13: The method according to any of Examples 1 to 6, wherein the singulation of the microelectronic component packages from the printed circuit board comprises singulation of the microelectronic component packages such that at least some of the microelectronic component packages comprise bond pads arranged in a grid. Example 14: The method according to one of Examples 1 or 7 to 11, wherein the at least one via is at least partially hollow and wherein the separation of the microelectronic component packages from the printed circuit board includes cutting the at least one via to form a ‘pin’. Example 15: A structure comprising the following: a plurality of microelectronic chips mounted on a printed circuit board, wherein the printed circuit board includes vias and subsets of the vias are positioned for electrical connection to a respective microelectronic chip of the plurality of microelectronic chips. Example 16: The structure from Example 15, wherein the base areas of the microelectronic chips of the multitude of microelectronic chips cover at least some of the vias of the printed circuit board. Example 17: The structure from Example 15, wherein the respective vias of the subsets of vias of the printed circuit board are located outside the base areas of the microelectronic chips of the multitude of microelectronic chips. Example 18: The structure from Example 17, wherein at least some of the vias are at least partially hollow. Example 19: The structure from Example 17 or Example 18, wherein the spacing of the vias of the printed circuit board is between 0.65 mm and 1 mm. Example 20: The structure of one of Examples 17 to 19, wherein the dimensions of the printed circuit board are 300 mm x 300 mm, 510 mm x 510 mm, 510 mm x 515 mm, 515 mm x 515 mm or 600 mm x 600 mm. Example 21: A method comprising: forming a rewiring layer on a printed circuit board, wherein the rewiring layer is electrically connected to vias of the printed circuit board; placing a plurality of microelectronic chips on the rewiring layer; electrically connecting the respective microelectronic chips of the plurality of microelectronic chips to the rewiring layer; and separating microelectronic component packages from the printed circuit board, wherein the respective microelectronic component packages comprise at least one microelectronic chip from the plurality of microelectronic chips and a section of the printed circuit board.

[0072] By using a printed circuit board (PCB) as disclosed herein, for example, packaging techniques can be implemented at the board level without the use of steel or glass substrates and without the need for substrate debonding processes. PCBs can utilize less expensive materials, be easier to manufacture, be lighter for a given stiffness, and reduce the need to maintain an inventory of components that are susceptible to wear and tear over time (e.g., oxidation, without limitation). Furthermore, PCBs can also reduce the discrepancy between the coefficient of thermal expansion between microelectronic components and the underlying substrate, potentially leading to less deformation, easier handling, and reduced reliance on wasteful dummy chips to compensate for the coefficient of thermal expansion.Furthermore, the use of printed circuit boards can reduce or eliminate the need to consider device drift and misalignment during panelization. While certain illustrative examples have been described in conjunction with the figures, a person skilled in the art will recognize and acknowledge that the scope of this disclosure is not limited to the examples explicitly shown and described herein. Rather, many additions, deletions, and modifications can be made to the examples described herein to create examples within the scope of protection of this disclosure, such as those expressly claimed, including statutory equivalents. Moreover, features of one disclosed example can be combined with features of another disclosed example while still falling within the scope of protection of this disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 497,134

[0001]

Claims

[1] Procedure, encompassing: Mounting a large number of microelectronic chips onto a printed circuit board; electrical connection of individual microelectronic chips of the multitude of microelectronic chips with at least one through-hole of the printed circuit board; and Isolating microelectronic component packages from the printed circuit board, wherein the respective microelectronic component packages comprise at least one microelectronic chip from the plurality of microelectronic chips and a section of the printed circuit board. [2] The method of claim 1, comprising forming a rewiring layer on the printed circuit board, wherein the rewiring layer is electrically connected to the at least one via before the plurality of microelectronic chips is placed on the printed circuit board, and wherein placing the plurality of microelectronic chips on the printed circuit board comprises placing the plurality of microelectronic chips on the rewiring layer. [3] Method according to claim 2, wherein forming the rewiring layer comprises positioning electrically conductive material of the rewiring layer on areas of the printed circuit board between vias of the printed circuit board, including the at least one via. [4] Method according to claim 2, wherein the electrical connecting of respective microelectronic chips of the plurality of microelectronic chips to the at least one via of the printed circuit board comprises melting of electrically conductive material extending from respective microelectronic chips of the plurality of microelectronic chips to the rewiring layer. [5] Method according to claim 4, wherein the melting of the electrically conductive material comprises directing energy emitted by a laser onto the electrically conductive material to melt the electrically conductive material. [6] Method according to any one of claims 1 to 5, comprising placing the plurality of microelectronic chips in flip-chip orientations when the plurality of microelectronic chips is mounted on the printed circuit board. [7] Method according to claim 1, which comprises positioning the active surfaces of the plurality of microelectronic chips, wherein the sides of the plurality of microelectronic chips are positioned such that they face away from the printed circuit board when the plurality of microelectronic chips is placed on the printed circuit board. [8] The method of claim 7, comprising forming a first rewiring layer on the printed circuit board, wherein the first rewiring layer is in electrical connection with the at least one via before the plurality of microelectronic chips is placed on the printed circuit board, wherein the first rewiring layer comprises distribution layer studs made of electrically conductive material, the studs having a height above the printed circuit board that is at least as large as the greatest thickness of any microelectronic chip of the plurality of microelectronic chips, and wherein placing the plurality of microelectronic chips on the printed circuit board comprises placing the plurality of microelectronic chips on sections of the rewiring layer between the studs. [9] Method according to claim 8, which comprises placing a molding material around the plurality of microelectronic components and around at least sections of the bolts. [10] Method according to claim 9, which comprises forming a second rewiring layer on the mold material, wherein the second rewiring layer is electrically connected to the bolts of the distribution layer and electrically to the plurality of microelectronic components. [11] Method according to claim 10, which comprises placing a passivation material to cover the second rewiring layer. [12] Method according to one of claims 1 or 7 to 11, wherein the singulation of the microelectronic component packages from the printed circuit board comprises singulation of the microelectronic component packages such that at least some of the microelectronic component packages comprise bond pads of the printed circuit board, which are located on a side of at least some of the microelectronic component packages facing away from the microelectronic component, are arranged along respective sides of the periphery of at least some of the microelectronic component packages and are electrically connected to respective vias of the printed circuit board, which comprise the at least one via. [13] Method according to any one of claims 1 to 5, wherein the singulation of the microelectronic component packages from the printed circuit board comprises singulation of the microelectronic component packages such that at least some of the microelectronic component packages comprise bond pads arranged in a grid. [14] Method according to one of claims 1 or 7 to 11, wherein the at least one via is at least partially hollow and wherein the singulation of the microelectronic component packages from the printed circuit board comprises cutting the at least one via to form a ‘pin’. [15] Structure, comprehensive: a large number of microelectronic chips that are mounted on a printed circuit board, wherein the circuit board includes vias and subsets of the vias are positioned for electrical connection with a respective microelectronic chip of the multitude of microelectronic chips. [16] Structure according to claim 15, wherein the base areas of the microelectronic chips of the plurality of microelectronic chips cover at least some of the vias of the printed circuit board. [17] Structure according to claim 15, wherein the respective vias of the subsets of the vias of the printed circuit board are located outside the base areas of the microelectronic chips of the plurality of microelectronic chips. [18] Structure according to claim 17, wherein at least some of the vias are at least partially hollow. [19] Structure according to claim 17, wherein the spacing of the vias of the printed circuit board is between 0.65 mm and 1 mm. [20] Structure according to any one of claims 17 to 19, wherein the dimensions of the printed circuit board are 300 mm x 300 mm, 510 mm x 510 mm, 510 mm x 515 mm, 515 mm x 515 mm or 600 mm x 600 mm. [21] Procedures, including: Forming a rewiring layer on a printed circuit board, wherein the rewiring layer is electrically connected to vias of the printed circuit board; Attaching a large number of microelectronic chips to the rewiring layer; electrical connection of the respective microelectronic chips of the multitude of microelectronic chips to the rewiring layer; and Isolating microelectronic component packages from the printed circuit board, wherein the respective microelectronic component packages comprise at least one microelectronic chip from the plurality of microelectronic chips and a section of the printed circuit board.

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