VERTICAL SAFETY ARRAY ARCHITECTURE

Abstract

Methods, systems, and devices for the architecture of vertical fuse arrays are described. A storage system may include a uniquely programmable array of fuses fabricated using techniques similar to those used to fabricate other components, layers, or both of the storage system. Each fuse in the array may include a semiconductor channel extending vertically from a substrate and coupled to an oxide material. Each fuse may further be coupled to a word line and a digit line, which may be configured to break through the oxide material to couple the digit and word lines. In some embodiments, the oxide material may be arranged on one or more sidewalls of the channel. Additionally or alternatively, the oxide material may be arranged on a top surface of an upper terminal of the channel.

Description

CROSS-REFERENCE

[0001] The present patent application claims priority from US patent application No. 18 / 771,079 by Rigano et al. entitled “VERTICAL FUSE ARRAY ARCHITECTURE”, filed on July 12, 2024, and from provisional US patent application No. 63 / 526,871 by Rigano et al. entitled “VERTICAL FUSE ARRAY ARCHITECTURE”, filed on July 14, 2023; each of which has been assigned to the applicant of this application and each of these applications is hereby expressly incorporated in its entirety by reference into this application. AREA OF TECHNOLOGY

[0002] The following concerns one or more storage systems that incorporate a vertical backup array architecture. GENERAL STATE OF THE ART

[0003] Storage devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within a storage device to different states. For example, binary memory cells can be programmed to one of two supported states, often referred to as logical 1 or logical 0. In some examples, a single memory cell can support more than two states, each of which can be stored. To access the stored information, the storage device can read states from the memory cells (e.g., sense, detect, retrieve, determine). To store information, the storage device can write states to the memory cell (e.g., program, set, assign).

[0004] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selective memory, chalcogenide memory technologies, non-OR (NOR) and non-AND (NAND) memory devices, and others. Memory cells can be described as having volatile or non-volatile configurations. Memory cells configured in a non-volatile configuration can retain stored logical states for extended periods, even without an external power source.Memory cells configured in a volatile configuration can lose stored states when disconnected from an external power source. FeRAM can achieve similar densities to volatile memory, but can exhibit non-volatile properties due to the use of a ferroelectric capacitor as the storage device. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 illustrates an example of a system that supports a vertical backup array architecture according to the examples disclosed in this document. Fig. Figure 2 illustrates an example of a storage die that supports a vertical backup array architecture according to the examples disclosed in this document. Fig. Figure 3 illustrates an example of a top view of a system that supports a vertical backup array architecture according to the examples disclosed in this document. Fig. Figure 4 illustrates an example of a cross-sectional view of a system that supports a vertical backup array architecture according to the examples disclosed in this document. Fig. 5A and Fig. Figure 5B illustrates examples of a three-dimensional view of a system that supports a vertical backup array architecture according to the examples disclosed in this document. Fig. 6A and Fig. Section 6B illustrates examples of a three-dimensional view of a system that supports a vertical backup array architecture according to the examples disclosed in this document. Fig. 7A and Fig. 7B illustrates examples of a top view of a system and an operating diagram of the system supporting a vertical backup array architecture according to examples disclosed in this document. Fig. 8A, Fig. 8B and Fig. Figure 8C illustrates examples of top views and a cross-sectional view of a system supporting a vertical backup array architecture according to examples disclosed in this document. DETAILED DESCRIPTION

[0005] Some memory systems may include one or more arrays of one-time programmable (OTP) memory cells, as well as arrays of volatile or non-volatile memory cells. Such arrays of OTP memory cells may store parameters (e.g., configuration parameters, calibration parameters) for operations of the memory system, such as read or write voltage, timing parameters, metadata, or a combination thereof. Additionally or alternatively, an OTP array may store information associated with defective rows, columns, or memory cells of the memory system's arrays. Some memory systems may additionally include one or more vertical thin-film transistors (TFTs), which may be implemented as switching components for the memory system. A memory system manufacturer may use different types of operations to fabricate vertical TFTs and OTP arrays (e.g.,Material deposition procedures, masking procedures, etching procedures). However, the use of different types of operations to form vertical TFTs and OTP arrays can increase manufacturing complexity, for example, by increasing the number of manufacturing steps and using additional manufacturing equipment.

[0006] As described in this document, a memory system may include an OTP array of anti-fuses fabricated using techniques similar to those used to fabricate other components, layers, or both of the memory system. Each anti-fuse in the array may include a semiconductor channel extending vertically from a substrate and coupled to a dielectric material, such as an oxide material. Each anti-fuse may further be coupled to a word line and a digit line, which may be configured to break down the dielectric material (i.e., the anti-fuse “burns out”) to couple the digit and word lines. In some embodiments, the dielectric material may be located on one or more sidewalls of the channel. Additionally or alternatively, the oxide material may be located on a top surface of an upper terminal of the channel.Since such an anti-fuse may include components similar to a vertical TFT (e.g., a vertically extending channel), the anti-fuse may be manufactured using techniques similar to those used to manufacture a vertical TFT, which may reduce the manufacturing complexity of the storage system.

[0007] Features of the revelation are initially discussed in the context of systems and chips, with reference to Fig. 1 and Fig. 2. Features of the disclosure are described in the context of top views, cross-sectional views, and three-dimensional views of systems with reference to the Fig. 3 to 8C described.

[0008] Fig. Figure 1 illustrates an example of a System 100 that supports a vertical backup array architecture according to examples disclosed in this document. The System 100 can include a host device 105, a storage device 110, and a plurality of channels 115 that couple the host device 105 to the storage device 110. The System 100 can include one or more storage devices 110, but aspects of the one or more storage devices 110 can be described in the context of a single storage device (e.g., storage device 110).

[0009] System 100 can include sections of an electronic device, such as a computer device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or another system. For example, System 100 can represent aspects of a computer, a laptop, a tablet computer, a smartphone, a mobile phone, a portable device, an internet-connected device, a vehicle control system, or the like. The storage device 110 can be a component of System 100 that is operational for storing data for one or more other components of System 100.

[0010] Parts of the system 100 can be examples of the host device 105. The host device 105 can be an example of a processor (e.g., a circuit, a processing circuit, a processing component) within a device that uses memory to perform operations, such as within a computer device, a mobile computer device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a mobile phone, a portable device, an internet-connected device, a vehicle control unit, a system on a chip (SoC), or any other stationary or portable electronic device, among other examples. In some examples, the host device 105 can relate to the hardware, firmware, software, or any combination thereof that implements the functions of an external memory controller 120.In some examples, the external storage controller 120 can be referred to as a host (e.g., a host device 105).

[0011] A storage device 110 can be a standalone device or component that can be operated to provide physical memory addresses / storage space that can be used or referenced by the system 100. In some examples, a storage device 110 can be configured to operate with one or more types of host device. The signaling between the host device 105 and the storage device 110 can be operated to support one or more of the following: modulation schemes for modulating the signals, different contact configurations for communicating the signals, different form factors for the physical packaging of the host device 105 and the storage device 110, clock signaling and synchronization between the host device 105 and the storage device 110, timing conventions, or other functions.

[0012] The storage device 110 can be operated to store data for the components of the host device 105. In some examples, the storage device 110 (e.g., operating as a secondary device to the host device 105, or operating as a dependent device of the host device 105) can respond to and execute commands provided by the host device 105 through the external storage controller 120. Such commands may include one or more write commands, read commands, refresh commands, or other commands.

[0013] The host device 105 can include one or more external storage controllers 120, processors 125, basic input / output systems (BIOS) components 130, or other components such as one or more peripheral components or one or more input / output controllers. The components of the host device 105 can be interconnected using a bus 135.

[0014] The processor 125 can be operated to provide functionality (e.g., control functionality) to the system 100 or the host device 105. The processor 125 can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or another programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. In such examples, the processor 125 can be, among others, a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or a system-on-a-chip (SoC).In some examples, the external memory controller 120 can be implemented by the processor 125 or be a part of it.

[0015] The BIOS component 130 can be a software component containing a BIOS operating as firmware, which can initialize and execute various hardware components of the system 100 or the host device 105. The BIOS component 130 can also manage the data flow between the processor 125 and the various components of the system 100 or the host device 105. The BIOS component 130 can contain instructions (e.g., a program, software) stored in one or more read-only memory (ROM), flash memory, or other non-volatile memory.

[0016] The storage device 110 can include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a capacity (e.g., a desired capacity, a defined capacity) for data storage. Each memory die 160 (e.g., a memory die 160-a, memory die 160-b, memory die 160-N) can include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). A memory array 170 can be a collection (e.g., one or more grids, one or more banks, one or more tiles, one or more sections) of memory cells, each memory cell being operable to store one or more data bits.A memory device 110 that includes two or more memory dies 160 can be referred to as multi-die memory or multi-chip package or as multi-chip memory or multi-chip package.

[0017] A memory die can be an example of a two-dimensional (2D) array of memory cells or an example of a three-dimensional (3D) array of memory cells. A 2D memory die can, in some examples, contain a single memory array. A 3D memory die can, in some examples, contain two or more memory arrays, which may be stacked on top of each other or positioned side by side (e.g., relative to a substrate). In some examples, memory arrays in a 3D memory die can be referred to as distinct sets or otherwise comprised (e.g., stacks, levels, layers, dies). A 3D memory die can contain any number of stacked memory arrays (e.g., two high, three high, four high, five high, six high, seven high, eight high).In some 3D storage dies, different stacks can share a common access line, so that some stacks can share one or more word lines, a digit line and / or a disk line.

[0018] The device memory controller 155 can include components (e.g., circuits, logic) that are operable to control the operation of the storage device 110. The device memory controller 155 can include hardware, firmware, or instructions that enable the storage device 110 to perform various operations and can be operable to receive, transmit, or execute commands, data, or control information relating to the components of the storage device 110. The device memory controller 155 can be operable to communicate with one or more of the external memory controllers 120, the one or more memory dies 160, or the processor 125. In some examples, the device memory controller 155 can control the operation of the storage device 110 described in this document in conjunction with the local memory controller 165 of the memory die 160.

[0019] A local memory controller 165 (e.g., local to a memory die 160) can include components (e.g., circuits, logic) that are operable to control the operation of the memory die 160. In some examples, a local memory controller 165 can be operable to communicate with the device memory controller 155 (e.g., to receive or transmit data or instructions, or both). In some examples, a memory device 110 may not include a device memory controller 155, and the local memory controller 165 or the external memory controller 120 can perform the various functions described in this document. As such, a local memory controller 165 can be operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or a combination thereof.Examples of components that may be included in the device memory controller 155 or the local memory controllers 165, or both, may include receivers for receiving signals (e.g., from the external memory controller 120), transmitters for sending signals (e.g., to the external memory controller 120), decoders for decoding or demodulating received signals, encoders for encoding or modulating signals to be transmitted, or various other components that can be operated to support the described operations of the device memory controller 155 or the local memory controller 165, or both.

[0020] The external memory controller 120 can be configured to facilitate communication of information (e.g., data, instructions, or both) between components of the system 100 (e.g., between components of the host device 105, such as the processor 125 and the storage device 110). The external memory controller 120 can process (e.g., convert, translate) communications exchanged between the components of the host device 105 and the storage device 110. In some examples, the external memory controller 120, or other components of the system 100, the host device 105, or their functions described herein, can be implemented by the processor 125. For example, the external memory controller 120 can be hardware, firmware, or software, or a combination thereof, implemented by the processor 125 or another component of the system 100 or the host device 105.While the external memory controller 120 is depicted as being outside the memory device 110, in some examples the external memory controller 120 or its functions described in this document may be implemented by one or more components of a memory device 110 (e.g., a device memory controller 155, a local memory controller 165) or vice versa.

[0021] The components of the host device 105 can exchange information with the storage device 110 via one or more channels 115. The channels 115 can be operational to support communication between the external storage controller 120 and the storage device 110. Each channel 115 can be an example of a transmission medium that carries information between the host device 105 and the storage device 110. Each channel 115 can include one or more signaling paths (e.g., transmission medium, a conductor) between the system 100 components and their associated terminals. A signaling path can be an example of an electrically conductive path that can be operated to carry a signal. For example, a channel 115 can be assigned to a first terminal (e.g.,comprising one or more pins, including one or more pads) on the host device 105 and a second connection on the storage device 110. A connection can be, for example, an electrically conductive input or output point of a device of the system 100, and a connection can be operational to function as part of a channel.

[0022] Channels 115 (and their associated signaling paths and connectors) can be used to transmit one or more types of information. For example, channels 115 can include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or any combination thereof. In some examples, signaling over channels 115 can be communicated using single-data-rate (SDR) or double-data-rate (DDR) signaling. With SDR signaling, a modulation symbol (e.g., the signal level) of a signal can be registered for each clock cycle (e.g., on the rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal can be registered for each clock cycle (e.g.,both on a rising and on a falling edge of a clock signal).

[0023] In some cases, a storage device 110 may include an OTP array of anti-fuses fabricated using techniques similar to those used to fabricate other components, layers, or both of the storage device 110. Each anti-fuse of the array may include a semiconductor channel extending vertically from a substrate and coupled to an oxide material. Each anti-fuse may further be coupled to a word line and a digit line, which may be configured to break down the oxide material (i.e., the anti-fuse “burns out”) to couple the digit line with a voltage when the word line is claimed. In some embodiments, the oxide material may be arranged on one or more sidewalls of the channel. Additionally or alternatively, the oxide material may be arranged on a top surface of an upper terminal of the channel (where, for example,(the TFT serves as a selection device). Since such an anti-fuse may include components similar to a vertical TFT (e.g., a vertically extending channel), the anti-fuse may be manufactured using techniques similar to those used to manufacture a vertical TFT, which may reduce the manufacturing complexity of the storage device 110.

[0024] Fig. Figure 2 illustrates an example of a Memory Die 200 that supports a vertical backup array architecture according to the examples disclosed in this document. The Memory Die 200 can be an example of the, with reference to Fig. The memory die 200 described in Section 1 may be a memory die 160. In some examples, the memory die 200 may be referred to as a memory chip, a storage device, or an electronic storage device. The memory die 200 may contain one or more memory cells 205, each of which may be programmable to store different logic states (e.g., programmed to one of a set of two or more possible states). For example, a memory cell 205 may be operable to store one bit of information at a time (e.g., a logical 0 or a logical 1). In some examples, a memory cell 205 (e.g., a multi-level memory cell) may be operable to store more than one bit of information at a time (e.g., a logical 00, a logical 01, a logical 10, a logical 11). In some examples, the memory cells 205 may be arranged in an array, as in a memory array 170 described with reference to Section 160. Fig. 1 is described.

[0025] In some examples, a memory cell 205 can store a state representative of the programmable states (e.g., a polarization state, a dielectric charge) in a capacitor. The memory cell 205 can include a logic memory component, such as a capacitor 240, and a switching component 245 (e.g., a cell selection component). A first node of the capacitor 240 can be coupled to the switching component 245, and a second node of the capacitor 240 can be coupled to a plate line 220. The switching component 245 can be an example of a transistor or any other type of switching device that selectively establishes or disconnects electronic communication between two components. In FeRAM architectures, the memory cell 205 can include a capacitor 240 (e.g., a ferroelectric capacitor) containing a ferroelectric material to store a charge (e.g., a dielectric).to store a polarization) that represents the programmable state.

[0026] The memory die 200 can contain access lines (e.g., word lines 210, digit lines 215, disk lines 220) arranged in a pattern, such as a grid-like pattern. An access line can be an electrically conductive line coupled to a memory cell 205 and used to perform access operations on that memory cell. In some examples, the word lines 210 can be called row lines. In some examples, the digit lines 215 can be called column lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, bit lines, or disk lines, or their analogues, are interchangeable without loss of understanding. Memory cells 205 can be located at the intersections of the word lines 210, the digit lines 215, or the disk lines 220.

[0027] Operations such as reading and writing can be performed on the memory cells 205 by activating access lines such as a word line 210, a digit line 215, or a disk line 220. By biasing a word line 210, a digit line 215, and a disk line 220 (e.g., by applying a voltage to the word line 210, the digit line 215, or the disk line 220), a single memory cell 205 can be accessed at its intersection. The intersection of a word line 210 and a digit line 215 can be designated as the address of a memory cell 205 in either a two-dimensional or a three-dimensional configuration. Activating a word line 210, a digit line 215, or a disk line 220 can involve applying a voltage to the respective line.

[0028] Access to the memory cells 205 can be controlled by a row decoder 225, a column decoder 230, a disk driver 235, or any combination thereof. For example, a row decoder 225 can receive a row address from the local memory controller 265 and activate a word line 210 based on the received row address. A column decoder 230 can receive a column address from the local memory controller 265 and activate a digit line 215 based on the received column address. A disk driver 235 can receive a disk address from the local memory controller 265 and activate a disk line 220 based on the received disk address.

[0029] Selecting or deselecting memory cell 205 can be accomplished by activating or deactivating switching component 245. Capacitor 240 can be in electronic communication with the digit line 215 using switching component 245. For example, capacitor 240 can be isolated from the digit line 215 when switching component 245 is deactivated, and capacitor 240 can be coupled to the digit line 215 when switching component 245 is activated.

[0030] A word line 210 can be an electrically conductive line in electronic communication with a memory cell 205, used to perform access operations on the memory cell 205. In some architectures, the word line 210 can be in electronic communication with a gate of a switching component 245 of a memory cell 205 and can be operated to control the switching component 245 of the memory cell. In some architectures, the word line 210 can be in electronic communication with a node of the capacitor of the memory cell 205, and the memory cell 205 may not contain a switching component.

[0031] A digit line 215 can be an electrically conductive line that couples the memory cell 205 to a sensing component 250. In some architectures, the memory cell 205 can be selectively coupled to the digit line 215 during parts of an access operation. For example, the word line 210 and the switching component 245 of the memory cell 205 can be operated to selectively couple or isolate the capacitor 240 of the memory cell 205 and the digit line 215. In some architectures, the memory cell 205 can be in electronic communication (e.g., constant) with the digit line 215.

[0032] The sensing component 250 can determine a state (e.g., a polarization state, a charge) stored on the capacitor 240 of the memory cell 205 and determine a logic state of the memory cell 205 based on the detected state. The sensing component 250 can include one or more sensing amplifiers to amplify the signal output by the memory cell 205. The sensing component 250 can compare the signal received from the memory cell 205 via the digit line 215 with a reference signal 255 (e.g., a reference voltage, a reference line). The detected logic state of the memory cell 205 can be provided as an output of the sensing component 250 (e.g., to an input / output 260) and can indicate the detected logic state of another component of a storage device (e.g., a storage device 110) that includes the memory die 200.

[0033] The local memory controller 265 can control the operation of the memory cells 205 by the various components (e.g., row decoder 225, column decoder 230, disk driver 235, and sensing component 250). The local memory controller 265 can be an example of the local memory device 165, which is described with reference to Fig. as described in Section 1. In some examples, one or more of the row decoder 225, the column decoder 230, the disk driver 235, and the sensing component 250 can be arranged together with the local memory controller 265. The local memory controller 265 can be operated to receive one or more instructions or data from one or more different memory controllers (e.g., an external memory controller 120 connected to a host device 105, another controller connected to the memory die 200), translate the instructions or the data (or both) into information that can be used by the memory die 200, perform one or more operations on the memory die 200, and communicate data from the memory die 200 to a host device 105 based on the execution of the one or more operations.The local memory controller 265 can generate row and column address signals to activate the target word line 210, the target digit line 215, and the target disk line 220. The local memory controller 265 can also generate and control various signals (e.g., voltages or currents) used during the operation of the memory die 200. In general, the amplitude, shape, or duration of an applied voltage or current discussed in this document can be varied and may differ for the various operations discussed in connection with the operation of the memory die 200.

[0034] The local memory controller 265 can be operated to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include, but are not limited to, a write operation, a read operation, a refresh operation, a preload operation, or an activation operation. In some examples, access operations by the local memory controller 265 can be performed in response to various access commands (e.g., from a host device 105) or coordinated in some other way. The local memory controller 265 can also be operated to perform other access operations not listed here, or other operations related to the operation of the memory chip 200 that are not directly connected with accessing the memory cells 205.

[0035] In some cases, a memory die 200 may include or be coupled to an OTP array of anti-fuses fabricated using techniques similar to those used to fabricate other components, layers, or both of the memory die 200. Each anti-fuse of the array may include a semiconductor channel extending vertically from a substrate and coupled to an oxide material. Each anti-fuse may further be coupled to a word line 210 and a digit line 215, which may be configured to break through the oxide material (i.e., the anti-fuse “burns through”) to couple the digit line 215 and the word line 210 (e.g., by applying a voltage potential above a threshold across the word line 210 and the digit line 215). In some embodiments, the oxide material may be arranged on one or more sidewalls of the channel.Additionally or alternatively, the oxide material can be arranged on an upper surface of an upper terminal of the channel (with, for example, the TFT serving as a selection device). Since such an anti-fuse can include components resembling a vertical TFT (e.g., a vertically extending channel), the anti-fuse can be fabricated using techniques similar to those used for fabricating a vertical TFT, which can reduce the fabrication complexity of the Memory Die 200.

[0036] Fig. Figure 3 illustrates an example of a System 300 scheme supporting a vertical backup array architecture according to examples disclosed in this document. The System 300 can be an anti-backup storage array. The System 300 can include one or more anti-backup cells 305, each of which can be programmed to store different logical states (e.g., set to logic 1 or logic 0). In some examples, the anti-backup cells 305 can be arranged in an array of rows and columns. The System 300 can be implemented in and thus coupled to a storage device (e.g., a storage device 110). For example, the System 300 can be an example of an OTP backup array for a storage device, an example of a supporting array for a storage die 200, or both. The System 300 can support the operation of a storage device. For example, the System 300 can store parameters (e.g.,B. Configuration parameters, calibration parameters) for storage device operations, such as read or write voltage, timing parameters, metadata, or a combination thereof. Additionally or alternatively, the system can store 300 pieces of information associated with defective rows, columns, or memory cells of the storage system's memory arrays.

[0037] In some examples, an anti-fuse cell 305 can store a state representing the programmable states in an anti-fuse 340. The anti-fuse cell 305 can include a logic memory component, such as the anti-fuse 340. In some examples, an anti-fuse cell 305 can additionally include a switching component 345 that can selectively connect the anti-fuse 340 to a voltage source, such as a grounded voltage source 350. A first terminal of the anti-fuse 340 can be selectively coupled to the grounded voltage source 350 via the switching component 345, and a second terminal of the anti-fuse 340 can be coupled to a digit line 315. The switching component 345 can be, for example, a transistor or any other type of switching device that selectively establishes or disconnects electronic communication between two components.

[0038] An anti-fuse cell 305 can be an OTP memory cell. For example, the anti-fuse 340 of an anti-fuse cell 305 may initially be in a high-resistance state, which may correspond to the anti-fuse cell 305 storing a first logical state (e.g., a logical 0). If a sufficiently high voltage is applied across the anti-fuse 340 (e.g., a voltage greater than a threshold voltage of the anti-fuse 340), the anti-fuse 340 can "blow" and transition to a low-resistance state, which may correspond to a second logical state (a logical 1). In some cases, the process of an anti-fuse 340 blowing may be referred to as fuse operation. Since fuse operation of an anti-fuse cell 305 may not be reversible, the anti-fuse cell 305 can be programmed once.

[0039] The system 300 can include access lines, such as word lines 310 extending in a first horizontal direction (e.g., the x-direction), and digit lines 315 extending in a second horizontal direction (e.g., the y-direction), arranged in a grid-like pattern. An access line can be an electrically conductive line coupled to an anti-backup cell 305 and can be used to perform access operations (e.g., backup operations, read operations) on the anti-backup cell 305. Operations such as read and backup can be performed on the anti-backup cells 305 by activating access lines such as a word line 310, a digit line 315, or both. By biasing a word line 310 and a digit line 315 (e.g.,Applying a voltage to word line 310 or digit line 315 allows access to a single anti-fuse cell 305 at its intersection. The intersection of a word line 310 and a digit line 315 can be referred to as the address of an anti-fuse cell 305. Activating a word line 310 or a digit line 315 can involve applying a voltage to the respective line. For example, if the switching component 345 is an n-type transistor, activating word line 310 can involve applying a voltage higher than the threshold voltage of the n-type transistor to activate the n-type transistor (e.g., to electrically couple the source and drain terminals of the n-type transistor). Alternatively, if the switching component 345 is a p-type transistor, activating word line 310 can involve applying a voltage below the threshold voltage of the p-type transistor (e.g.,a voltage lower than the voltage of the source and drain terminals of the p-type transistor) to activate the p-type transistor.

[0040] Access to the anti-safety cells 305 can be controlled by a word line decoder 325, a digit line decoder 330, or both. For example, a word line decoder 325 can receive a row address from a controller (e.g., a memory controller such as the local memory controller 265) and activate a word line 310 based on the received row address. A digit line decoder 330 can receive a column address from the controller and activate a digit line 315 based on the received column address. In some examples, a digit line decoder 330 can activate a digit line 315 by activating a switching component 335 (e.g., a transistor) connected to the digit line 315. Activating the switching component 335 can apply a voltage to the digit line 315 by coupling the digit line 315 to a voltage source 338.

[0041] Securing the anti-fuse cell 305 can be achieved by activating the switching component 345 using a word line 310, which can couple the first terminal of the anti-fuse 340 to the grounded voltage source 350, and by applying a first voltage (e.g., a high voltage, a fuse voltage) to a digit line 315, which is coupled to the second terminal of the anti-fuse 340. The resulting voltage across the anti-fuse 340 can be sufficiently high (e.g., greater than the gate oxide breakdown voltage of the anti-fuse 340) to blow the anti-fuse 340 and thus transition it from a high-resistance state to a low-resistance state.

[0042] Reading the anti-fuse cell 305 can be achieved by activating the switching component 345 and applying a second voltage (e.g., a low voltage, a read voltage lower than the gate oxide breakdown voltage of the anti-fuse 340) to a digit line 315. If the anti-fuse 340 has been protected (e.g., blown), activating the switching component 345 can couple the digit line 315 to the grounded voltage source 350 via the switching component 345. Alternatively, if the anti-fuse 340 has not been protected, the digit line 315 can remain isolated from the grounded voltage source 350. A component coupled to the digit line 315 (e.g. a sensing component) can measure the current or voltage on the digit line 315 to determine whether the anti-fuse 340 has been protected, and thus determine the logic state stored by the anti-fuse cell 305.

[0043] Fig. Figure 4 illustrates an example of a cross-sectional view of a System 400 supporting a vertical security array architecture according to examples disclosed in this document. System 400 can be an example of a section of an anti-security cell (e.g., an anti-security cell 305 as described with reference to Fig. (as described in section 3). The System 400 can be implemented in a storage device (e.g., a storage device 110) that is fabricated in multiple layers using respective fabrication operations. The storage device can, for example, include a substrate layer containing a set of transistors or other circuitry (e.g., a complementary metal-oxide-semiconductor (CMOS) layer) and one or more metal layers that can be used as access lines (e.g., digit lines, word lines, disk lines) for memory cells, such as FeRAM memory cells. The storage device can also include a layer of vertical TFTs between the memory cells and the substrate, which can be used to access the memory cells.For example, each memory cell can include a ferroelectric capacitor with a first node coupled to a first terminal of a TFT and a second node coupled to a plate line. The TFT can include a second terminal coupled to the substrate, and accordingly, the TFT can be activated to couple the memory cell to circuits in the substrate, for example, as part of an access operation.

[0044] The System 400 can be fabricated using techniques similar to those used to fabricate a storage device. For example, the System 400 may include a layer 405 (e.g., a CMOS layer, a CuA layer, a substrate layer) implementing a switching component 410. The switching component 410 may include a channel area 415, a terminal 420 coupled to a grounded voltage source 425 (e.g., which may be connected to a conductor track), and a terminal 430. The switching component 410 may include a gate 435, which may be configured to activate the switching component 410 to couple the terminal 420 to the terminal 430. In some cases, the gate 435 may be coupled to an access line extending in a horizontal direction (e.g., the x-direction), such as a word line 310, as described in [reference to]. Fig. 3 described.

[0045] The system 400 can include a layer 408 formed above layer 405. Layer 408 can include one or more electrically conductive contacts manufactured using techniques similar to those used to manufacture metal lines (e.g., access lines, digit lines 215) of a storage device. Layer 408 can include an electrically conductive contact 432 above and coupled to terminal 430, an electrically conductive column 433 above and coupled to electrically conductive contact 432, and an electrically conductive area 438 above and coupled to electrically conductive column 433.

[0046] System 400 can include a second layer 440, which is an example of an anti-safety measure such as the one referred to in Fig. The anti-fuse 340 described in section 3 may be included. The second layer 440 may be fabricated using techniques similar to those used to form a TFT layer of a memory device. For example, in a fabrication process of the memory device, a step may be taken in which sections of the second layer 440, including a semiconductor material used for a channel 450 of the anti-fuse, are deposited or grown over the first layer 405 (e.g., and layer 408), and as part of the same step, sections of a TFT layer (e.g., sections containing the semiconductor material) of the memory device may be deposited or grown. The anti-fuse may have a terminal 445 coupled via the electrically conductive area 438 to the terminal 430 of the switching component 410, a channel 450 of the semiconductor material extending in a vertical direction (e.g.,the z-direction) extends over terminal 430, and includes a terminal 455 over channel 450. In some examples, the semiconductor material forming channel 450 may be formed with additional or different doping (e.g., N-type doping) as channels of a TFT layer of a storage device.

[0047] The anti-locking layer can include an oxide material 460 arranged on the side walls of the channel 450, and the second layer 440 can include an access line 465 adjacent to the oxide material 460 and extending in a second horizontal direction (e.g., the y-direction). The access line 465 can be, as shown in Fig. Figure 4 shows that the access line 465 may be adjacent to the oxide material 460 on several side walls of the channel 450, or it may be adjacent to the oxide material 460 on a single side wall of the channel 450. In some cases, the access line 465 may be an example of the digit line 315, as shown in Figure 4. Fig. 3 described.

[0048] A controller can access the anti-fuse via the access line connected to gate 435 and access line 465. For example, to protect the anti-fuse, the controller can activate switching component 410 to couple terminal 445 to the grounded voltage source 425 and apply an initial voltage to access line 465. This initial voltage can be high enough to cause the oxide material 460 to break down, which can couple (e.g., fuse) access line 465 to channel 450. For example, the initial voltage can exceed the threshold voltage of the anti-fuse. Alternatively, to read the anti-fuse, the controller can activate switching component 410 and apply a second voltage (e.g., a read voltage) to access line 465. If the oxide material 460 has been penetrated, activating the switching component 410 can couple the access line 465 to the grounded voltage source 425.Alternatively, if the oxide material 460 has not been penetrated, the access line 465 can remain isolated from the grounded voltage source 425. A component coupled to the access line 465 (e.g., a sensing component) can sense the current or voltage on the access line 465 in order to read the logical state stored by the anti-fuse.

[0049] Fig. 5A and Fig. Figure 5B illustrates examples of a three-dimensional view of a System 500 and a System 501, respectively, which support a vertical backup array architecture according to examples disclosed in this document. The System 500 and the System 501 can each be an example of an array of antibackup cells 505 (e.g., an array of antibackup cells 505-a, an array of antibackup cells 505-b), each of which can be an example of an array of antibackup cells 305, as described in [reference to...]. Fig. 3 described. System 500 and System 501 can each include a set of anti-backup channels 540 (e.g., anti-backup channels 540-a, anti-backup channels 540-b), each of which incorporates aspects of the second layer 440, as described with reference to Fig. As described in Section 4, the anti-fuse channels 540 may include, for example, the channel 450, the terminal 445, the terminal 455, or a combination thereof, arranged in rows extending along the x-direction and columns extending along the y-direction. Each column of anti-fuse channels 540 may be adjacent to a corresponding access line 565 (e.g., an access line 565-a, an access line 565-b), which may be an example of an access line 465. Furthermore, each anti-fuse channel 540 may include an oxide material (e.g., an oxide material 460) formed on one or more side walls of the anti-fuse channel 540 and in contact with the access line 565. For example, an access line 565 may be in contact with the oxide material on one or more side walls of the anti-fuse channel 540.

[0050] Each anti-fuse cell 505 can include an electrically conductive surface 538 (e.g., an electrically conductive surface 538-a, an electrically conductive surface 538-b), which can be an example of an electrically conductive surface 438. The electrically conductive surface 538 can be coupled via an electrically conductive column 533 (e.g., electrically conductive column 533-a, electrically conductive column 533-b) to a switching component (e.g., a switching component 410), which can selectively couple the electrically conductive surface 538 to a grounded voltage source. In some examples, several anti-fuse channels 540 can be arranged on a single electrically conductive surface 538 in one or more rows, one or more columns, or both.For example, a first column of anti-fuse channels 540 on the electrically conductive surface 538 can each be coupled to a first access line 565, and a second column of anti-fuse channels 540 on the electrically conductive surface 538 can each be coupled to a second access line 565. Accordingly, each anti-fuse cell 505 can be linked to one or more access lines 565 and contain one or more anti-fuse channels 540, the respective terminals of which are coupled to a single electrically conductive surface 538.

[0051] The system 500 can include anti-fuse channels 540 between adjacent anti-fuse cells 505. For example, the system 500 can include one or more anti-fuse channels 540 between a first electrically conductive surface 538 and a second electrically conductive surface 538. The one or more anti-fuse channels 540 can be insulated from the first electrically conductive surface 538 and the second electrically conductive surface 538 and, accordingly, can be excluded from an anti-fuse cell 505.

[0052] Including multiple anti-fuse channels 540 in a single anti-fuse cell 505 can improve the reliability of oxide material breakdown during a fuse operation of the anti-fuse cell 505. For example, as part of the fuse operation, a fuse voltage can be applied to each of the anti-fuse channels 540 of the anti-fuse cell 505 (e.g., using the one or more access lines 565 connected to the anti-fuse cell 505). Because the voltage at which the oxide material breaks down can vary for each anti-fuse channel 540 (e.g., due to slight differences in the coverage area, in an oxide composition, differences in the applied voltage, or a combination thereof), each anti-fuse channel 540 may have a probability of failing to fuse successfully during the fuse operation.Accordingly, the inclusion of multiple anti-backup channels 540 in the anti-backup cell 505 increases the probability that at least one anti-backup channel 540 of the anti-backup cell 505 will successfully provide a backup. Since the presence of at least one backup anti-backup channel 540 on an electrically conductive surface 538 can provide a sufficiently conductive path between an access line 565 and the electrically conductive surface 538, the presence of multiple anti-backup channels 540 can thus increase the reliability of a backup operation for the anti-backup cell 505.

[0053] Furthermore, the System 500 and System 501 can be manufactured using some processing steps common to the fabrication of a TFT layer of a memory device. For example, a first step in a fabrication process of the memory device can form the electrically conductive areas 538 by depositing and etching an electrically conductive material and can, as part of the first step, fabricate sections of one or more digit lines of a memory array by depositing and etching the electrically conductive material. A second step in a fabrication process of the memory device can further form the anti-backup channel 540 by depositing and etching a semiconductor material and can, as part of the second step, form sections of a TFT array for a memory array of the memory device by depositing and etching the semiconductor material.

[0054] In some examples, System 501 can be fabricated using additional or modified processing steps of the processing steps used to fabricate System 501. For example, as part of the processing steps to form the anti-fuse channels 540-b, a processing step for System 501 may involve etching the semiconductor material in the x-direction, which may expose the electrically conductive material of the electrically conductive area 538 (e.g., a “complete” trench may be etched in the x-direction). The processing step may also involve a “partial” etching of the semiconductor material in the y-direction. For example, the partial etching in the y-direction may not remove a portion of the semiconductor material, which may form one or more secondary channels 510 extending in the x-direction.

[0055] The second channels 510 can couple multiple channels 565-b within a single anti-fuse cell 505-b, which can increase electrical conductivity between the multiple channels 565-b. Such increased electrical conductivity can increase the probability of oxide material breakdown during fuse operation of an anti-fuse cell 505-b and thus improve the reliability of fuse operation. In some cases, the second channels 510 between adjacent anti-fuse cells 505-b can be separated in the x-direction, for example, by etching a trench 515 into the semiconductor material.

[0056] Fig. 6A and Fig. Figure 6B illustrates examples of a three-dimensional view of a System 600 and a System 601, respectively, which support a vertical backup array architecture according to examples disclosed in this document. The System 600 and the System 601 may each incorporate aspects of the System 500 and the System 501, respectively. For example, the system 600 and the system 601 can include a set of anti-lock cells 605 (e.g., a set of anti-lock cells 605-a, a set of anti-lock cells 605-b), each anti-lock cell 605 having an electrically conductive surface 638 (e.g., an electrically conductive surface 638-a, an electrically conductive surface 638-b) coupled to a switching component via an electrically conductive column 633 (e.g., an electrically conductive column 633-a, an electrically conductive column 633-b), as well as one or more sections of anti-lock channels 640 (e.g.,Anti-fuse channels 640-a, anti-fuse channels 640-b), which are arranged on the electrically conductive surface 638 and coupled to one or more access lines 665 (e.g. access line 665-a, access lines 665-b), which are examples of the corresponding components as described with reference to the . Fig. 5A and Fig. 5B were described.

[0057] The anti-fuse channels 640-a of the system 600 can extend over several anti-fuse cells 605-a, several electrically conductive surfaces 638-a, or both. For example, the semiconductor material of a channel of each anti-fuse channel 640-a, as well as the oxide material between the semiconductor material and an associated access line 665-a, can extend in the y-direction over several electrically conductive surfaces 638-a. Such an extension can increase the surface area of ​​the interface between the access lines 665-a and the oxide material, which can increase the probability of oxide material breakdown during a fuse operation of an anti-fuse cell 605-a and thus improve the reliability of the fuse operation.

[0058] Additionally or alternatively, the anti-security channels 640-b of the system 601 can extend over a single anti-security cell 605-b and a single electrically conductive area 638-b. For example, as part of the fabrication of the anti-security channels 640-b, a groove 610 extending in the x-direction can be etched into the semiconductor material to separate a first anti-security channel 640-b of a first anti-security cell 605-b from a second anti-security channel 640-b of a second anti-security cell 605-b that is adjacent to the first anti-security cell 605-b in the y-direction. Such separation can reduce the electrical conductivity between adjacent anti-security cells 605-b, which can reduce interference between adjacent anti-security cells 605-b during access operations.

[0059] The expansion of the semiconductor and oxide materials of an anti-fuse channel 640 can be implemented using techniques similar to those used in the fabrication of System 500. However, in the fabrication of System 600, one or more fabrication steps of System 500 can be omitted. For example, the fabrication of System 500 may involve forming a linear structure of the semiconductor material, such as by etching one or more grooves in the y-direction of a planar layer of the semiconductor material and depositing the oxide material on the sidewalls of the linear structures. The individual anti-fuse channels 640 can then be formed by etching one or more grooves in the x-direction. To form the expanded channels of the anti-fuse channels 640, the fabrication of System 600 may omit the etching of the grooves in the x-direction.Such omissions can reduce the complexity of the manufacturing process, for example by decreasing the number of steps used to manufacture the System 600.

[0060] Additionally or alternatively, the anti-security channels 640-b of the system 601 can extend over a single anti-security cell 605-b and a single electrically conductive area 638-b. For example, as part of the fabrication of the anti-security channels 640-b, a groove 610 extending in the x-direction can be etched into the semiconductor material to separate a first anti-security channel 640-b of a first anti-security cell 605-b from a second anti-security channel 640-b of a second anti-security cell 605-b that is adjacent to the first anti-security cell 605-b in the y-direction. Such separation can reduce the electrical conductivity between adjacent anti-security cells 605-b, which can reduce interference between adjacent anti-security cells 605-b during access operations.

[0061] Fig. 7A and Fig. Section 7B illustrates examples of a top view of a System 701 and an operating diagram of the System 701 supporting a vertical backup array architecture according to examples disclosed in this document. The System 701 may incorporate aspects of the System 300, as referenced in Fig. 3 described. For example, the system 701 can be a scheme of an architecture for an anti-backup memory array, comprising one or more digit lines 715 extending in the x-direction and coupled to a digit line decoder 730, and one or more word lines 710 extending in the y-direction and selectively coupled to a voltage source 738 via corresponding switching components 735 operated by a word line decoder 725, each of which can be an example of the corresponding component, as described with reference to Fig. 3 was described.

[0062] The 701 system can include an array of 705 anti-fuse cells. A 705 anti-fuse cell can include some aspects of a 305, 505, 605 anti-fuse cell, or a combination thereof. For example, a 705 anti-fuse cell can include a 740 anti-fuse, which may include aspects of a 340 anti-fuse and a 540 or 640 anti-fuse channel, or a combination thereof. However, the 705 anti-fuse cell may not include a switching component to selectively couple the 740 anti-fuse to an access line. Instead, a terminal of the 740 anti-fuse (e.g., a 445 terminal) may be directly coupled to a 715 digit line, and an oxide material formed on one or more sidewalls of a 740 anti-fuse channel (e.g., a 450 channel) may be adjacent to a 710 word line.Omitting the switching component in an anti-fuse cell 705 can reduce the space requirement of the system 701, which can enable a higher storage density.

[0063] To operate the system 701 (e.g., to perform backup operations, read operations, or both), the word line decoder 725 and the digit line decoder 730 can manage the voltages applied to selected word lines 710 and selected digit lines 715, and can place unselected word lines 710 and unselected digit lines 715 in a potential-free state. For example, the following illustrates Fig. 7B a sequence of security operations which includes a security operation 750 for an anti-security cell 705-a, a security operation 755 for an anti-security cell 705-b, a security operation 760 for an anti-security cell 705-c and a read operation 765 for the anti-security cell 705-b.

[0064] To perform the safety operation 750 for the anti-safety cell 705-a, the word line decoder 725 can select the word line 710-c by applying a first voltage to the word line 710-c, and the digit line decoder 730 can select the digit line 715-c by applying a second voltage to the digit line 715-c. The word line decoder 725 can put the unselected word lines 710 (e.g., word line 710-a, word line 710-b, word line 710-d, and word line 710-e) into a potential-free state, and the digit line decoder 730 can put the unselected digit lines 715 (e.g., digit line 715-a, digit line 715-b, digit line 715-d, and digit line 715-e) into a potential-free state. In some examples, the voltage difference between the first voltage and the second voltage can correspond to the gate oxide breakdown voltage of the anti-fuse cell 705-a.For example, the first voltage can have a first polarity (e.g., positive 3.5 volts (V)), and the second voltage can have a second polarity of the same magnitude as the first voltage (e.g., negative 3.5 V). Therefore, by applying the first voltage to the word line 710-c and the second voltage to the digit line 715-c, a fuse voltage (e.g., 7 V) can be applied to the anti-fuse cell 705-a, which can cause the oxide material of the anti-fuse cell 705-a to break down, thus protecting the anti-fuse cell 705-a.

[0065] To perform the safety operation 755 for the anti-safety cell 705-b, the word line decoder 725 can apply the first voltage to the word line 710-d, and the digit line decoder 730 can apply the second voltage to the digit line 715-c. Since the word line decoder 725 can put the word line 710-c into a potential-free state (e.g., because the word line 710-c may not be selected), no current may flow from the word line 710-c to the digit line 715-c, even though the word line 710-c and the digit line 715-c are coupled via the secured anti-safety cell 705-a.

[0066] Similarly, to perform the fuse operation 760, the word line decoder 725 can apply the first voltage to word line 710-d, and the digit line decoder 730 can apply the second voltage to digit line 715-b. Since the digit line decoder 730 can put digit line 715-c into a potential-free state (e.g., because digit line 715-c may not be selected), no current may flow from digit line 715-c to word line 710-d, even though digit line 715-c and word line 710-d are coupled via the secured anti-fuse cell 705-b.

[0067] To perform a read operation for the anti-fuse cell 705-b, the word line decoder 725 can apply a third voltage (e.g., a read voltage) to the word line 710-d, and the digit line decoder 730 can apply a fourth voltage to the digit line 715-c. In some examples, the fourth voltage can have a different (e.g., lower) magnitude than the first, second, and third voltages. For example, the fourth voltage can be zero. Therefore, the voltage across the anti-fuse cell 705-b can be lower than the gate oxide breakdown voltage of the anti-fuse cell 705-b. Therefore, if the anti-security cell 705-b has been secured (e.g., as in operation 755), a current can flow between the word line 710-d and the digit line 715-c, which can correspond to reading a first logical state (e.g., a logical 1).Alternatively, if the anti-safety cell 705-b has not been secured, the word line 710-d and the digit line 715-c remain isolated, and no current can flow between the word line 710-d and the digit line 715-c, which may correspond to reading a second logical state (e.g., a logical 0). Since the digit line decoder 730 can put the digit line 715-b into a potential-free state and the word line decoder 725 can put the word line 710-c into a potential-free state (e.g., because the digit line 715-b and the word line 710-c may not be selected), no current may flow between the unselected and the selected access lines, even though the digit line 715-b and the word line 710-d are coupled via the secured anti-security cell 705-c and the digit line 715-c and the word line 710-c are coupled via the secured anti-security cell 705-a.

[0068] Fig. 8A, Fig. 8B and Fig. Figure 8C illustrates examples of top views of Systems 801 and 803 and a cross-sectional view of System 802, which supports a vertical backup array architecture according to examples disclosed in this document. System 801 may incorporate aspects of System 300, as described in [reference to relevant document]. Fig. 3 described. For example, the system 801 can be a scheme of an architecture for an anti-backup memory array, comprising one or more digit lines 815 extending in the x-direction and selectively coupled to a voltage source 838 via respective switching components 835 with a digit line decoder 830, and one or more word lines 810 extending in the x-direction and coupled to a word line decoder 825, each of which can be an example of the corresponding component, as described with reference to Fig. 3 was described.

[0069] The 801 system can include an array of anti-fuse cells 805. An anti-fuse cell 805 can include an anti-fuse 840 coupled between a switching component 845 and a digit line 815. The switching component 845 can selectively couple the anti-fuse 840 to a grounded voltage source 850 and can be activated by activating a linked word line 810.

[0070] The 845 switching component can be an example of a vertical TFT. For example, it illustrates Fig. Figure 8B shows a cross-sectional view of a vertical TFT. The switching component 845 can include a terminal 811, which is coupled to a grounded voltage source (e.g., coupled to the conductor track 850) below the terminal 811, a channel 812, which extends vertically (e.g., in the z-direction) above the terminal 811, and a terminal 813 above the channel 812. The switching component 845 can be operated using a word line 810 (e.g., the word line 810 can act as the gate of the vertical TFT). Thus, activating the word line 810 can cause the switching component 845 to become conductive and thereby couple the terminal 811 to the terminal 813. In some embodiments, the switching component 845 can include an oxide material 860, which is an example of the one described with reference to Fig. The oxide material 460 described in section 4 may be located between the word line 810 and the channel 812.

[0071] The terminal 813 of the switching component 845 can be coupled to the anti-fuse 840 positioned above the terminal 813. The anti-fuse 840 can include an electrically conductive contact 855 above the terminal 813 and an oxide material 814 between the terminal 813 and the electrically conductive contact 855. The electrically conductive contact 855 can also be coupled to a digit line 815 positioned above the electrically conductive contact.

[0072] In some examples, the anti-fuse cell 805 can be implemented using a single switching component 845 (e.g., a single vertical TFT) coupled with a corresponding anti-fuse 840, as described with reference to Fig. 8B described. Additionally or alternatively, the anti-fuse cell 805 can be implemented using multiple switching components 845 (e.g., multiple vertical TFTs), each switching component 845 being coupled to a respective anti-fuse 840. In such examples, the anti-fuses 840 of the multiple switching components 845 can each be coupled to the same digit line 815 (e.g., the anti-fuses 840 can be connected in parallel).

[0073] The digit line decoder 830 and the word line decoder 825 can access the anti-fuse cell 805 by operating the word line 810 and the digit line 815, which are linked to the anti-fuse cell 805. For example, to protect the anti-fuse cell 805, the word line decoder 825 can activate the switching component 845 to couple the anti-fuse 840 to the grounded voltage source 850, and the digit line decoder 830 can apply an initial voltage to the digit line 815. The initial voltage can be high enough to cause the oxide material 814 to break down, which can couple (e.g., fuse) the digit line 815 to channel 812. For example, the initial voltage can exceed the gate oxide breakdown voltage of the anti-fuse 840. Alternatively, the word line decoder 825 can activate the switching component 845 to read the anti-fuse, and the digit line decoder 830 can supply a second voltage (e.g.A voltage (e.g., a reading voltage) can be applied to the digit line 815. If the oxide material 814 has been penetrated, activating the switching component 845 can couple the digit line 815 to the grounded voltage source 850. Alternatively, if the oxide material 814 has not been penetrated, the digit line 815 can remain isolated from the grounded voltage source 850. A component coupled to the digit line 815 (e.g., a sensing component) can sense the current or voltage on the digit line 815 in order to read the logical state stored by the anti-fuse 805.

[0074] Fig. Figure 8C illustrates a top view of a System 803 that includes an array of switching components 845. The System 803 can be an example of the System 801, implementing aspects of the System 802 as the switching component 845 and the anti-fuse 840 of an anti-fuse cell 805. For example, the System 803 can include one or more grounded voltage sources 850 extending in the y-direction. Each grounded voltage source 850 can be coupled, via a switching component 845 (e.g., a vertical TFT), to an anti-fuse 840 positioned above the grounded voltage source 850. The System 803 can include one or more word lines 810 extending in the x-direction, each word line 810 being coupled to a row of anti-fuse cells 805 (e.g., as the gate of each of a row of vertical TFTs).

[0075] In some examples, a subset of the vertical TFTs can include an oxide material 814 and an electrically conductive contact 855 formed on an upper surface of the vertical TFT. For example, the array of switching components 845 can be arranged according to a grid 865 in the x-direction (e.g., a distance between adjacent columns). However, to maintain adequate spacing between adjacent digit lines 815 (e.g., sufficient spacing to mitigate short circuits or capacitive coupling between digit lines 815), the digit lines 815 can be arranged according to a larger grid 875 than the grid 865. For example, the grid 875 can be an integer multiple of the grid 865 such that each row of digits 815 is arranged over a corresponding electrically conductive contact 855. The integer can be selected based on a spacing sufficient for the digit lines 815.Additionally, to maintain a suitable distance between the active word lines 810, the electrically conductive contacts 855, or both (e.g., a distance large enough to mitigate short circuits or capacitive coupling between adjacent electrically conductive contacts 855 and the linked word lines 810), the electrically conductive contacts 855 can be arranged according to a grid 870 in the y-direction that is larger than a grid 872 of the switching components 845 in the y-direction. For example, the grid 870 can be an integer multiple of the grid 872, the integer being selected based on a distance sufficient for the word lines 810 or electrically conductive contacts 855. Accordingly, a minimum size of an anti-security cell 805 can be determined by grid 865, grid 870, grid 872, grid 875, or a combination thereof. For example, the one in . Fig.Figure 8C illustrated anti-security cell 805 having a dimension in the x-direction (e.g., a length, grid 875) that is four times the grid 865, and a dimension in the y-direction (e.g., a height, grid 870) that is twice the grid 872. However, a person skilled in the art can see that such a selection of integers is only an example and that other selections are possible. In some examples, the digit lines 815 can be configured as access lines (e.g., bit lines, digit lines) for a memory array. For example, the digit lines 815 could be examples of bit lines for a memory array formed above system 803. In such cases, the switching component 845 can be configured as a selection component for the memory array.

[0076] It should be noted that the procedures described in this document represent possible implementations and that the operations and steps can be rearranged or otherwise modified, and that other implementations are possible. Furthermore, sections of two or more of the procedures can be combined.

[0077] This document describes an institution. The following is an overview of aspects of the institution as described in this document:

[0078] Aspect 1: A device comprising: a first layer comprising a switching component and a first access line extending in a first horizontal direction configured to activate the switching component; and a second layer above the first layer in a vertical direction, the second layer comprising: an anti-fuse comprising a channel extending in the vertical direction and a dielectric material arranged on at least one side wall of the channel, the channel being located above a first terminal coupled to the switching component; and a second access line extending in a second horizontal direction perpendicular to the first horizontal direction and coupled to the dielectric material.

[0079] Aspect 2: The device according to Aspect 1, wherein: the first layer further comprises a second switching component coupled to a third access line extending in the first horizontal direction and configured to activate the second switching component; and the second layer further comprises a second anti-fuse coupled to the second access line, wherein the second anti-fuse comprises a second channel extending in the vertical direction, and the dielectric material is arranged on at least one side wall of the second channel, wherein the second channel is located above a second terminal coupled to the second switching component, and wherein a semiconductor material forming the channel and the second channel extends from the channel of the anti-fuse to the second channel of the second anti-fuse.

[0080] Aspect 3: The setup according to Aspect 2, wherein a first section of the dielectric material is configured to break down at least partially based on the activation of the switching component, and a second section of the dielectric material is configured to break down at least partially based on the activation of the second switching component.

[0081] Aspect 4: The device according to one of aspects 1 to 3, further comprising: a third layer between the first layer and the second layer, wherein the third layer includes an electrically conductive plate that couples a connection below the anti-fuse to the switching component.

[0082] Aspect 5: The device according to aspect 4, further comprising: a plurality of second anti-fuses, wherein each second anti-fuse of the plurality of second anti-fuses comprises a respective channel above a second terminal coupled to the switching component via the electrically conductive plate, and a respective dielectric material arranged on at least one respective side wall of the respective channel.

[0083] Aspect 6: The arrangement according to aspect 5, wherein the second access line is coupled to the respective dielectric material of each from a first subset of the plurality of second anti-fuses, and a third access line extending in the second horizontal direction is coupled to the respective dielectric material of each from a second subset of the plurality of second anti-fuses.

[0084] Aspect 7: The device according to one of aspects 4 to 6, wherein the third layer further comprises a second electrically conductive plate adjacent to the electrically conductive plate, wherein the second electrically conductive plate couples a connection of a second anti-fuse to a second switching component.

[0085] Aspect 8: The device according to aspect 7, further comprising: a third anti-fuse between the anti-fuse and the second anti-fuse, wherein the third anti-fuse is insulated from the electrically conductive plate and the second electrically conductive plate.

[0086] Aspect 9: The setup according to one of aspects 1 to 8, wherein the switching component includes a first terminal coupled to an earthed voltage source and a second terminal coupled to the first terminal of the channel.

[0087] Aspect 10: The setup according to one of aspects 1 to 9, further comprising: a first decoder coupled to the first access line and configured to apply a first voltage to the first access line to activate the switching component; and a second decoder coupled to the second access line and configured to apply a second voltage to the second access line.

[0088] Aspect 11: The setup according to Aspect 10, wherein the dielectric material is configured to break down at least partially based on activation of the switching component and application of the second voltage to the second access line.

[0089] Aspect 12: The setup according to one of aspects 1 to 11, wherein the switching component includes a complementary metal oxide semiconductor (CMOS) transistor within a substrate.

[0090] This document describes an institution. The following is an overview of aspects of the institution as described in this document:

[0091] Aspect 13: A device comprising: an anti-fuse comprising a channel extending in a vertical direction and a dielectric material arranged on at least one side wall of the channel; a digit line comprising a plurality of digit lines extending in a first horizontal direction, the digit line being connected to a terminal below the anti-fuse; and a word line comprising a plurality of word lines extending in a second horizontal direction perpendicular to the first horizontal direction and in contact with the dielectric material of the anti-fuse.

[0092] Aspect 14: The setup according to Aspect 13, further comprising: a digit line decoder coupled to the multitude of digit lines and configured to select the digit line as part of an access operation for anti-security; and a word line decoder coupled to the multitude of word lines and configured to select the word line as part of the access operation.

[0093] Aspect 15: The setup according to Aspect 14, wherein, as part of a programming operation for the anti-security, the digit line decoder is configured to apply a first voltage of a first polarity to the digit line, and the word line decoder is configured to apply a second voltage of a second polarity to the word line.

[0094] Aspect 16: The setup according to aspect 15, wherein, as part of the programming operation, the digit line decoder configures one or more non-selected digit lines of the multitude of digit lines into a potential-free state, and the word line decoder configures one or more non-selected word lines of the multitude of word lines into a potential-free state.

[0095] Aspect 17: The setup according to one of aspects 15 to 16, where one magnitude of the first voltage is equal to one magnitude of the second voltage.

[0096] This document describes an institution. The following is an overview of aspects of the institution as described in this document:

[0097] Aspect 18: A device comprising: a first access line extending in a first horizontal direction; a vertical transistor above a first terminal coupled to the first access line and located in a vertical direction above it, a channel region above the first terminal and a second terminal above the channel region; a second access line extending in a horizontal direction perpendicular to the first horizontal direction and coupled to the channel region of the vertical transistor; a dielectric material above the second terminal of the vertical transistor; and an electrically conductive contact coupled to the dielectric material.

[0098] Aspect 19: The arrangement according to aspect 18, further comprising: a third access line above the electrically conductive contact and extending in the first horizontal direction, wherein the third access line is configured as a bit line for an array of memory cells above the vertical transistor.

[0099] Aspect 20: The setup according to Aspect 19, wherein the dielectric material is configured to break down at least partially based on activating the vertical transistor using the second access line, applying a first voltage to the first access line and applying a second voltage to the third access line.

[0100] The information and signals described herein can be represented using any of a wide variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols referenced in the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings may depict signals as a single signal; however, the signal may also represent a bus of signals, the bus being capable of having a variety of bit widths.

[0101] The terms "electronic communication," "electrically conductive contact," "connected," and "coupled" can refer to a relationship between components that supports the flow of signals between them. Components are considered to be electronically communicating with each other (e.g., in electrically conductive contact, connected, or coupled) if there is an electrical path (e.g., an electrically conductive path) between them that can support the flow of signals (e.g., charge, current, voltage) between them at any given time. At any given time, an electrically conductive path between components that are in electronic communication with each other (e.g., in electrically conductive contact, connected, or coupled) can be an open circuit or a closed circuit, depending on the operation of the device that includes the connected components.An electrically conductive path between connected components can be a direct path between the components themselves, or it can be an indirect path that may include intermediate components such as switches, transistors, or other devices. In some examples, the flow of signals between the connected components can be interrupted temporarily, for example, by using one or more intermediate components such as switches or transistors.

[0102] The term "coupling" (e.g., "electrical coupling") can refer to a transitional state from an open-loop relationship between components, in which signals cannot currently be communicated between the components (e.g., via an electrically conductive path), to a closed-loop relationship between components, in which signals can be communicated between the components (e.g., via the electrically conductive path). When a component, such as a controller, couples other components, the component triggers a change that allows signals to flow between the other components via an electrically conductive path that previously did not permit signal flow.

[0103] The term "isolated" refers to a relationship between components in which no signals can currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, two components separated by a switch positioned between them are disconnected when the switch is open. When a controller isolates two components from each other, the controller causes a change that prevents signals from flowing between the components via an electrically conductive path that previously allowed signal flow.

[0104] The terms "layer" or "plane" used in this text refer to an organization (e.g., a layer, a sheet) of a geometric structure (e.g., relative to a substrate). Each layer or plane can have three dimensions (e.g., height, width, and depth) and cover at least a portion of a surface. For example, a layer or plane can be a three-dimensional structure in which two dimensions are larger than a third, e.g., a thin film. Layers or planes can contain different elements, components, or materials. In some examples, a layer or plane may be composed of two or more sublayers or subplanes.

[0105] As used in this document, the term "electrode" can refer to an electrical conductor and, in some cases, to an electrical contact with a memory cell or other component of a memory array. An electrode may include a conductor track, wire, electrically conductive line, electrically conductive layer, or the like, providing a conductive path between components of a memory array.

[0106] The devices discussed in this paper, including a storage arrangement, can be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate or portions of the substrate can be controlled by doping using various chemicals, including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other dopant.

[0107] A switching component (e.g., a transistor) discussed in this paper may represent a field-effect transistor (FET) and may comprise a three-terminal component including a source (e.g., a source terminal), a drain (e.g., a drain terminal), and a gate (e.g., a drain terminal). The terminals may be connected to other electronic components by electrically conductive materials (e.g., metals, alloys). The source and drain may be conductive and may comprise a doped (e.g., heavily doped, degenerate) semiconductor region. The source and drain may be separated by a doped (e.g., lightly doped) semiconductor region or channel. If the channel is n-type (e.g., most charge carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (e.g.,Since most charge carriers are holes, the FET can be designated as a p-type FET. The channel can be covered by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to conduct. A transistor can be "on" or "activated" when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. The transistor can be "off" or "disabled" when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

[0108] The description presented in this document, in conjunction with the accompanying drawings, describes example configurations and does not represent all examples that can be implemented or that fall within the scope of the claims. The term "exemplary" as used in this document means "serving as an example, case, or illustration" and not "preferred" or "advantageous over other examples." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can also be applied without these specific details. In some cases, known designs and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0109] In the accompanying figures, similar components or features may share the same reference numeral. Furthermore, different components of the same type can be distinguished by following the reference numeral with a hyphen and a second designation that differentiates the similar components. If only the first reference numeral is used in the description, the description applies to each of the similar components with the same first reference numeral, regardless of the second reference numeral.

[0110] The functions described in this document can be implemented in hardware, in software executed by a processor, in firmware, or in a combination thereof. If implemented in software executed by a processor, the functions can be stored on a computer-readable medium or transferred to it as one or more instructions (e.g., code). Other examples and implementations are within the scope of the disclosure and the attached claims. Due to the nature of software, the functions described in this document can be implemented, for example, using software executed by a processor, hardware, firmware, hardwiring, or combinations thereof.Features that implement functions can also be physically located in different positions, including a distribution such that sections of functions are implemented in different physical locations.

[0111] For example, the various illustrative blocks and modules described in connection with this disclosure can be implemented or executed using a processor, such as a DSP, an ASIC, an FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, another programmable logic device, or any combination thereof, to perform the functions described herein. A processor can be, for example, a microprocessor, a controller, a microcontroller, a state machine, or any type of processor. A processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0112] As used in this document, including in the claims, "or" in a list of elements (e.g., in a list of elements preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that, for example, a list of at least one of A, B, or CA, or B or C, or AB or AC, or BC or ABC (i.e., A and B and C) means A and B and C. The expression "based on" used in this document is not to be interpreted as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without exceeding the scope of this disclosure. In other words, as used in this document, the expression "based on" is to be interpreted in the same way as the expression "at least partly based on".

[0113] Computer-readable media include both non-transitory computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another. A non-transitory storage medium can be any available medium accessible to a computer. By way of example, and not limited to, non-transitory computer-readable media can include: RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc ROM (CD-ROM) or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code resources in the form of instructions or data structures and that can be accessed by a computer or processor.Furthermore, any connection is more accurately described as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source via coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then these technologies are included in the definition of the medium. Disk and disc, as used in this document, include CD, laserdisc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of the above are also included in the scope of computer-readable media.

[0114] The description in this document is provided to enable a person skilled in the art to manufacture or use the disclosure. Various modifications to the disclosure will be obvious to those skilled in the art, and the generic principles defined in this document can be applied to other variations without departing from the scope of the disclosure. Therefore, the disclosure is not limited to the examples and designs described in this document but has the broadest scope consistent with the principles and new features disclosed herein. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 18 / 771,079

[0001] US 63 / 526,871

[0001]

Claims

[1] Facility comprising the following: a first layer comprising a switching component and a first access line extending in a first horizontal direction configured to activate the switching component; and a second layer above the first layer in a vertical direction, the second layer comprising the following: an anti-fuse comprising a channel extending in the vertical direction and a dielectric material arranged on at least one side wall of the channel, wherein the channel is arranged above a first terminal coupled to the switching component; and a second access line that extends in a second horizontal direction perpendicular to the first horizontal direction and is coupled to the dielectric material. [2] Device according to claim 1, wherein: the first layer further comprises a second switching component coupled to a third access line extending in the first horizontal direction and configured to activate the second switching component; and the second layer further comprises a second anti-fuse coupled to the second access line, wherein the second anti-fuse comprises a second channel extending in the vertical direction, and the dielectric material is arranged on at least one side wall of the second channel, wherein the second channel is located above a second terminal coupled to the second switching component, and wherein a semiconductor material forming the channel and the second channel extends from the channel of the anti-fuse to the second channel of the second anti-fuse. [3] Device according to claim 2, wherein a first section of the dielectric material is configured to break down at least partially based on the activation of the switching component, and a second section of the dielectric material is configured to break down at least partially based on the activation of the second switching component. [4] Device according to claim 1, further comprising: a third layer between the first layer and the second layer, wherein the third layer comprises an electrically conductive plate that couples a connection below the anti-fuse to the switching component. [5] Device according to claim 4, further comprising: a plurality of second anti-fuses, wherein each second anti-fuse of the plurality of second anti-fuses comprises a respective channel above a second terminal coupled to the switching component via the electrically conductive plate, and a respective dielectric material arranged on at least one respective side wall of the respective channel. [6] Device according to claim 5, wherein the second access line is coupled to the respective dielectric material of each from a first subset of the plurality of second anti-fuses and a third access line extending in the second horizontal direction is coupled to the respective dielectric material of each from a second subset of the plurality of second anti-fuses. [7] Device according to claim 4, wherein the third layer further comprises a second electrically conductive plate adjacent to the electrically conductive plate, wherein the second electrically conductive plate couples a connection of a second anti-fuse to a second switching component. [8] Device according to claim 7, further comprising: a third anti-fuse between the anti-fuse and the second anti-fuse, wherein the third anti-fuse is insulated from the electrically conductive plate and the second electrically conductive plate. [9] Device according to claim 1, wherein the switching component comprises a first terminal coupled to an earthed voltage source and a second terminal coupled to the first terminal of the channel. [10] Device according to claim 1, further comprising: a first decoder that is coupled to the first access line and configured to apply a first voltage to the first access line in order to activate the switching component; and a second decoder that is coupled to the second access line and is configured to apply a second voltage to the second access line. [11] Device according to claim 10, wherein the dielectric material is configured to break down at least partially based on activation of the switching component and application of the second voltage to the second access line. [12] Device according to claim 1, wherein the switching component comprises a complementary metal oxide semiconductor (CMOS) transistor within a substrate. [13] Institution comprising the following: an anti-fuse comprising a channel extending in a vertical direction and a dielectric material arranged on at least one side wall of the channel; a digit line consisting of a plurality of digit lines extending in a first horizontal direction, the digit line being coupled to a terminal below the anti-fuse; and a word line consisting of a multitude of word lines, extending in a second horizontal direction perpendicular to the first horizontal direction and in contact with the dielectric material of the anti-fuse. [14] Device according to claim 13, further comprising: a digit line decoder coupled to the multitude of digit lines and configured to select the digit line as part of an access operation for anti-security; and a word line decoder that is coupled with the multitude of word lines and configured to select the word line as part of the access operation for anti-security. [15] Device according to claim 14, wherein, as part of a programming operation for the anti-security, the digit line decoder is configured to apply a first voltage of a first polarity to the digit line, and the word line decoder is configured to apply a second voltage of a second polarity to the word line. [16] Device according to claim 15, wherein as part of the programming operation the digit line decoder configures one or more non-selected digit lines of the plurality of digit lines into a potential-free state and the word line decoder configures one or more non-selected word lines of the plurality of word lines into a potential-free state. [17] Device according to claim 15, wherein one magnitude of the first voltage is equal to one magnitude of the second voltage. [18] Institution comprising the following: a first access line extending in a first horizontal direction; a vertical transistor above a first terminal coupled to the first access line and located in a vertical direction above it, a channel area above the first terminal and a second terminal above the channel area; a second access line extending in a second horizontal direction perpendicular to the first horizontal direction and coupled to the channel area of ​​the vertical transistor; a dielectric material above the second terminal of the vertical transistor; and an electrically conductive contact that is coupled to the dielectric material. [19] Device according to claim 18, further comprising: a third access line above the electrically conductive contact and extending in the first horizontal direction, wherein the third access line is configured as a bit line for an array of memory cells above the vertical transistor. [20] Device according to claim 19, wherein the dielectric material is configured to break down at least partially based on activation of the vertical transistor using the second access line, application of a first voltage to the first access line and application of a second voltage to the third access line.

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