ADDRESS SPACE MANAGEMENT IN A REGISTER OF A SYSTEM BASE CHIP

Abstract

Examples include managing the address space in a register bank of a system base chip. A setup includes a bus slave and a system base chip. The system base chip includes a register bank, an access control to limit the bus slave's reach to a selected set of register bank addresses, and an address space manager to specify the selected register bank address set.

Description

PRIORITY CLAIM

[0001] This application claims the priority benefit of the international patent application with serial number PCT / CN2023 / 107648, which was filed on 17 July 2023 and the disclosure of which is hereby incorporated herein by reference in its entirety. AREA

[0002] Examples generally refer to 10SPE physical layers (PHY). Some examples generally refer to a system-based chip implementing a transceiver of a 10SPE PHY and a microcontroller implementing a controller of the 10SPE PHY. Some examples generally refer to a system-based chip managing address space in a register bank of the system-based chip. BACKGROUND

[0003] Integrated circuits (ICs) are used in a variety of operating contexts and can be subjected to a variety of stresses. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] To make it easy to identify the discussion of a specific element or action, the principal number(s) in a reference sign refer to the figure number in which that element is first introduced. Fig. Figure 1 is a block diagram representing a system and architecture of a system base chip (SBC) designed to manage register access and extend the address space of a 10BASE-T1S transceiver, according to one or more examples. Fig. Figure 2 is a block diagram of a system that includes a system base chip and a microcontroller, according to one or more examples. Fig. Figure 3 is a schematic diagram showing exemplary formats for an MDIO bitstream and an I2C bitstream received by MDIO slave with address space management and I2C slave, respectively, according to one or more examples. Fig. Figure 4 is a schematic diagram illustrating examples of specific usage registers according to one or more examples. Fig. 5A is a schematic diagram that represents a register bank or part thereof in an exemplary environment and according to one or more examples. Fig. 5B is a schematic diagram that further illustrates the structure of the registry in an exemplary environment. Fig. Figure 6 illustrates an exemplary process for representing the behavior of an access control logic to enable a modification of address assignments within a system base chip or its address controller, according to one or more examples. Fig. Figure 7 is a flowchart illustrating the process of adding non-native register addresses to the address assignment for the MDIO slave, thereby extending its accessible register range, according to one or more examples. Fig. Figure 8 is a flowchart that depicts a process for validating address access requests to ensure they are within the authorized address allocation, according to one or more examples. Fig. 9 illustrates an aspect of the subject according to one or more examples. Fig. Figure 10 is a block diagram of a switching logic that can be used in some examples to implement various functions, operations, actions, processes or procedures disclosed herein. FORM(S) OF EXECUTION OF THE INVENTION

[0005] The following detailed description refers to the accompanying drawings, which form part of this document and illustrate specific examples of embodiments in which the present disclosure can be exercised. These examples are described in sufficient detail to enable those skilled in the art to put the present disclosure into practice. However, other examples may also be used, and structural, material, and procedural modifications may be made without altering the scope of protection of the disclosure.

[0006] The illustrations presented herein are not intended to be actual views of any particular process or system, or of any particular device or structure, but are merely idealized representations used to describe the examples discussed herein. The drawings presented herein are not necessarily to scale. Similar designs or components in the various drawings may retain the same or similar numbering for the convenience of the reader; however, the similarity in numbering does not imply that the designs or components are necessarily identical in size, composition, configuration, or any other characteristic.

[0007] The following description may include examples to enable those skilled in the art to put the disclosed examples into practice. The use of the terms "exemplary", "as an example", and "for instance" means that the accompanying description is explanatory, and although the scope of protection of the disclosure is intended to include the examples and their legal equivalents, the use of these terms is not intended to limit the scope of protection of any example or of this disclosure to the specified components, steps, features, functions, or the like.

[0008] It is readily apparent that the components of the examples described here in general terms and illustrated in the drawing can be arranged and designed in a multitude of different configurations. Therefore, the following description of various examples is not intended to limit the scope of protection of this disclosure, but is merely representative of various examples. While the different aspects of the examples may be depicted in drawings, these drawings are not necessarily drawn to scale unless expressly stated otherwise.

[0009] Furthermore, the specific implementations shown and described are only examples and should not be interpreted as the only way to implement the present disclosure unless otherwise stated herein. Elements, circuits, and functions may be shown in block diagram form to avoid obscuring the present disclosure with unnecessary details. Conversely, the specific implementations shown and described are only examples and should not be interpreted as the only way to implement the present disclosure unless otherwise stated herein. Additionally, block definitions and the distribution of logic between different blocks are examples of a specific implementation. It is readily apparent to those skilled in the art that the present disclosure can be implemented in practice through numerous other distribution solutions.Details concerning timing considerations and the like have been largely omitted, insofar as such details are not necessary for a complete understanding of the present disclosure and are within the capabilities of skilled persons.

[0010] It is evident to those skilled in the art that information and signals can be represented using a variety of different technologies and techniques. Some drawings may illustrate signals as a single signal for the sake of clarity in representation and description. It is also evident to those skilled in the art that the signal can represent a bus of signals, where the bus can have a variety of bit widths, and the present disclosure can be implemented with any number of data signals, including a single data signal.

[0011] The various illustrative logic blocks, modules, and circuits described in connection with the examples disclosed herein may be implemented or carried out using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein.A general-purpose processor (which may herein be referred to as a host processor or simply a host) may be a microprocessor, but alternatively it may be any conventional processor, control unit, microcontroller, or state machine. A processor may also be implemented as a combination of data processing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. A general-purpose computer, including a processor, is considered a specialized computer, while the general-purpose computer executes computational instructions (e.g., software code, without limitation) relating to the examples discussed herein.

[0012] The examples can be described as a process represented as a program flowchart, flow diagram, structure diagram, or block diagram. Although a flowchart can describe steps of operation as a sequential process, many of these operations can be performed in a different order, in parallel, or substantially simultaneously. Furthermore, the order of the steps can be changed. A process can correspond, without limitation, to a method, thread, function, procedure, subroutine, or subprogram. Moreover, the methods disclosed herein can be implemented in hardware, software, or both. When implemented in software, the functions can be stored or transmitted as one or more instructions or as code on computer-readable media.Computer-readable media include both computer storage media and communication media, including all media that support the transfer of a computer program from one location to another.

[0013] Any reference to an element herein using a label such as "first," "second," etc., does not restrict the set or order of such elements unless such restriction is expressly stated. Rather, these labels herein may be used as a convenient method for distinguishing between two or more elements or instances of an element. Thus, a reference to a first and a second element does not mean that only two elements may be inserted there, or that the first element must in any way precede the second element. Furthermore, unless otherwise stated, a set of elements may comprise one or more elements.

[0014] In the sense used herein, the term "essentially" means, with respect to a given parameter, property, or condition, and includes, to an extent understandable to a person skilled in the art, that the given parameter, property, or condition is fulfilled with a small degree of variance, such as within acceptable manufacturing tolerances. For example, depending on the specific parameter, property, or condition that is essentially fulfilled, the parameter, property, or condition may be fulfilled to at least 90%, at least 95%, or even at least 99%.

[0015] As used herein, relational terms such as “above”, “below”, “on”, “underlying”, “above”, “below” are used without restriction for the sake of clarity and expediency in understanding the revelation and the accompanying drawings, and are not associated with or dependent on any particular preference, orientation or order, unless the context clearly indicates otherwise.

[0016] In this description, the term "coupled" and derivatives thereof may be used to indicate that two elements work together or interact with each other. When an element is described as "coupled" to another element, the elements may be in direct physical or electrical contact, or intermediate elements or layers may be present. Conversely, when an element is described as "directly coupled" to another element, no intermediate elements or layers are present. The term "connected" may be used interchangeably with the term "coupled" in this description and has the same meaning unless explicitly stated otherwise or the context would indicate otherwise to a person skilled in the art.

[0017] As used herein, the terms “activate”, “deactivate” and derivatives thereof, when used in relation to a pen, mean to activate or deactivate a signal associated with the pen (e.g., a signal specifically assigned to the pen, or a signal to which the pen is specifically assigned, without limitation).

[0018] A system-based chip (SBC) is an integrated circuit (IC) that combines several functions for the operation of an electronic system. An SBC typically integrates various different functions onto a single chip, including, but not limited to: Power management functions such as voltage regulators, circuit breakers, or protection switching logic, without limitation, for managing the power supply for the system; communication interfaces such as CAN (Controller Area Network), LIN (Local Interconnect Network), SPI (Serial Peripheral Interface), or I2C (Inter-Integrated Circuit), without limitation; embedded systems such as state machines or microprocessors, without limitation, that control and coordinate tasks; analog functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), temperature sensors, and other signal conditioning switching logic; and diagnostic and safety functions, such as monitoring and reporting voltage levels, temperature, or fault conditions, without limitation.

[0019] Single-board computers (SBCs) are found in a variety of operating contexts, including automotive and industrial applications. A non-restrictive example of an automotive application for SBCs is in 10SPE networks, i.e., 10 Mbps Single Pair Ethernet networks, also known as "10BASE-T1S networks." 10SPE is a network technology specified in IEEE 802.3 clauses 147 and 148. 10SPE can be used to provide collision-free, deterministic transmission in a multidrop network.

[0020] In some cases, a transceiver (xcvr) and a controller of a 10SPE physical layer device (PHY) may reside on different dies, as a non-restrictive example, so that the respective dies undergo different processing conditions. Such an architecture is referred to herein as a "split-PHY" architecture. The digital blocks of the PHY controller, which are susceptible to damage during high-voltage temperature processes, reside on a first die that is not subjected to high-voltage temperature processes. Analog and digital blocks of the PHY transceiver, which are not susceptible to damage during high-voltage temperature processes or which require such high-voltage temperature processes, reside on a second die that undergoes such high-voltage temperature processes.

[0021] The 10SPE transceiver interface standard, currently under specification development by Technology Committee 14 of the Open Alliance (hereinafter referred to as the “TC14 standard”), defines a hardware interface (in particular a 3-pin hardware interface) for communication between a PHY transceiver and a PHY controller in a split-PHY architecture.

[0022] In 10SPE, a microcontroller (MCU) implements the PHY controller functions, and an SBC implements the PHY transceiver functions. In 10SPE, the SBC's non-transceiver responsibilities include regulated power supply, high-voltage domain observability / control, and functional safety mechanisms for the MCU to achieve a safe state. In addition to transceiver functions, the SBC can implement other electronic system functions such as power management, watchdog timers, monitors, and general-purpose input / output (GPIO) without restriction.

[0023] TC14 describes the low-power behavior (sleep-wake behavior) of the PHY transceiver for partial networking. Partial networking refers to a feature that enables selective power management and communication capabilities within a network. Partial networking allows certain network nodes or devices to enter a low-power or sleep state while maintaining basic communication functionality. In Ethernet networks, partial networking is used to optimize power consumption, particularly in automotive or industrial applications. Allowing selected devices to enter a low-power or sleep state can reduce overall power consumption, extend battery life, or improve energy efficiency without limitation.

[0024] The system base chip (SBC) incorporates a 10BASE-T1S transceiver, which necessitates an extended register area due to the limited number of vendor-specific registers defined by the Open Alliance Specification (OA specification). The OA specification allows access to 32 registers via the Management Data Input / Output (MDIO) interface, of which only 15 are available for vendor-specific use. Sometimes it may be desirable to have additional registers for purposes such as non-restrictive examples, tuning, testing, eFuse, and debugging without limitations.

[0025] One or more examples generally relate to the management of address spaces in a register bank of an SBC implementing a 10BASE-T1S transceiver. An SBC implementing a 10BASE-T1S transceiver is able to extend a register range associated with the 10BASE-T1S transceiver beyond the 32 registers defined by the OA specification and manages indirect access to other register ranges within the SBC.

[0026] In one or more examples, the SBC uses at least two of the 15 vendor-specific registers to function as control / address and data registers, thereby enabling access to an extended register area beyond the 32 registers specified in the OA specification. One of the at least two registers is used as a control register and includes fields for read / write control and the address of the extended configuration register. The other of the at least two registers is used as a data register and holds the data to be written to or read from the extended register specified by the control register.

[0027] In one or more examples, an SBC includes a bank of registers that are subdivided (e.g., logically subdivided, physically subdivided, or both, without limitation) into at least two groups: a first group of registers accessible by an MDIO driver, and a second, distinct group of registers accessible by an I2C driver. The MDIO driver handles access to registers in the transceiver-specific address space, and an I2C driver manages access to registers for non-transceiver functions such as power supply and watchdog functions, using a separate register space (e.g., a register space distinct from the transceiver-specific address space).

[0028] In some cases, the respective firmwares of the MDIO and I2C drivers may contain a list of resources, including register addresses, that the firmware can use. However, in some cases, the firmware may be customizable, making it vulnerable to unauthorized access. In one or more examples, the SBC includes hardware locking to ensure that cross-access between MDIO- and I2C-accessible register areas is prevented during normal operation, thus maintaining security and integrity. Attempting to access the wrong resources will result in a violation, and hardware on the SBC will prevent the access from being completed. In this way, the SBC-specific registers are not accessible via the MDIO driver, and the transceiver-specific registers are not accessible via I2C.

[0029] In one or more examples, hardware locking can be temporarily disabled using a specific set or sequence of cryptographic keys (“access keys”) as a non-restrictive example. It may be desirable to disable hardware locking, as a non-restrictive example, for debugging, testing, or programming without limitations. Access keys disable hardware locking, thus allowing cross-disclosing access to registers by both the MDIO and I2C drivers.

[0030] Fig. Figure 1 is a block diagram representing a System 100 and a System Basis Chip (SBC) architecture designed to manage register access and extend the address space of a 10BASE-T1S transceiver, according to one or more examples.

[0031] The System 100 includes a System Base Chip (SBC) 102 and one or more bus slaves 112. The System Base Chip 102 includes an address space manager 104, an access control 106, and a register bank 110. The access control 106 includes an access control logic 108.

[0032] The bus slave(s) 112 is / are a device that operates as a peripheral device or subordinate device to a bus master in a computer or electronic communication system.

[0033] In a bus-based architecture, the electronic communication system, data, and control signals can be transmitted between the respective bus slave(s) 112 (via bitstreams) and between bus slave(s) 112 and bus masters using a bus. Bus slave(s) 112 monitor a bus (e.g., MDIO or I2C) for commands or requests addressed to them, process the received data or instructions, and provide the requested information or execute the requested actions. One or more bus slave(s) 112 can be implemented on the system base chip (SBC) 102 or another device as needed.

[0034] One or more of the 112 bus slaves can be MDIO bus slaves (Management Data Input / Output bus slaves). Non-restrictive examples of MDIO bus slaves include physical layer transceivers (PHY transceivers), Ethernet switches (e.g., Gigabit Ethernet switches, without restriction), network interface cards (NICs), Ethernet media converters, and Ethernet routers and gateways.

[0035] One or more of the Bus Slave(s) 112 can be an I2C bus slave (Inter-Integrated Circuit bus slave). Non-restrictive examples of I2C bus slaves include sensors, memory chips, or peripheral devices. One or more of the Bus Slave(s) 112 can be a PCI bus system (Peripheral Component Interconnect bus system). Non-restrictive examples of PCI bus slaves include a network card, sound card, or peripheral device. Bus Slave(s) 112 monitor the bus for commands or requests addressed to them, process the received data or instructions, and provide the requested information or perform the requested actions.

[0036] Address space manager 104 dynamically manages the accessibility of one or more buses to register bank 110. Address space manager 104 operates by adding or removing addresses from a selected set of addresses in register bank 110. The selected set of addresses corresponds to a selected portion of the register bank's address space with which a bus (e.g., MDIO bus or I2C bus, without restriction) can interact. In one or more examples, address space manager 104 manages the accessibility of one or more buses to register bank 110 in response to an address space expansion request 114. An address space expansion request 114 can identify a bus slave (e.g., one of the bus slave(s) 112, without restriction) and include an identification of a desired address space expansion (e.g., a number of additional registers or addresses, or a quantity of additional memory, without restriction).For example, an address space expansion request 114, which requests an expansion of the transceiver-specific address space, can identify a 10BASET1S transceiver and specify a number of additional registers. In some cases, it may be desirable to reduce the expanded address space of a bus slave (e.g., to free up space for another bus slave, without restriction), and so an address space expansion request 114 can also identify a bus slave and include an identification of a desired address space subtraction (e.g., a number of registers or addresses to be subtracted, or a quantity of memory to be subtracted, without restriction). In one or more examples, the address space manager 104 will not reduce the address space below the native address space of the bus (e.g., a minimum number of addresses or registers in a specification, without restriction).

[0037] In this way, the address space manager 104 effectively controls the range of registers in the registry 110 that a bus (or bus slave) has read or write access to, thus providing flexibility and ensuring efficient use of the registry's resources. As a non-restrictive example, in response to an address space expansion request 114, the address space manager 104 adjusts the range of accessible addresses, thereby effectively controlling which sections of the registry a bus can interact with. This ensures flexibility and efficient use of the registry's resources.

[0038] Access control 106 restricts the reach of a bus to the selected addresses of register 110 that correspond to a selected section of register 110's address space. Access control 106 enforces an interaction boundary within register 110 for a given bus. It does this by blocking all attempts to interact with addresses outside the selected set of addresses in the register's address space. This ensures that a given bus can only read from or write to the allocated address range, as a non-restrictive example, thereby protecting the integrity of the other addresses within the register.

[0039] The access control logic 108 (“Access Control Logic 108”) of the access control 106 acts as a security mechanism for extending the selected set of addresses in the address space of the registry 110. In one or more examples, the access control logic 108 permits the address space manager 104 to add or remove addresses from the selected set of addresses only if a valid set of access keys is provided. This key-based validation process ensures the secure and controlled expansion of the accessible address space and prevents unauthorized or unintended modifications. Thus, for specific address spaces or parts of the registry, the access control logic 108 is informed of predefined sequences or sets of digital keys, each of which authorizes any changes to address spaces.The access control logic 108 is also informed about the current states of the respective address spaces, including which addresses are currently part of the selection set.

[0040] A native bus address is an address (e.g., an address in a bus slave such as a register in register bank 110, without restriction) that can be directly accessed by a given bus master. As used herein, the term "directly accessed" (and derivatives thereof) means accessed using a single access operation (e.g., a single read or write operation, without restriction), and the term "directly accessible" means accessible using a single access operation. As a non-restrictive example of a directly accessible address: an address is placed on the address line, decoded in the register bank, and data is read from or written to the data line. This direct approach enables uniform firmware driver operations. In contrast to a native address, an extensible address is an address (e.g.,(of registers in Registry Bank 110, without restriction), which requires more than a single access operation to access. Expandable addresses are not directly accessible in a single step and involve additional steps, such as using a register as a staging register.

[0041] Fig. Figure 2 is a block diagram of a System 200. The System 200 includes a System Base Chip 202 and a Microcontroller 214. The System Base Chip 202 includes an MDIO slave with address space management 204, an access control logic 206, an I2C slave 208, an access control 210, and a register bank 212. The Microcontroller 214 includes an MDIO master 216 and an I2C master 218.

[0042] The MDIO slave with address space management 204 is an MDIO bus slave and an address space manager (e.g., the address space manager 104 from Fig. 1) Access control logic 206 is a non-restrictive example of access control logic 108 by Fig. 1. Access control 210 is a non-restrictive example of access control 106 of Fig. 1. Register bank 212 is a non-restrictive example of register bank 110 of Fig. 1.

[0043] The System Basis Chip 202 integrates both the Register Bank 212 and a PHY transceiver (neither xcvr logic nor a finite state machine is shown) and offers a flexible address space allocation mechanism. Initially, a specific portion of the Register Bank 212's address space is dedicated exclusively to the MDIO bus / PHY transceiver, and a specific portion of the Register Bank 212's address space is dedicated exclusively to the I2C slave 208. The System Basis Chip 202 provides dynamic address space management (including, without restriction, adding or subtracting address spaces within the selected address space set).

[0044] This allows the entire address space assigned to the I2C slave 208, or a portion thereof (in Fig. 2, referred to as "extended register addresses" or "ext reg addr"), which may include the entire address space of the SBC for non-PHY transceiver-specific functions or a portion thereof, is made accessible to the MDIO slave, thereby extending the range of addresses with which the MDIO can interact. The allocation process is controlled by an address space manager (e.g., an address space manager 104, without restriction), which here is integrated with the MDIO slave, but it may be a separate logic block (e.g., not integrated with the MDIO slave, without restriction). The allocation process is governed by an access control logic 206, which maintains secure and controlled access to the resources of register bank 212 for the purpose of extending or reducing the address space.The access control logic 206 ensures secure and controlled access to the register bank by verifying the provided keys and validating address space modifications. A signal line for an unlock indication (UNLOCK) is shown between the access control logic 206 and the access control 210. The unlock signal is used to control the modification of address assignments. In one or more examples, address assignments can be managed, as a non-restrictive example, in an address domain table of the MDIO slave or an extended domain table. The access control circuit 206 requires a correct set of keys to generate the unlock signal. After validation, the unlock signal allows the MDIO slave with address space management 204 (part of the MDIO slave) to modify the address space, such as adding or removing addresses.In various examples, a first value of the unlock signal can enable a modification of the address assignments, and a second, different (different from the first value) value of the unlock signal can disable modifications to the address assignments.

[0045] Non-restrictive examples of adjusting address assignments include updating control registers or a table (e.g., extended register control & data (referred to as "EXTN CTRL & DATA") in...). Fig. 1) without limitation) to include new addresses within the MDIO allocation. Adjusting address allocations can also include updating control registers or a table to set a register as a staging register for accessing one or more extended registers, as discussed below. Adjusting the address allocation can also include updating (optionally including) control registers or a table to remove addresses from the I2C allocation.

[0046] The MDIO slave with address space management 204 is responsible for managing the register space accessible via the MDIO interface. As discussed above, this can include transceiver-specific address spaces. Signal lines are shown for address (addr) and data (data) between the MDIO slave with address space management 204 and the access controller 210, and between the I2C slave 208 and the access controller 210. Signals on the address line specify the register address in register bank 212 to be accessed (read from or written to), and signals on the data line transmit the actual data to be written to or read from the specified register address.In one example considered, the MDIO slave with address space management 204 or the I2C slave 208 receives address information from the MDIO master 216 or the I2C master 218 and uses this signal to identify specific registers in the register bank 110.

[0047] This structure offers a high degree of flexibility and efficiency in managing the registry's address space and makes it adaptable to the changing requirements of operating the system base chip or the MDIO slave.

[0048] Register bank 212 includes several specific usage registers: a command register and a blocking control register, whose bits are used to control access to and allocation of sections of register bank 212's address space. This arrangement allows flexible, controlled, and secure access to the registers within the bank, as well as their manipulation, particularly for extended or indirect access scenarios.

[0049] Fig. Figure 3 is a schematic diagram showing exemplary formats for an MDIO bitstream 300 and an I2C bitstream 302 received by the MDIO slave with address space management 204 and the I2C slave 208 respectively, according to one or more examples.

[0050] MDIO and I2C each have one data line and one clock line (clock line not shown). Since they each have one data line, data is received as a bitstream, in the format of MDIO bitstream 300 and I2C bitstream 302.

[0051] Referring to the MDIO bitstream 300, bits #1 through #8 are preamble bits, a sequence that prepares the MDIO slave for incoming data. Bit #9 is the start sequence, signaling the beginning of the MDIO frame. Bits #11 and #12 specify the operation type, such as read or write. The next four bits (bits #13-#16) denote the physical address and identify which MDIO device the instruction is intended for. The next five bits (bits #17-#21) are the register address within the target device. The remaining bits are the data payload for the operation.

[0052] Referring to the I2C bitstream 302, the I2C bitstream begins with a start bit, indicating the start of communication. The start bit is followed by a 7-bit address field, which specifies the I2C slave device address. The next bit indicates the operation type (read or write). The following bit is an acknowledgment bit, sent by the I2C slave to confirm receipt of the address. The subsequent bits contain the data payload to be transferred, either read from or written to the I2C slave device. The last bit of the I2C bitstream 302 is a stop bit, marking the end of communication. Both the MDIO driver and the I2C driver utilize bitstreams for data transmission and ensure synchronized communication over a single data line and an accompanying clock line (not shown).The MDIO bitstream 300 and the I2C bitstream 302, their respective formats and bit values, enable access to and management of the register areas within the SBC, allowing precise control and data transmission to and from the MDIO and I2C slaves.

[0053] Fig. Figure 4 is a schematic diagram showing examples of specific usage register 400, according to one or more examples.

[0054] Fig. Figure 4 illustrates the structure and function of exemplary specific usage registers 400 within the SBC, including the tax register, the extension tax register, and the data staging register. These registers are used to manage the extended address space and to ensure secure and flexible access to the register bank's resources. The tax register handles key-based security mechanisms, the extension tax register manages read / write operations for extended addresses, and the data staging register enables indirect data access.

[0055] Control Register 408: This register includes three key-related fields: the first key bit, the second key bit, and an enable bit. The first key bit indicates whether the first key (key1) has been received. It is reset (or cleared) on every write operation to a specific register called SFTR, except when writing to key2. The second key bit signals the receipt of the second key (key2). It allows write access to the SFTR register when both key1 and key2 are '1'. This bit is also reset on every write operation to another specific register, SFIRm. The enable bit acts as a control signal for firmware access (FW access) to all control status register (CSR) bits in an indirect domain. When set to '1', it enables FW access, and when set to '0', it disables FW access.Before enabling or disabling this bit, specific key values ​​must be written to the SFTR register: SFTR-key1 (16'h4149) followed by SFTR-key2 (16'h4155), as non-restrictive examples. SFTR and SFTRm are not shown.

[0056] Extension Control Register 402: This register contains several fields, including an extended address field, a read control, and a write control. The extended register address field is used to hold an address that is part of the selectable range of the register bank's address space. The read control serves as a control signal. When this bit is set to '1', the data stored in extended register 406, referenced by the extended register address stored in extension control register 402, can be read from data staging register 404. The write control functions operate similarly. When set to '1', the data held in data staging register 404 is written to extended register 406, which is assigned to the current extended address.

[0057] The data staging register 404 can be a memory-mapped register. In one or more examples, the system-basis chip 202 or a peripheral device (not shown) maps specific addresses in register bank 212 (the extended address space of register bank 212) to different registers, thereby enabling direct access to these registers through standard memory read and write operations. As a non-restrictive example, an address decoding mechanism is provided that maps unique addresses to specific registers of register bank 212.

[0058] “Reserved” fields are shown to illustrate that not all fields in the specific usage registers need be used exclusively for the address space allocation and access control discussed herein, although they may be used.

[0059] Fig. 5A is a schematic diagram that represents a register bank 502 or part thereof in an exemplary environment and according to one or more examples.

[0060] Register bank 502 includes the allocated native MDIO address space 512 and expandable addresses 514. The native MDIO address space 512 comprises various key register addresses for managing MDIO operations and secure access. In this specific example, the native MDIO address space 512 includes MDIO register address 504, a lock control register address 506, an expansion control register address 508, and a data staging register address 510.

[0061] Register bank 502 is the primary memory area for configuration and operating registers within the system base chip (SBC). The native MDIO address space 512 is the portion of the register bank reserved for addresses natively accessible via the MDIO interface. The MDIO register addresses 504 are standard addresses used for typical MDIO operations, such as configuration and status monitoring. The lock control register address 506 is used to control access permissions and lock or unlock specific sections of the register bank. The expansion control register address 508 manages address space expansion, including controlling read and write operations to expanded addresses. The data staging register address 510 acts as an intermediary for data transfer, providing data to be read from or written to the expanded register space.Expandable addresses 514 are initially located outside the native MDIO address space, but can be dynamically assigned to it.

[0062] Following an address allocation process, extended data register address(es) 516 become logically part of the native MDIO address space 512 and are accessible via the data staging register address 510. The extension control register address 508 and the blocking control register address 506 enable access management and secure modification of the registry's address space. The data staging register address 510 facilitates indirect access to extended addresses and ensures seamless data transfer between the extended and native address spaces.

[0063] Notably extensible addresses 514 include extended data register address(es) 516, which, after an address assignment process, are now logically part of the native MDIO address space 512, as they are accessible via the data staging register address 510.

[0064] Fig. Figure 5B is a schematic diagram that further illustrates the structure of register bank 502 in an exemplary environment. Fig. Section 5B highlights that once the expandable addresses 514 are allocated and integrated into the native MDIO address space 512, they become accessible as part of the overall register space managed by the system base chip (SBC). Identical part numbers carry the same descriptions as in the description of Fig. 5B. In particular, expandable addresses 514, which are initially located outside the native address space, can be reassigned to extend the MDIO addressable space. Furthermore, after reassignment, extended data register address(es) 516 are integrated into the native MDIO address space 512, making them accessible via the data staging register address 510.

[0065] Fig. Figure 6 illustrates an exemplary process 600 for representing the behavior of an access control logic to enable the modification of address assignments within a system base chip or its address controller, according to one or more examples. Although the exemplary process 600 represents a specific sequence of operations, the sequence can be modified without infringing upon the scope of protection of this disclosure. For example, some of the illustrated operations can be performed in parallel or in a different sequence that does not substantially affect the function of the process 600. In other examples, different components of an exemplary device or system implementing the process 600 can perform functions essentially at the same time or in a specific sequence.One or more operations of process 600 may be performed, as non-restrictive examples, by access control logic 108, access control logic 206, access control 106, access control 210, system base chip (SBC) 102, system base chip 202, system 100 or system 200.

[0066] The system starts process 600 with hardware locking enabled, preventing unauthorized changes to the address assignments.

[0067] According to one or more examples, process 600 can include receiving keys from an unlock logic during operation 602. The SBC receives a set of keys from the unlock logic. These keys, if validated, are intended to authorize changes to a requester's address space.

[0068] According to one or more examples, process 600 may include validating received keys in operation 604. In one or more examples, the unlocking logic validates the received keys to ensure they match expected values. Only if the keys are correct and validated can process 600 proceed to allow modification.

[0069] If the keys are not validated (e.g., validation fails without restriction), the hardware lock remains active, and no changes can be made to the address assignments. The SBC's address controller continues to prevent unauthorized modifications and maintains the integrity and security of the registry's address space. Optionally, one or more examples may include an error handling mechanism to log the failed attempt or trigger a security alert. This ensures that any unauthorized attempt to modify the address space is recorded and can be handled accordingly.

[0070] According to one or more examples, process 600 can include enabling a modification of the address assignments on the address controller of the system base chip during process 606. After successful key validation, the unlock logic signals the address controller. The address controller is then activated to modify the address assignments, thereby enabling secure changes to the address space within the register bank.

[0071] In one or more examples, keys can be received as needed over one or more cycles. As a specific, non-restrictive example, the unlock logic can proceed through two verification states: Lock 1 and Lock 2. A transition from Lock 1 to Lock 2 occurs when Key 1 is written, and from Lock 2 to unlock when Key 2 is written. If keys are not written, or are not written within a predetermined number of clock cycles, a finite state machine of the unlock logic transitions from Lock 2 to Lock 1. Process 600 can optionally execute this behavior every time a read or write operation is initiated, or once and then remain in an unlocked state until a reset signal is received.

[0072] Fig. Figure 7 is a flowchart illustrating the process of adding non-native register addresses to the address assignment for the MDIO slave, thereby extending its accessible register range, according to one or more examples. Although the exemplary process 700 represents a specific sequence of operations, the sequence can be modified without infringing upon the scope of protection of this disclosure. For example, some of the illustrated operations can be performed in parallel or in a different sequence that does not substantially affect the function of process 700. In other examples, different components of an exemplary device or system implementing process 700 can perform functions essentially simultaneously or in a specific sequence.One or more operations of process 700 can be performed, as non-restrictive examples, by access control logic 108, access control logic 206, address space manager 104, MDIO slave with address space management 204, access control 106, access control 210, system base chip (SBC) 102, system base chip 202, system 100 or system 200.

[0073] According to one or more examples, process 700 can include selecting N non-native register addresses to add to an address assignment for an MDIO slave in operation 702. In operation 702, process 700 selects a set of N non-native register addresses to be added to the MDIO slave's address assignment. N is an integer greater than or equal to 1.

[0074] According to one or more examples, process 700 can include requesting rights to modify the address assignments of the MDIO slave in operation 704. A request is made to obtain the necessary rights to change the address assignments. This step ensures that only authorized modifications are made to the MDIO slave's address space.

[0075] In some cases, a request to change address assignments may be denied. If the request is denied, no changes will be made to the address space. The integrity and security of the existing address space will be preserved, preventing unauthorized or unintentional modifications. Optionally, an error handling mechanism can log the failed attempt or trigger a notification. This ensures that any unauthorized or failed attempt to modify the address space is recorded and can be handled accordingly.

[0076] According to one or more examples, if granted rights to modify the address assignment of the MDIO slave, process 700 can include adding the n non-native register addresses to the address assignment for the MDIO slave, so that they are extended register addresses of the MDIO slave at process 706. If the request for rights to modify the address assignments is granted, the selected non-native register addresses are added to the address assignment of the MDIO slave. These addresses become extended register addresses for the MDIO slave, thereby extending its accessible register range.

[0077] Non-restrictive examples of modifying address assignments include updating control registers or a table to include new addresses within the MDIO assignment. Address assignment modification can also include updating (optionally including) control registers or a table to remove addresses from the I2C allocation.

[0078] Fig. Figure 8 is a flowchart depicting a process 800 for validating address access requests to ensure they are within the authorized address allocation, according to one or more examples. Although Example 800 represents a specific sequence of operations, the sequence can be modified without infringing upon the scope of protection of this disclosure. For example, some of the depicted operations can be performed in parallel or in a different sequence that does not substantially affect the function of 800. In other examples, different components of an exemplary device or system implementing 800 can perform functions essentially at the same time or in a specific sequence.One or more operations of 800 can be performed as non-restrictive examples by the Access Control Logic 108, the Access Control Logic 206, the Address Space Manager 104, the MDIO Slave with Address Space Management 204, the Access Control 106, the Access Control 210, the System Base Chip (SBC) 102, the System Base Chip 202, the System 100 or the System 200.

[0079] According to some examples, the procedure involves receiving a requested address at an address controller of a system-based chip during operation 802. The SBC's address controller receives a request containing the address the requester intends to access.

[0080] According to some examples, the procedure includes determining whether the requested address is within the requester's address allocation during operation 804. The address controller checks whether the requested address lies within the address allocation assigned to the requester. This step ensures that only authorized addresses are accessible.

[0081] According to some examples, if it is determined that the requested address is not within the requester's address mapping, the procedure includes blocking access at operation 806. If the requested address is not within the authorized address mapping, access is blocked. This prevents unauthorized access to protected registers.

[0082] According to some examples, if it is determined that the requested address is within the requester's address mapping, the procedure includes blocking access at operation 808. If the requested address is within the authorized address mapping, access is granted. The requester can then read from or write to the specified address to the extent permitted.

[0083] Fig. Figure 9 is a block diagram representing a system which is a specific non-restrictive example of System 200.

[0084] It is understood by experts that functional elements of the examples disclosed herein (e.g. functions, operations, actions, processes and / or procedures) can be implemented in any suitable hardware, software, firmware or combinations thereof. Fig. Section 10 illustrates non-restrictive examples of implementations of functional elements disclosed herein. In some examples, some or all sections of the functional elements disclosed herein can be performed by hardware capable of executing the functional elements.

[0085] Fig.Figure 10 is a block diagram of a switching logic 1000, which can be used in some examples to implement various functions, operations, actions, processes, or procedures disclosed herein. The switching logic 1000 includes one or more processors 1002 (hereafter sometimes referred to as "processors 1002") that are operatively coupled to one or more data storage devices 1004 (hereafter sometimes referred to as "storage 1004"). The storage 1004 includes machine-executable code 1006 stored thereon, and the processors 1002 include the logic circuit 1008. The machine-executable code 1006 includes information describing functional elements that can be implemented (e.g., executed) by the logic circuit 1008. The logic circuit 1008 is adapted to implement (e.g. execute) the functional elements described by the machine-executable code 1006.The switching logic 1000 should be considered as special hardware configured to execute the functional elements described by the machine-executable code 1006. In some examples, the processors 1002 can execute the functional elements described by the machine-executable code 1006 sequentially, concurrently (e.g., on one or more different hardware platforms), or in one or more parallel process streams.

[0086] When the machine-executable code 1006 is implemented by the logic circuit 1008 of the processors 1002, it modifies the processors 1002 to perform operations of examples disclosed herein. As a non-restrictive example, the machine-executable code 1006 can modify the processors 1002 to perform some or all of the operations of processes for managing address space in a register bank of a system-basis chip.

[0087] As a non-restrictive example, the machine-executable code 1006 can adapt the processors 1002 to perform some or all of the features, functions, or operations disclosed herein for managing or using address space in a register bank of a system-basis chip.

[0088] The processors 1002 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, another programmable device, or any combination thereof designed to perform the functions disclosed herein. A general-purpose computer, including a processor, is considered a special-purpose computer while the general-purpose computer executes functional elements corresponding to the machine-executable code 1006 (e.g., software code, firmware code, hardware descriptions) that refers to examples in the present disclosure.It should be noted that a general-purpose processor (which may also be referred to herein as a host processor or simply as the host) can be a microprocessor, but alternatively, the Processors 1002 can include any conventional processor, controller, microcontroller, or state machine. The Processors 1002 can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0089] In some examples, the storage 1004 includes volatile data storage (e.g., random access memory (RAM)) and non-volatile data storage (e.g., without limitation, flash memory, a hard disk drive, a solid-state drive, or erasable programmable read-only memory (EPROM)). In some examples, the processors 1002 and the storage 1004 can be implemented in a single device (e.g., in a semiconductor device product, in a system-on-a-chip (SoC), without limitation). In some examples, the processors 1002 and the storage 1004 can be implemented in separate devices.

[0090] In some examples, the machine-executable code 1006 may include computer-readable instructions (e.g., software code, firmware code). As a non-restrictive example, the computer-readable instructions may be stored by the memory 1004, directly called by the processors 1002, and executed by the processors 1002 using at least the logic circuit 1008. Also as a non-restrictive example, the computer-readable instructions may be stored on the memory 1004, transferred to a storage device (not shown) for execution, and executed by the processors 1002 using at least the logic circuit 1008. Accordingly, in some examples, the logic circuit 1008 includes an electrically configurable logic circuit 1008.

[0091] In some examples, the machine-executable code 1006 can describe hardware (e.g., switching logic) that is to be implemented in the logic circuit 1008 to execute the functional elements. This hardware can be described at a number of abstraction levels, from concrete transistor layouts to highly abstract description languages. At a high abstraction level, a hardware description language (HDL), such as an IEEE standard hardware description language (HDL), can be used. Non-restrictive examples include Verilog, System Verilog, or Very Large Scale Integration (VLSI) hardware description languages ​​(VHDL).

[0092] HDL descriptions can be transformed at will into descriptions at any of numerous other levels of abstraction. As a non-restrictive example, a high-level description can be transformed into a logic-level description, such as a register transfer language (RTL), a gate-level description (GL), a layout-level description, or a mask-level description. As a non-restrictive example, microoperations performed by hardware logic circuits (e.g.,The operation of the logic circuit 1008 (gates, flip-flops, registers, without limitation) is to be carried out in an RTL and then converted into a GL description by a synthesis tool. The GL description can be converted into a layout-level description corresponding to a physical layout of an integrated circuit, a programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof by a placement and routing tool. Accordingly, in some examples, the machine-executable code 1006 may include an HDL, an RTL, a GL description, a mask-level description, another hardware description, or any combination thereof.

[0093] In examples where the machine-executable code 1006 includes a hardware description (at any level of abstraction), a system (not shown, but including storage 1004) implements the hardware description provided by the machine-executable code 1006. As a non-restrictive example, the processors 1002 can include a programmable logic device (e.g., an FPGA or a PLC), and the logic circuit 1008 can be electrically controlled to implement switching logic corresponding to the hardware description. Also as a non-restrictive example, the logic circuit 1008 can include hard-wired logic that is manufactured by a production system (not shown, but including storage 1004) according to the hardware description of the machine-executable code 1006.

[0094] Regardless of whether the machine-executable code 1006 includes computer-readable instructions or a hardware description, the logic circuit 1008 is adapted to execute the functional elements described by the machine-executable code 1006 when the functional elements of the machine-executable code 1006 are implemented. It should be noted that, although a hardware description may not directly describe functional elements, a hardware description indirectly describes functional elements that can perform the hardware elements described by the hardware description.

[0095] As used in this disclosure, the terms “module” or “component” may refer to specific hardware implementations configured to perform the actions of the module or component and / or software objects or routines that can be stored on and / or executed by general-purpose hardware (e.g., computer-readable media, processing devices, without limitation) of the computing system. In some examples, the various components, modules, engines, and services described in this disclosure may be implemented as objects or processes that run on the computing system (e.g., as separate threads).Although some of the systems and methods described in the present disclosure are generally described as being implemented in software (stored on and / or executed by universal hardware), specific hardware implementations or a combination of software and specific hardware implementations are also possible and are considered.

[0096] As used in the present revelation, the term “combination” in relation to a multitude of elements can include a combination of all the elements or any of several different subcombinations of some of the elements. For example, the phrase “A, B, C, D or combinations thereof” can refer to any one of A, B, C or D; the combination of each of A, B, C and D; and any subcombination of A, B, C or D, such as A, B and C; A, B and D; A, C and D; B, C and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0097] Terms used in this disclosure, and in particular in the accompanying claims (e.g., the main parts of the accompanying claims, without limitation), are generally to be understood as "open" terms (e.g., the term "including" should be interpreted as "including, without limitation," the term "having" should be interpreted as "having at least"; the term "includes" should be interpreted as "includes, without limitation"). As used herein, the term "each" means "some or a whole." As used herein, the term "all" means a "whole."

[0098] Furthermore, if a specific number is intended in an introductory claim statement, this intention will be expressly stated in the claim, and in the absence of such a statement, no such intention exists. For example, the following appended claims may contain the use of the introductory phrases "at least one" and "one or more" to introduce claim statements. However, the use of such phrases should not be interpreted to imply that introducing a claim statement with the indefinite articles "one" or "a" limits a particular claim containing such an introduced claim statement to examples that contain only one such statement, even if the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "one" or "a" (e.g.,“A” and / or “an” should be interpreted as meaning “at least one” or “one or more”, without restriction); the same applies to the use of certain articles used to introduce claims.

[0099] Even if a specific number of an introduced claim statement is explicitly stated, the person skilled in the art will additionally recognize that such a statement should be interpreted as meaning at least the stated number (e.g., the mere statement of "two statements" without any other modifiers means at least two statements, or two or more statements without limitation). Furthermore, in cases where a convention is used analogously to "at least one of A, B, and C, without being limited thereto" or "one or more of A, B, and C, without being limited thereto," such a construction should generally include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, without being limited thereto.

[0100] Furthermore, any disjunctive word or phrase representing two or more alternative terms, whether in the description, claims, or drawings, should be understood as including either term, either term, or both terms. For example, the phrase "A or B" should be understood to include the possibilities of "A" or "B" or "A and B".

[0101] Other non-restrictive examples include: Example 1: Setup comprising: a bus slave; a system base chip including: a register bank; an access control for limiting the range of the bus slave to a selected set of register bank addresses; and an address space manager for setting the selected set of register bank addresses. Example 2: Setup according to Example 1, wherein, for setting the selected set of addresses of the registry bank, the address space manager is designed to: change addresses within the selected set of addresses of the registry bank. Example 3: Setup according to one of Examples 1 and 2, wherein, to change addresses within the selected set of addresses of the registry, the address space manager is designed to: add or remove addresses from the selected set of addresses of the registry. Example 4: Setup according to one of Examples 1 to 3, wherein, to limit the range of the bus slave to the selected set of register bank addresses, the access control is designed to: allow interaction of the bus slave with registers of the register bank corresponding to the selected set of register bank addresses; and block interaction of the bus slave with registers of the register bank corresponding to addresses outside the selected set of register bank addresses. Example 5: Setup according to one of examples 1 to 4, where the bus slave is a management data input / output bus slave. Example 6: Setup according to one of Examples 1 to 5, where the selected set of registry addresses includes native addresses of the bus slave. Example 7: Setup according to one of Examples 1 to 6, wherein the access control is designed to: allow the address space manager to modify the selected set of registry addresses, at least partially, in response to a key-based validation process. Example 8: Setup according to one of Examples 1 to 7, comprising: another bus slave, wherein the access control is designed to: restrict the range of the additional bus slave to another selected group of addresses of the register bank. Example 9: Setup according to one of Examples 1 to 8, wherein a register of the register bank includes a first key field, a second key field and an enable field, wherein the first key field indicates whether a first key has been received and validated or not, wherein the second key field indicates whether a second key has been received and validated or not, and wherein the enable field indicates whether the firmware has access to an entirety of bits of a control status register of the system base chip or not. Example 10: Setup according to any of Examples 1 to 9, wherein a register of the register bank includes an extended address field, a read field, and a write field, wherein the extended address field is designed to hold an extended address in the selected set of addresses of the register bank, wherein the extended address is associated with an extended register; wherein the read field indicates whether or not data can be read from the extended register via a data staging register; and wherein the read field indicates whether or not data can be written to the extended register via a data staging register. Example 11: Setup according to one of Examples 1 to 10, where the extended register is a memory-mapped register. Example 12: Setup according to one of Examples 1 to 11, wherein the address space manager, in response to a debug state of the system base chip, is designed to set the selected set of register bank addresses such that it encompasses an entirety of a register bank address space. Example 13: Setup according to any of Examples 1 to 12, comprising: a physical layer transceiver, wherein the access control is designed to: restrict the reach of the physical layer transceiver to a further selected set of addresses of the register bank, wherein the selected set of addresses is different from the further selected set of addresses. Example 14: Procedure comprising: selecting N non-native register addresses to add to an address assignment for an MDIO slave; requesting rights to modify address assignments of the MDIO slave; and, if rights to modify the address assignment of the MDIO slave are granted, adding the N non-native register addresses to the address assignment for the MDIO slave such that they are extended register addresses of the MDIO slave.

[0102] Although the present disclosure has been described herein with respect to certain illustrated examples, those skilled in the art will recognize and understand that the present invention is not limited to these. Rather, many additions, omissions, and modifications can be made to the illustrated and described examples without altering the scope of protection of the invention as claimed below together with its legal equivalents. Furthermore, features of one example can be combined with features of another example and still remain within the scope of protection of the invention as envisaged by the inventor. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] CN 2023 / 107648

[0001]

Claims

[1] Institution, encompassing: a bus slave; a system base chip that includes: a registry bank; an access control to limit the range of the bus slave to a selected set of addresses in the registry; and an address space manager to set the selected set of addresses in the registry bank. [2] Device according to claim 1, wherein the address space manager is designed to set the selected set of addresses of the registry bank: To change addresses within the selected set of addresses of the registry bank. [3] Device according to claim 2, wherein, for changing addresses within the selected set of addresses of the registry bank, the address space manager is designed to: To add or remove addresses from the selected set of addresses in the registry. [4] Device according to claim 2, wherein the access control is designed to limit the range of the bus slave to the selected set of addresses of the register bank: to enable interaction of the bus slave with registers of the registry that correspond to the selected set of registry addresses; and to block the interaction of the bus slave with registers of the registry that correspond to addresses outside the selected set of registry addresses. [5] Device according to claim 1, wherein the bus slave is a management data input / output bus slave. [6] Device according to claim 1, wherein the selected set of registry addresses includes native addresses of the bus slave. [7] Device according to claim 1, wherein the access control is designed to: to enable the address space manager to change the selection set of addresses of the registry bank, at least partially, in response to a key-based validation process. [8] Device according to claim 1, comprising: another bus slave, the access control is designed to: to limit the range of the additional bus slave to a further selected set of addresses of the registry bank. [9] Device according to claim 1, wherein a register of the register bank includes a first key field, a second key field and a release field, where the first key field indicates whether a first key has been received and validated or not, where the second key field indicates whether a second key was received and validated or not, where the enable field indicates whether the firmware has access to a set of bits of a control status register of the system base chip or not. [10] Device according to claim 1, wherein a register of the register bank includes an extended address field, a read field and a write field, wherein the extended address field holds an extended address in the selected set of addresses of the registry bank, wherein the extended address is linked to an extended register; where the read field indicates whether or not data can be read from the extended register via a data staging register; and where the read field indicates whether data can be written to the extended register via a data staging register or not. [11] Device according to claim 10, wherein the extended register is a memory-mapped register. [12] Device according to claim 1, wherein the address space manager, in response to a debug state of the system base chip, is designed to set the selection set of register bank addresses such that it includes an entirety of a register bank address space. [13] Device according to claim 1, comprising: a physical layer transceiver, the access control is designed to: to restrict the range of the physical layer transceiver to a further selected set of addresses of the registry bank, where the selected set of addresses differs from the other selected set of addresses. [14] Procedures, including: Selecting N non-native register addresses to add to an address assignment for an MDIO slave; Requests for rights to modify address assignments of the MDIO slave; and When granting rights to modify the address assignment of the MDIO slave, add the N non-native register addresses to the address assignment for the MDIO slave, so that they are extended register addresses of the MDIO slave.

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