SYSTEM WITH A PARTICIPANT IN A DATA NETWORK AND CORRESPONDING PARTICIPANTS

Description

[0001] The invention relates to a system with a subscriber of a wired data network and a corresponding subscriber, in particular a subscriber of a local bus system.

[0002] EP 1 368 728 B1 discloses a synchronous, clocked communication system with a relative clock and a method for setting up such a system. To ensure clock-synchronous data exchange, the participants are continuously resynchronized during operation.

[0003] The duration of a communication cycle is between 10 µs and 10 ms.

[0004] A clock recovery circuit is known from US 2012 / 0008727 A1. Clock recovery encompasses data transfer rates between 1 and 30 Gbps or higher. Clock recovery is also known from "HFTA-07.0: Precision Reference Clock Usage in Clock and Data Recovery Circuits," www.maximintegrated.com, March 13, 2003.

[0005] DE 10 2012 108 696 A1 discloses a data bus subscriber with a data bus interface, which has - a downstream data bus input for receiving data from a higher-level data bus subscriber and - a clock generator for generating an internal clock signal for the data bus subscriber. The data bus subscriber has a synchronization unit for synchronizing the clock generator to the clock signal of the higher-level data bus subscriber, wherein the synchronization unit is configured to detect transitions in the downstream data stream received at the downstream data bus input. The synchronization unit is configured to regulate the frequency of the internal clock signal depending on the detected transitions and to set a defined phase position of the internal clock signal relative to the detected transitions.

[0006] US 2014 / 281656 A1 describes an HPC system in which processor clock signals are generated for each processor, ensuring that all processor clock signals have the same frequency. Furthermore, during a startup process, all processor time stamp counters are set to display identical times. Each blade of the HPC system receives a recovered clock signal from a synchronous communications network to which the blade is connected. The blade generates a processor clock from the recovered clock signal and makes it available to the processors on the blade.

[0007] EP 1 653 651 A2 describes a modular numerical control device with low-jitter synchronization, comprising a main computer and at least one controller unit, which, starting from the main computer, are connected to one another in series via serial data transmission channels. The at least one controller unit contains a first receiver unit for receiving a serial data stream arriving from the main computer and a first transmitter unit for outputting a serial data stream. Furthermore, a clock recovery unit is provided in the at least one controller unit, which derives a synchronous clock signal from the serial data stream arriving at the first receiver unit and feeds it to the first transmitter unit, which uses it as a transmission clock signal, so that the serial data stream arriving at the first receiver unit and the serial data stream output by the first transmitter unit are coupled to one another in a phase-locked manner.

[0008] J. Aweya's publication "Implementing Synchronous Ethernet in Telecommunication Systems," IEEE Communications Surveys & Tutorials, IEEE; USA, Vol. 16, No. 2, April 1, 2024, pages 1080–1113, XP011547644, explains the structure, function, and implementation of a Synchronous Ethernet (Sync-E). Examples of Sync-E node timing architectures and some network timing applications and related problems are described.

[0009] The object of the present invention is to provide a system with a subscriber of a wired data network that is as improved as possible, as well as a subscriber that is as improved as possible. This object is achieved by a system having the features of claim 1. Advantageous further developments are the subject of dependent claims.

[0010] Accordingly, a participant in a wired data network is provided. The wired data network is, in particular, a local bus system. A wired data network enables the transmission of data, for example, via electrically and / or optically conductive connections. A local bus system can be connected to a higher-level fieldbus system via a coupler.

[0011] The subscriber has an internal clock for generating a clock signal with a clock frequency for the subscriber. An internal clock is to be understood as at least one internal clock, whereby the subscriber can have a plurality of clocks that generate a different clock signal and / or a different clock frequency. The internal clock is arranged in the subscriber itself. For example, the internal clock is a component of a circuit of the subscriber. The clock signal is a signal that can provide a clock to circuit components of the subscriber. The clock signal is, for example, a digital square wave signal with a high edge steepness and low jitter.

[0012] The subscriber has a receive circuit for receiving a serial receive data stream. A receive circuit is to be understood as at least one receive circuit; for example, a subscriber with two bus connections may require at least two receive circuits. Accordingly, a serial receive data stream is to be understood as at least one serial receive data stream. A serial receive data stream is part of a serial data transmission. Using serial data transmission, digital data can be transmitted autonomously on one or more line pairs. The serial receive data stream can, for example, be bit-serial data transmission, with one or more lines being able to be used in parallel. To transmit the serial receive data stream, the data can be complex modulated, whereby the signals generated by modulation no longer have individual bits, e.g. QAM4 or QAM64.

[0013] The subscriber has a processing circuit for inputting parallel received data and outputting parallel transmitted data. A processing circuit is understood to mean at least one processing circuit; for example, two receive circuits can be assigned to different processing circuits. Advantageously, the processing circuit is configured to input a fixed number of bits as parallel received data, for example, 8 bits. According to an advantageous development, the respective number of parallel bits of the parallel received data and the parallel transmitted data is the same.

[0014] The subscriber has a transmit circuit for transmitting a serial transmit data stream. A transmit circuit is to be understood as at least one transmit circuit. For example, the subscriber can have two bus connections for the transmission of two different additional subscribers, whereby each bus connection can be assigned a transmit circuit. Accordingly, a serial transmit data stream is to be understood as at least one serial transmit data stream. A serial transmit data stream is part of a serial data transmission. Using serial data transmission, digital data can be transmitted autonomously on one or more line pairs. The serial transmit data stream can, for example, be implemented as a bit-serial data transmission, whereby one or more lines can be used in parallel.To transmit the serial data stream, the data can be complexly modulated, whereby the signals generated by modulation no longer have individual bits, e.g. QAM4 or QAM64.

[0015] According to an advantageous development, the receiving circuit has a serial-to-parallel converter for converting serial receive data of the serial receive data stream into parallel receive data. A serial-to-parallel converter is to be understood in the sense of at least one serial-to-parallel converter; for example, with two line pairs of serial transmission, two serial-to-parallel converters can convert the data in parallel. A serial-to-parallel converter advantageously has at least one input for the serial receive data and parallel outputs for the parallel receive data and is designed to convert the serial receive data into parallel receive data. For example, the serial-to-parallel converter has digital memory cells and is designed as a register, in particular as a shift register.

[0016] According to an advantageous development of the invention, the receiving circuit has a synchronization unit for synchronizing the internal clock to the data clock frequency contained in the serial received data stream. A synchronization unit is to be understood in the sense of at least one synchronization unit. The synchronization unit is preferably a circuit. The synchronization unit is integrated, for example, on a semiconductor chip, for example together with at least parts of the clock. The synchronization comprises, for example, frequency synchronization, wherein the clock frequency of the internal clock is automatically adjusted. According to developments of the invention, the synchronization can comprise one or more additional synchronizations, for example, phase synchronization or amplitude synchronization.Because the data clock frequency is included in the serial receive data stream, it can, for example, exist implicitly as information in the receive data stream; for example, the smallest period between two transitions is an inverse of the data clock frequency. Accordingly, no explicitly transmitted frequency value is required for synchronization. Preferably, the synchronization unit is configured to detect transitions in the received serial receive data stream and to regulate the clock frequency of the internal clock depending on the detected transitions. For example, transitions in a bit-serial signal are signal edges between low and high. For example, transitions in a modulated data stream are transitions between modulation states. For example, in QAM4 there are four states between which transitions can be detected.

[0017] According to an advantageous development of the invention, the transmission circuit has a parallel-to-serial converter for converting the parallel transmission data into serial transmission data of the transmission data stream. A parallel-to-serial converter is to be understood in the sense of at least one parallel-to-serial converter; for example, for two line pairs of the serial transmission, two parallel-to-serial converters can convert the data in parallel. The parallel-to-serial converter advantageously has at least one output for the serial transmission data and parallel inputs for the parallel transmission data and is designed to convert the parallel transmission data into serial transmission data. For example, the parallel-to-serial converter has digital memory cells and is designed as a register, in particular as a shift register.

[0018] According to an advantageous development of the invention, the internal clock generator is configured to output a first clock signal derived from the clock signal to the transmitting circuit, so that the conversion of the parallel transmit data into serial transmit data for the serial transmit data stream is clocked by the first clock signal. According to an advantageous development of the invention, the internal clock generator has a clock output for outputting the first clock signal, and the transmitting circuit has a clock input for inputting the first clock signal.

[0019] According to an advantageous development of the invention, a first clock frequency of the first clock signal is equal to the data clock frequency contained in the serial receive data stream by the control. According to an advantageous development of the invention, minimal differences between an actual frequency value and a target frequency value are controlled to zero by the control.

[0020] According to an advantageous development of the invention, the clock generator is configured to output a second clock signal derived from the clock signal to the processing circuit, so that processing of the parallel received data and / or the parallel transmitted data is clocked by the second clock signal. The first clock signal and the second clock signal can be different or identical. Furthermore, in other developments of the invention, it is possible for the clock generator to output a third clock signal or additional clock signals. According to an advantageous development of the invention, the processing circuit has a clock input for inputting the second clock signal.

[0021] According to an advantageous development of the invention, the processing circuit is configured for processing to forward the parallel received data. Advantageously, the forwarding occurs without buffering entire data packets. Preferably, the processing circuit is configured to output the parallel transmitted data based on the parallel received data to the transmitted circuit after a predetermined number of clock pulses of the second clock signal. The predetermined number of clock pulses is preferably less than twenty clock pulses, for example, only two clock pulses. For example, the parallel received data is modified or forwarded unchanged by the subscriber using the processing circuit in a first-in-first-out manner. For example, consecutive data from one and the same data packet can be received and transmitted simultaneously when forwarded by the subscriber.

[0022] According to an advantageous development of the invention, the processing circuit is additionally configured to store the parallel received data at least partially in a memory area for evaluation and / or to read the parallel transmitted data at least partially from a memory area in order to output the read parallel transmitted data to the transmitting circuit and / or to change a number of bit values ​​of the parallel received data in order to output the parallel received data with the change as parallel transmitted data to the transmitting circuit. A memory area is to be understood in the sense of at least one memory area. The memory is advantageously arranged in the subscriber or at least accessible by the subscriber.

[0023] According to an advantageous development of the invention, the clock generator is configured to output the second clock signal at a second clock frequency. The second clock frequency is controlled to be equal to, an integer multiple of, or an integer fraction of the data clock frequency contained in the serial receive data stream.

[0024] According to an advantageous development of the invention, the clock frequency of the clock generator is equal to or an integer fraction or an integer multiple of the data clock frequency contained in the serial receive data stream.

[0025] According to an advantageous development of the invention, the processing circuit has a memory area for an instruction list. An instruction list is to be understood in the sense of at least one instruction list. The processing circuit is configured to execute the processing based on the instructions contained in the instruction list. The processing circuit is configured to clock the reading of the instructions from the instruction list using the second clock signal.

[0026] According to an advantageous development of the invention, the clock generator comprises at least one quartz oscillator with a voltage-trimmable clock frequency. Advantageously, the quartz oscillator is a component of at least one phase-locked loop.

[0027] According to an advantageous development of the invention, the clock frequency of the clock generator can only be set within a range of less than 1% of the clock frequency, in particular less than 200 ppm of the clock frequency.

[0028] According to an advantageous development of the invention, the receiving circuit has a decoder for decoding the parallel received data. A decoder is understood to mean at least one decoder. Advantageously, the decoder is clocked by the first clock signal. According to an advantageous development of the invention, the transmitting circuit has an encoder for encoding the parallel transmitted data. An encoder is understood to mean at least one encoder. Advantageously, the encoder is clocked by the first clock signal.

[0029] According to an advantageous development of the invention, the receiving circuit has a descrambler for descrambling the parallel received data. A descrambler is understood to mean at least one descrambler. The descrambler is preferably clocked by the first clock signal. According to an advantageous development of the invention, the transmitting circuit has a scrambler for scrambling the parallel transmitted data. A scrambler is understood to mean at least one scrambler. The scrambler is advantageously clocked by the first clock signal.

[0030] According to an advantageous development of the invention, the processing circuit is configured to output the parallel transmission data after a predetermined number of clock cycles of the second clock signal after input of the parallel reception data.

[0031] According to the invention, the subscriber has a clock circuit for outputting a time. A clock circuit is understood to mean at least one clock circuit. Accordingly, a time is understood to mean at least one time.

[0032] According to an advantageous development of the invention, a clock pulse of the clock circuit is derived from the clock signal at the clock frequency. The clock circuit is advantageously connected to a clock output of the clock. Advantageously, the clock pulse, as a result of the control, is equal to, or a fraction of, or a multiple of the data clock frequency contained in the serial receive data stream. In principle, it is possible for the clock pulse to be a non-integer fraction or a non-integer multiple of the data clock frequency. Preferably, however, the clock pulse, as a result of the control, is an integer fraction or an integer multiple of the data clock frequency contained in the serial receive data stream.

[0033] According to an advantageous development of the invention, the processing circuit is configured to synchronize the time. The processing circuit is configured to evaluate a time value from the parallel received data and, based on the time value, to set the time of the clock circuit. The time of the clock circuit can also be based on a known or determined number of clock pulses required to receive and / or evaluate the parallel received data and / or to set the time. For example, the time of the subscriber's clock circuit can be synchronized to a reference time of another subscriber, with the time value being received from the other subscriber.

[0034] According to an advantageous development of the invention, the processing circuit is configured to evaluate a time increment value from the parallel received data and, based on the time increment value, to set a time increment of the clock circuit. For example, the time increment can be used to determine the speed of the clock.

[0035] According to an advantageous development of the invention, the clock circuit is designed such that the time is not controlled by a time controller of the clock circuit.

[0036] According to an advantageous development of the invention, the processing circuit is configured to determine a current time value and / or a current time increment value from the clock circuit and write it into the parallel transmission data. To write the current time value, the processing circuit is preferably configured to generate the received time value by incrementing bits of the received time value. The bits are incremented when the received time value is passed through and transmitted as the current time value. As a result of the passing through, the receiving of the time value and the transmission of the current time value occur partially simultaneously. Thus, it is preferably not necessary to first receive the time value in full and temporarily store it in order to generate and transmit the current time value.Preferably, the current time value is the sum of the received time value and a time delta of a known or determined transmission delay by the subscriber. Accordingly, a subsequent subscriber receiving the current time value can synchronize itself to the time of the preceding subscriber using the current time value.

[0037] The subject matter of the invention is not limited to the previously described embodiments. Thus, the described features or partial features can also be combined in other configurations. Possible embodiments of the invention are explained in the following description of the figures. These show: Figure 1 shows a schematic representation of a participant in a wired network of one embodiment; Figure 2 shows a schematic representation of a participant in a wired network of another embodiment; Figure 2a shows a schematic representation of memory areas of a memory; Figure 3 shows a schematic representation of an embodiment of a system with a local bus and a higher-level bus; and Figure 3a shows a schematic representation of a data packet.

[0038] In Figure 1 A subscriber 1 of a wired data network 7 is shown schematically. In the embodiment of the Figure 1the data network 7 is designed for serial data transmission. With serial data transmission, data is transmitted autonomously on a single line or a number of line pairs. With serial transmission, there is no need to take into account the propagation time differences between different lines, so that higher transmission frequencies are possible. In a simple case, serial data transmission can be designed as bit-serial data transmission, whereby several lines can be used in parallel for serial data transmission, such as with Gigabit Ethernet or HDMI. Complex modulations can also be used for serial data transmission, such as QAM16, QAM64 or similar, which no longer recognize individual bits (e.g. PCI Express, USB 3.X, etc.). Different serial interfaces, connectors, voltages, modulations, protocols and software interfaces are defined depending on the serial data transmission.

[0039] The embodiment in Figure 1 shows, in a highly simplified block diagram, the subscriber 1 of the wired data network 7. The invention is not limited to exactly one subscriber; usually, a large number of subscribers can be connected to one another in a wired data network 7.

[0040] Subscriber 1 has an internal clock generator 100 for generating a clock signal S TG with a clock frequency f TG for subscriber 1. In the embodiment of the Figure 1 The clock frequency f TG can be adjusted within a frequency range by a synchronization unit 121. For this purpose, the internal clock 100 is connected to the synchronization unit 121.

[0041] Participant 1 of the embodiment in the Figure 1has a receiving circuit 120 for receiving a serial receive data stream S SR from the wired data network 7. The serial receive data stream S SR consists in the simplest case of a sequence of zeros and ones on one or more serial lines. Likewise, in the embodiment of the Figure 1 possible to use modulation methods for serial transmission of the serial receive data stream S SR (in Figure 1 not shown).

[0042] Participant 1 of the embodiment of the Figure 1 also has a processing circuit 130 for inputting parallel receive data D PR and for outputting parallel transmit data D PT. The processing circuit 130 is in the embodiment of the Figure 1formed by digital logic. It is possible to form the digital logic by a programmable processor; preferably, the digital logic of processing circuit 130 is formed by hard-wired logic elements, so that processing circuit 130 itself does not have any processing software. Processing circuit 130 is connected to receiving circuit 120 so that the parallel received data D PR can pass from receiving circuit 120 to processing circuit 130.

[0043] Participant 1 of the embodiment of the Figure 1 also has a transmission circuit 140 for transmitting a serial transmission data stream S ST on the wired data network 7. The serial transmission data stream S ST consists in the simplest case in a sequence of zeros and ones on one or more serial lines of the wired data network 7. Likewise, in the embodiment of the Figure 1possible to use modulation methods for serial transmission of the serial transmit data stream S ST (in Figure 1 not shown). The processing circuit 130 is connected to the transmitting circuit 140 so that the parallel transmit data D PT can pass from the processing circuit 130 to the transmitting circuit 140.

[0044] The receiving circuit 120 of subscriber 1 of the embodiment of the Figure 1has a serial-parallel converter 122 for converting serial receive data D SR into parallel receive data D PR. The serial receive data D SR are contained in the serial receive data stream S SR on the wired data network 7. In a particularly simple embodiment of the serial-parallel converter 122, this is designed as a shift register, wherein the serial receive data D SR is applied to the serial input of the shift register and the parallel receive data D PR is output to the parallel outputs of the shift register (in Figure 1 not shown).

[0045] The receiving circuit 120 of subscriber 1 of the embodiment of the Figure 1also has the synchronization unit 121 for synchronizing the internal clock generator 100. The synchronization unit 121 is designed to synchronize the internal clock generator 100, in particular its clock frequency f TG , to the data clock frequency f SR contained in the serial receive data stream S SR. The data clock frequency depends on the distance between transitions between successive different values, e.g., low and high, of the serial receive data stream S SR. The data clock frequency f SR contained in the serial receive data stream S SR corresponds to a clock frequency with which a transmitter (in Figure 1 not shown) clocks the data stream S SR. Subscriber 1 in the embodiment of the Figure 1is configured to synchronize itself to a clock frequency of the transmitter connected via the wired data network 7 by means of the data clock frequency f SR, so that the clock frequency f TG follows the data clock frequency f SR precisely and with little delay. The synchronization unit 121 is configured to detect the transitions in the received serial receive data stream S SR and to control the clock frequency f TG of the internal clock 100 depending on the detected transitions. In addition to the exemplary embodiment of the Figure 1 In addition to the serial-parallel converter 122 and synchronization unit 121 shown, the receiving circuit 120 has several further subcircuits for the function of receiving the serial data stream S SR and further functions, which are shown in Figure 1 are not shown.

[0046] The transmission circuit 140 of subscriber 1 of the embodiment of the Figure 1has a parallel-to-serial converter 142 for converting the parallel transmission data D PR into serial transmission data D ST of the transmission data stream S ST. The serial transmission data D ST are transmitted in the serial transmission data stream S ST to another participant (in Figure 1 not shown) in the wired data network 7. The transmission circuit 140 of subscriber 1 of the embodiment of the Figure 1 is shown in a highly simplified manner and preferably has further subcircuits for the functions of the transmitting circuit 140, such as coding circuit, modulation circuit, amplifier circuit or the like, which are shown in Figure 1are not shown. The transmitting circuit 140 and the receiving circuit 120 can be connected to different additional participants. It is also possible for the transmitting circuit 140 and the receiving circuit 120 to be connected, for example, for a duplex connection to the same participant or, for example, via a switch to several additional participants.

[0047] In the example of Figure 1 The internal clock generator 100 is configured to output a first clock signal CLK 1 derived from the clock signal S TG. To derive the first clock signal CLK 1 from the clock signal S TG, the clock frequency f TG of the clock signal S TG is, for example, multiplied or divided by an integer. It is also possible to adapt the amplitude or steepness of clock edges for the derivation. In the embodiment of the Figure 1a first clock frequency f 1 of the first clock signal CLK 1 is equal to the data clock frequency f SR contained in the serial receive data stream S SR by the control of the synchronization unit 121. The clock generator 100 is connected to the parallel-to-serial converter 142 of the transmit circuit 140 for outputting the first clock signal CLK 1 to the parallel-to-serial converter 142, so that the conversion of the parallel transmit data D PR into serial transmit data D ST for the serial transmit data stream S ST is clocked by the first clock signal CLK 1. By clocking by means of the first clock signal CLK 1, a transmit data clock frequency f ST in the transmit data stream S ST is regulated to be equal to the first frequency f 1 and equal to the data clock frequency f SR of the receive data stream S SR within the framework of the control of the synchronization unit 121.

[0048] The clock generator 100 is in the embodiment of the Figure 1to output a second clock signal CLK 2 derived from the clock signal S TG to the processing circuit 130. To derive the second clock signal CLK 2 from the clock signal S TG, the clock frequency f TG of the clock signal S TG is, for example, multiplied or divided by an integer. It is also possible to adapt the amplitude or steepness of clock edges for the derivation. In a simple embodiment, a second frequency f 2 of the second clock signal CLK 2 corresponds to the first frequency f 1 of the first clock signal CLK 1 . It is possible for the second clock signal CLK 2 to correspond to the first clock signal CLK 1 . Alternatively, the processing circuit 130 can, for example, be clocked higher so that more computing resources are available for processing. For example, the second frequency f 2 is an integer or non-integer multiple of the clock frequency f TG .At least the processing of the parallel receive data D PR and / or the parallel transmit data D PT is clocked by the second clock signal CLK 2.

[0049] In a simply designed subscriber 1, the processing circuit 130 is sufficient to ensure the functions of the subscriber 1. For example, the processing circuit 130 is sufficient to read digital input data at digital input terminals or to output digital output data at output terminals (in Figure 1not shown). If the subscriber 1 is to perform more complex functions, the subscriber 1 has a programmable processing unit 190, for example a processor such as a CPU or a microcontroller. The programmable processing unit 190 is connected to the processing circuit 130 for exchanging data. For example, the parallel received data D PR and / or the parallel transmitted data D PT can be exchanged between the processing circuit 130 and the programmable processing unit 190. The programmable processing unit 190 can be used, for example, to convert measured values ​​or control values ​​for the parallel received data D PR and / or the parallel transmitted data D PT. In the embodiment of the Figure 1the programmable arithmetic unit 190 is clocked by the second clock signal CLK 2 , so that the clocking of the programmable arithmetic unit 190 also depends on the data clock frequency f SR contained in the serial receive data stream S SR .

[0050] In Figure 2 Another embodiment with a subscriber 1 in a wired data network 7 and two further subscribers 2, 3 is shown schematically. In Figure 2 In the embodiment shown, reference is made to subscriber 1 in the middle between the other subscribers 2 and 3, wherein a serial receive data stream S SR is sent by the other subscriber 3 and received by subscriber 1. The subscriber 1 sends a transmit data stream S ST to the subscriber 2, wherein the transmit data stream S ST is received by the other subscriber 2. In the embodiment of the Figure 2In the data stream, serially transmitted data is passed in data packets through a plurality of communication-ready participants. A data packet is generated only once and can, for example, be modified by each participant. A data packet can also be referred to as a telegram.

[0051] Participant 1 in the example of Figure 2 has a receiving circuit 120 and a transmitting circuit 140 and a clock generator 100 and a processing circuit 130. Optionally, the participant 1 in the embodiment of the Figure 2 also a clock circuit 180 and a programmable arithmetic unit 190.

[0052] The receiving circuit 120 of subscriber 1 is configured to receive the serial receive data stream S SR . The receiving circuit 120 has an input circuit 129, which may, for example, have an amplifier or the like. The input circuit 129 is configured to output serial receive data D SR . The receiving circuit 120 has a serial-parallel converter 122 for converting the serial receive data D SR of the serial receive data stream S SR into the parallel receive data D PR . Depending on the configuration of the parallel receive data D PR , the receiving circuit 120 has further subcircuits. In the exemplary embodiment of the Figure 2 the data is also encoded and scrambled (scramble - German: scramble, encrypt).

[0053] In the example of Figure 2The receiving circuit 120 has a decoder 123 for decoding the parallel received data D PR ". The decoder 123 outputs decoded parallel received data D PR '. An input of the decoder 123 is connected to an output of the serial-parallel converter 122. An output of the decoder 123 is connected to an input of a descrambler 124. The decoder 123 is in the embodiment of the Figure 2 clocked by a first clock signal CLK 1. In the embodiment of the Figure 2Decoder 123 is designed as a 10b8b decoder. Alternatively, other decoders can be used for other encodings, such as 64b66b code or Manchester. With the 8b10b code, the maximum run length of identical bits is limited to five by appropriately selecting the codewords for pure data transmission, i.e., the level changes during a transition after at most five clock cycles. This enables simple clock recovery from the serial receive data stream S SR .

[0054] In the example of Figure 2The receiving circuit 120 has a descrambler 124 for descrambling the parallel received data D PR '. An input of the descrambler 124 is connected to the output of the decoder 123. An output of the descrambler 124 is connected to an input of a processing circuit 130. The descrambler 124 outputs descrambled parallel received data D PR . The descrambler 124 is clocked by the first clock signal CLK 1 .

[0055] In the example of Figure 2Clock recovery is provided. The aim of clock recovery is to determine the transmission clock of the transmitter, i.e. of subscriber 3, from a received serial receive data stream S SR and thus to enable, among other things, the precise sampling of the serial receive data stream S SR and to correctly align (synchronize) the transmission data stream S ST sent towards the other subscriber 2. Clock recovery is used on the receiver side of subscriber 1 to determine periodic sampling times of the received serial receive data stream S SR. This precise alignment in time enables the serial receive data stream S SR to be evaluated as precisely as possible, and bit errors are accordingly rare. Clock recovery makes parallel clock transmission using a separate clock transmission channel for synchronization unnecessary.

[0056] In order to be able to obtain the transmission clock with the data clock frequency f SR from the serial receive data stream S SR, the serial receive data stream S SR must have a sufficient number of signal edges, e.g. in bit-serial transmission, so that long sequences of '1' or '0' without transitions, ie without edges in the transmission, are to be avoided. This is done in the embodiment of the Figure 2 This is achieved by 8b10b coding, among other things. Figure 2 The serial receive data stream S SR with transitions TR and the period T SR associated with the transitions is shown schematically over time t. The data clock frequency f SR corresponds to the inverse of the period T SR .

[0057] The receiving circuit 120 has a synchronization unit 121 for synchronizing the internal clock generator 100 to the data clock frequency f SR contained in the serial receive data stream S SR . The synchronization unit 121, together with the internal clock generator 100, forms a phase-locked loop (PLL) such that the frequency f TG of the internal clock generator 100 is controlled based on the data clock frequency f SR contained in the serial receive data stream S SR . In other words, the synchronization unit 121 is configured to detect the transitions TR in the received serial receive data stream S SR and to control the clock frequency f TG of the internal clock generator 100 depending on the detected transitions TR.For example, the frequency f TG of the internal clock 100 corresponds to the data clock frequency f SR or the frequency f TG of the internal clock 100 is an integer fraction of the data clock frequency f SR or the frequency f TG of the internal clock 100 is an integer multiple of the data clock frequency f SR .

[0058] The internal clock generator 100 in the embodiment of the Figure 2 is used to generate a clock signal S TG with the clock frequency f TG for the subscriber 1 itself. In the embodiment of the Figure 2 The entire participant 1 is clocked based on the clock signal S TG , so that no additional clock is required for circuit components of participant 1. The clock generator 100 has a quartz oscillator 101 with a voltage-trimmable clock frequency f TG . Such quartz oscillators are also known as VCXOs (Viscous X-ray Spectrometers). V oltage C controlled ( X )crystal O scillator), TCVCXO (engl.T temperature C compensated V oltage C controlled ( X )Crystal O scillator) or OCVCXO ( O ven C controlled V oltage C controlled ( X )Crystal O scillator) and stand for temperature-compensated or heated adjustable quartz oscillators.

[0059] Advantageously, the clock frequency f TG of the clock generator 100 can only be adjusted within a range of less than 1% of the clock frequency f TG . Preferably, the clock frequency can only be changed in the order of 100 ppm. In the embodiment of the Figure 2 The quartz oscillator 101 is part of a phase-locked loop (PLL) P hare L locked L oop), wherein the phase-locked loop PLL comprises at least parts of the clock generator 100 and the synchronization unit 121.

[0060] The internal clock generator 100 is configured to output a first clock signal CLK 1 derived from the clock signal S TG to the transmitting circuit 140. The first clock signal CLK 1 has the first frequency f 1. To derive the first clock signal CLK 1, the internal clock generator 100 has, for example, a further phase-locked loop (not shown), by means of which the clock frequency f TG is multiplied by an integer to obtain the first clock frequency f 1. In the exemplary embodiment of the Figure 2 the internal clock generator 100 is designed to regulate the first clock frequency f 1 of the first clock signal CLK 1 such that the first clock frequency f 1 is equal to the data clock frequency f SR contained in the serial receive data stream S SR.

[0061] The clock 100 in Figure 2is also configured to output a second clock signal CLK 2 derived from the clock signal S TG at least to the processing circuit 130, so that processing of the parallel receive data D PR and / or the parallel transmit data D PT is clocked by the second clock signal CLK 2. The clock generator 100 is configured to output the second clock signal CLK 2 at a second clock frequency f 2, wherein the second clock frequency f 2 is, for example, an integer multiple of the data clock frequency f SR contained in the serial receive data stream S SR or an integer fraction of the data clock frequency f SR contained in the serial receive data stream S SR. In the illustrated embodiment of the Figure 2 For example, if the second clock signal CLK 2 is equal to the first clock signal CLK 1 , the first frequency f 1 is therefore also equal to the second frequency f 2 .

[0062] In the example of Figure 2A processing circuit 130 is shown for inputting the parallel received data D PR and outputting the parallel transmitted data D PT . Accordingly, the processing circuit 130 is connected to the receiving circuit 120 and the transmitting circuit 140. The processing circuit 130 is configured to forward the parallel received data D PR in order to output the parallel transmitted data D PR based on the parallel received data D PR to the transmitting circuit 140 after a predetermined number of clock cycles of the second clock signal CLK 2 . Thus, the number of clock cycles of the second clock signal CLK 2 is always the same for all parallel received data D PR and is thus deterministically delayed.Since all sub-circuits 129, 122, 123, 124, 133, 144, 143, 142, 149 in the transmission chain between the input of the serial receive data stream S SR and the serial transmit data stream S ST cause no delay or a delay caused by the first clock signal CLK 1 and / or the second clock signal CLK 2, the total delay for the data stream S SR , S ST is predetermined by the subscriber 1 and is constant and thus deterministic.

[0063] In the example of Figure 2the processing circuit 130 has a manipulation circuit 133 for bit-granularly changing individual or all bits of the parallel receive data D PR . The changed parallel receive data D PR is the parallel transmit data D PT . To control the change, the processing circuit 130 has a digital logic 132. The digital logic 132 is connected to the manipulation circuit 133 and to a memory 131. The parallel receive data D PR can be changed by the manipulation circuit 133, but cannot be buffered, so that when the parallel receive data D PR is present on the input side, the parallel transmit data D PT is output at the same time. The enable signal EN2 for the parallel transmit data D PT is, however, delayed by the predetermined number of clock cycles of the second clock signal CLK 2 compared to the input of the parallel receive data D PR .For example, the enable signal EN2 constantly delays the forwarding of the parallel transmission data D PT by two clock cycles of the second clock signal CLK 2.

[0064] Processing of the parallel received data D PR can consist of executing a bit operation on the received parallel received data D PR. In this case, the processing can also be said to be bit-granular. The bit operations that can be performed are based, for example, on a reduced instruction set that the subscriber 1 can execute, such as "SKIP", "MOVE", "NEGATION", "INCREMENT", "AND" and "OR" or a combination thereof. The processing circuit 130 has a memory area 131c in the memory 130 for an instruction list IL. The memory 131 and the memory area 131c are, in the exemplary embodiment, the Figure 2ashown schematically. The processing circuit 130 is configured to execute the processing based on instructions I1, I2, I3, I4, I5 contained in the instruction list IL, wherein reading of the instructions I1, I2, I3, I4, I5 from the instruction list IL is clocked by the second clock signal CLK2.

[0065] Which bit operations are to be carried out in which order is stored in subscriber 1 with the aid of the instruction list IL. An instruction list IL can be sent to the respective subscriber 1 in advance in a first data packet and represents the programming of subscriber 1. This instruction list IL contains for each part, e.g. an 8-bit symbol, of the parallel receive data D PR or for each bit of the parallel receive data D PR at least one instruction I1, I2, I3, I4, I5, i.e. an operation that is to be carried out with the corresponding bit. For each symbol, a fixed number or a predetermined number of instructions I1, I2, I3, I4, I5 can be present in the instruction list IL. This means that subscriber 1 executes a certain number of instructions I1, I2, I3, I4, I5 per symbol in the time available to it for processing.For example, if node 1 is not supposed to process a bit, the corresponding instruction list IL can be empty for the corresponding bit or contain a "SKIP" instruction. The instruction list IL can also contain the number of repetitions for a specific instruction I1, I2, I3, I4, I5. For example, the instruction list IL can contain a "SKIP" instruction with the instruction to repeat it twice. In this case, the next two bits are not processed but skipped. Parameters can also be specified for the instructions "MOVE," "NEGATION," "INCREMENT," "AND," and "OR."

[0066] Instructions I1, I2, I3, I4, I5 accordingly control manipulation circuit 133, which, for example, sets and / or clears a number of bits in a symbol of the parallel receive data D PR. It is also possible for a number of bits of the parallel receive data D PR to be incremented in order to add another value to a value in the parallel receive data D PR. It is useful to temporarily store an overflow bit from the parallel receive data D PR during the increment. It is also possible for manipulation circuit 133 to combine setting and / or clearing and / or incrementing.

[0067] The processing circuit 130 can, for example, perform a series of further processing operations using the instructions I1, I2, I3, I4, I5. For example, the processing circuit 130 is configured to store the parallel received data D PR in a memory area 131a for evaluation. Alternatively or in combination, it is possible to at least partially read out the parallel transmitted data D PT from a memory area 131b in order to output the read data as parallel transmitted data D PT to the transmitting circuit 140. Alternatively or in combination, it is possible to change a number of bit values ​​of the parallel received data D PR in order to output the parallel received data D PR with the change as parallel transmitted data D PT to the transmitting circuit 140.

[0068] In the example of Figure 2The processing circuit 130 is clocked by the second clock signal CLK 2 . The processing circuit 130 is configured to output the parallel transmission data D PT after a predetermined number of clock cycles of the second clock signal CLK 2 following the input of the parallel reception data D PR . The delay by the processing circuit 130 is thus temporally deterministic and independent of a program execution in a computing unit. Nevertheless, it is possible to process the data during the predetermined number of clock cycles and, for example, to add or subtract another value from a received value without having to temporarily store the parallel reception data D PR in a memory prior to processing.

[0069] The participant in the embodiment of the Figure 2The transmission circuit 140 has a transmission circuit 140 for transmitting a serial transmission data stream S ST . The transmission circuit 140 has a scrambler 144 for scrambling the parallel transmission data D PT . The scrambler 144 is clocked by the first clock signal CLK 1 . The scrambler 144 uses linear feedback shift registers or fixed tables to reversibly convert the parallel transmission data D PT using a relatively simple algorithm. The reversal is performed by the descrambler 124. The transmission circuit 140 also has an encoder 143 for encoding the parallel transmission data D PT ' and outputting coded parallel transmission data D PT ". The encoder 143 is, for example, an 8b10b encoder. The encoder 143 is clocked by the first clock signal CLK 1 .The transmission circuit 140 has a parallel-to-serial converter 142 for converting the parallel transmission data D PT " output by the encoder 143 into serial transmission data D ST , wherein the transmission data D ST is inserted into the transmission data stream S ST . The transmission circuit 140 also has an output circuit 149, which is also clocked by means of the first clock signal CLK 1. The output circuit 149 has, for example, a last register in the transmission chain that is clocked by the first clock signal CLK 1, so that the serial transmission data D ST is output at exactly the same regulated frequency as the data clock frequency f SR of the reception data stream S SR .

[0070] In the example of Figure 2Subscriber 1 also has a programmable processing unit 190 for processing a subscriber-specific program. The programs in the programmable processing unit 190 run synchronously with the processing of the parallel receive data D PR and the parallel transmit data D PT . The programmable processing unit 190 is clocked by the second clock signal CLK 2 . Accordingly, processing in higher protocol layers is also ideally deterministic.

[0071] In the example embodiment, participant 1 has Figure 2also has a clock circuit 180. The clock circuit 180 is also referred to below as clock 180. The clock circuit 180 is used for time control and / or acquisition. The clock circuit 180 is, for example, a component of a distributed clock system. For example, the clock circuit 180 can be used to determine a reading time of, for example, sensor data, or an output of control data, for example for controlling an actuator, can be set to a specific time based on a time of the clock circuit 180. This is interesting, for example, when several participants 1, 2, 3 control a process and are to acquire a process image at a predetermined common time. In the embodiment of the Figure 2The clock circuit 180 is also clocked by the first clock signal CLK 1 or the second clock signal CLK 2, so that the clock circuit 180 runs faster or slower depending on the data clock frequency f SR . However, the clock 180 runs through the control of the PLL according to a preceding station 3 from which the serial receive data stream S SR is received by the station 1.

[0072] Investigations by the applicant have shown that the training of participant 1 in the embodiment of the Figure 2 With clock recovery and clocked output of the serial transmission data D ST with the same frequency, as well as the clock-controlled processing with the same frequency, participants 1, 2 can be formed, which can work with high temporal precision in relation to each other.

[0073] In Figure 3A system is schematically shown with nodes 1, 2, and 3 connected via a local bus 7, and nodes 3, 4 connected via a higher-level bus 6. The higher-level bus 6 can be configured as a fieldbus. Device 3, which is connected to both the fieldbus 6 and the local bus 7, acts as a gateway and can also be referred to as a coupler, head-end station, or local bus master.

[0074] By the system according to the embodiment of the Figure 3 The aim is to synchronize subordinate clocks 180, 280 with a superordinate clock 370, 380 in order to provide a distributed, synchronized time in the system with spatially separated participants 1, 2, 3. This can also be referred to as a distributed clock.

[0075] A first subscriber 1 and a second subscriber 2 are connected to the coupler 3 via the local bus 7. The first subscriber 1 has an internal clock 100 for generating a clock signal with a clock frequency for the first subscriber 1. The first subscriber 1 also has a receiving circuit 120 for receiving a serial receive data stream and a transmitting circuit 140 for transmitting a serial transmit data stream. The receiving circuit 120 has a serial-to-parallel converter (in Figure 3 not shown) for converting serial receive data of the serial receive data stream into parallel receive data. The transmit circuit 140 has a parallel-to-serial converter (in Figure 3 not shown) to convert the parallel transmission data into serial transmission data of the transmission data stream.

[0076] Accordingly, the second participant 2 of the local bus 7 also has a clock generator, a receiving circuit and a transmitting circuit. These are Figure 3 but not shown.

[0077] For communication via the local bus 7, the coupler 3 has a local bus-side transmit-receive circuit 340 and for communication via the field bus 6, a field bus-side transmit-receive circuit 320. In the embodiment of the Figure 3 The higher-level clock 380 can be synchronized within the local bus system to another, higher-level clock 480.

[0078] The clock 380 of the coupler 3 is connected to the clock 480 of a higher-level controller 480, e.g. a PLC ( S storage P programmable S control), synchronized by means of a control system. In the exemplary embodiment of the Figure 3The coupler 3 has a control loop for clock synchronization. This control loop contains the local clock 385, which outputs the time t SM based on the manipulated variable of the speed. The actual time t SM is captured and temporarily stored at the time of receipt of message 60 by means of the hold element 382. The target time TS FB is contained in message 60. A local error is determined from the actual time and the target time TS FB by the difference element 383 and input to the input of the PI controller 384.

[0079] A reference clock is used to cyclically determine the local error, which is then to be eliminated using a suitable controller 384. For this purpose, the controller 384 can change the speed of the clock 380 to be synchronized as a manipulated variable to control the local error to zero. The reference clock is implemented by the event "Receipt of a specific communication message" 60. The message 60 contains, for example, the target value TS FB for the time, which is used to calculate the local error.

[0080] For control purposes, the Figure 3in the coupler 3, a PI controller 384 is used, which changes the speed of the clock circuit 385 so that in the regulated state, the clock 380 of the coupler 3 runs just as fast as the higher-level clock 480 of the PLC 4, i.e. the drift error is regulated to zero, and that the clock 380 of the coupler 3 supplies the same time t SM as the higher-level clock 480 of the PLC 4, i.e. the offset error is regulated to zero. A special feature is the drift error. This drift error refers to the speed difference between the clocks 380 and 480 to be synchronized. The speed error of both clocks 380, 480 is due to the slightly different frequencies of the clock generators 300, 400 used in each participant 3, 4, whereby quartz oscillators or MEMS or other oscillators of the clock generators 300, 400 have slightly different frequencies.

[0081] The drift represents the first derivative of the local error. This means that if the local error increases continuously, then the drift is not zero. If the local error is constant, then the drift is zero and there is only an offset error. The offset error is also due to the fact that even two clocks running at exactly the same speed must be synchronized at least once. The manipulated variable, which the PI controller 384 of the coupler 3 in the embodiment of the Figure 3 is the speed of the clock circuit 385. An offset error can thus be compensated for with an artificial "drift error." This means that the controller 384 changes the speed of the clock circuit 385 for a limited time in order to compensate for an offset error.

[0082] In the control loop, a plurality of sampling cycles are used to establish synchronization with the master clock 480. The PI controller 384 is designed to be slow, as the local error is often subject to various disturbances, such as noise, sporadic outliers, and discretization errors. Due to the slow design of the PI controller 384, the disturbances have only a limited effect on the time t SM to be synchronized. With slow control, synchronization (locking) takes a correspondingly long time, so the disturbances have only a very limited effect.

[0083] The lock-in process can be shortened by sampling the PI controller 384 more frequently, but this results in increased communication overhead, as more messages 60 must be transmitted over bus 6. Message 60 can also be referred to as a synchronization telegram. Furthermore, the CPU load is higher if the control loop is implemented in a software program. Alternatively, the PI controller 384 could be dimensioned "faster," but this would increase the disturbances' impact on the residual synchronization error.

[0084] When using a PI controller 384, a PT2 behavior or a higher-order transfer behavior results for the closed control loop as the transfer function. This can result in an oscillatory system, i.e., the step response does not result in a local error that asymptotically approaches zero, but rather resembles a damped oscillation whose amplitude asymptotically approaches zero. To determine whether the clock 380 is synchronized or not, the local error is checked to see whether it lies within a window around zero. With a step response that resembles a damped oscillation, this window can be entered and exited several times during the synchronization process before the amplitude has become so small that the residual error lies permanently within the window.Accordingly, the synchronization process is completed when the residual error has not left the window for a certain time.

[0085] In the example of Figure 3 A clock signal CLK M from the clock generator 300 of the coupler 3 is present both at a clock input 381 of the clock 380 with control loop and, optionally, at an input 371 of an unregulated clock 370. Both clocks 380 and 370 are shown only as examples of their function and can be generated by the same circuit. The unregulated clock 370 runs exactly in time with the clock generator 300 and can be used when no synchronization with the clock 480 of the PLC 4 is required. The transmit / receive circuit 340 of the coupler 3 is also clocked for communication via the local bus 7 based on the clock signal CLK M from the clock generator 300 of the coupler 3. Data packets, e.g. the synchronization telegram 70, are output at exactly the same time as the clock signal CLK M.

[0086] This utilizes the fact that a synchronization unit 121 of a first participant 1 is used in the physical layer PHY. The coupler 3 is designed, for example, as the master of the local bus 7, and the first participant 1 and a second participant 2 are designed, for example, as slaves of the local bus 7. However, the invention is not limited to master-slave bus systems; the invention can alternatively be used for multiple access (English - C rear S sense M ultiple A Access (CSMA) or a point-to-point connection can be used. The synchronization unit 121 can also be referred to as a CDR (Communication Data Transfer Protocol). C lock- and DATA recovery). The synchronization unit 121 of the first subscriber 1 is configured to detect transitions in the received serial data stream. The received data stream can be received by the receive circuit 120 of the first subscriber 1 from the transmit / receive circuit 340 of the coupler 3. The synchronization unit 121 is configured to regulate the clock frequency of the internal clock 100 of the first subscriber 1 depending on the transitions detected in the received data stream.

[0087] The internal clock generator 100 of the first participant 1 is configured to output a first clock signal CLK 1 derived from the clock signal to a clock circuit 180. A first clock frequency of the first clock signal CLK 1 is, due to the control of the synchronization unit 121, equal to the data clock frequency contained in the serial receive data stream and thus equal to the frequency of the clock signal CLK M of the clock generator 300 of the coupler 3. The clock signal CLK M of the clock generator 300 of the coupler 3 can also be referred to as the master clock signal CLK M. Accordingly, the clocks 370, 380, 180, 280 in the local bus system are clocked with clock signals CLK M , CLK 1 with the same clock frequency, whereby the clock frequencies differ only slightly from one another until the control by the synchronization unit 121 at the PHY level engages.Preferably, the clock frequencies deviate from each other by a maximum of + / - 100 to 200 ppm until the control by the synchronization unit 121 at the PHY level locks in. For the control loop of the synchronization unit 121 in the PHY physical layer, the controller sampling rate is several orders of magnitude higher than the sampling rate for the control in the clock 380. Therefore, transient responses of the control by the synchronization unit 121 in the PHY physical layer are completed in a fraction of the time required for the transient response of the control loop of the clock 380 of the coupler 3 with the PI controller 384.

[0088] If the clock signal CLK M and CLK 1, synchronized by the synchronization unit 121 using CDR, is used to operate the master clock 380, 370 of the coupler 3 and the slave clocks 180, 280 of the participants 100, 200, the drift error is zero. A simple P-controller in the local clock 180, 280 is then sufficient to synchronize the offset error. The P-controller can be completely omitted if, as in the exemplary embodiment of the Figure 3the message 70 can be transmitted deterministically and advantageously without jitter in the local bus 7. Deterministic means that each message 70 transmitted via the local bus 7 requires a fixed, unchanging number of clock cycles—for example, 16.5 clock cycles—or a fixed, unchanging period of time—for example, 33 µs—for transmission from the coupler 3 to the first station 1 (transit time). Likewise, the transmission from the first station 1 to the second station 2 and, if applicable, to each additional station (not shown) on the bus 7 is deterministic. In the case of deterministic transmission, the clock 180 of the first station 1 is configured to set its time t S1 to the time value TS LB1 contained in the message 70 or a time value derived therefrom.

[0089] An offset can be added to the time value TS LB1 contained in the message 70, for example to compensate for the propagation time of the message 70 via the physical layer PHY. For example, the time value TS LB1 is based on the time t SM of the coupler 3 and the propagation time required to transmit the message 70. Alternatively, the derived time value is calculated based on the transmitted time value TS LB1 and a propagation time known to the first subscriber 1 that is required to transmit the message 70. The first subscriber 1 has a processing circuit 130 for parallel data processing, wherein the processing circuit 130 is configured to read the time value TS LB1 from the message 70 and to forward it to the clock 180. Furthermore, the processing circuit 130 is configured toto change it to another time value TS LB2, which is transmitted to the clock 280 of the subsequent second subscriber 2 by means of the transmitting circuit 140 via the bus 7.

[0090] Through the embodiment of the Figure 3 The advantage is achieved that one of the times t M or t SM of the coupler 3 is almost perfectly synchronized with the times t S1 , t S2 of the participants 1, 2. Thus, the clocks 180, 280 of the participants 1, 2 and the used master clock 370 or 380 of the coupler 3 do not differ from each other, thus they do not have any drift that would have to be corrected. In the embodiment of the Figure 3Both participants 1 and 2 each have a computing unit 190 and 290 - for example, a microcontroller - and both participants 1 and 2 each have an interface 150, 250 - for example, cable connection contacts - for the external connection of an actuator 512, 522 and / or sensor 511, 521 or the like. The clocks 180, 280 of participants 1, 2 can also be implemented as software in the computing unit 190, 290 of the respective participant 1, 2. Due to the almost perfect synchronization of the clocks 180 and 280 of the first participant 1 and the second participant 2, respectively, the sensor values ​​of the sensors 511, 512 can be recorded at exactly the same time and / or the actuators 512, 522 within participants 1, 2 of the bus 7 can be controlled at exactly the same time.

[0091] Figure 3a schematically illustrates a message 70 for transmission over bus 7. Message 70 has a header H, a time increment TV (e.g., 28 bits), a time value TS LB1 (e.g., 64 bits), and a check value CRC. The time increment TV defines the speed of the master clock 380 of coupler 3. This ensures that the slave clocks 180, 280 of participants 1, 2 use the same time increment and always run parallel to the master clock 380 of coupler 3. In this way, the higher-level clock 380 of the coupler 3 can be synchronized with the PI controller 384 to the higher-level clock 480 of the control unit 4 (PLC) connected via the fieldbus 6 by means of the control loop of the coupler 3, and all subordinate clocks 180, 280 follow it and thus the synchronization of the clock 380 of the coupler 3, without any additional synchronization of the participants 1, 2 outside the physical layer PHY being required.A control loop within the clock 180, 280 of a node 1, 2 (i.e., outside the physical layer PHY) can be completely eliminated; nodes 1, 2 follow the clock of coupler 3 slavishly, with virtually no delay. This greatly simplifies the implementation of a distributed clock system. The requirement for logic and software resources is minimal in the . Figure 3 significantly reduced compared to conventional solutions.

[0092] Due to the fast clock synchronization, participants 1, 2 of bus 7 are practically ready for operation after booting. Complete clock synchronization of participants 1, 2 is achieved with the first message 70, even if the clock 380 of coupler 3 is still in the synchronization phase before locking. Coupler 3 is configured to send another message 70 when coupler 3 detects that a new participant X (not shown) has been added, or when an existing participant 1, 2 undergoes a hardware reset, or when the clock 380 of coupler 3 needs to be discontinuously synchronized by setting it to a completely new time t PLC of PLC 4, or when PI controller 384 has calculated a new speed value TV.

[0093] In the example of Figure 3the residual error between the times t SM of coupler 3 and the times t S1 , t S2 of participants 1, 2 is smaller than an error that could be achieved with a separate PI controller in each participant 1, 2. The largest part of this very small residual error is caused by the (possibly not exactly known) propagation times on bus 7 and the measurement and compensation of these propagation times on bus 7. In contrast, neither noise nor outliers contribute to the residual error.

[0094] In the example of Figure 3The solution is also presented in which a clock 370 of coupler 3 does not need to be synchronized to a higher-level clock and is therefore precisely timed by the clock generator 300 of coupler 3, for example, using a quartz oscillator. In this case, the transmission of the time increment TV can be omitted, since this is the same for all participants 1, 2, and 3 of bus 7 anyway. It is also possible to transmit the time increment TV only once, since it remains constant thereafter. In this case, message 70 does not need to be transmitted cyclically either.

[0095] For example, an event-dependent transmission, e.g. when adding a new participant, is sufficient. By means of a selection circuit 390 - for example a multiplexer - in the embodiment of the Figure 3 Both watches 370, 380 can be selected alternatively. List of reference symbols

[0096] 1, 2 Subscriber, slave 3 Head station, coupler, master 4 Control device, control station, PLC 6 Higher-level bus, fieldbus 7 Data network, bus, local bus, lower-level bus 60, 70 Message, synchronization telegram 100 Clock generator 120 Receive circuit 121 Synchronization unit 122 Serial-to-parallel converter 123 Decoder 124 Descrambler 129 Input circuit 130 Processing circuit 131 Memory 132 Digital logic 133 Manipulation circuit 131a, 131b, 131c Memory area 140 Transmit circuit 142 Parallel-to-serial converter 143 Encoder 144 Scrambler 149 Output circuit 150, 250 I / O interface 180, 280Clock circuit, clock 190, 290Arithmetic unit, processor, microcontroller 300Clock generator 320Transceiver, transmit-receive circuit 340Transceiver, transmit-receive circuit 370Clock circuit, clock 371, 381Clock input 380Clock 382Hold circuit 383Differential element 384PI controller 385Clock circuit 390Selection circuit, multiplexer 400Clock generator 480Clock 511, 521Sensor 512, 522Actuator CLK1, CLK2 Clock signal CLK M Clock signal CRC Check value D SR Serial receive data D ST Serial transmit data S TG Clock signal f1, f2 Clock frequency f TG Clock frequency f SR Data clock frequency H Header IL Instruction list I1, I2, I3, I4, I5 Instruction PHY Physical layer S SR Receive data stream S ST Transmit data stream TR Transition, signal edge TV Time increment TS LB1 , TS LB2 , TS FB Time value, time stamp t Time T SPS , t M , t SM , t S1 , t S2 Time T SR Period D PR , D PR ', D PR "parallel receive data D PT , D PT ', D PT "parallel transmit data

Claims

1. System having a head-end station (3) and at least one subscriber (1) connected to the head-end station (3) via a wired local bus (7), - in which the head-end station (3) has a field-bus-side transmitting / receiving circuit (320) for communication via a field bus (6), - in which the head-end station (3) has a local-bus-side transmitting / receiving circuit (340) for communication via the local bus (7), - in which the head-end station (3) has a clock (380) with a control loop for clock synchronization with a higher-level clock (480) connected via the field bus (7), - in which the head-end station (3) has a clock generator (300) for generating a clock signal (CLKM) which is applied to the clock (380) via a clock input (381) and is used to clock the local-bus-side transmitting / receiving circuit (340), with the result that messages (70) from the transmitting / receiving circuit (340) are output in a manner exactly clocked with the clock signal (CLKM), in which the subscriber (1) - has an internal second clock generator (100) for generating a clock generator signal (STG) at a clock generator frequency (fTG) for the subscriber (1), - has a receiving circuit (120) for receiving a serial receive data stream (SSR), - has a processing circuit (130) for inputting parallel receive data (DPR) and for outputting parallel transmit data (DPT), and - has a transmitting circuit (140) for transmitting a serial transmit data stream (SST), - has a clock circuit (180) for outputting a time (tS1), in which - the receiving circuit (120) of the subscriber (1) has a serial-parallel converter (122) for converting serial receive data (DSR) of the serial receive data stream (SSR) into the parallel receive data (DPR), - the receiving circuit (120) of the subscriber (1) has a synchronization unit (121) for synchronizing the internal clock generator (100) with the data clock frequency (fSR) contained in the serial receive data stream (SSR), - the synchronization unit (121) of the subscriber (1) is configured to detect transitions (TR.) in the received serial receive data stream (SSR) and to control the clock generator frequency (fTG) of the internal clock generator (100) on the basis of the detected transitions (TR), - the transmitting circuit (140) of the subscriber (1) has a parallel-serial converter (142) for converting the parallel transmit data (DPT) into serial transmit data (DST) of the transmit data stream (SST), - the internal clock generator (100) of the subscriber (1) is configured to output a first clock signal (CLK1) derived from the clock generator signal (STG) to the transmitting circuit (140), such that the conversion of the parallel transmit data (DPT) into serial transmit data (DST) for the serial transmit data stream (SST) is clocked by means of the first clock signal (CLK1), - a first clock frequency (f1) of the first clock signal (CLK1) is equal to the data clock frequency (fSR) contained in the serial receive data stream (SSR) as a result of the control, - the first clock signal (CLK1) is used to operate the clock circuit (180), - the clock generator (100) of the subscriber (1) is configured to output a second clock signal (CLK2) derived from the clock generator signal (STG) to the processing circuit (130), such that processing of the parallel receive data (DPR) and / or the parallel transmit data (DPT) is clocked by means of the second clock signal (CLK2), and - each message (70) on the local bus (7) is transmitted deterministically with a fixed, invariable number of clock pulses or a fixed, invariable period of time, and the clock circuit (180) of the subscriber (1) is configured to set its time (tS1) to a time value (TSLB1) contained in the message (70) or a time value derived therefrom.

2. System according to Claim 1, in which for the processing, the processing circuit (130) is configured to forward the parallel receive data (DPR) in order to output the parallel transmit data (DPT) based on the parallel receive data (DPR) to the transmitting circuit (140), in particular after a predefined number of clock pulses of the second clock signal (CLK2).

3. System according to Claim 2, in which for the processing, the processing circuit (130) is additionally configured - to store the parallel receive data (DPR) at least partially in a memory area (131a) for an evaluation; and / or - to read the parallel transmit data (DPT) at least partially from a memory area (131b) in order to output the read parallel transmit data (DPT) to the transmitting circuit (140); and / or - to change a number of bit values of the parallel receive data (DPR) in order to output the parallel receive data (DPR) with the change as parallel transmit data (DPT) to the transmitting circuit (140).

4. System according to one of the preceding claims, in which the clock generator (100) is configured to output the second clock signal (CLK2) at a second clock frequency (f2), wherein the second clock frequency (f2) is equal to or is an integer multiple of the data clock frequency (fSR) contained in the serial receive data stream (SSR) as a result of the control.

5. System according to one of the preceding claims, in which the clock generator frequency (fTG) of the clock generator (100) is equal to or is an integer fraction or an integer multiple of the data clock frequency (fSR) contained in the serial receive data stream (SSR) as a result of the control.

6. System according to one of the preceding claims, in which - the processing circuit (130) has a memory area (131c) for an instruction list (IL), - the processing circuit (130) is configured to perform the processing based on instructions (I1, I2, I3, I4, I5) contained in the instruction list (IL), and - the processing circuit (130) is configured to clock reading of the instructions (I1, I2, I3, I4, I5) from the instruction list (IL) using the second clock signal (CLK2).

7. System according to one of the preceding claims, in which - the clock generator (100) has a crystal oscillator (101) with a clock generator frequency (fTG) that can be trimmed using voltage, and - the crystal oscillator (101) is part of a phase locked loop (PLL).

8. System according to one of the preceding claims, in which - the clock generator frequency (fTG) of the clock generator (100) can be set only within a range of less than 1% of the clock generator frequency (fTG).

9. System according to one of the preceding claims, in which - the receiving circuit (120) has a decoder (123) for decoding the parallel receive data (DPR"), wherein the decoder (123) is clocked by means of the first clock signal (CLK1), and / or - the transmitting circuit (140) has a coder (143) for coding the parallel transmit data (DPT"), wherein the coder (143) is clocked by means of the first clock signal (CLK1).

10. System according to one of the preceding claims, in which - the receiving circuit (120) has a descrambler (124) for descrambling the parallel receive data (DPR'), wherein the descrambler (124) is clocked by means of the first clock signal (CLK1), and / or - the transmitting circuit (140) has a scrambler (144) for scrambling the parallel transmit data (DPT), wherein the scrambler (144) is clocked by means of the first clock signal (CLK1).

11. System according to one of the preceding claims, in which - the processing circuit (130) is configured to output the parallel transmit data (DPT) after a predefined number of clock pulses of the second clock signal (CLK2) after input of the parallel receive data (DPR).

12. System according to one of the preceding claims, in which the processing circuit (130) is configured to synchronize the time (tS1) by - the processing circuit (130) being configured to evaluate the time value (TSLB1) from the parallel receive data (DPR) and to set the time (tS1) of the clock circuit (180) based on the time value (TSLB1).

13. System according to one of the preceding claims, in which - the processing circuit (130) is configured to evaluate a time increment value (TV) from the parallel receive data (DPR) and to set a time increment of the clock circuit (180) based on the time increment value (TV).

14. System according to one of the preceding claims, in which - the processing circuit (130) is configured to determine a current time value (TSLB2) and / or a current time increment value (TV) from the clock circuit (180) and to write it / them to the parallel transmit data (DPT).