Creating an ohmic contact and an electronic component with an ohmic contact

Description

[0001] The invention relates to a method for producing an ohmic contact in an electronic component. The invention relates to an electronic component with an ohmic contact for a buried semiconductor.

[0002] An ohmic contact is a junction between a metal and a semiconductor with a small electrical resistance.

[0003] A buried semiconductor is a semiconductor located inside an electronic component. It is usually a layer of semiconductor located between two other layers.

[0004] A local ohmic contact for the buried semiconductor is a metal electrical conductor or a semiconductor of the ohmic contact that is passed through a hole of the electronic component and contacts the buried semiconductor.

[0005] To produce an electronic component, one or more layers can be applied to a substrate. The one or more layers can consist of semiconductors. One or more of these applied semiconductor layers can consist of doped semiconductors, in particular n-doped semiconductors. Semiconductors can be doped with chlorine or iodine, for example. Doping with fluorine is also possible, but is generally less suitable than chlorine and iodine. P-doping is also possible, but in many cases less suitable. An electrically insulating cover layer can be applied to the one or more semiconductor layers applied to the substrate. The one or more semiconductor layers are then buried semiconductor layers within the meaning of the present invention.To create an ohmic contact for a buried semiconductor layer, a hole can be created that leads through the cap layer to the buried semiconductor layer. The hole can be created by etching. After the hole is created, it can be filled with a metal to create a local ohmic contact that can be electrically contacted above the cap layer. This makes it possible, for example, to subsequently equip an electronic component with additional gate electrodes, which are required for unipolar devices such as field-effect transistors or electron spin qubits.

[0006] In electronic components comprising substrates or layers made of GaAs and AlGaAs or Si and SiGe, metals can be thermally alloyed into a hole created in a capping layer at high temperatures to contact a buried semiconductor and create a local ohmic contact. Additional dopants can be locally introduced by ion implantation before alloying a metal to create suitably good ohmic contacts.

[0007] The known methods for creating a local ohmic contact are not suitable for all compound semiconductors. For example, the II-VI compound semiconductor ZnSe cannot tolerate the high temperatures required for efficient alloying with a metal. Ion implantation can severely damage the crystal structure of such compound semiconductors, significantly reducing their conductivity. Creating a junction between a metal and a semiconductor with low electrical resistance is then impossible in this way. This problem occurs primarily with II-VI compound semiconductors. However, III-V compound semiconductors can also be affected.

[0008] It may be of interest to be able to operate electronic components at low temperatures. This may be necessary, for example, for electron spin qubits in a quantum computer.

[0009] III-V compound semiconductor field-effect transistors are known from US 2018 / 096885 A1. A method for forming a semiconductor structure is also disclosed. The method first comprises forming source / drain regions on opposite sides of a gate structure located on a compound semiconductor channel layer. Subsequently, source / drain contact openings are formed. Each of the source / drain contact openings exposes a portion of one of the source / drain contact regions. Next, metal-semiconductor alloy regions are formed within the source / drain contact openings.

[0010] A group II-VI compound semiconductor device and a method for its production are known from EP 0 674 347 A1. The method comprises forming a semiconductor layer on a semiconductor substrate, forming an intermediate layer on the semiconductor layer, and subsequently forming an electrode layer on the intermediate layer.

[0011] EP 1150360 A2 discloses a method for producing a compound semiconductor device with an ohmic electrode with a low contact potential and an apparatus for producing a compound semiconductor device. The method includes substrate cleaning steps.

[0012] The object of the invention is to be able to produce an ohmic contact in an electronic component, specifically a local ohmic contact for buried III-V compound semiconductors or II-VI compound semiconductors of an electronic component. This should preferably also be possible for II-VI compound semiconductors that can be doped with chlorine. The ohmic contact should preferably also enable operation of the associated electronic component at low temperatures.

[0013] The object of the invention is achieved by a method having the features of the first claim and an electronic component having the features of the dependent claim. Advantageous embodiments are set forth in the dependent claims.

[0014] To solve this problem, a method for producing an ohmic contact for an electronic component is provided. To produce the electronic component, a layer consisting of a semiconductor, i.e., a semiconductor layer, is applied directly or indirectly to a substrate. If the semiconductor layer is applied directly to the substrate, there is no further layer between the semiconductor layer and the substrate. If the semiconductor layer is applied indirectly to the substrate, there are one or more layers between the substrate and the semiconductor layer.

[0015] A semiconductor surface to be contacted is wet-chemically etched. The wet-chemically etched surface is rinsed with radicals. The surface rinsed with radicals is treated with a metal vapor, the metal vapor containing a metal that the semiconductor also contains. An electrical conductor or a semiconductor is applied to the surface rinsed with radicals. In this way, it is possible to create a connection to a semiconductor that can easily be damaged by conventional manufacturing processes to such an extent that the creation of a junction with a low electrical resistance is not possible. Surprisingly, it has been found that such problems can be solved by chemical etching followed by rinsing with radicals, even if the surface was previously treated in a damaging way, such as by ion etching.

[0016] A radical is an atom or molecule with at least one unpaired valence electron. Purging with hydrogen radicals has proven to be suitable for this purpose.

[0017] Wet-chemical etching and subsequent rinsing with radicals have proven to be crucial steps in contacting sensitive II-VI and III-V compound semiconductors in such a way that almost perfectly linear current-voltage characteristics and extremely low contact resistances can be achieved at room temperature and at very low temperatures.

[0018] Preferably, purging is carried out in the absence of oxygen. Purging is preferably carried out in an ultra-high vacuum, thus also in the absence of oxygen, to achieve a further improved result. This design is particularly advantageous for compound semiconductors that can oxidize rapidly in air. ZnSe is an example of a compound semiconductor that can oxidize rapidly in air. Oxidation can lead to the formation of an electrically non-conductive surface oxide layer that acts as a barrier to current transport. This can prevent a junction with a low electrical resistance.

[0019] The result can be further improved by rinsing at an increased temperature of, for example, 100°C to 200°C.

[0020] Rinsing is preferably carried out for several minutes, for example 2-10 minutes, to achieve the desired results.

[0021] In wet chemical etching, chemical bonds in the material being processed are broken down by etching media and converted into soluble components. Etching media typically used are K 2 Cr 2 O 7 + HBr + H 2 O or NH 3 + H 2 O 2 + H 2 O or K 2 Cr 2 O 7 + H 2 SO 4 + H 2 O.

[0022] Preferably, wet chemical etching is carried out for a few seconds, for example 2-10 seconds, in order to be able to contact the compound semiconductor in a suitable manner.

[0023] The semiconductor prepared for the creation of an ohmic contact by wet-chemical etching followed by rinsing with radicals can be a II-VI compound semiconductor or a III-V compound semiconductor. II-VI compound semiconductors that can be doped with chlorine benefit most from the process. Examples of such II-VI compound semiconductors are (Zn,Mg)Se, (Zn,Cd)Se, (Zn,Mg)SSe, (ZnCd)SSe, ZnSe,CdSe, or ZnSSe.

[0024] The metal of the compound semiconductor is preferably selected from zinc (Zn), cadmium (Cd), magnesium (Mg), and / or beryllium (Be). The non-metal of the compound semiconductor is preferably selected from selenium (Se) and / or sulfur (S).

[0025] To produce an ohmic contact for a buried semiconductor, a manufacturing process may include the following steps: Applying one or more semiconductor layers to a substrate; applying an electrically non-conductive cover layer to the one or more applied semiconductor layers, wherein the cover layer may consist of an electrically non-conductive dielectric; creating a hole through the cover layer to a semiconductor layer; this surface of the semiconductor layer accessible through the hole is wet-chemically etched as described above, this wet-chemically etched surface is rinsed with radicals as described above, a doped semiconductor is applied to this surface rinsed with the radicals, and a metal, for example aluminum, is applied to the applied doped semiconductor.

[0026] An electronic component manufactured in this way can then be equipped with a gate electrode, for example.

[0027] The hole created in the capping layer, which extends through the capping layer, can be partially or completely filled with the doped semiconductor. The hole created in the capping layer can extend through one or more additional layers below the capping layer to reach the desired semiconductor layer. One or more of the additional layers can be semiconductor layers, i.e., consist of a semiconductor.

[0028] A plurality of holes may be created in a cover layer to establish a plurality of local ohmic contacts.

[0029] Filling the holes with a doped semiconductor is preferably done by molecular beam epitaxy. This enables selective growth. Growth can thus be restricted to the area of ​​holes. This type of deposition using molecular beam epitaxy is known as the regrowth process. Manufacturing is simplified by this process. An additional step, namely the etching away of doped semiconductor between a plurality of holes, is eliminated. However, this does not preclude the possibility that, in one embodiment of the invention, a subsequently applied metal layer between holes or between manufactured ohmic contacts is etched away. Advantageously, a subsequently applied metal layer between holes or between manufactured ohmic contacts is etched away in such a way that this step also generates one or more additional gate electrodes independently of the ohmic contacts.

[0030] To manufacture an electronic component, which in its finished state can be a unipolar component and which can also be used at low temperatures, one or more semiconductor layers can be applied to the substrate in an ultra-high vacuum. Subsequently, the cover layer can be applied to the one or more applied semiconductor layers in the ultra-high vacuum. During coating, the surfaces of the layers in this embodiment are not exposed to the atmosphere, and consequently, neither is the surface to which the cover layer is applied.

[0031] Adjacent semiconductor layers consist of different semiconductor materials and / or are at least differently doped.

[0032] For example, a first semiconductor layer can be applied to the substrate. Subsequently, a second semiconductor layer can be applied to the first semiconductor layer. Subsequently, a third semiconductor layer can be applied to the second semiconductor layer. Subsequently, a capping layer can be applied to the third semiconductor layer. However, more than three semiconductor layers can also be applied before a capping layer is applied.

[0033] The first and / or third deposited semiconductor layers can be made of (Zn,Mg)Se, (Zn,Cd)Se, Zn(S,Se), or (Zn,Mg)(S,Se). The second layer can be made of ZnSe or CdSe. These materials are particularly suitable for producing a unipolar component that can be used even at low temperatures, for example, to serve as qubits in a quantum computer. The second layer can be produced as a doped layer, but this is not required.

[0034] The cover layer can be made of an oxide ceramic. The cover layer consists, for example, of aluminum oxide, silicon oxide, or hafnium oxide. However, the cover layer can also be made of another material, such as silicon nitride. These materials can serve as optimal gate dielectrics for producing unipolar components, such as 2D or 3D field-effect transistors or electrostatically defined electron spin qubits. The invention therefore also relates to unipolar components of this type.

[0035] In general, an electrically non-conductive dielectric is suitable as a material for the cover layer to produce unipolar components.

[0036] The substrate can be made of a semiconductor. The substrate can be made of a III-V semiconductor or a II-VI compound semiconductor to allow for the suitable formation of II-VI semiconductor layers on the substrate. The substrate can therefore be made of GaAs, ZnSe, (In,Ga)As, InAs, (In,Ga)P, (In,Ga,Al)P, InAs, or InP.

[0037] A hole through the cover layer can be created by wet chemical etching, particularly with HF. Alternatively, the hole can be created by reactive ion etching, particularly with CHF 3 + O 2 .

[0038] If the hole is to be extended into underlying layers, this can be achieved by reactive ion etching. This can typically be done using Cl 2 +Ar, Cl 2 +BCl 3, or CH 4 +H 2 +Ar, for example, in the case of compound semiconductors consisting of (Zn,Mg)Se, Zn(S,Se), CdSe, or ZnSe.

[0039] Dry etching processes can severely damage the crystal structure of compound semiconductors close to the surface. However, subsequent chemical wet etching and subsequent rinsing with radicals can resolve the resulting problems, making it possible to create junctions with low electrical resistance. Rinsing is particularly effective in the absence of oxygen if the semiconductor in question is prone to oxidation.

[0040] To create a hole through the cover layer by etching, an etching mask can be applied to the cover layer. The cover layer can consist of a photoresist with a hole provided in it. The hole-enclosed resist can be produced by optical lithography.

[0041] After a hole through the cover layer has been created by etching to the desired depth, the surface of the deposited semiconductor to be contacted can be wet-chemically etched as previously described.

[0042] After this final etching, the etching mask can be removed. For technical reasons, it is advisable to clean the surface, for example, with a solvent such as isopropanol. In particular, the surface of the deposited semiconductor that is to be contacted, i.e., the semiconductor layer intended for the ohmic contact, should be cleaned.

[0043] To further improve the desired technical result, it is advantageous to thermally treat the component after etching and preferably also after cleaning. This can be done at a temperature between 100°C and 200°C. The thermal treatment can last several minutes, for example, at least 15 minutes. The thermal treatment can be completed after 60 minutes at the latest, as no further beneficial effect can usually be achieved after that time. Therefore, a treatment time of approximately 30 minutes is sufficient.

[0044] To achieve a further improved technical result, the thermal treatment is preferably carried out in an ultra-high vacuum. This allows adverse environmental influences to be avoided.

[0045] Following the thermal treatment, the component can be purged with radicals, particularly hydrogen radicals, preferably for several minutes. This preferably takes place in an ultra-high vacuum, particularly preferably in the ultra-high vacuum provided for the thermal treatment. This prevents the component to be manufactured from coming into contact with the atmosphere after the thermal treatment and before the purging with radicals.

[0046] After rinsing with radicals, the surface of the semiconductor layer to be contacted is treated with a metal vapor. The metal vapor contains a metal that is also present in the semiconductor. For example, if the semiconductor is made of ZnSe, the metal vapor contains zinc as the metal. In the case of ZnSe, the metal vapor is therefore generated from a zinc source. Metal is thermally evaporated by such a metal source. Any existing metal defects can thus be filled, which can lead to a further improved desired technical result. Processing with the metal vapor preferably takes place in an ultra-high vacuum, preferably in the ultra-high vacuum already provided for previous steps. As before, contact with the atmosphere is then prevented.

[0047] Finally, the hole can be fully or partially filled with a semiconductor, generally a semiconductor that matches the semiconductor to be contacted. For example, if a layer consisting of ZnSe is to be contacted, the hole is preferably fully or partially filled with ZnSe. However, the two semiconductors can differ in their doping. For example, the hole can be fully or partially filled with n-doped ZnSe to contact a layer made of undoped ZnSe.

[0048] The hole is preferably filled with the semiconductor at a temperature particularly suitable for growth, for example, 200-400 °C. A temperature of 300 °C, for example, is suitable for ZnSe. The hole is filled in an ultra-high vacuum, preferably in the ultra-high vacuum already provided for previous steps to continue to prevent contact with the atmosphere.

[0049] Once the hole has been completely or partially filled with a semiconductor, metal is then deposited onto the semiconductor. This is done, for example, using a metal vapor deposition system. This preferably takes place in the aforementioned ultra-high vacuum, preventing contact with the atmosphere. The semiconductor produced, for example, by regrowth, cannot oxidize before the metal has been deposited.

[0050] Aluminum is a particularly suitable metal, but titanium and magnesium are also suitable.

[0051] To enable the latter steps to be performed in situ in an ultra-high vacuum, the required systems are interconnected by the ultra-high vacuum. This chamber contains a molecular beam epitaxy system for compound semiconductors, a vapor deposition system for metals such as aluminum, an atomic layer deposition system, and a radical source, such as hydrogen radicals.

[0052] Comparative tests have shown that in this way, in the case of sensitive compound semiconductors, an ohmic contact with significantly better properties can be provided compared to the known state of the art.

[0053] The invention also relates to an electronic component producible by the method, comprising a plurality of semiconductor layers on a substrate and a cover layer on the one or more semiconductor layers applied to the substrate, the cover layer consisting of an electrically non-conductive dielectric. Adjacent semiconductor layers consist of different II-VI semiconductors, so that a heterojunction is present. A hole created provides access that leads through the cover layer to a semiconductor layer and extends into it. The access is at least partially filled with a II-VI semiconductor. A metallic contact is applied to the II-VI semiconductor. This metallic contact at least completely fills the access, so that it extends at least to the outside of the cover layer. As a rule, the metallic contact protrudes outwards from the cover layer. The metallic contact is made in particular of aluminum.

[0054] The first and / or third applied semiconductor layer preferably consists of (Zn,Mg)Se, Zn(S,Se), (Zn,Cd)Se, or (Zn,Mg)(S,Se). The second semiconductor layer consists in particular of ZnSe or CdSe. The cover layer preferably consists of aluminum oxide, silicon oxide, hafnium oxide, or silicon nitride. The substrate can consist of GaAs, ZnSe, AlAs, InAs, GaP, AlP, or InP, or of mixed forms such as (In,Ga)As or (In,Al)GaP.

[0055] The invention further relates to a unipolar component, which can be constructed as described above. The unipolar component can be a field-effect transistor or a high-mobility transistor. It can be an electron spin qubit component.

[0056] The invention is explained in more detail below using an example.

[0057] They show: Figure 1: Layer structure with a ZnSe layer; Figure 2: Layer structure with a hole; Figure 3: Layer structure with a hole partially filled with semiconductor; Figure 4: Layer structure with applied aluminum; Figure 5: Layer structure with completed, local ohmic contact; Figure 6: Measured current-voltage characteristics; Figure 7: Further structure for an electronic component with buried semiconductor layers and local ohmic contact.

[0058] The Figure 1shows a substrate 1 made of gallium arsenide, onto which a buried first semiconductor layer 2 made of (Zn,Mg)Se has been applied in situ in the ultra-high vacuum on the first semiconductor layer 2. A buried second semiconductor layer 3 made of ZnSe has been applied in situ in the ultra-high vacuum on the second semiconductor layer 3. A buried third semiconductor layer 4 made of (Zn,Mg)Se has been applied in situ in the ultra-high vacuum on the third semiconductor layer 4. The application takes place, for example, by atomic layer deposition. The layers can be several tens of nanometers thick, for example 20 nm thick.

[0059] In situ means that the Figure 1 The structure was not removed from the ultra-high vacuum during its manufacture, so that no adverse oxidation effects could occur.

[0060] After deposition of the Al 2 O 3 layer, the structure is removed from the ultra-high vacuum. Using conventional optical lithography, a mesh mask with holes is defined in a previously applied photoresist, in which the ohmic contacts will later be formed by regrowth. At the positions of the holes, the Al 2 O 3 layer 5 is first opened either wet-chemically with HF or by reactive ion etching with CHF 3 + O 2. Then, the underlying (Zn,Mg)Se and ZnSe layers 4 and 3 are opened by reactive ion etching with Cl 2 + Ar. Thus, etching is carried out as shown in the Figure 2 shown to create a hole 6. The semiconductor layer 3 can be contacted through this hole 6.

[0061] After reactive ion etching, the resulting radiation damage is removed by wet-chemical re-etching for approximately 5 seconds using a solution of K2Cr2O7 + HBr + H2O. The photoresist is then removed, and the etched ZnSe semiconductor layer 3 is cleaned with isopropanol and returned to the ultra-high vacuum for the regrowth process. The structure is then heated to 150°C in the ultra-high vacuum for 30 minutes and then rinsed with hydrogen radicals for 5 minutes. This removes chemical residues from the etching and cleaning process, as well as any oxide residues on the surface. The etched layer is then slowly heated under zinc flux to the growth temperature of 300°C, suitable for the regrowth process. This serves to fill any remaining zinc defects near the etched surface.A chlorine-doped ZnSe layer 7 is then grown using molecular beam epitaxy (MBE) under standard growth parameters. This is described in the . Figure 3 shown. Layer 7 should be at least thick enough to fill the hole up to the Al 2 O 3 layer 5. Otherwise, the metal 8 on layer 7 would laterally contact layer 4 and thus the semiconductor (Zn,Mg)Se. This could be disadvantageous and should therefore be avoided.

[0062] Subsequently, the newly grown doped ZnSe layer 7 is coated in situ with aluminum 8 as an ohmic contact material, which in the Figure 4 The in situ deposited aluminum layer 8 prevents the formation of an oxide between the chlorine-doped ZnSe layer 7 and the aluminum layer 8, allowing unhindered current transport through the aluminum-ZnSe interface.

[0063] In a final step, the excess aluminum and ZnSe between the actual local contacts is removed by means of optical lithography and subsequent wet chemical etching until the Figure 5 shown structure is achieved.

[0064] The layer thicknesses in the Figure 5 are shown only schematically. Thus, the two semiconductor layers 2 and 4 can be thicker than the semiconductor layer 3. The cover layer 5 can be thinner than the semiconductor layer 3. Advantageously, the semiconductor layer 7 is at least thick enough to extend into the dielectric layer 5.

[0065] In this way, excellent local ohmic contacts with minimal contact resistance and a linear current-voltage characteristic at room temperature and low temperature can be realized. Figure 6shows a diagram with correspondingly linear current-voltage characteristics measured at room temperature RT (solid line) and 4 K (dashed line) using the setup described in the Figure 7 The distance between two ohmic contacts of the component used for the measurement was 30 µm. The measured current in milliamperes is plotted against the applied voltage in volts. In addition to the excellent linearity of the current-voltage characteristics, the measurement also allows the contact resistance and the sheet resistance of the Figure 7 Determine the resistance of the component shown. At room temperature, the contact resistance is ρ K ≤ 3×10 -5< Ωcm 2< and the sheet resistance is ρ s ≤ 6×10 -2< Ωcm, at low temperature, the contact resistance is ρ K ≤ 8×10 -3< Ωcm 2< and the sheet resistance is ρ s ≤ 4×10 -2< Ωcm

[0066] The Figure 7The component shown comprises a substrate 1 made of gallium arsenide. On the substrate is an undoped, approximately 20 nm thick ZnSe semiconductor layer 2. On the ZnSe semiconductor layer 2 is an approximately 800 nm thick, chlorine-doped ZnSe semiconductor layer 3. On the semiconductor layer 3 is an approximately 20 nm thick dielectric layer 5 made of Al 2 O 3 . An access to the semiconductor layer 2 created by a hole has been completely filled with chlorine-doped ZnSe, i.e., with ZnSe:Cl. Aluminum 8 with a thickness of approximately 120 nm is applied to this ZnSe:Cl filling 7.

Claims

1. Method for producing an ohmic contact for an electronic component, wherein a layer (3) consisting of a semiconductor is applied directly or indirectly to a substrate (1), wherein a surface of the applied semiconductor (3) to be contacted is wet-chemically etched, the wet-chemically etched surface is rinsed with radicals, the surface rinsed with radicals is processed with a metal vapor, wherein the metal vapor includes a metal which is also present in the semiconductor, and an electrical conductor (8) or a semiconductor (7) is applied to the surface rinsed with radicals.

2. Method according to the preceding claim, characterized in that rinsing is carried out with hydrogen radicals.

3. Method according to one of the preceding claims, characterized in that rinsing is carried out in an ultra-high vacuum.

4. Method according to one of the preceding claims, characterized in that rinsing is carried out at a temperature between 100°C and 200°C.

5. Method according to one of the preceding claims, characterized in that wet-chemical etching is carried out with K2Cr2O7 + HBr + H2O or with NH3 + H2O2 + H2O or with K2Cr2O7 + H2SO4 + H2O.

6. Method according to one of the preceding claims, characterized in that wet chemical etching is carried out for 1 to 20 seconds.

7. Method according to one of the preceding claims, characterized in that the semiconductor (3) is a II-VI semiconductor or a III-V semiconductor and consists in particular of (Zn,Mg)Se, Zn(S,Se), ZnSe, CdSe or (Zn,Mg)(S,Se).

8. Method according to one of the preceding claims, characterized in that the metal of the semiconductor is selected from zinc (Zn), cadmium (Cd), magnesium (Mg) and / or beryllium (Be).

9. Method according to one of the preceding claims, characterized in that the non-metal of the semiconductor is selected from selenium (Se) and / or sulphur (S).

10. Method according to one of the preceding claims, characterized in that the semiconductor is doped with chlorine (CI) or can be doped with chlorine (CI).

11. Electronic component having one or more semiconductor layers (2, 3, 4) on a substrate (1), a cover layer (5) on the one or more semiconductor layers (2, 3, 4) applied to the substrate (1), wherein the cover layer (5) consists of an electrically non-conductive dielectric, having an access (6) which leads through the cover layer to a semiconductor layer (3) and extends into the latter, wherein adjacent semiconductor layers (2, 3, 4) consist of different II-VI semiconductors, wherein the access (6) is at least partially filled with a doped II-VI semiconductor (7) and a metallic contact (8) is applied to the doped II-VI semiconductor (7), which contact extends to the outside of the cover layer (5) or projects outwards with respect to the cover layer (5).

12. Electronic component according to the preceding claim, characterized in that the first and / or the third applied semiconductor layer (2, 4) consists of (Zn,Mg)Se, (Zn,Mg)(S,Se), (Zn,Be)Se, Zn(S,Se) and / or in that the second semiconductor layer (3) consists of ZnSe.

13. Electronic component according to one of the two preceding claims, characterized in that the cover layer (5) consists of aluminium oxide, silicon oxide, hafnium oxide or silicon nitride.

14. Electronic component according to one of the three preceding claims, characterized in that the substrate (1) consists of GaAs, ZnSe, (In,Ga)As, InAs, (In,Ga)P, (In,Ga,AI)P or InP.

15. Electronic component according to one of the preceding claims, characterized in that it is a unipolar component.