Method for manufacturing a high-resolution thermal infrared sensor array in a vacuum-filled wafer-level housing

Description

[0001] The invention relates to a method for producing a high-resolution thermal infrared sensor array in a vacuum-filled wafer-level housing with particularly small dimensions, which consists of at least two wafers, a cover wafer and a central wafer with a plurality of sensitive infrared sensor pixels, each on a thin, slotted membrane above a heat-insulating cavity.

[0002] For applications of infrared sensor arrays for small, cost-effective thermal cameras, both high spatial and thermal resolution and minimal housing dimensions of the sensor module are important.

[0003] This is especially true for so-called mobile applications, such as those found in smartphones or similar.

[0004] These applications must achieve high thermal resolution with good measurement accuracy in the smallest possible space, while maintaining the smallest overall dimensions of the sensor module. A very low height of the infrared array sensor module is particularly important, for example, to accommodate a miniaturized thermal camera constructed with it within the smartphone housing itself. A total height of the sensor array, including the entire optics, of < 2.5...3 mm is necessary to accommodate the mini thermal camera next to the small CMOS camera in the same viewing direction on the circuit board.

[0005] Only thermal (uncooled) sensors can be considered as infrared sensor arrays. This group of thermal sensors includes microbolometers, pyroelectric arrays, and thermopile arrays (TP arrays).

[0006] To achieve the required measurement accuracies, continuously modulated mechanical choppers are required for pyroelectric arrays, and so-called mechanical shutters are required for microbolometers. These must be integrated into the beam path in addition to the sensor array and infrared optics. The additional mechanical dimensions of the controlled chopper or shutter assemblies increase the housing height and complicate installation into a smartphone housing. Only thermopile sensor arrays (TP arrays) achieve the required measurement accuracies without additional mechanical choppers or shutters in the beam path.

[0007] For miniaturized, high-resolution thermopile arrays, pixel dimensions must be small, which requires hermetic encapsulation of the sensitive array chip under vacuum. Since conventional packages (such as metal packages, e.g., those of the TO series) are also too large, wafer-level packaging (WLP) remains the most promising option. This is a particularly cost-effective form of vacuum sealing for thermopile array chips, in which a wafer assembly with the active elements in the center is hermetically sealed under high vacuum.

[0008] The WLP has the additional advantage that all silicon-based wafers have the same thermal expansion coefficient. This means that if the sensor's temperature changes during packaging or use, no additional stress is created between the lid / sensor and / or base wafer, as they all have the same expansion coefficient.

[0009] Since individual sensor pixels in a sensor array only deliver a very small voltage signal (typically in the µV range), the signals must be amplified nearby, ideally within the sensor package itself. Since a high-resolution array sensor contains a large number of pixels on the same sensor chip, a large number of preamplifiers (operating in parallel) are also required.

[0010] Infrared thermopile sensor arrays are well known in various shapes and designs. Thermopile sensors manufactured using silicon micromachining typically consist of a thin membrane on which thermocouples manufactured using thin-film technology are located. Beneath the membrane is a cavity in the substrate.

[0011] The "hot" contacts of the thermocouples are located in the central part of the membrane, and the "cold" contacts are located on the silicon edge, which serves as a heat sink. Between them are, for example, narrow, long beams (webs) that connect the central part of the membrane (absorber area) to the heat sink (the silicon edge of the pixel) and contain one or more thermocouples.

[0012] On both sides of the long beams are slits that separate the beams from the central part or the silicon well (supporting body). Most of the absorption of IR radiation occurs in the central region of the membrane. Especially in arrays with high spatial resolution, the pixels are small and the perforations (slits) are very narrow. To increase the fill level of the sensor, an infrared shield (umbrella) can be stretched over the membrane or pixel, allowing more infrared radiation to be absorbed through the larger surface area.

[0013] The thermocouples (on the beams) are located relatively close to the Si sink, so that a larger part of the heat can flow to the sink via the gas in between.

[0014] This leads to signal loss. To counteract this, vacuum sealing is used.

[0015] The slits in the membrane are used to create the cavity underneath. A wafer bonded to it is used to create a hermetically sealed closure. However, the isotropic etching of the substrate beneath the membrane requires protection of the surrounding electronics to avoid potential damage.

[0016] US 2008 / 0128620 A1 describes a wafer level package for several thermopiles on a thin membrane, under or above which there are cavities for thermal isolation, which are usually etched anisotropically (KOH), but optionally also with DRIE.

[0017] The necessary parallel signal processing with a large number of channels, which would be necessary to create a high-resolution TP array with a large number of small pixels, is not possible due to lack of space.

[0018] EP 2889 909 proposes a solution with multiple slits in the area of ​​the pixel absorber to better guide the Si sacrificial layer under the membrane out of the die. However, this results in a loss of effective absorber area and thus signal and measurement accuracy.

[0019] WO 2015004166 A1 describes a method for hermetically sealing an electronic device with reduced stress. Here, too, complex processing is required to expose the pixels, and the application of reflective metal layers to the bottom of the cavity beneath the pixel is difficult or very complex.

[0020] None of the solutions allows the production of particularly small and highly sensitive pixels and the accommodation of the necessary signal processing channels in a particularly small area.

[0021] DE 10 2006 122 850 presents a high-resolution thermopile array in the WLP. This array consists of three interconnected wafers (lid, sensor chip, and base).

[0022] However, the thicknesses of the three interconnected wafers are approximately the same, meaning that the middle sensor wafer, with its cavities etched through the entire wafer using bulk micromachining with vertical holes, limits the achievable pixel size due to tolerances. Furthermore, too many pixels cannot be accommodated on the sensor wafer because there isn't enough space for the necessary parallel signal processing channels.

[0023] US 8519336 B2 proposes a configuration in which an IR detecting device is located above a reflective layer. An arithmetic evaluation circuit is also located on the underlying circuit board. Three silicon substrates (wafers) are combined here. The receiving unit consists of a thermopile and a pressure-reduced and sealed pit in a silicon substrate. The reflective layer forms a kind of niche beneath the receiving unit. The surface of the niche is made of a reflective material, such as gold or aluminum. This arrangement reflects IR radiation that was not primarily detected in the receiving unit and focuses it back onto the receiving unit for further detection.

[0024] The "niches" with the reflective structures have a parabolic mirror-like shape so that as much of the IR radiation as possible can be reflected back to the receiving unit.

[0025] The necessary electrical contacts extend from the backside of the top wafer to the front side of the middle wafer via through-silicon vias (TSVs) through the middle wafer in a "3-wafer sandwich" to the backside of the wafer and a signal processing unit, and finally vias to the backside of the bottom wafer and solder contacts. This makes this thermopile array SMD-capable in the WLP.

[0026] This means that the signal lines can in principle be routed either outside the pixel area or between the pixels, whereby the signal processing for each pixel can be carried out in the bottom wafer below the pixels.

[0027] Typical TSVs manufactured using current state-of-the-art technology require lateral dimensions on the wafer that are approximately one-tenth of the wafer thickness. Consequently, typical vias for a wafer thickness of 400 to 500 µm would be approximately 40 to 50 µm in size.

[0028] This does not allow the production of particularly high-resolution arrays with particularly small pixels, because the size of the vias in the pixel field alone increases the lateral pixel dimensions.

[0029] However, this is too much for arrays as a small camera chip in a smartphone, because a lens optic with the appropriate focal length must also be mounted above the sensor array chip.

[0030] CN 102 583 220 B discloses an infrared detector consisting of a first Si substrate on which a passivation layer with a CMOS circuit is located, as well as an infrared absorbing layer on a membrane above a recess (sensor pixel) and a second substrate which is provided with a recess above the IR absorbing layer / membrane.

[0031] On the sides of the membrane are vias created by deep etching and a metal fill. To expose the vias, the substrate is thinned on the back, but this does not affect the pixel size.

[0032] DE 10 2012 216 618 A1 relates to an arrangement of at least two wafers for detecting electromagnetic radiation, consisting of a first wafer with an array of infrared sensor elements (sensor pixels), a second wafer with an integrated evaluation circuit connected to the sensor array via vias. Furthermore, a third wafer is provided, which serves as a cap wafer and covers the sensor array on the first wafer.

[0033] This is intended to separate ASIC and MEMS structures by implementing them on different wafers. Vias are provided for electrical connection. Measures for producing particularly small sensor pixels are not described.

[0034] None of the state-of-the-art solutions allows the production of a high-resolution infrared sensor array with very many, very small pixels and a particularly low installation height (e.g., so that they fit into a smartphone or similar device) that can be easily manufactured in a normal, CMOS-compatible process.

[0035] The sensitivity of an infrared sensor also depends on heat dissipation via the gas surrounding the sensor and can be increased through vacuum-tight packaging. In a vacuum-tight housing, signal losses due to heat conduction via the gas are nonexistent or very minimal. However, conventional vacuum housings used in assembly and interconnection technology require a lot of material and are expensive to achieve the necessary vacuum tightness. Even standard chip bonding can become a costly and problematic factor due to outgassing and leaks. Since the individual housing materials are usually different (base, cap, optical window), they also have different thermal expansion coefficients, which can lead to mechanical stress and leaks.

[0036] Packaging and vacuum-tight sealing at the wafer level is cost-effective and can be implemented for mass production. The necessary vacuum tightness is achieved by encapsulating the thermopile sensor wafer with a lid and a bottom wafer.

[0037] A disadvantage of the well-known wafer level packages (WLPs) for thermopile arrays is their relatively large height, which results from the combination of several individual wafers. This is because each individual wafer must be processed, including cavities, metallization, filter layers, etc. Given the size of modern semiconductor wafers (which range between 200 and 300 mm in diameter), this requires a certain minimum wafer thickness. If it were too thin (e.g., only 100...200 µm), it would break during processing (handling) in most systems currently in production.

[0038] Wafer thicknesses of approximately 400-500 µm are currently typical and can be processed with reasonable yield in series production. A composite of two wafers then has a thickness of approximately 0.8-1 mm for two composite wafers, and approximately 1.2-1.5 mm for a composite of three wafers (the particularly preferred variant with bulk micromechanics as in the known solutions). This prevents the achievement of very low installation heights (e.g., for use in smartphones).

[0039] A second disadvantage of the current technology is the low spatial resolution due to excessively large thermopile pixels. The smallest thermopile arrays known to date have pixel dimensions of 90 µm.

[0040] A third disadvantage of known thermal infrared array solutions (e.g., thermopile arrays) is their large lateral size, which also complicates their integration into small mobile devices such as smartphones. Typically, the sensor array chips are mounted in metallic TO packages or metal hermetic packages, whose external dimensions are significantly larger than the sensor chip itself.

[0041] The object of the invention is to provide a method for producing a high-resolution thermal infrared sensor array in a vacuum-filled wafer-level package using monolithic silicon micromechanics technology in the wafer-level package, which achieves a particularly high spatial resolution (due to very small pixels) and a very high degree of filling with the smallest package dimensions, in particular a very low overall thickness, and can be manufactured cost-effectively using standard CMOS-compatible processes.

[0042] The problem underlying the invention is solved by the features of the main claim. Further embodiments of the invention emerge from the associated subclaims.

[0043] According to the invention, the object is achieved in that at least two, preferably three or more semiconductor wafers, e.g. made of silicon or infrared-transparent glass for the cover wafer, are first processed separately and then mounted and thereby gradually thinned: The lid wafer is preferably provided with a cavity of a few tens to a few hundred µm on its underside, and then both wafer sides are coated with so-called anti-reflective or filter layers. These filter layers are intended to enable particularly high transmission of the lid wafer in the infrared range and also to filter out certain spectral ranges where, for example, transmission losses in the atmosphere occur, which would lead to distance dependence when measuring distant objects.

[0044] These filter layers can also consist of special subwavelength structures. The cavity depth can, for example, be approximately half the total thickness of the lid wafer, as this also increases the wafer's transmission for IR radiation. However, the remaining thickness must not be too small to ensure the wafer assembly remains mechanically stable.

[0045] The middle wafer, or the wafer containing the sensor pixels, is provided with the usual functional layers. These include, for example, several layers of polycrystalline or amorphous silicon with varying conductivity, absorber structures (preferably so-called umbrellas), and CMOS structures for signal processing. All surface-side steps (such as the creation of the subsequent slits in the membrane for thermal insulation from the Si substrate) must be completed before joining.

[0046] According to the invention, the middle sensor wafer has a very low residual thickness of < 200...300 µm, preferably < 50-100 µm, after thinning. This offers two advantages over previously known thermopile array solutions.

[0047] On the one hand, much smaller thermopile pixels can be processed than previously known because the Si edges of the pixels remaining after the DRIE etching process (which act as thermal isolation and heat sink for the cold contacts) can be reduced to a few micrometers.

[0048] On the other hand, much smaller lateral dimensions for electrical vias from the front to the back of the thermopile wafer (or the bottom wafer) can be realized than would be possible with standard wafer thicknesses of, for example, approximately 400 - 500 µm.

[0049] With the current state of the art, typically achievable lateral dimensions of TSVs are approximately one-tenth of the wafer thickness. Consequently, typical vias for a wafer thickness of 400 µm would be approximately 40 µm in size. However, if the wafer were thinned to, say, 30 µm, the vias would be only approximately 3 µm in size. This allows, in advanced embodiments, every pixel to be connected to the backside, even with particularly small thermopile pixel dimensions.

[0050] The preparation of the electrical contacts for external processing of the sensor signals from the array pixels includes: Either the middle wafer, containing the sensor pixels and part of the signal processing electronics, is routed directly to the outside via prepared bond pads in the middle wafer and later wire bridges, or the signal processing is routed to the bottom wafer, e.g., via very small vias (so-called through-silicon vias, TSVs). Further signal processing (ROIC) can be housed on the bottom wafer. There is more space there than next to the thermopile array on the middle wafer.

[0051] In the best case, each pixel is even individually routed to the bottom wafer. This is made possible by the particularly thin central wafer, which allows for very small and particularly precise vias in the corners of the pixels, thus further increasing the packing density of the array.

[0052] In addition to signal processing such as preamplifiers and analog-to-digital converters, a large part of the digital signal processing, including image analysis, can be accommodated on the lower bottom wafer (ROIC) in the form of processors.

[0053] In order to bring signals further down to the carrier substrate, additional vias / through holes can be located in the bottom wafer to route signals directly down to suitable contacts such as solder bumps.

[0054] The adjustment on the thermal pads of a Quad Flat No Leads Package (QFN Package) can also be useful for dissipating unwanted heat in the ASIC.

[0055] The lid wafer contains a pit created using suitable methods, such as wet etching or DRIE. For mechanical stability, the pit should be no more than 50% as deep as the thickness of the lid wafer.

[0056] In one variant, the bottom wafer (ROIC) can also be thinned to < 0.2 ... 0.3 mm so that the entire stack of three wafers is as thin as possible to fit into a mobile device, such as a smartphone.

[0057] The invention is explained in more detail below using an exemplary embodiment. The accompanying drawing figures show: Fig. 1: the basic structure of an inventive, very thin infrared sensor array in a vacuum wafer level package as a sectional view; Fig. 2: the preparation of the cover wafer, sensor wafer, and base wafer as individual wafers prior to assembly in the wafer level package; Fig. 3: the individual assembly steps of the individual wafers to form an inventive, thin wafer assembly in a wafer level package with cavities etched free from the back under the pixels in the sensor wafer; Fig. 4: a design of a very thin thermal array chip in the WLP that does not require vias (TSVs); Fig. 5: a design of a very thin thermal array chip in the WLP with cavities etched free on the front in the sensor wafer; Fig. 6: a particularly simplified design of a very thin thermopile array in a wafer level package with only two wafers; Fig. 7: a configuration of a very thin thermal array into a surface-mount package (SMD-capable package); Fig.Fig. 8: shows a further embodiment of a thermopile array with an additional base wafer containing further signal or image processing components; and Fig. 9: shows an embodiment of a very thin infrared array with a flipped mounting of the thermopile wafer.

[0058] It is understood that in the Fig. 1 bis 9 only a section of the different wafers is shown and that the wafers are actually much larger in area and each contain a large number of the described structures next to each other, which are separated into individual thermal infrared sensor arrays by sawing after completion.

[0059] Fig. 1 shows the basic structure of a very thin infrared sensor array in a vacuum wafer-level package with an upper cover wafer 1, a thinned central wafer 3, and a bottom wafer 4 after the respective wafer assembly, but before dicing. In the cover wafer 1, a cavity 10 is located above each group of sensor pixels 5.

[0060] The infrared sensor array contains Fig. 1 several groups of infrared sensor arrays with several sensor pixels 5, next to each other, or in groups of four or more in a regular distribution, wherein narrow strips 5' on the central wafer 3 without sensor pixels 5 are kept free between the groups and wherein a cavity 10 is located in the cover wafer 1 above each group of sensor pixels 5. The individual cavities 10 are separated from one another by webs 1', each of which is supported on a strip 5' and mechanically stabilizes the cover wafer 1.

[0061] For example, four groups of sensor pixels 5 can be arranged in quadrants distributed over the surface of the central wafer 3, so that the strips 5' intersect in a cross-shaped manner. The cavities 10 in the cover wafer 1 are then arranged accordingly, so that the webs 1' also intersect in a cross-shaped manner and are supported on the strips 5' of the central wafer 3.

[0062] The maximum number of sensor pixels 5 or corresponding groups that can be realized on a central wafer 3 is only limited by the size of the sensor pixels 5 and the lateral dimensions of the wafer.

[0063] The cover wafer 1 with filter layers 2 is the thickest and, together with the webs 1' supported on the strips 5', provides stability to the wafer assembly to be created. The central wafer 3 contains a plurality of thermal sensor pixels 5 and cavities 11 in the central wafer 3 below each sensor pixel 5, each of which is delimited by a membrane 5" that is connected to the surrounding central wafer 3. On each membrane 5" is an IR radiation absorber in the form of an umbrella 7 ( Fig. 2 ). The cavities 11 are bounded laterally by essentially vertical walls in the central wafer 3 and, as shown in the drawing, at the top by the membrane.

[0064] These explanations also apply to the embodiments described below in order to avoid repetition.

[0065] The base wafer 4, which is provided with a getter agent 14 introduced beneath each group of sensor pixels 5, was significantly thinned after assembly to typically <50...100 µm thickness. The sensor pixels 5, along with the cavities 10 and 11 that thermally insulate the sensor pixels 5, are hermetically sealed during sealing under a vacuum atmosphere. If necessary, the effects of outgassing on the stable vacuum are suppressed by igniting the getter agent 14.

[0066] For the transmission of the electrical signals generated by the pixels 5, contact pads 15 for wire bridges 17 are located on the bottom wafer 4 in the edge region outside the cover wafer 1.

[0067] In Fig. 2 A process for preparing the three sub-wafers (lid wafer 1, central wafer 3, bottom wafer 4) for wafer assembly (WLP) is shown.

[0068] In the first step, a silicon wafer polished on both sides ( Fig. 2a ), the later lid wafer 1, as described above, is provided with the cavities 10 ( Fig. 2b ) and then coated with anti-reflective or filter layers 2 on both sides Fig. 2c These filter layers 2 could also be applied to lenses of an optical system, which may be located above the cavities 10. However, the cost of the individual lenses is significantly higher than for filters in a wafer composite.

[0069] The sensor pixels 5 are generated on the central wafer 3, the sensor wafer ( Fig. 2d ) and preferably with additional three-dimensional absorber structures, the umbrellas 7 on the membranes 5'', to increase the fill factor on the sensor pixels 5 ( Fig. 2e ) in that the umbrellas 7 extend in area beyond the dimensions of the membranes 5" located underneath, without touching adjacent umbrellas 7.

[0070] On the top side of the base wafer 4, further CMOS structures 8 are integrated ( Fig. 2f ) and for each chip (ie for each group of sensor pixels 5) at least one cavity 13 in the bottom wafer 4 for the introduction of the getter 14 ( Fig. 2 g ). Since the fabrication of CMOS structures 8 is well known, it will not be discussed further here.

[0071] The CMOS structures 8 contain CMOS evaluation circuits and, if necessary, further circuits for signal processing up to image processors. The integration of an EEPROM is also particularly advantageous for later storing measurement and calibration values ​​of the individual sensor pixels 5 in the infrared sensor array itself. Furthermore, the central wafer 3 is preferably provided with vias 6 ( Fig. 7 ) are provided with electrical connections from the CMOS side to the underside of the wafer.

[0072] At a location below the future pixel area in the base wafer 4 or below each group of sensor pixels 5, a cavity 13 is preferably introduced using a conventional silicon wet or dry etching step, and the getter agent 14 is deposited in this cavity to create a long-term stable vacuum. This area can be small and located both below and next to the pixels, but must be connected to the front side of the central wafer 3 via one or more etched holes in the membrane 5".

[0073] The assembly of the three individual wafers to form a complete wafer stack in a first embodiment shows Fig. 3 , with the assembly steps of the three individual wafers to form a thin wafer composite in the wafer level package with cavities 11 etched from the back in the central wafer 3 under the sensor pixels 5.

[0074] The lid wafer 1 and the central thermopile wafer, ie the central wafer 3 ( Fig. 3a ), are joined together to form a solid composite ( Fig. 3c ), e.g., by wafer bonding or gluing. This is followed by the thinning of the sensor wafer 3 ( Fig. 3d ) from the back or bottom side and a deep etching step into the sensor wafer 3 ( Fig. 3e ) for producing a cavity 11 under each pixel 5, as well as the adjustment and mounting of the bottom wafer 4 on the central wafer 3 ( Fig. 3f ). Finally, the bottom wafer 4 is thinned ( Fig. 3g ) also from the back, as well as the electrical contact ( Fig. 3h ) of the finished sandwich arrangement with a wiring carrier by wire bridges 17, or alternatively via vias 6 between the sensor pixels 5 ( Fig. 7 ).

[0075] Although other thermal sensor methods, such as pyroelectric or bolometric sensor pixels, are also possible, the sensor principle is described below using the example of a thermopile pixel, the construction of which is basically known.

[0076] For the sake of completeness, however, it should be mentioned that the Umbrellas 7 on the 5'' membranes, in contrast to Fig. 1 suspended above the cavities 11 by means of narrow beams 11', as can be seen from Fig. 9g It can be seen that slits 11'' are formed between the beams 11' and the membrane 5" as well as between the beams 11' and the edge of the central wafer 3 surrounding the cavities 11 on the sides for thermal insulation. In thermopile pixels, thermophilic structures extend over the beams 11', the "hot" contacts of which are located on the membrane 5" and the "cold" contacts of which are on the edge surrounding the cavities 11, which acts as a heat sink.

[0077] It should also be mentioned that this special variant is created by joining the flipped later bottom wafer 4 on the thermopile wafer, whereby the underside of the membrane 5'' of the flipped wafer assembly ( Fig. 9f, g ) have been applied.

[0078] During assembly, in the first main step, the lid wafer 1 with the cavities 10 and the applied filter layers 2 are positioned opposite the central wafer 3 ( Fig. 3b ) so that the sensitive sensor pixels 5 with the corresponding absorber layers located thereon (e.g. umbrellas 7 above the membranes 5'') can protrude into the cavity of the cover wafer 10.

[0079] The alignment of the three wafers can be carried out via dry or wet etched structures in the cover wafer 1, for example using a suitable infrared microscope.

[0080] Both wafers (lid wafer 1 and central wafer 3) are mechanically firmly and hermetically sealed together ( Fig. 3c This is achieved using well-known eutectic wafer bonding processes (e.g., anodic bonding, soldering, or melting of glass frit, adhesive bonding, or welding). Although the glass frit process is preferred due to its popularity, the eutectic bonding process, particularly the SLID process utilizing liquid-solid phase diffusion, also offers significant advantages. The bonding temperature is sometimes well below 400°C and is therefore fully CMOS compatible. The materials must, of course, be carefully selected according to the required CMOS compatibility.

[0081] During bonding, a liquid eutectic forms at the interface between the two wafers. During the cooling process, a bonded connection is formed between the wafers. This bonded connection not only ensures excellent hermetic sealing, but also ensures the stability of the resulting stack, which is beneficial for the subsequent process steps.

[0082] Subsequently, the back side of the central wafer 3 is thinned (e.g. by mechanical processes such as grinding and polishing), see Fig. 3d The remaining thickness of the central wafer 3 or the wafer with the sensor pixels 5 should not be more than 200 µm, but preferably <20...50 µm, before the membranes 5" under the sensor pixels 5 are etched free from the back, e.g. by dry etching (DRIE), and thereby the heat-insulating cavities 11 (see Fig. 3 e) This can also cause the through-contacts 6 (so-called vias 6 - see e.g. in Fig. 5 , 7 or 8 ), from the central wafer 3 to the base wafer 4 with the other components of the CMOS signal processing 8. The through-contacts 6 can also be manufactured with significantly smaller lateral dimensions and more precisely due to the significantly thinned central wafer(s) 3.

[0083] The thinning before the DRIE etching process and the production of the vias 6 has several important functions in the sense of the invention: The thickness of the central wafer 3, typically 400-500 µm, can be reduced to very thin substrate thicknesses of <200 µm and preferably <20...50 µm, which reduces the thickness of the overall structure. The very thin remaining substrate of the central wafer 3 can be etched through much more precisely using DRIE etching because, as the wafer thickness decreases, the tolerances during the etching process (so-called tilt) naturally have little or no influence on the transfer accuracy of the etching mask used for etching. Using DRIE, the etching mask is transferred to the side facing the upper cover wafer 1 with very high precision, enabling very small pixel structures. The lateral size of the vias 6 can be significantly reduced due to the very thin central wafer 3. The DRIE etching process (usually implemented as a single-wafer process) is faster and therefore significantly more cost-effective due to the shallow etching depth..

[0084] In the next assembly step, the bottom wafer 4 with the CMOS circuit 8 on the front side and the cavities 13 for the getter agent 14 in front is aligned to the two upper wafers (lid wafer 1 and central wafer 3) that have already been mounted on one another ( Fig. 3f ) and mechanically bonded by wafer bonding. This bottom wafer 4 is then thinned on the bulk side (back side) ( Fig. 3g ), and the possibly required or existing electrical vias 6 (so-called through-silicon vias, TSV) 6 are formed and contacted.

[0085] To achieve the highest possible temperature resolution, the central wafer 3 should be hermetically sealed in a vacuum atmosphere. This can already be achieved with a standard wafer-level package.

[0086] While an additional getter agent is not absolutely necessary, it has been shown that an incorporated getter agent 14, preferably activated by thermal stimulation (heating) during or after wafer bonding, supports a long-term stable vacuum. Electrically activated getter agents 14 are also possible; for this, appropriate leads must be introduced into the bottom wafer 4.

[0087] In principle, the getter agent can also be used in the lid wafer 1 (see Fig. 6a ) or at the edge of the central wafer 3 next to the sensor pixels 5. However, since the central wafer 3 must have functional holes (through slots 11" in the membrane 5" and holes in the substrate), the most elegant and preferred method is to accommodate the getter agent 14 in the bottom wafer 4 below the sensor pixels 5. This is because the arrangement of the slots 11" and holes in the central wafer 3 easily allows gas exchange from the top to the bottom.

[0088] In a final step, the sandwich of the joined and thinned three wafers is separated into individual separate array chips on a (in Fig. 3h ) not shown) wiring carrier and electrically contacted, for example, via wire bond bridges 17 ( Fig. 3h ). Such a wiring carrier can be a printed circuit board (PCB, e.g. the circuit board in a mobile phone), a metal housing, or a so-called QFN housing with a very thin base.

[0089] As a result, the overall composite of individual wafers cannot be significantly thicker than a single wafer, according to the invention. Because as a combined composite of, for example, only 500 µm thick, it is easy to handle (process, measure, and transport) and divide into individual chips.

[0090] A particularly easy-to-manufacture design of the thermopile array does not require any TSVs (vias) and is available in Fig. 4 shown.

[0091] The first four steps are carried out as in Fig. 3 a - d. Here the procedure is shortened to Fig. 4a and b are summarized.

[0092] This is followed by the backside etching step ( Fig. 4c ) in which the cavities 11 for thermal insulation of the overlying membranes for the sensor pixels 5 are created, whereby no through-holes are prepared. The bottom wafer 4 is prepared with cavities 13 for the getter agent 14, and this is introduced ( Fig. 4d ) and connected to the two upper wafers already mounted on top of each other and thinned ( Fig. 4e ). On the top side of the central wafer 3 with the sensor pixels 5 and the CMOS signal processing 8, conventional bond pads 15 are applied to the outer edge of each chip.

[0093] These are exposed, for example, by sawing into the wafer assembly from above with a wider saw blade, before the assembly is cut into individual chips with a thin saw blade. After exposing the bond pads 15 and before separating the wafer stack, the thermopile arrays can be tested for their functionality in the wafer assembly using standard automatic wafer testers.

[0094] In the last step ( Fig. 4f ), the separated thermopile sensor array chip consisting of three sub-wafers is electrically connected to external components using standard wire bonding techniques with wire bridges 17. Using these wire bridges 17 and a simple adhesive or solder connection, the entire array chip can be mounted, e.g., as a chip-on-board on a printed circuit board, in a ceramic or metal package, or, particularly preferably, in a so-called QFN package with a very thin base to maintain the advantage of the flat package.

[0095] The basic principle of the very thin wafer level package for thermal sensors with particularly small sensor pixels 5 can also be designed for the variant in which the cavities 10, 11 for thermal insulation of the sensor pixels 5 are not etched from below through the central wafer, but are introduced from above using known sacrificial layer technologies (so-called surface micromachining).

[0096] Such a variant is in Fig. 5 , in which the design of the high-resolution thermal sensor in the vacuum wafer level package (WLP) with three wafers is shown and in which the etching out of the cavity 16 for the thermal insulation of the sensor pixels 5 from above the central wafer 3 is carried out by known sacrificial layer technologies.

[0097] In this case, the central wafer 3 with the thermally sensitive sensor pixels 5 ( Fig. 5b ) using sacrificial layer technology known per se, a cavity 16 is created beneath each sensor pixel 5 through slits 11" in the membrane 5". This can be achieved, for example, using sacrificial layers known per se (such as porous silicon), or as oxide using SOI technology, or by anisotropic wet etching of the bulk silicon beneath the membrane of the sensor pixel 5. The dissolved materials are guided outward through the slits 11" in the membrane 5".

[0098] The resulting cavities 16 under each sensor pixel 5 ensure that the slotted membrane 5" with the infrared-sensitive functional layers of the sensor pixels 5 is thermally insulated from the silicon substrate (central wafer 3) and enables a high sensor signal under the subsequent vacuum atmosphere.

[0099] If, among other things, the anisotropic etching process is used, a small etching depth of only a few 10 µm is achieved for very small pixels (e.g. < 50 µm), so that the central wafer 3 can be thinned accordingly without the cavity 16 being etched through to the underside of the central wafer 3, which would prevent a vacuum seal.

[0100] During assembly, the central wafer 3 ( Fig. 5b ) with the lid wafer 1 ( Fig. 5a ) firmly connected by wafer bonding ( Fig. 5c ) and then thinned to a small thickness ( Fig. 5d ). As in the previous embodiment in Fig. 3 Electrical vias 6 (TSVs) are provided between the front and back of the central wafer 3 with the sensor pixels 5 or the first stages of the signal processing channels 8 integrated on the central wafer 3 ( Fig. 5e ). In addition, preferably at least one hole should be etched through the central wafer (not shown), or one or more cavities 16 should be etched anisotropically through the entire wafer, or the wafer should be thinned to such an extent that the cavities 16 are exposed so that the gettering agent 14 in the cavity 13 of the bottom wafer 4 ( Fig. 5f ) can ensure a stable vacuum in the cavities 10, 16 below and above the sensor pixels 5.

[0101] In principle, the gettering agent can also be used in the cavity of the cover wafer 10 with the filter layers (see Fig. 6a ), however, there is more space in the bottom wafer 4 and there are also fewer disturbing effects for the sensor pixels 5 and the filter layers when activating the getter agent 14.

[0102] The base wafer 4 with the further CMOS signal processing components 8 is mechanically firmly and hermetically connected to the cover wafer 1 and the central wafer 3 by conventional wafer bonding ( Fig. 5g ) and thinned to a small thickness, so that this WLP triple composite can also be very thin (< 0.5 to < 1.0 mm).

[0103] As a special form (deviating from all other solutions with three or more wafers in the composite), there is a particularly simple design for a thermopile array with cavities 16 etched from above, which are Fig. 6 is shown.

[0104] Fig. 6 shows a design of the high-resolution thermal sensor in a vacuum wafer level package with only two wafers, the cover wafer 1 and the central wafer 3, in which the cavity 16 for thermal insulation of the sensor pixels 5 is etched out from above the central wafer 3 using known sacrificial layer technologies.

[0105] The first steps are equivalent to the variant according to Fig. 5 In contrast to the solution in Fig. 5 requires the Fig. 6 However, the design shown does not have any vias 6 or a base wafer 4.

[0106] In this case, a getter agent 14 must be introduced as far as possible at the outermost edge of the cavity 10 of the cover wafer 1 next to the filter layer 2 opposite the sensor pixels 5 ( Fig. 6a ) so that the viewing angle of the sensor array is not restricted.

[0107] After the wafer-to-wafer bonding of the cover wafer 1 and the central wafer 3 with the cavities 16 under the sensor pixels 5, the (central) wafer 3 with the pixels 5 is thinned in the composite ( Fig. 6b ) and via bond pads 15 at the chip edge and contact bridges 17, electrical contacts are made to an electronics outside the array chip ( Fig. 6c ). It is understood that a plurality of bond pads 15 with wire bridges 17 may be required for this purpose.

[0108] Even though this two-wafer solution according to the invention appears very simple, certain disadvantages compared to all other solutions according to the invention with three or more wafers should be pointed out: The integration density is significantly lower than in the previous solutions, since no signal processing can be "outsourced" to the bottom wafer, which is not present here, and the gettering agent 14 must be accommodated in the cavity 10 of the lid wafer 1 next to the filter layer 2. While the final thickness of the array after thinning the (central) wafer 3 can be very small (this task is fulfilled by the solution in Fig. 6 ), the lateral dimension of the (central) wafer 3 must be larger to accommodate the complete pixel-side signal processing. This increases the external dimensions of the array chip, or fewer sensor pixels 5 can be accommodated on a chip of the same size. Due to the lower degree of integration, there are consequently losses in temperature resolution and / or spatial resolution (minimum pixel size) compared to the previous solutions, even with the same size.

[0109] In this variant, it is recommended to thin the thickness of the central wafer 3 less, or to leave it at a similar thickness to that of the cavity 10 of the lid wafer 1. This will result in fewer problems with the deflection of the lid wafer 1 and the central wafer 3 chips due to the vacuum inside.

[0110] In a further embodiment, the particularly flat "sandwich" made of three wafers can be designed in such a way that it becomes "surface mountable" (SMD-capable) (see Fig. 7 ).

[0111] Both the sensor chip in the central wafer 3 and the bottom wafer 4 must be equipped with known vias 6, 18 (TSV vias) ( Fig. 7a ).

[0112] Such vias 6, 18 can have lateral dimensions of just a few µm in the current state of the art. This requires very thin wafers. This allows them to be accommodated both in the corner area of ​​the individual sensor pixels 5 (which can lead to the relocation of the entire pixel-side signal processing 8 to the bottom wafer 4) and in the edge area of ​​the central wafer 3 next to the pixel array (focal plane), in order to place part of the signal processing 8 into the bottom wafer 4.

[0113] The vias 6 each terminate with contact pads not shown separately, so that vias 18 (electrical contacts) through the bottom wafer 4 between the two wafers are possible after assembly.

[0114] The back side of the base wafer 4 receives solder bumps 9, which are placed on the vias 18 of the thinned base wafer 4 after thinning ( Fig. 7b ).

[0115] To achieve surface mountability, the bottom wafer contains 4 Vias 18 (TSVs) with a particularly small diameter from the surface with the CMOS structures 8 to the underside of the central wafer 3 and the bottom wafer 4, from where the contacts for the interface to external components for further signal processing or for the power supply are led out; solder bumps 9 on the lower ends of the vias 18 to mechanically and electrically connect the sensor chip (central wafer 3) to an underlying wiring carrier (e.g., a printed circuit board - not shown).

[0116] However, several special features must be observed when assembling the three wafers: The wafers must be aligned very precisely to each other, which can be achieved, for example, by etching holes in the lid wafer 1 using dry-etching technology (DRIE) or similar etching processes, which allow for the comparison of alignment marks. An infrared alignment method is also suitable for this purpose, because the silicon wafers are transparent to IR radiation.

[0117] An alignment hole or several asymmetric holes or notches in the corners of the upper lid wafer 1 (filter wafer) can contribute to the precise, position-oriented assembly of the wafer stack during the SMD process.

[0118] In a special embodiment, vias 6 are introduced in the corners of each sensor pixel 5 in the central wafer 3 to the underlying base wafer 4 on which the CMOS signal processing takes place.

[0119] In a further special embodiment, another base wafer 19 (CMOS wafer) can be mounted under the base wafer 4 with the sensor-side (analog / digital) signal processing (see Fig. 8 This additional base wafer 19 can contain additional image processing functions, e.g., an image processor, large data memories, or other digital computing units. This allows the sensor chip to perform even more image processing functions while maintaining the same external dimensions (length / width) and being only slightly thicker.

[0120] For this purpose, the wafer stack is pre-assembled with the original bottom wafer 4 ( Fig. 8a ) and thinned as previously described. After the contact formation, however, no solder bumps are applied to the bottom wafer 4, but only contact pads 20, which enable the subsequent electrical connection to the additional bottom wafer 19 ( Fig. 8b ). Thereafter, the additional bottom wafer 19 with additional signal processing components 22, such as image processors or larger digital image memories, is aligned with the upper wafers, and the through-contacts 21 matching the bottom wafer 4 are formed in the second bottom wafer 19, and corresponding vias are prepared for the final electrical contacting of the entire assembly of the wafer stack via contact bumps 9' at the lower end of the intermediate connections 21 ( Fig. 8e ).

[0121] The upper wafers and the additional bottom wafer 19 are mechanically firmly connected to the bottom wafer 4 by conventional wafer bonding methods, and a contact is formed (electrical interconnection) between the wafer sides lying on top of each other ( Fig. 8d ).

[0122] In the last process steps, the thinning of the additional base wafer 19 and the subsequent formation of the contact bumps 9 for the SMD assembly (e.g. solder, conductive adhesives or the like) takes place see Fig. 8e ).

[0123] After thinning, the resulting 4-way wafer stack can have a total thickness of < 0.5...< 1 mm, because the lid wafer 1 (filter wafer) remains the thickest, while the three wafers arranged underneath can each be thinned to < 100 µm as a whole, as long as the wafer stack as a whole has sufficient mechanical stability for wafer handling.

[0124] In Fig. 9 A further design of the thermopile array in the wafer level package is shown, which also works without TSV. In contrast to Fig. 4 , which also works without TSV, however, due to the flipped assembly, a direct electrical contact is possible via the respective contact pads 25 of the central wafer 3 and the contact pads 24 of the bottom wafer 4 with integrated further image processing ( Fig. 9a, g This even makes it possible to completely integrate the evaluation electronics on the base wafer 4 and free up space for more sensor pixels 5. The pixel density can thus be increased even further.

[0125] Fig. 9 shows a thermopile array in the wafer level package with a flipped, very thinned central wafer 3, without vias (through holes) ( Fig. 9a-f) und Fig. 9g an enlarged detail with an Umbrella 7 on the diaphragm 5".

[0126] This is a particularly cost-effective variant. The bottom wafer 4 is positioned with its front side on the front side of the central wafer 3. Both front sides, with the respective contact pads and a solder paste or similar means for establishing an electrical contact (not shown), are aligned with each other. Then, the bottom wafer 4, with the contact pads 24 on the bottom wafer 4, is aligned directly with the contact pads 25 on the central wafer 3 ( Fig. 9a ). Both wafers are then mechanically bonded together using standard wafer bonding methods and the central wafer 3 is then thinned considerably, ideally to < 15µm ( Fig. 9b ).

[0127] Subsequently, the cavities 11 for the pixels are driven in using DRIE and the three-dimensional absorber structure, i.e. the umbrellas 7, is inserted into them. ( Fig. 9c ). The cover wafer 1 is thinned and the cavities and filter layers are inserted ( Fig. 9d ). The lid wafer 1 is then mechanically bonded to the wafer composite consisting of the base wafer 4 and the central wafer 3 using conventional wafer bonding methods ( Fig. 9e ).

[0128] The entire wafer assembly consisting of the three wafers is then flipped so that the bottom wafer 4 is now at the bottom. ( Fig. 9f ). The chip can now be placed and glued onto a suitable substrate and electrically contacted with an underlying substrate (not shown) by means of wire bond bridges 17.

[0129] The application of solder bumps mentioned in previous embodiments is also possible to attach the chip to underlying substrates such as a printed circuit board (PCB) or similar. The wire bond bridges 17 are omitted in this case.

[0130] Due to this method, no vias are required, since the CMOS electronics on the bottom and central wafer 4, 3 are contacted directly via the respective contact pads 24, 25.

[0131] For illustration purposes, Fig. 9g A section of a pixel area is shown. The umbrella 7 is located on the membrane 5" in the cavity 11 of the sensor pixel 5 (in contrast to the previous versions). The contact pad 24 of the bottom wafer 4 is electrically connected to the contact pad 25 of the central wafer 25. The signal processing 8 (CMOS processing) is located on the bottom wafer 4.

[0132] For the sake of completeness, it should be mentioned that, in principle, additional thin wafers can also be added to the wafer stack. Energy-efficient semiconductor technology, especially for the signal processing and microprocessor circuits on the lower wafers, is desirable so that the overall power dissipation does not have a significant impact on the so-called heat shock problem of the thermally sensitive wafer. Excessive power dissipation in the wafer stack leads to long transient responses after power-up and measurement errors.

[0133] The Fig. 3 - 9 The described embodiments with cavities 11, 16 which are etched from the front or from the back, for assembly by wire bonding in COB technology in QFN packages or automatic assembly via SMD as well as the use of further base wafers 19 with additional signal processing components can of course be combined with one another as desired.

[0134] All of the described embodiments solve the problem of constructing a particularly flat, vacuum-tight and mechanically stable thermopile array.

[0135] In addition, the examples of implementation - except for the simplified variants in Fig. 4 and Fig. 6 - two major advantages over the state of the art: On the one hand, almost the entire area of ​​the central wafer 3 can be used for the sensor pixels 5 themselves, while the considerable area also required for the signal processing channels 8 is arranged on the underlying bottom wafer 4. This achieves the smallest possible dimensions of the sensor sandwich, which in turn is an advantage for small IR camera modules in so-called "mobile devices" (such as smartphones) that achieve a particularly high degree of integration or high packing density. On the other hand, the central wafer 3 with the sensor pixels 5 can be manufactured using a technology specifically tailored to thermopile structures, while the (or other) bottom wafers 4, 19 can be manufactured using a "mixed-signal" CMOS technology that does not need to integrate or take special thermopile structures into account.

[0136] After Fig. 9 Due to the flipped assembly, it is even possible to accommodate the entire signal processing on the lower base wafer 19

[0137] The second task of a particularly high-resolution thermopile array (spatial and thermal) is solved by three inventive measures: The central wafer 3 has, especially in the solutions with cavity 11 etched from the back of the wafer (i.e. after Fig. 3 , 4 , 7 and 8 , 9) after thinning to such a small residual thickness that it is possible to construct much smaller thermopile pixels than previously known. This means that the Si edges of the sensor pixels 5 remaining after DRIE etching around the cavities 11 (which serve as thermal isolation and a heat sink for the cold contacts) can be reduced to a few micrometers. This makes the remaining membrane size larger in relation to the pixel dimensions, and smaller pixels become possible (e.g., < 25...50 µm). The signal electronics (ROIC) are preferably accommodated on the bottom wafer 4, 19 via very small vias 6 (with a small diameter). There is more space there than next to the thermopile array on the central wafer 3. Ideally, almost the entire chip area can be used for the focal plane array. ( Fig.9 ) If the bottom wafer 4 (or as in Fig. 5 , 7 and 8An additional bottom wafer (19) with almost the entire chip area usable for the signal processing channels (SPCs) allows for a high-resolution array to have fewer sensor pixels (5) sharing a signal processing channel, or more area remains for individual preamplifiers. While a larger number of SPCs operating in parallel reduces the noise bandwidth, the preamplifier noise decreases with a larger area. Both measures reduce noise and improve the noise-limited temperature resolution (NETD) of the pixels.

[0138] The functionality is briefly explained using a thermal array sensor with thermopile pixels. In principle, the following also applies to other thermal sensor principles, such as pyroelectric sensors or microbolometers.

[0139] The thermopile structures are integrated in a known manner on a silicon chip manufactured on a wafer (the central wafer 3 with the sensor pixels 5). A thermopile array contains a large number of individual sensor pixels 5, which are usually arranged in a matrix in rows and columns.

[0140] After the actual CMOS process, special CMOS-compatible microsystem technology processes lead to the production of the sensor pixels 5, which are located, for example, on a thin dielectric layer such as silicon dioxide, silicon nitride, silicon carbide or a combination thereof.

[0141] After the CMOS process of the central wafer 3, the MEMS process takes place. In the first phase of the MEMS process (before assembly with the cover wafer 1), the passivation layers above the thermocouples are thinned, and the slots 11" for thermal insulation of the beams 11' are driven from the wafer top side to the silicon bulk boundary. This is typically done using dry etching or similar anisotropic processes.

[0142] The central part of the 5" membrane is equipped with an infrared absorber layer ( Fig. 2d ). Preferably, three-dimensional umbrellas 7 (screen structures) are created for this purpose in order to give the sensor pixel 5 a particularly high degree of filling ( Fig. 2e ). Additional absorber layers can be applied to the Umbrellas 7 to further increase infrared sensitivity.

[0143] The further MEMS steps take place only after the assembly of cover wafer 1 and the central wafer ( Fig. 3a-c ) using known wafer bonding techniques.

[0144] The etching of the cavities 11 under the thermopile sensor pixels 5 ( Fig. 3e In all variants with an ideally back-etched cavity 11 under the pixels, etching is performed only after the central wafer 3 or the wafer with the sensor pixels 5 in the wafer composite with the cover wafer 1 has been thinned to a small thickness in order to increase the precision of the etching. In principle, however, etching at another location is also possible, especially if CMOS compatibility requirements of wafer factories permit it and safe wafer handling is guaranteed.

[0145] After thinning the central thermopile wafer 3 ( Fig. 3d ) the cavity 11 is driven into the already strongly (typically < 50...100 µm) thinned central wafer 3 from the rear side ( Fig. 3e ) by DRIE dry etching.

[0146] After the second MEMS phase, three self-supporting thin membranes 5'' are created on the front side of the central wafer, consisting of the above-mentioned dielectric layers and isolation slots 11'' for the webs (beams 11'). These membranes, in addition to thermal insulation for the sensitive IR pixels, also enable gas exchange (vacuum between the top and bottom of the sensor pixels and the effectiveness of the getter (e.g. Fig. 3f und g ), as already described.

[0147] Hot contacts and the thermoelectric elements are located on the 5" membranes in the center of the thermopile sensor pixels. Between the area of ​​the hot contacts in the central part of the 5" membrane and the silicon well, the thermocouples are guided on beams 11' (narrow connecting elements). These beams are thermally insulated from the central part of the 5" membrane and the silicon well (the silicon material surrounding the cavity 11) by the slits 11" in the 5" membrane, thus reducing heat transfer from the hot contacts on the 5" membrane to the silicon well.

[0148] Semiconductor materials with a high Seebeck coefficient are suitable for thermocouples. Polysilicon, amorphous silicon layers, SiGe layers, as well as specially implanted layers with high thermoelectric coefficients (such as bismuth or antimony and their compounds) are possible.

[0149] The lid wafer 1 is preferably made of silicon, like all other wafers underneath, because then all wafers have the same thermal expansion coefficient, but in principle other materials, such as glass substrates or other organic and inorganic materials, are also possible in order to meet the requirements for the necessary optical properties (e.g. Ge or so-called chalcogenides).

[0150] The bottom wafer 4, 19 is preferably made of silicon, but can also be made of other materials such as glass—with the disadvantage of a lower degree of integration, because then no or far fewer signal processing functions can be integrated than is possible with silicon wafers. Likewise, the bottom wafer 4, 19 can be made of organic materials and, for example, contain organic electronics to simplify use on flexible carriers, such as in foldable smartphones.

[0151] The known processes and arrangements for the production and assembly of the individual wafers have deliberately been discussed only very briefly here, as they are already known.

[0152] The vacuum-filled wafer-level housing is understood as an evacuated wafer-level housing, or as a wafer-level housing in which a vacuum prevails. Bezugszeichenliste

[0153] 1 upper lid wafer 1 land 2 filter layer 3 central wafer 4 bottom wafer 5 sensor pixel 5 stripe 5 membrane 6 through-hole 7 umbrella (radiation collector) 8 CMOS signal processing channels 9 bump 9 bump 10 cavity in filter wafer 11 cavity 11 beam 11 slit 12 pixel with umbrella 13 cavity 14 getter agent 15 bond pad 16 cavity 17 wire bridge 18 through-hole 19 additional bottom wafer 20 contact pad 21 contact pad 22 signal processing 23 contact pad 24 contact pad 25 contact pad

Claims

1. Method for fabricating a high-resolution thermal infrared sensor array in a vacuum-filled wafer-level package with particularly small dimensions, which consists of at least two wafers, a cover wafer (1) and a central wafer (3) with a plurality of sensitive infrared-sensitive sensor pixels (5) with a size of < 50 µm each on a thin, slotted membrane (5'') above a heat-insulating cavity (11) in the central wafer (3), wherein the lid wafer (1) is provided on the inside with at least one cavity (10), the depth of which corresponds to some 10 µm to half the total thickness of the lid wafer (1) and is mechanically firmly connected to the prepared central wafer (3) with the infrared-sensitive pixels (5) by wafer bonding, whereby the central wafer (3) is subsequently thinned from the back of the wafer to a predetermined thickness of less than 200 µm, wherein depth etchings are made to produce one cavity (11) under each pixel (5) after thinning the central wafer (3), and wherein, after thinning the central wafer (3), at least one bottom wafer (4) is fixed to the back of the wafer by wafer bonding and then thinned.

2. Method according to claim 1, characterized in that the heat-insulating cavity (11) under the slit membrane (5'') of each infrared-sensitive sensor pixel (5) is etched into the central wafer (3) from the front side through the slits (11'') in the membrane (5'') after the central wafer (3) has been thinned to a predetermined thickness.

3. Method according to claim 1, characterized in that the heat-insulating cavity (11) under the membrane (5'') of each infrared-sensitive pixel (5) is etched into the central wafer (3) from the rear side after the central wafer (3) has been thinned to a predetermined thickness.

4. Method according to any of the preceding claims, characterized in that at least part of the signal preprocessing of the sensor pixels is integrated on the central wafer (3) in addition to the sensor pixels (5).

5. Method according to any of the preceding claims, characterized in that, after thinning, vertical interconnect accesses (6) with particularly small lateral dimensions are introduced into the central wafer (3) from the front side to the rear side of the central wafer (3).

6. Method according to any of the preceding claims, characterized in that the bottom wafer or wafers (4) are thinned to a thickness of less than 300 µm after wafer bonding.

7. Method according to any of the preceding claims, characterized in that the bottom wafer (4) is provided with a part of the signal processing of the sensor array.

8. Method according to any of the preceding claims, characterized in that the bottom wafer (4) is provided with vertical interconnect accesses (18) from the front side to the rear side.

9. Method according to any of the preceding claims, characterized in that the bottom wafer (4) lying at the bottom in each case is provided on its underside with metallizations which enable it to be SMD mounted by soldering, welding or gluing.

10. Method according to any of the preceding claims, characterized in that the bottom wafer (4) is provided with at least one cavity (10) into which a getter means (14) for stabilizing a vacuum is introduced, and in that this getter means (14), after its subsequent activation by a perforation in the sensor pixels (5) or at least one additional hole in the central wafer (3), ensures the hermeticity of a cavity (10) in the top wafer (1) above the sensor pixels (5).

11. Method according to any of the preceding claims, characterized in that at least one further bottom wafer (4') is arranged under the bottom wafer (4), which contains further signal processing components, image processors or chips for artificial intelligence.

12. Method according to any of the preceding claims, characterized in that the lid wafer (1) is made of an infrared-transmissive material, such as silicon, germanium, zinc sulphide, chalcogenide or a polymer.

13. Method according to any of the preceding claims, characterized in that infrared- transmissive anti-reflective or filter layers are applied to both sides of the cover wafer (1).

14. Method according to claim 13, characterized in that the infrared-transmissive anti-reflective layers are provided with a long-pass or band-pass coating in order to block predetermined wavelength ranges.

15. Method according to any of claims 5 to 14, characterized in that the vertical interconnect accesses (6) of the central wafer (3) are mechanically and electrically connected to the contact pads (20) on the front side of the bottom wafer (4) with vertical interconnect accesses (18) of the bottom wafer (4) and with vertical interconnect accesses (21) of an additional bottom wafer (19) and subsequently thinned, and in that the vertical interconnect accesses (21) in the additional bottom wafer (19) are provided with contact pads (9').