Method and circuit for compensating low-dropout voltage regulators

Description

BACKGROUND

[0001] Power management is an issue for circuits having several power supplies, especially when the circuits and power supplies are located on a single chip, such as a system-on-chip (SoC) circuit. Some of these circuits are powered by one or more DC-to-DC converters, which are followed by numerous low dropout regulators (LDOs), wherein each LDO is associated with a power domain. Sometimes, a single SoC circuit has multiple power domains. These power domains may include digital signal processing cores, several banks of memory circuits, analog units, Bluetooth radio, and audio units.

[0002] A load step on an LDO occurs when the load powered by an LDO changes. Maintaining the accuracy of voltages output by LDOs during load step conditions from no load to full load is important for proper operation of the power domains. One method of maintaining accuracy during a load step is by the inclusion of an external load capacitor coupled to each LDO. With so many LDOs on each circuit and the circuits becoming smaller, the use of an external load capacitor for each of the LDOs is not practical because of the size and costs of the external capacitors. US 2012 212199 A1 discloses a low drop out voltage regulator. US 6369618 B1 discloses a temperature and process independent exponential voltage-to-current converter circuit. US 2004 061554 A1 discloses a variable gain amplifier for use in communications.SUMMARY

[0003] The invention is defined by the features of the appended claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0004] FIG. 1 is a schematic diagram of a low dropout regulator (LDO). FIG. 2 is a schematic diagram of an LDO with a class AB input stage and without compensation. FIG. 3 is a block diagram of an LDO which is an illustrative example not forming part of the claimed invention that has compensation. FIG. 4 is a schematic diagram of an LDO which is an illustrative example not forming part of the claimed invention having a gain boost amplifier nested therein. FIG. 5 is a detailed schematic diagram of an LDO which is an illustrative example not forming part of the claimed invention with a gain boost amplifier nested therein. FIG. 6 is a flowchart describing a method of compensating a LDO. DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0005] In the drawings, like reference numerals designate similar or equivalent elements. Illustrated ordering of acts or events is not limiting, as some acts or events may occur in different order and / or concurrently with other acts or events. Furthermore, some illustrated acts or events may be optional to implement a methodology in accordance with example embodiments.

[0006] As circuits become more integrated, they have many different devices, components, and subcircuits that often operate independent of each other or at least partially independent of each other. As used herein, the term circuit can include a collection of active and / or passive elements that perform a circuit function, such as an analog circuit or control circuit. The term circuit can also include an integrated circuit where all the circuit elements are fabricated on a common substrate. These different systems usually require their own power source or power domain, with many systems requiring multiple power domains. Examples of these different systems include processors, memory devices, radio transmitters and receivers, and audio units. A circuit, such as an integrated circuit, may have several of these systems and may have inputs for only one or two input voltages. These input voltages are coupled to DC-to-DC converters that provide power to multiple low dropout regulators (LDOs), wherein each LDO provides power to each of the systems. In some cases, a single circuit may have as many as fifty LDOs.

[0007] An LDO converts and regulates a high input voltage to a lower output voltage. A dropout voltage is the amount of headroom required to maintain a regulated output voltage. Accordingly, the dropout voltage is the minimum voltage difference between the input voltage and the output voltage required to maintain regulation of the output voltage. The input voltage minus the voltage drop across a pass element within the LDO equals the output voltage. For example, a 3.3V regulator that has 1.0V of dropout requires the input voltage to be at least 4.3V. Another example application involving LDOs is for generating 3.3V from a 3.6V Li-Ion battery, which requires a much lower dropout voltage of less than 300mV.

[0008] FIG. 1 is a schematic diagram of an LDO 100. The LDO 100 has an input 102 that receives an input voltage V IN at the input 102 during operation of the LDO 100. An output 104 provides an output voltage V OUT present during operation of the LDO 100. A pass transistor Q PASS is coupled between the input 102 and the output 104. A pass voltage across the pass transistor Q PASS is the difference between the input voltage V IN and the output voltage V OUT . The minimum pass voltage for sustaining the operation of the LDO 100 is the dropout voltage.

[0009] A voltage divider 108 consisting of resistors R11 and R12 is coupled between the output 104 and a common node, which in the example of FIG. 1 is a ground node. A node N11 is located between resistors R11 and R12 and has a feedback voltage V FB present during operation of the LDO 100. A load capacitor C L is coupled between the output 104 and the ground node. The equivalent series resistance (ESR) of the load capacitor C L is depicted as resistor R ESR . A load resistance R L is also coupled between the output 104 and the ground node.

[0010] The gate of the pass transistor Q PASS is coupled to a pass capacitor C11 and the output of a differential amplifier 110. The differential amplifier 110 has a first input coupled to a reference voltage V REF and a second input coupled to node N11, which has the feedback voltage V FB present during operation of the LDO 100. The output of the differential amplifier 110 is proportional to the difference between the reference voltage V REF and the feedback voltage V FB and serves to drive the gate of the pass transistor Q PASS . If the feedback voltage V FB is less than the reference voltage V REF , the differential amplifier 110 drives the gate of the pass transistor Q PASS harder to increase the output voltage V OUT . Likewise, if the feedback voltage V FB is greater than the reference voltage V REF , the differential amplifier 110 reduces the drive on the gate of the pass transistor Q PASS , which lowers the output voltage V OUT .

[0011] Conventional LDOs, such as the LDO 100, require some minimum load capacitance C L and / or minimal ESR, noted as resistor R ESR , for stability / compensation. For example, when the LDO 100 undergoes a load step, meaning that a load coupled to the output 104 of the LDO 100 changes, transients with significant settling times can be generated. The trend with conventional LDOs is for lower quiescent current, such as quiescent currents limited to less than ten percent of the maximum load current. The maximum load current is the maximum current that may pass through the pass transistor Q PASS . These low quiescent currents, along with other factors, cause the transient reaction time during a load step to be in the microsecond range, which is not acceptable in many applications. Larger load capacitance in the load capacitor C L reduces the transient settling time by improving the compensation of the LDO 100. However, due to limitations in silicon die area, on-chip load capacitors have low capacitance and result in longer transient settling times, which is not acceptable in many applications. Resolving this transient problem requires the use of bulky, off-chip load capacitors which increase board area and component count of the circuit in which the LDO 100 is located. Some LDOs have been developed that can operate with or without a load capacitance and have extremely fast reaction time in response to load steps. However, these fast responding LDOs have low gain for stability purposes, which has the drawback of low accuracy in their output voltages. Increasing the gain of these LDOs increases the accuracy of the output voltage, but it has the drawback of decreasing the stability, which leads to stability problems during load steps.

[0012] The LDOs described herein provide stability by way of compensation under load step conditions with high gain, which yields high accuracy. The high gain and stability is achieved without the addition of load or compensation capacitors. The LDOs provide different gains depending on the difference between the input and output voltages. A gain boost amplifier nested within the LDO serves to increase the DC accuracy of the LDO after the load step. Several different circuit schematic diagrams are described herein as examples of the LDOs. These schematic diagrams are not limiting, because variations of the circuits may perform the functions of the LDOs described herein.

[0013] FIG. 2 is a schematic diagram of an LDO 200 with a class AB input stage 204 and without compensation. The LDO 200 is an example of circuitry that may be coupled to the compensation circuits described herein. The LDO 200 has an input 206 that is coupled to an input voltage V IN during operation of the LDO 200. The LDO 200 generates and regulates an output voltage V OUT at an output 208 during operation of the LDO 200. A reference input 210 is coupled to a reference voltage V REF that exists during operation of the LDO 200. An error voltage V E (not shown in FIG. 2) is the difference between the reference voltage V REF and the output voltage V OUT . Transistors Q21 and Q22 form the input of an error amplifier 214 with the gate of transistor Q22 being coupled to the reference voltage V REF and the gate of transistor Q21 being coupled to the output 208. In some examples, the output voltage V OUT is coupled to the error amplifier 214 by way of a voltage divider (not shown), so the voltage received by the error amplifier 214 is proportional to the output voltage V OUT , but not equal to the output voltage V OUT . The error amplifier 214 has high input impedances as seen by the reference voltage V REF and the output voltage V OUT . The output of the error amplifier 214 is a differential voltage on the drains of transistors Q21 and Q22. The voltages on the drains of transistors Q21 and Q22 are referred to individually as VG1 and VG2. The gate of the pass transistor Q PASS is driven by the output of the error amplifier 214 by way of transistors Q23 and Q24 that form a portion of a second amplifier.

[0014] The outputs of the error amplifier 214 are coupled to the sources of transistors Q25 and Q26 that form a common gate amplifier. Accordingly, the voltages VG1 and VG2 exist at the sources of transistors Q25 and Q26 during operation of the LDO 200. The drains of transistors Q25 and Q26 are coupled to a node N21, which is coupled to a current source I21. Node N21 is also coupled to the gate of a transistor Q27, wherein the drain of transistor Q27 is coupled to the sources of transistors Q21 and Q22 in the error amplifier 214. The voltage on node N21 and the gate of transistor Q27 is a feedback voltage V FB . The source of transistor Q27 is coupled to a node, such as ground as shown in FIG. 2. The current flowing through transistor Q27 is the tail current I TAIL of the error amplifier 214. As used herein the term tail current I TAIL refers to the combined currents in the source terminals of the differential pair of transistors Q21 and Q22 in the error amplifier 214. Transistors Q23, Q24, Q28, and Q211 are symmetric current mirror loads for the LDO 200. Transistors Q213 and Q214 serve as current mirrors for transistors Q211 and Q24.

[0015] The gate of the pass transistor Q PASS is driven by the output of the error amplifier 214 by way of transistor Q24, which serves as a portion of a second amplifier described herein. A voltage at the gate of the pass transistor Q PASS changes the source-to-drain resistance of the pass transistor Q PASS . Transient conditions, such as those resulting from load steps on the output 208, are detected by monitoring the error voltage V E , which is the difference between the reference voltage V REF and output voltage V OUT . When the error voltage V E is negligible, the voltages VG1 and VG2 are substantially the same, which causes the current through transistors Q25 and Q26 to be substantially the same. Accordingly, the current through each of transistors Q25 and Q26 is half of the current generated by the current source I21. This sets the currents through the transistors Q21 and Q22 in the error amplifier 214 to be substantially equal. The error amplifier 214 operates in a quiescent state in these conditions. The voltages VG1 and VG2 set the currents in the error amplifier 214 by setting input stage currents.

[0016] When the error voltage V E rises, the voltages VG1 and VG2 differ. When the error voltage V E is greater than a predetermined value, the smaller voltage of VG1 and VG2 triggers a higher current in the corresponding transistors Q25 and Q26, which forces the feedback voltage V FB to increase. As a result, the error amplifier 214 leaves its quiescent state. This increase in the feedback voltage V FB increases the tail current I TAIL flowing through transistor Q27 in proportion to the error voltage V E . Thus, the tail current I TAIL in the error amplifier 214 increases in proportion to the error voltage V E , which provides for fast transient response. More specifically, this change in tail current I TAIL results in higher current drive in the input stage to move the gate of the pass transistor Q PASS faster during the load step, so as to minimize transients during the load step. Nonlinearity in the LDO 200 is provided by the combination of transistors Q28 / Q29 and Q23 / Q210 during these conditions. In some examples where the transistors have a ratio of four, an error voltage V E of 100mV has 1000x tail current increase.

[0017] FIG. 3 is a block diagram of an LDO 300 that has compensation nested therein and which is an illustrative example not forming part of the claimed invention. The block diagram of the LDO 300 includes passive components that may or may not be included in a final circuit of the LDO 300. Some of the passive components shown in FIG. 3 are representative of the input and output impedances of the amplifiers in the LDO 300. The LDO 300 has an amplifier 304 that includes the input stage 204 of the error amplifier 214 of FIG. 2. A second amplifier 310 includes the pass transistor Q PASS (not shown) and the associated components. The combination of the amplifiers 304 and 310 constitutes the LDO 200 of FIG. 2. Compensation is achieved by reducing the voltage gain of the input stage 204, depicted as the amplifier 304, by limiting the resistance of a resistor R31 as described herein. In some examples, the resistance R31 is the resistance coupled to the gate of the pass transistor Q PASS . Limiting the resistance of resistor R31 reduces the overall gain of the LDO 300, which results in low DC accuracy, but stabilizes the LDO 300. Recuperating the voltage gain of the LDO 300 includes nesting of the stages and boosting the gain of an existing, already stable, amplifier, such as the error amplifier 214 described hereinabove. Nesting of the amplifier stages is performed with the LDO 300 rather than cascading gain stages in series as is done in conventional applications. The nesting of the amplifiers in the LDO 300 is performed by a gain boost amplifier 314, which recuperates the gain for DC accuracy. The amplifier 314 tracks the voltage at its inputs and ensures that the voltage V OUT is equal to the voltage V REF to achieve DC accuracy.

[0018] FIG. 4 is a schematic diagram of an LDO 400 having a gain boost amplifier nested therein and which is an illustrative example not forming part of the claimed invention. The LDO 400 has many of the same components as the LDO 200 of FIG. 2 and has the same reference numerals applied to those components. The LDO 400 includes a gain boost amplifier 402 having an output coupled to the gate of a transistor Q41. Transistor Q41 is coupled between the sources of transistors Q213 and Q214 and the ground node. Accordingly, the current flow through transistors Q213 and Q214 is based on the output of the amplifier 402. The inputs of the amplifier 402 are coupled to the gate of transistor Q213 and the drain of transistor Q214, which is coupled to the gate of the pass transistor Q PASS . The gain boost amplifier 402 is a tracking amplifier that ensures its inputs always track each other. More specifically, the gain boost amplifier 402 ensures that the voltage at the gate of transistor Q213 and the voltage at the gate of the pass transistor Q PASS track each other. The tracking is achieved by regulating the drain current of transistor Q41, which is achieved by the drive provided to the gate of transistor Q41 by the output of the amplifier 402.

[0019] FIG. 5 is a schematic diagram of an example LDO 500 with the gain boost amplifier 402 nested therein and which is an illustrative example not forming part of the claimed invention. The LDO 500 includes the LDO 200 of FIG. 2 with the addition of the gain boost amplifier 402 of FIG. 4 that provides compensation and load stability. The LDO 500 includes substantially the same circuitry as the LDO 200 of FIG. 2 with the addition of the gain boost amplifier 402. Compensation in the LDO 500 is achieved by limiting the voltage gain of the error amplifier 214, which is accomplished by limiting the resistance at the gate of the pass transistor Q PASS .

[0020] As shown in FIG. 5, transistors Q51 and Q52 are biased by a fraction of the currents through transistors Q53 and Q54, which achieves the lower voltage gain in the error amplifier 214. If the voltage gain in the error amplifier 214 is small, the overall gain of the LDO 500 may not be sufficient for acceptable load regulation. Transistors Q41 and Q55-Q58 form the gain boosting amplifier. With this gain boosting amplifier, the voltages at the gates of the pass transistor Q PASS and transistor Q213 track each other.

[0021] In some examples, the gain boosting amplifier 402 is designed to be slowed by the use of resistor R51 and capacitor C51 so that it does not affect the stability of the LDO 500. For example, resistor R51 and capacitor C51 form a filter that slows the amplifier 402. In some examples, the filter is not included in the LDO 500.

[0022] FIG. 6 is a flowchart 600 describing a method of compensating an LDO. Step 602 of the flowchart 600 includes receiving a first voltage that is proportional to an output voltage of the LDO. Step 604 includes comparing the first voltage to a reference voltage using the error amplifier. Step 606 includes changing the gain of the error amplifier in response to comparing the first voltage to the reference voltage, wherein the change of gain provides gain boost to the output of the LDO. Step 608 includes changing the DC gain of the LDO in response to the comparing, wherein changing the gain reduces the difference between the first voltage and the reference voltage.

[0023] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

Claims

1. A low dropout regulator, LDO, (200), comprising: an input (206) to receive a voltage input (VIN) and an output (208) to provide an output voltage (Vout); an error amplifier (214) having an input including a first input transistor (Q21) and a second input transistor (Q22), a gate of the first input transistor (Q21) coupled to the output (208) of the LDO (200) and a gate of the second input transistor (Q22) coupled to a reference voltage (VREF), the error amplifier (214) operable to output a differential voltage proportional to the difference between the output voltage (VOUT) of the LDO (200) and the reference voltage (VREF), the differential voltage being provided between the drains of the first and second input transistors (Q21, Q22); third and fourth transistors (Q25, Q26), the drains of the second input transistor (Q22) and the first input transistor (Q21) being respectively coupled to the sources of the third and fourth transistors (Q25, Q26) that form a common gate amplifier, the gates of the third and fourth transistors (Q25, Q26) being coupled, the drains of the third and fourth transistors (Q25, Q26) being coupled to a node (N21); fifth, sixth, seventh and eighth transistors (Q211, Q28, Q210, Q29) having sources coupled to the voltage input (VIN), the fifth, sixth and eighth transistors (Q211, Q28, Q29) having gates being coupled, the gates of the fifth and sixth transistors (Q211, Q28) and the drains of the sixth and seventh transistors (Q28, Q210) being coupled to the drain of the second input transistor (Q22), the drain of the eighth transistor (Q29) being coupled to the drain of the first input transistor (Q21); a pass transistor (QPASS), a ninth transistor (Q23), a tenth transistor (Q24), the gates of the ninth and tenth transistors (Q23, Q24) being coupled to the gate of the seventh transistor (Q210) and to the drain terminal of the ninth transistor (Q23), the sources of the ninth and tenth transistors (Q23, Q24) being coupled to the voltage input (VIN); an eleventh transistor (Q27) having a gate coupled to the node (N21), the drain of the eleventh transistor (Q27) being coupled to the sources of the first and second input transistors (Q21, Q22), wherein the voltage on the node (N21) and the gate of the eleventh transistor (Q27) is a feedback voltage (VFB), wherein the node (N21) is coupled to a first terminal of a current source (I21) of the LDO (200), the current source (I21) having a second terminal coupled to a ground node, the source of the eleventh transistor (Q27) being coupled to the ground node; and twelfth and thirteenth transistors (Q213, Q214) having a respective gate coupled to each other and coupled to a drain of the twelfth transistor (Q213), the drain of the twelfth transistor (Q213) being coupled to the drain of the fifth transistor (Q211), a drain of the thirteenth transistor (Q214) being coupled to the gate of the pass transistor (QPASS), sources of the twelfth and thirteenth transistors (Q213, Q214) being respectively coupled to the ground node; the pass transistor (QPASS) having a drain and source coupled between the voltage input (VIN) to the LDO (200) and the output (VOUT) of the LDO (200), the gate of the pass transistor (QPASS) being coupled to the drain of the tenth transistor (Q24), the gate of the pass transistor (QPASS) being configured to be driven by the output of the error amplifier (214) by way of the ninth and tenth transistors (Q23, Q24).

2. The LDO of claim 1, wherein the error amplifier (214) comprises a differential amplifier having a tail current (ITAIL) and wherein the tail current (ITAIL) is set in response to the output of the error amplifier (214).

3. The LDO of claim 2, wherein the tail current (ITAIL) is increased in response to the error amplifier (214) indicating a difference between the output voltage (VOUT) at the output (208) of the LDO (200) and the reference voltage (VREF), and wherein the tail current (ITAIL) is decreased in response to the error amplifier (214) indicating the output voltage (VOUT) at the output (208) of the LDO (200) and the reference voltage (VREF) being substantially the same.

4. The LDO of claim 2, wherein the error amplifier (214) has a differential output coupled to the sources of the third and fourth transistors (Q25, Q26) of the common gate amplifier, wherein the tail current (ITAIL) is set in response to the output of the common gate amplifier.

5. The LDO of claim 1, the output of the common gate amplifier being coupled to the gate of the eleventh transistor (Q27) and is operable to control a tail current (ITAIL) of the error amplifier (214).

6. A method for compensating a low dropout regulator, LDO, (200), the LDO (200) having an input (206) to receive a voltage input (VIN) and an output (208) to provide an output voltage (Vout) and an error amplifier (214), the error amplifier (214) having an input including a first input transistor (Q21) and a second input transistor (Q22), a gate of the first input transistor (Q21) coupled to the output (208) of the LDO (200) and a gate of the second input transistor (Q22) coupled to a reference voltage (VREF), the LDO (200) further comprising third and fourth transistors (Q25, Q26), the drains of the second input transistor (Q22) and the first input transistor (Q21) being respectively coupled to the sources of the third and fourth transistors (Q25, Q26) that form a common gate amplifier, the gates of the third and fourth transistors (Q25, Q26) being coupled, the drains of the third and fourth transistors (Q25, Q26) being coupled to a node (N21), the LDO (200) further comprising fifth, sixth, seventh and eighth transistors (Q211, Q28, Q210, Q29) having sources coupled to the voltage input (VIN), the fifth, sixth and eighth transistors (Q211, Q28, Q29) having gates being coupled, the gates of the fifth and sixth transistors (Q211, Q28) and the drains of the sixth and seventh transistors (Q28, Q210) being coupled to the drain of the second input transistor (Q22), the drain of the eighth transistor (Q29) being coupled to the drain of the first input transistor (Q21), the LDO (200) further comprising a pass transistor (QPASS), a ninth transistor (Q23), a tenth transistor (Q24), the gates of the ninth and tenth transistors (Q23, Q24) being coupled to the gate of the seventh transistor (Q210) and to the drain terminal of the ninth transistor (Q23), the sources of the ninth and tenth transistors (Q23, Q24) being coupled to the voltage input (VIN), the LDO (200) further comprising an eleventh transistor (Q27) having a gate coupled to the node (N21), the drain of the eleventh transistor (Q27) being coupled to the sources of the first and second input transistors (Q21, Q22), wherein the voltage on the node (N21) and the gate of the eleventh transistor (Q27) is a feedback voltage (VFB), wherein the node (N21) is coupled to a first terminal of a current source (I21) of the LDO (200), the current source (121) having a second terminal coupled to a ground node, the source of the eleventh transistor (Q27) being coupled to the ground node; and the LDO (200) further comprising twelfth and thirteenth transistors (Q213, Q214) having a respective gate coupled to each other and coupled to a drain of the twelfth transistor (Q213), the drain of the twelfth transistor (Q213) being coupled to the drain of the fifth transistor (Q211), a drain of the thirteenth transistor (Q214) being coupled to the gate of the pass transistor (QPASS), sources of the twelfth and thirteenth transistors (Q213, Q214) being respectively coupled to the ground node; the method comprising: receiving a first voltage that is proportional to an output voltage (VOUT) of the LDO (200); comparing the first voltage to a reference voltage (VREF) using the error amplifier (214); outputting, by the error amplifier (214), a differential voltage proportional to the difference between the first voltage and the reference voltage (VREF), the differential voltage being provided between the drains of the first and second input transistors (Q21, Q22); and changing the gain of the error amplifier (214), by the error amplifier (214), in response to comparing the first voltage to the reference voltage (VREF), wherein the change of gain provides gain boost to the output (VOUT) of the LDO (200); wherein the pass transistor (QPASS) having a drain and a source coupled between the voltage input (VIN) and the output (VOUT) of the LDO (200), the gate of the pass transistor (QPASS) being coupled to the drain of the tenth transistor (Q24).

7. The method of claim 6, wherein the changing the gain of the LDO (200) reduces the difference between the first voltage and the reference voltage (VREF).

8. The method of claim 6, wherein the LDO (200) comprises the error amplifier (214) comprising a differential amplifier having inputs coupled to the reference voltage (VREF) and the first voltage, the differential amplifier operable to compare the first voltage to the reference voltage (VREF); wherein the differential amplifier has a tail current (ITAIL); wherein changing the gain of the error amplifier (214) comprises changing the tail current (ITAIL).

9. The method of claim 8, wherein changing the tail current (ITAIL) comprises: increasing the tail current (ITAIL) in response to the output voltage (VOUT) being different than the reference voltage (VREF); and decreasing the tail current (ITAIL) in response to the output voltage (VOUT) being substantially the same as the reference voltage (VREF).