ESD protection circuit and its manufacturing process

Description

Domain

[0001] This disclosure relates to electrostatic discharge protection circuits and methods of manufacturing them. Statement of Prior Art

[0002] Electrostatic discharge issues are increasingly prevalent today as components in electronic circuits become smaller and closer together. Protecting electronic circuits from electrostatic discharge is an important issue to ensure the reliability and longevity of these circuits.

[0003] There is therefore a continuing need for higher-performance ESD protection circuits. More specifically, there is a continuing need to improve the quality of protection to meet the increasing performance demands of high-speed applications.

[0004] US 2014 / 0319598 describes optimized configurations for integrating steering diodes into low capacitance transient voltage suppressors

[0005] Document EP 2 741 330 describes an ESD protection circuit.

[0006] US 2013 / 0075747 describes an ESD protection circuit using low leakage Zener diodes formed by microwave radiation.

[0007] Document US 2011 / 0163352 describes a multi-channel monolithic ESD protection device.

[0008] Document US 2018 / 00477718 describes a semiconductor structure of an ESD protection device and its manufacturing method. Summary

[0009] The invention relates to an ESD protection circuit as defined by claim 1, and a method of manufacturing the same as defined by claim 6.

[0010] Thus, one embodiment provides an ESD protection circuit comprising a terminal connected to the cathode of a first diode and to the anode of a second diode, the cathode of the second diode not being made of epitaxially grown silicon.

[0011] According to one embodiment, the circuit comprises a second terminal connected to the cathode of a third diode and to the anode of a fourth diode.

[0012] According to one embodiment, the cathode of the fourth diode is not made of epitaxially grown silicon.

[0013] According to one embodiment, the anode of the first diode is connected to the anode of a first avalanche diode and the anode of the third diode is connected to the anode of a second avalanche diode.

[0014] According to one embodiment, the cathodes of the second and fourth diodes and of the first and second avalanche diodes are connected to the same node.

[0015] According to one embodiment, the cathodes of the first and second avalanche diodes comprise N-doped epitaxial silicon.

[0016] According to one embodiment, the cathodes of the second and fourth diodes are made of solid silicon.

[0017] According to one embodiment, the anodes of the first, second, third and fourth diodes comprise P-doped epitaxial silicon.

[0018] Another embodiment provides a method of fabricating an ESD protection circuit comprising a terminal connected to the cathode of a first diode and the anode of a second diode, the cathode of the second diode not being made of epitaxially grown silicon.

[0019] According to one embodiment, the method comprises a step of etching cavities in a semiconductor substrate.

[0020] According to one embodiment, the substrate is N-doped silicon.

[0021] According to one embodiment, the substrate is solid silicon.

[0022] According to one embodiment, the method comprises a step of forming silicon epitaxy in the cavities.

[0023] According to one embodiment, the epitaxial silicon located in each cavity constitutes the cathode of an avalanche diode.

[0024] According to one embodiment, the method comprises forming a series diode and a parallel diode of each avalanche diode. Brief description of the drawings

[0025] These and other features and advantages will be set forth in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which: there figure 1 schematically illustrates an example of an electrostatic discharge protection circuit; and the figure 2is a sectional view illustrating one embodiment of the circuit of the figure 1 . Detailed description

[0026] The same elements have been designated by the same references in the various figures and, moreover, the various figures are not drawn to scale. For the sake of clarity, only the elements useful for understanding the embodiments described have been shown and are detailed. In particular, the systems in which the embodiments described can be used are not detailed.

[0027] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made to the orientation of the elements concerned in the figures. Unless otherwise specified, the expressions "approximately", "substantially", "about" and "of the order of" mean within 10%, preferably within 5%.

[0028] Unless otherwise specified, when referring to two elements connected together, this means that these elements are directly connected without any intermediate element other than conductors, and when referring to two elements connected or coupled together, this means that these two elements can be directly connected (connected) or connected through one or more other elements.

[0029] There figure 1 schematically illustrates an example of an electrostatic discharge protection circuit 10.

[0030] The circuit 10 comprises two terminals 12 and 14. One of the terminals 12 and 14 is for example connected to ground and the other to a contact pad, not shown, which is to be protected. The circuit 10 also comprises a central connection node 16.

[0031] Alternatively, the central node can be connected to ground and terminals 12 and 14 can be connected to contact pads not shown.

[0032] Terminal 12 is connected to node 16 by a diode 18a whose anode is connected to terminal 12 and whose cathode is connected to node 16. In addition, terminal 12 is connected to node 16 by a diode 20a in series with an avalanche diode 22a. More precisely, the cathode of diode 20a is connected to terminal 12 and its anode is connected to the anode of avalanche diode 22a. The cathode of avalanche diode 22a is connected to node 16. Diode 20a and avalanche diode 22a are therefore in parallel with diode 18a, between terminal 12 and node 16.

[0033] Similarly, terminal 14 is connected to node 16 by a diode 18b whose anode is connected to terminal 14 and whose cathode is connected to node 16. In addition, terminal 14 is connected to node 16 by a diode 20b in series with an avalanche diode 22b. More precisely, the cathode of diode 20b is connected to terminal 14 and its anode is connected to the anode of avalanche diode 22b. The cathode of avalanche diode 22b is connected to node 16. Diode 20 and avalanche diode 22b are therefore in parallel with diode 18b, between terminal 14 and node 16. Avalanche diodes 22a and 22b are for example Zener diodes.

[0034] For example, we consider that terminal 14 is connected to ground and that terminal 12 is connected to a contact pad.

[0035] A positive voltage spike at terminal 12 turns diode 18a on and, if the amplitude of the voltage spike is high enough to cause the avalanche phenomenon in diode 22b, then avalanche diode 22b and diode 20b. The spike is therefore dissipated to ground. A negative voltage spike at ground causes a similar phenomenon. The voltage spike turns diode 18b on and, if the amplitude of the voltage spike is high enough to cause the avalanche phenomenon in diode 22a, then avalanche diode 22a and diode 20a. The voltage spike is therefore dissipated by terminal 12. Circuit 10 is therefore bidirectional.

[0036] The choice of the thresholds of the avalanche diodes 22a and 22b makes it possible to choose from which amplitude the voltage peak must be dissipated.

[0037] There figure 2 is a sectional view illustrating an embodiment of the circuit 10 of the figure 1

[0038] Circuit 10 includes, from left to right in figure 2 , a zone 24 where the avalanche diode 22a is formed ( figure 1 ) and the 20a diode ( figure 1 ), a zone 26 where the diode 18a is formed ( figure 1 ), a zone 28 where the diode 18b is formed ( figure 1 ) and a zone 30 where the avalanche diode 22b is formed ( figure 1 ) and diode 20b ( figure 1 ).

[0039] The different zones are separated from each other and from neighboring components by insulating wells 32, for example N-doped wells.

[0040] The circuit 10 comprises a substrate 34 made of semiconductor material, for example silicon. The substrate 34 is N-doped (N+). The substrate 34 is for example made of solid silicon.

[0041] The substrate 34 contains regions 36 of epitaxially grown silicon. The epitaxially grown silicon of the regions 36 is N-doped. A region 38 of P-doped silicon (P+) is located in the upper part in each region 36.

[0042] Regions 36 and 38 extend into areas 24 and 30, for example over more than 90% of their widths. Regions 38 are separated from wells 32 by substrate portions 34 and / or region portions 36.

[0043] Regions 36 and 38 located in area 24 constitute the cathode and anode of avalanche diode 22a, respectively. Similarly, regions 36 and 38 located in area 30 constitute the cathode and anode of avalanche diode 22b, respectively.

[0044] The circuit 10 further comprises a layer 40 of P-doped epitaxial silicon. The layer 40 is located on the substrate 34 and on the regions 36 and 38. This layer 40 extends over the substrate, at least in the areas 24, 26, 28 and 30.

[0045] The zones 24 and 30 each comprise, in the upper part of the layer 40, a region 42 (42a in zone 24 and 42b in zone 30) of N-doped silicon (N+). The regions 42 correspond to the cathode of the diode 20a (zone 24) and the diode 20b (zone 30). The parts of the layer 40 located in the zones 24 and 30 constitute the anodes of the diode 20a (zone 24) and the diode 20b (zone 30). The contacts between the layer 40 and the regions 38 in the zones 24 and 30 form the electrical connections between the anodes of the diodes 20a and 20b and the anodes of the avalanche diodes 22a and 22b.

[0046] In areas 26 and 28, diodes 18a and 18b are formed by the N-doped substrate and the P-doped layer 40. Areas 26 and 28 each comprise, for example, in the upper part, a region 44 (44a in area 26 and 44b in area 28) of P-doped silicon (P+), more heavily doped than layer 40, so as to facilitate contact. The silicon of the substrate is, for example, solid silicon. The cathodes of diodes 18a and 18b therefore do not comprise epitaxially grown silicon.

[0047] The circuit further comprises a layer of insulator 50, for example made of thermal oxide. The layer 50 comprises openings exposing the regions 42 and 44. Layers 52 of conductive material, for example a metal, extend on the sides of portions of the layer 50 so as to electrically connect each region 42 to a region 44. More specifically, the region 42a of the area 24 is connected to the region 44a of the area 26 by a layer 52a and the region 42b of the area 30 is connected to the region 44b of the area 28 by a layer 52b.

[0048] Thus, substrate 34 constitutes node 16, regions 42 and 44 of zones 24 and 26 constitute, for example, terminal 12 and regions 42 and 44 of zones 28 and 30 constitute, for example, terminal 14.

[0049] The avalanche threshold values ​​of the avalanche diodes 22a and 22b depend on the depths and resistivities of the regions 36 of the zones 24 and 30. For example, the regions 36 of the zones 24 and 30 have a depth of between about 5 and about 10 μm, and have a resistivity greater than about 0.07 Ω.cm. The regions 36 may have substantially the same dimensions. The avalanche diodes 22a and 22b then have substantially the same avalanche threshold value. The regions 36 may also have different dimensions, more particularly a different depth. The avalanche thresholds of the avalanche diodes 22a and 22b are then different and independent of each other.

[0050] For example, we consider that terminal 12 ( figure 1 ), consisting of regions 42a and 44a and layer 52a, is connected to a contact pad not shown. For example, we consider that terminal 14 ( figure 1), consisting of regions 42b and 44b and layer 52b, is connected to ground. When a positive voltage peak occurs at terminal 12, for example when a user touches the contact pad not shown, the diode in area 26 (18a, figure 1 , consisting of the part of layer 40 in zone 26 and the substrate 34) becomes conductive. If the amplitude of the peak is sufficiently large to trigger the avalanche phenomenon of the avalanche diode in zone 30 (22b, figure 1 , consisting of regions 36 and 38 of zone 30), this avalanche diode as well as the diode of zone 30 (20b, figure 1 , consisting of region 42b and layer 40 of area 30) become conductive. The voltage peak is thus dissipated into the ground. Similarly, when a positive voltage peak occurs at terminal 14, the diode in area 28 (18b, figure 1, consisting of the part of layer 40 in zone 28 and the substrate 34) becomes conductive. If the amplitude of the peak is sufficiently large to trigger the avalanche phenomenon of the avalanche diode in zone 24 (22a, figure 1 , consisting of regions 36 and 38 of zone 24), this avalanche diode as well as the diode of zone 24 (20a, figure 1 , consisting of region 42a and layer 40 of zone 24) become conductive. The voltage peak is then dissipated by terminal 12.

[0051] An example of the circuit manufacturing process of the figure 2 comprises a step of forming first and second cavities at the locations where it is desired to form the regions 36. Silicon is formed by epitaxy in the cavities so as to form the regions 36. The dimensions, in particular the depth, of the first and second cavities may be substantially equal or different. The regions 38 are then formed in the regions 36.

[0052] The method further comprises steps of epitaxial formation of layer 40, formation of regions 42 and 44 in layer 40, formation of insulating wells 32 between the different zones, formation of layer 50 and formation of conductive layers 52. The method also comprises the steps of doping the different regions and layers.

[0053] It would have been possible to choose not to form a cavity and to form a silicon layer by epitaxy over the entire substrate 34. Zones 26 and 28 corresponding to diodes 18a and 18b would then have included a layer of N-doped epitaxial silicon, like zones 24 and 26. However, this layer of epitaxial silicon would lead to an increase in the dynamic resistance of diodes 18a and 18b which would therefore conduct less quickly and would degrade the quality of the circuit protection. In addition, it would then no longer be possible to choose the avalanche thresholds of avalanche diodes 22a and 22b independently of each other. In addition, diodes 18a and 18b would then be degraded and would be less fast.

[0054] Particular embodiments have been described. Various variations and modifications will be apparent to those skilled in the art. In particular, the described embodiments also apply to a unidirectional circuit comprising only one diode 18a or 18b, one diode 20a or 20b and one avalanche diode 22a or 22b.

[0055] In addition, the insulating wells 32 may be replaced by insulating trenches, for example made of silicon oxide or silicon nitride.

[0056] Furthermore, the conductivity types of the different parts described can be reversed.

[0057] Regions 36 and 38 then extend over the entire width of regions 24 and 30. Regions 36 and 38 may optionally extend outside the insulating trenches 32 delimiting zones 24 and 30. Regions 36 and 38 may optionally extend over a part, for example less than 30%, of zones 26 and 28. This makes it possible to retain in zones 24 and 30 only the most doped or least damaged parts of regions 36 and 38.

[0058] Alternatively, if it is desired to isolate the areas 26 and 28 from the portions of the regions 36 and 38 extending outside the areas 24 and 30, it is possible to form insulating trenches 32 between the areas 26 and 28 and the regions 36 and 38. The area between the areas 24 and 26 and that between the areas 28 and 30 are then covered by the insulating layer 50 and the conductive layer 52.

[0059] Various embodiments with various variations have been described above. It will be noted that a person skilled in the art will be able to combine various elements of these various embodiments and variations without demonstrating inventive step.

Claims

1. An ESD protection integrated circuit on semiconductor substrate comprising : a first layer (40), formed on the substrate in first (24) and third (30) areas, of which are defined the anode regions of first (20a) and third (20b) diodes; in an upper part of said first and third areas of the first layer, regions defining the cathodes of the first (20a) and third (20b) diodes; in an upper part of second (26) and fourth (28) areas of the first layer, regions (44a, 44b) defining the anodes of the second (18a) and fourth (18b) diodes; a first terminal (12) connected to the cathode (42a) of the first diode (20a) and to the anode (44a) of the second diode (18a), the cathode of the second diode not being made of epitaxial silicon; a second terminal (14) connected to the cathode (42b) of a third diode (20b) and to the anode (44b) of a fourth diode (18b), and wherein : the anode of the first diode is connected to the anode (38) of a first avalanche diode (22a) and the anode of the third diode is connected to the anode (38) of a second avalanche diode (22b), the cathodes (36, 34) of the second and fourth diodes and of the first and second avalanche diodes being connected to a same node (16) and the avalanche diodes being made of regions in the substrate (34).

2. The circuit of claim 1, wherein the cathode of the fourth diode is not made of epitaxial silicon.

3. The circuit of claim 1 or 2, wherein the cathodes of the first and second avalanche diodes comprise N doped epitaxial silicon.

4. The circuit of any of claims 1 to 3, wherein the cathodes of the second and fourth diodes are made of silicon bulk.

5. The circuit of any of claims 1 to 4, wherein the anodes of the first, second, third, and fourth diodes comprise P doped epitaxial silicon (40).

6. A method of manufacturing an ESD protection circuit according to any of claims 1 to 5, comprising a terminal (12) connected to the cathode (42a) of a first diode (20a) and to the anode (44a) of a second diode (18a), where the cathode of the second diode is not made of epitaxial silicon.

7. The method of claim 6, comprising a step of etching cavities in a semiconductor substrate.

8. The method of claim 7, wherein the substrate is N doped silicon.

9. The method of claim 6 or 7, wherein the substrate is solid silicon.

10. The method of any of claims 7 to 9, comprising a step of forming by epitaxy silicon in the cavities.

11. The method of claim 10, wherein the epitaxial silicon located in each cavity forms the cathode of an avalanche diode.

12. The method of claim 11, comprising forming a diode in series and a diode in parallel with each avalanche diode.