LOWER PERFORMANCE REFERENCE FOR AN ANALOGUE-TO-DIGITAL CONVERTER

Description

Field of the Disclosure

[0001] The disclosure relates to arrangements for providing a voltage reference that may be used as a reference signal in an analog to digital converter, for example a pipeline SAR analog to digital converter, the reference having lower power requirements than existing arrangements.Background

[0002] Analog to digital converters require accurate voltage references for accurate conversions to occur. Off-chip voltage reference sources are often used to provide temperature compensated voltage references, but circuitry is usually required on chip to isolate the accurate but slow settling off-chip reference from the dynamic loading of the ADC reference and to ensure that the ADC reference settles to sufficient accuracy during each conversion. As ADC conversion rates increase, and ADC architectures become more complicated to support higher conversion rates, the need to provide a settled and stable reference signal for each conversion becomes more challenging. US 10,218,268 B1 discloses a voltage reference circuit having a switched capacitor arrangement coupled to the output of an amplifier.Summary of the Disclosure

[0003] One approach is to use a fast, wide bandwidth on-chip amplifier to drive the reference input to the ADC to the same level as the external reference such that very little charge is then taken from the external reference, but the use of such an amplifier has trade-offs in terms of high power.

[0004] According to one aspect, there is provided an integrated voltage reference supply circuit for an analog-to-digital converter as defined in the appended independent claim 1. According to another aspect, there is provided a method of providing a voltage reference for an analog-to-digital converter as defined in appended independent claim 10. Further features according to embodiments are defined in the appended dependent claims.Brief description of the Drawings

[0005] Examples of the present disclosure will now be described with reference to the accompanying drawings, wherein like reference numerals refer to like parts, and wherein: - Figure 1 is a diagram of a pipeline SAR converter that forms the basis of examples of the present disclosure not covered by the scope of protection of the claims but useful for understanding the invention; Figure 2 is a diagram of a comparator circuit that can be used in place of the fast amplifier of Figure 1 in a first example of the present disclosure; Figure 3 is a circuit diagram of a circuit that may be used as the threshold adjust block of Figure 2 that may be used in the first example of the disclosure; Figure 4 is a circuit diagram of a comparator circuit that may be used in the first example; Figure 5 is a circuit diagram of a second comparator circuit that may be used in the first example, that permits programmable thresholds per bit trial; Figures 6 and 7 are diagrams that illustrate the effect of changing the comparator threshold; Figure 8 is a diagram that illustrates the operation of the first example; Figure 9 is a diagram that illustrates the operation of the first example when the threshold is not fully adjusted; Figure 10 is a diagram that illustrates the operation of the first example when the threshold is adjusted fully between bit trials; Figure 11 is a circuit diagram that illustrates how the capacitive loading of the internal reference may also be adjusted between bit trials; Figure 12 is a circuit diagram illustrating that the comparator may operate at a different, lower, voltage than the rest of the circuitry; Figure 13 is a circuit diagram of a second example of the present disclosure that uses a further capacitor connected to the internal reference, and a slower amplifier according to the invention as claimed; Figure 14 is a flow diagram illustrating the operation of the first example; Figure 15 is a circuit diagram of a third example of the present disclosure that uses a further capacitor connected to the internal reference, and a slower amplifier according to the invention as claimed; Figure 16 is a circuit diagram of a fourth example of the present disclosure, not covered by the scope of protection of the claims but useful for understanding the invention, that uses a different voltage reference (for example an on-chip reference) which is at a different level than a required level; and Figure 17 is a circuit diagram of a fifth example of the present disclosure that also uses a different voltage reference that is at a different voltage level than a required voltage level, according to the invention as claimed. Detailed Description

[0006] Analog to digital converters (ADCs) require accurate references for proper signal conversion. As the sample rates of ADCs increase then for some ADC architectures where the reference signal is not constant, the ability to provide a settled reference signal from an external temperature compensated reference circuit is challenged, as there is often insufficient time to switch in the external reference and have it settle to the proper reference value between conversions. This problem can be particularly exacerbated when using some pipeline SAR converter architectures, wherein low resolution conversion of a number of the most significant bits is used to generate the majority of the digital output, but very fast bit trials are then used to obtain accurate conversion for the least significant bits that define the overall conversion accuracy. In such converter architectures the reference voltage to the pipeline ADC is required to settle very quickly, and much more quickly than would be possible by supply of the reference directly from the external reference.

[0007] In order to allow for fast settling of the signal, our prior co-pending US patent application no. US15 / 916,009 describes how a fast amplifier may be used during the more significant and earlier bit trials to drive the internal reference to the same voltage as the external reference. During subsequent conversion of the less significant bits, the ADC reference is isolated from this fast buffer and instead driven directly by the external reference. Since the conversion of the less significant bits draws very little charge from the reference, the external reference is not significantly perturbed during this phase of the conversion and accurate conversion can be achieved. However, such an arrangement requires a complicated fast amplifier that takes up excessive chip space and consumes lots of power to operate. To reduce power consumption of the whole converter circuit it would be advantageous to replace this amplifier with an alternative, more power efficient arrangement.

[0008] The present disclosure describes two arrangements that address this issue. In the simplest arrangments according to the invention as claimed, shown in Figures 13, 15, or 16, a low-bandwidth and hence slow amplifier, stabilized by a necessarily large off-chip capacitor at its output, in the 100nF range, is used to replace the high power fast amplifier. The capacitor is connectable by a switch to the internal reference node that feeds the reference of the ADC. The capacitor is charged in use to substantially the same voltage as the external reference voltage, and is used to keep the internal reference substantially at the desired external reference voltage from bit-trial to bit-trial. The internal reference is switched from the capacitor to the external reference at the beginning of each residue generation phase. This provides a simple arrangement to ensure that the internal reference is kept substantially at or near the external reference from bit trial to bit trial and that very little perturbing charge is taken from the slow settling but accurate external reference.

[0009] In the second arrangment, not covered by the scope of protection of the claims but useful for understanding the invention, described in the other Figures, no additional capacitor is needed, and instead the high speed amplifier is replaced by a transistor switch between a supply voltage and the internal reference and a comparator. The comparator receives as one input the external reference, and as its other input the internal reference, and controls the transistor switch to bring the internal reference close to the external reference. The use of the comparator and transistor switch is more power efficient than the fast amplifier, but suffers from comparator delay, and potential overshoot which can limit the accuracy of this arrangement. In order to address these issues, a comparator threshold adjustment circuit is used to adjust the comparator threshold over a number of conversion cycles to reduce any errors between the comparator output providing the internal reference and the external reference. Usually the system is able to settle within 5 or 6 conversion cycles. The comparator threshold adjustment circuit acts to integrate the error between the internal reference and the external reference from cycle to cycle and adjusts the comparator threshold from cycle to cycle to try and drive the error to zero.

[0010] Figure 1 illustrates the pipeline successive approximation (SAR) converter architecture that forms the background of the present disclosure. Here, the ADC converter comprises analog to digital converter ADC1 that receives the signal to be converted from input node Vin. ADC1 performs a relatively low resolution conversion using an internal reference Vref2_internal, that is derived from the accurate external reference Vref via amplifier Amp2. Amp2 can be a slow, relatively inaccurate amplifier, as the conversion performed by ADC1 does not require a highly accurate reference input. ADC1 feeds its converted data to digital to analog converter DAC1, which also receives Vin. DAC1 outputs a residue signal to residue amplifier RA, which outputs an amplified residue signal to analog to digital converter ADC2 to complete the conversion. The full operation of the pipeline SAR converter described above is not needed for the purposes of understanding the present disclosure, although its operation can be found in US15 / 916,009 referenced earlier. For the purposes of the present disclosure, however, it is necessary to appreciate that in order to operate correctly and produce accurate conversions that DAC1 does require an accurate reference input while DAC1 is being loaded from ADC1.

[0011] In the arrangement of Figure 1, the reference input to DAC1 is provided by a further internal reference signal Vref_internal, which is derived from the accurate, temperature compensated external (i.e. off-chip) reference Vref, in the following manner. The voltage reference source provides an accurate reference signal Vref to an input pin, to which is also connected a large (10uF) stabilizing capacitor C1, which is therefore charged to Vref. A high bandwidth fast amplifier Amp1 is further provided, having its non-inverting input connected to the input pin to which Vref is supplied. Its output is connected via a first "convert" switch to the reference input node of DAC1, on which is provided Vref_internal. The inverting input of Amp1 is also connected to this same node i.e. the Vref_internal node (although it can instead be connected directly to the amplifier output). The Vref_internal node is further connected by a second "sample" switch to the input pin to which Vref is supplied. The "sample" and "convert" switches will usually operate in anti-phase i.e. when one is turned on (closed), the other is turned off (opened).

[0012] The operation of the above circuit is as follows. Prior to residue generation by the ADC (DAC1), the "convert" switch is closed and the "sample" switch is opened. The amplifier AMP1 operates to try and maintain the Vref_internal node at the same voltage as the Vref node while the changing Data values on the DAC1 inputs cause large charges to be drawn from Vref_Internal. Just prior to residue generation the "convert" switch is opened and the "sample" switch is closed, to allow the external reference Vref to be fed to DAC1. However, because Amp1 has been keeping Vref_internal very close to Vref, very little current needs to be drawn from Vref or C1, and hence Vref experiences little disturbance, thus permitting high sampling rates.

[0013] As noted above, however, in order to provide such operation, Amp1 must have wide bandwidth and fast operation, and hence consumes significant power.

[0014] Lower power solutions are therefore desirable, particularly for mobile applications.

[0015] To address this issue a different circuit can be used, which makes use of a comparator and switch to replace the high speed amplifier. The structure of this circuit will be described next, followed by its operation.

[0016] Figure 2 illustrates a comparator and switch circuit that can be used to replace the high speed amplifier Amp1 in some examples of the disclosure. Here a comparator Comp1 is provided, which has its inverting input connected to the Vref node, to which in use the stable external reference signal is applied. As in the circuit of Figure 1, Vref is also supplied via sample switch S1 to the reference input of digital to analog converter DAC1, which forms part of the pipeline SAR converter (the remainder of the converter circuit is not shown, but would be the same as described previously in Figure 1). A large 100pF capacitor (C1) is also connected between the DAC1 reference input and an internal node Vrefn. The purpose of this capacitor is to make the job of loading the DAC very simple, as it avoids the risk of top plate nodes going outside the rails. The large capacitor also makes the capacitance on Vref_internal almost constant, which is useful in order to obtain full accuracy of the technique.

[0017] The output of the comparator is fed to the gate of a transistor MP1, which has its drain and source terminals connected between a supply voltage VDD1 and the reference input of DAC1. The reference input node of DAC1 is also connected to the non-inverting input of the comparator. The supply VDD1 is higher than Vref. Finally, a threshold adjust block, described further below with respect to Figure 3, is provided, that receives as an input the signal on the DAC1 reference input node, as well as control signals "sample" (S) and "dump" (D), and acts to output a threshold control signal to the comparator. The comparator circuitry is shown in more detail in Figures 4 and 5.

[0018] Figure 3 illustrates in more detail the internal circuitry within the Threshold Adjust block of Figure 2. Here, the Vref_internal signal taken from the reference input node of DAC1 is fed via a capacitor C1 to two switches MN1 and MN2, which are respective transistors controlled to be on or off by respective "sample" (for MN1) and "dump" (for MN2) control signals fed to their gates. MN1 is connected between the bottom plate of C1 and a Vbias node at which a bias voltage is provided. MN2 is connected between the bottom plate of C1 and an inverting input of an amplifier Amp1. The non-inverting input of Amp1 is connected to Vbias. A second capacitor C2 provides a feedback loop from the output of the amplifier to the inverting input. The output of the amplifier provides the "Threshold_adjust" control signal that is fed to the threshold control input of comparator Comp1 of Figure 2.

[0019] Figures 4 and 5 show an example long tailed pair differential amplifier that can be used as the comparator Comp1. The long tailed pair differential amplifier arrangement is provided with the "Threshold_adjust" signal via transistor MN4, which skews the threshold of the comparator to adjust the threshold. In more detail, the long tailed pair comprises two pairs of transistors MP1 and MP2, and MN1 and MN2, with MP1 and MN1 connected in series with each other, and MP2 and MN2 connected in series, with the gates of MP1 and MP2 being commonly connected to the drain of MP1. The Vref signal is input to the gate of MN1, and the Vref_internal signal at the reference input to DAC1 is connected to the gate of MN2. The source terminals of MN1 and MN2 are connected together and connect to the GND terminal via the "long-tail" transistor MN3, the gate of which receives a biasing voltage Vbias. The output of the differential amplifier is taken from the node connecting MP2 and MN2, and is fed via an inverting amplifier BUF to the gate of a further transistor MP3, which is the same as transistor switch MP1 of Figure 2.

[0020] As noted above, such a comparator circuit has the ability to adjust the threshold of the comparator via the "Threshold_adjust" signal fed into the comparator via MN4. Figure 4 shows a relatively simple arrangement where a single Threshold_adjust signal is provided, to set a single comparator threshold, as shown for example by the horizontal dotted line in Figure 7. Alternatively, Figure 5 shows the same comparator circuit, but this time the MN4 device is replaced by a programmable current source which allows adjustment of the gain between the voltage on the Threshold_adjust input and the resulting comparator threshold adjustment. This adjustment can be on a per bit trial or DAC load basis. Ideally, the gain of the programmable current source will be reduced for the final loading of the DAC to ensure that MP3 always turns on for the final DAC load. Figure 6 shows an example of how the comparator thresholds, indicated by the dashed lines, may be adjusted from bit trial to bit trial. The solid lines show the voltage on the internal reference.

[0021] The overshoot of the internal reference above the threshold voltage is due to the time delay through the comparator and switch circuit. The final threshold is dynamically adjusted over a number of conversions by the threshold adjustment circuit, so that for the last DAC load the overshoot equals the final threshold voltage and the internal reference voltage 'over-shoots' to the required reference voltage. Figure 7 shows the potential consequence of not adjusting the threshold voltage during the conversion: The last 2 DAC loads do not trip the comparator circuit and the voltage error on the internal reference gets larger. Further details of this threshold adjusting will be apparent from following description of the whole operation of the circuit.

[0022] Given the above circuit arrangements i.e. the circuit of Figure 2 having the threshold adjust circuit of Figure 3 and the comparators of Figure 4 and 5, Figures 8 to 10 and 14 illustrate the operation of the circuit.

[0023] Referring first to Figures 2, 8, and 14, the operation of the comparator circuit to bring Vref_internal to Vref over one cycle will be described, without considering threshold adjustment, which will be described further later. In this respect, remember that the purpose of the comparator circuit of Figure 2 is to bring Vref_internal, which is fed as the reference to DAC1, close to Vref so that when Vref_internal is switched to Vref, the charge taken from Vref is very small, resulting in acceptable error on Vref, even when operating the convertor at high speed. In addition, the control loop for the comparator is of finite bandwidth, and hence the response of the comparator to changes in voltages on its two inputs is not instant, and instead there is a short time delay between changes on the comparator inputs, and a change in the comparator output. However, in the present arrangement this time delay, caused by the finite bandwidth of the comparator, causes some overshoot in the comparator output, but in a determinable fashion which helps to bring Vref_internal closer to Vref.

[0024] With the above in mind, consider Figure 8, which shows how Vref_internal varies with respect to Vref over multiple bit trials undertaken to obtain a single ADC sample. At the start of a sample generation cycle Vref_internal is at Vref having been connected to Vref from the previous sample. The bit trial cycles then start, with the first step being that Vref_internal is disconnected from Vref by turning off switch S1 (s.13.2 of figure 14) i.e. the "sample" switch of Figure 1. On the first data load of DAC1, with S1 switched off, Vref_internal falls to be further away from Vref, as shown by period A1 in Figure 8. As Vref_internal falls the difference between Vref and Vref_internal increases, until the increase is larger than the threshold Vt_comparator set for the comparator, and the comparator then starts to output a signal. However, due to the limited bandwidth of the comparator loop, there is some time delay between the comparator threshold voltage being passed and the output of the comparator starting to increase, hence period A1 extends beyond the point in time when Vref_internal reaches Vt_comparator.

[0025] Due to the difference between Vref_internal and Vref, the comparator output increases, turning on MP1 so that VDD1 starts to supply current to bring Vref_internal back up. As a result, Vref_internal stops falling and starts to rise back up towards Vref, as shown in period B1 in Figure 8, and s.13.4 of Figure 14. MP1 is kept turned on by the output of the comparator and hence Vref_internal is kept being brought up towards Vref until the point that the difference between Vref_internal and Vref is then again within the threshold voltage of the comparator, which in Figure 8 occurs at the end of period B1. However, as mentioned previously because the control loop for the comparator is of finite bandwidth, there will be a finite amount of time during which the comparator continues to output an ON signal to switch MP1, which is shown as time period C1 in Figure 8. During this time period the Vref_internal signal continues to move towards the Vref signal level, and hence the Vref_internal signal will always move closer to the Vref signal than the threshold Vt_comparator. By appropriate selection of the threshold voltage, therefore, it is possible to exploit the finite loop bandwidth of the comparator to have the Vref_internal signal come to rest at almost exactly Vref, as will be explained later.

[0026] Returning to Figure 8, however, at the start of the next bit trial (2 nd< bit trial), Vref_internal will again fall, during period A2, and is then again brought back up towards Vref by the comparator controlling MP1 during period B2. Again however, due to the finite bandwidth of the comparator control loop there is some overshoot during time C2, with the result that Vref_internal ends up closer to Vref than Vt_comparator. In this example, the same result is obtained during the 3 rd< bit trial, because the threshold Vt_comparator is constant. At the end of the bit trials (assuming there are three, but there could be more), switch S1 is turned back on, and the residual error E in this case between Vref_internal and Vref is then compensated to bring Vref_internal up to Vref by drawing current from the external Vref via switch S1.

[0027] In the above example of Figure 8, therefore, there remained a residual error E that has to be compensated from Vref. However, it should be seen from the above that if the threshold Vt_comparator is set appropriately for each bit trial, then the residual error E at the end of the bit trials can be minimised. Figures 9 and 10 illustrate this further.

[0028] Consider first Figure 9. This shows the situation where again a fixed threshold Vt_comparator has been used, and here three bit trial or DAC load cycles are again shown, with Vref_internal being brought up to Vref by the comparator circuit of Figure 2. For the first two cycles the differences to Vref at which Vref_internal settles out are sufficiently large that they are greater than the threshold voltage Vt_comparator, and hence the comparator and switch operates to bring Vref_internal further towards Vref, and to then overshoot. However, in this case for the third bit trial Vref_internal does not fall to less than the threshold of the comparator, and hence the comparator does not operate to bring Vref_internal towards Vref, as shown. In this case, when S1 is turned on to connect Vref_internal to Vref then more charge will need to be taken from Vref and C1 to bring Vref_internal up to Vref, resulting an error voltage on Vref.

[0029] In order to address this issue, and as noted previously, the threshold of the comparator can be adjusted from bit trial to bit trial so that it is always less than the possible error between Vref_internal and Vref. Adjustment of the threshold on a per bit trial or per DAC load basis is shown in Figure 10, where it can be seen that the comparator threshold Vt_comparator is adjusted so that it is always less than the possible error on Vref_internal. By making this adjustment of the comparator threshold the comparator will always help to drive Vref_internal towards Vref for every bit trial. In particular, for the third bit trial the threshold has been adjusted to be very close to, but still below, Vref. This ensures the fall in Vref_internal caused by the third bit trial is still larger than the comparator threshold so that the comparator causes MP1 to turn on, but also ensures that the overshoot of the Vref_internal past the threshold voltage due to the finite comparator control loop bandwidth does not raise Vref_internal to be higher than Vref, but instead that it causes Vref_internal to be at Vref. As noted previously, with Vref_internal at Vref no charge needs to pass from Vref when the sample switch of Figure 1 closes.

[0030] Regarding how the threshold is adjusted, and returning to Figure 3, the "sample" switch goes from high to low just prior to closing the switch S1 between Vref_internal and Vref. This effectively samples Vref_internal on C1 just before it is switched to connect to Vref, and hence Vref_internal at that point is equal to the sum of Vref plus some error voltage E (e.g. E1... En). When S1 closes (turns on) Vref_internal moves to Vref, and the error E on Vref_internal is transferred to the bottom plate of C1. The "dump" switch then turns on and this transfers the charge E.C1 to C2. The amplifier Amp1 with C2 connected in feedback around it act as an integrator and keeps a running sum of the error E on Vref_internal. The resulting Threshold_adjust control signal therefore adjusts from error to error (E1... En), with the aim of making the error running sum equal to zero over multiple conversions.

[0031] Alternative arrangements for the above described threshold adjust circuit could also be used. For example, a digital implementation can be obtained by using an ADC to measure the error voltage E after it has passed through the "dump" switch, and then have a digital integrator to sum the error voltages. A DAC would then be used to generate the "Threshold_adjust" control signal from the digital integrator output. An alternative digital implementation would be to use a 1 bit sigma delta and use the error signal from it as the Threshold_adjust signal.

[0032] Turning now to Figure 11, this demonstrates a further optimization to allow the described technique to work to full accuracy. A shown in Figure 2, a large 100pF capacitor C1 is connected to Vref_internal next to DAC1. This large 100pF capacitor makes the task of loading the DAC very simple, as it avoids the risk of top plate nodes going outside the rails. It also makes the capacitance on the Vref_internal nodes almost constant. However, for the described technique to work to full accuracy the capacitance on Vref_internal has to be fixed when the "sample" switch in Figure 1 goes high. In order to obtain this fixed capacitance, an additional block Cload_adjust is provided which comprises a number of selectable capacitors with attendant controllable switches, so that a particular value capacitor can be switched in per bit trial.

[0033] The Cload_adjust block acts to modify the capacitance on Vref_internal dependent on the data loaded in to DAC1, and in particular selects a capacitance value (when required - for some values of CDAC then no adjustment may be required) to switch in as Cload so that the sum of CDAC (i.e. the DAC capacitance including the 100pF capacitor C1) + Cload_adjust is constant. The threshold adjust circuit of figure 3 integrates the vref_internal errors (E1... En) when the sample switch of figure 1 closes and forces the sum of these voltage errors to zero over time. If the capacitance is constant then forcing the sum of voltage errors to zero also forces the sum of charge errors (Q1... Qn), pulled from Vref, to zero.

[0034] Referring next to Figure 12, this illustrates a power saving arrangement, where capacitors C1 to C3 plus switches S1 and S2 allow the comparator circuit to be DC isolated from the remainder of the circuit so that it can operate at a lower supply voltage VDD2 than VDD1, where VDD2 is less than VDD1. Specifically, the provision of the capacitors C1 to C3 provides the DC isolation of the comparator, whilst the switches S1 and S2 that connected to a further internal reference Vbias2, provide for DC level shifting to allow the comparator to operate at lower voltages than the remainder of the circuit. This allows the whole overall arrangement to save power. It should be noted that the operation of this circuit removes the requirement for a precise voltage on the Vref input to this circuit, instead the requirement is that Vref should be a stable voltage. The input Vref could, for example, be connected to VDD.

[0035] Figure 13 illustrates an alternative second example of the present disclosure according to the invention as claimed.

[0036] As noted previously, it is based on the arrangement of Figure 1, described previously, but replaces the fast amplifier Amp1 with a slower, lower bandwidth amplifier that is easier to implement and has less chip area and power requirements. However, in order to accommodate the lesser performance of the amplifier in bringing Vref_internal up to Vref a large (circa 100nF) capacitor C3 is provided on the output of the amplifier to help the amplifier provide charge to bring Vref_internal to Vref. In operation, when Vref_internal is disconnected from Vref (i.e. the "sample" switch opens) then the slow amplifier helps to bring it back to Vref, aided by charge from C3, which has been charged to Vref. In this respect, C3 acts as a battery capacitor at Vref, to help bring and maintain the Vref_internal node to Vref. During the sampling phase when the "sample" switch is closed and the "convert" switch at the output of Amp1 is open, the slow amplifier Amp1 acts to re-charge C3 back to Vref, by replacing any charge that was depleted from it during the "convert" phase when it is connected to Vref_internal.

[0037] Concerning the circuit design of the lower bandwidth amplifier, various low bandwidth amplifiers are suitable, and one such amplifier which can be used is the reference buffer amplifier described in US5854574 A.

[0038] Figure 15 shows a further alternative example according to the invention as claimed, similar to the example of Figure 13. Here again a large battery capacitor C3 is provided, and AMP1 is the slower, lower bandwidth amplifier that is easier to implement and has less chip area and power requirements, such as the reference buffer amplifier from US5854574A. However, instead of the output of AMP1 being switched so that it provides charge to the reference input of DAC1, switch S5 is provided that switches the output of AMP1 to charge the battery capacitor C3, but that also switches the battery capacitor C3 so as to supply charge to the DAC1 reference input, at the same time switching the output of AMP1 out of circuit. That is, in other words, S5 switches battery capacitor C3 between two phases of operation; a first phase (shown in Figure 15), where the "Sample" switch is open and the switch S5 switches the battery capacitor so that it is supplying charge to the internal reference of DAC1 to maintain Verf_internal at or near to Vref, and a second phase (just prior to and during residue generation), where the "Sample" switch is closed such that Vref_internal is connected to Vref for residue generation), and S5 connects capacitor C3 to AMP1 for recharging back to Vref.

[0039] With such an arrangement the internal reference of DAC1 is being sustained at or near to Vref for some periods of the conversion cycle corresponding to the first phase solely by the charge stored in capacitor C3, which of course will deplete. However, in many implementations of the ADC for which the present arrangement is envisaged for use, the duty cycle of when the internal DAC reference is fed from C3 (during the first phase) versus when it is fed from the external Vref (during the second phase) is such that the first phase is often commonly much shorter than the second phase, meaning that the capacitor C3 supplies charge to the DAC1 internal reference for much shorter periods than C3 is then being charged by AMP1. One typical example duty cycle would be for a 25ns conversion to conversion cycle S1 may typically be closed for 18ns of that time (with DAC1 then being fed the external Vref), meaning that S5 is switched to receive the output of AMP1 for that same time. That would then leave 7 nS of the duty cycle where S5 is switched to supply Vref_internal from capacitor C3, and the Sample switch is open.

[0040] Both the arrangements of Figures 13 and 15 provide simple alternative solutions to the problem of providing a fast amplifier for provision of a fast settling reference to an ADC, but is possible only where there is chip space for or external pin access to the large battery capacitor C3.

[0041] While it is often convenient for the reference input to the comparator Vref_comp or to the low power amplifier Vref_amp to be connected to the reference input Vref, this is not strictly necessary. For example, in other examples these references could be generated by an on-chip voltage reference. What is more, in such cases the Voltage reference output does not need to be the same value as the external reference Vref, as will be apparent from the following further examples of the disclosure, shown in Figures 16 and 17. In these examples, a different reference voltage level is used, which is then adjusted to approximately Vref using appropriate biasing around the amplifier (for the example of Figure 16) or comparator (for the example of Figure 17).

[0042] In the example shown in Figure 16, according to the invention as claimed, (which is related to the examples of Figures 13 and 15, in that a low-bandwidth amplifier is used with a capacitor to keep Vref_internal near to Vref), connecting the negative input of AMP2 to the output of the resistor attenuator formed by resistors R1 and R2, results in the output of the amplifier being at a different voltage to the input. In this example, where R1 equals R2, the amplifier output voltage is twice that on Vref_amp. The output of Amp1 would need to be set close to or equal to the voltage on Vref to minimise charge drawn from Vref when the Sample switch closes. The combination of Amp1, the Voltage reference and R1 and R2 could represent a low dropout (LDO) linear regulator. In which case the output of Amp1 would be a regulated supply voltage that may be shared by other circuits while also being used to charge Vref_internal when the Convert switch is closed. The LDO may be co-located on the same die as the ADC but may also be an external component.

[0043] Figure 17 shows an alternative arrangement not covered by the scope of protection of the claims but useful for understanding the invention, which is related to the example of Figures 2 and 3, and which operates in the same or a similar fashion to that example. Similarly, with the arrangement shown in Figure 17, the resistor attenuator formed by R1 and R2 attenuates the voltage on Vref_internal by a factor of 2, so that the voltage on Vref_internal will be driven by the comparator and switch combination to twice the voltage on Vref_comp. As before (i.e. the circuit of Figures 2 and 3), this circuit will need to drive Vref_internal to close to the voltage on Vref while Vref_internal is disconnected from Vref.

Claims

1. An integrated voltage reference supply circuit for an analog to digital converter, ADC, the voltage reference supply circuit comprising: an input node that, in use, receives an external voltage reference signal (Vref); a battery capacitor (C3); a low-bandwidth amplifier (Amp1) receiving a voltage reference signal (Vref_amp) at a first one of its signal input and configured to supply, at an output node, the voltage on the external voltage reference signal (Vref) to the battery capacitor (C3), wherein for a given converter sampling rate the amplifier (Amp1), is of lower bandwidth than would need to be the case if the battery capacitor (C3) is not provided; and switching circuitry (Sample, S5) arranged to switch selectively an internal node (Vref_internal) between the input node, and the battery capacitor, so as to directly receive the external voltage reference signal (Vref) by connecting the internal node directly to the input node, the internal node (Vref_internal) being the reference input of a DAC forming part of the ADC; wherein prior to an operating phase of the ADC that requires a reference signal at the internal node (Vref_internal), the switching circuitry, (Sample, S5) is firstly operated, during a first phase of operation, so as to disconnect the internal node (Vref_internal) from the input node and connect it to the battery capacitor (C3), whereby the battery capacitor (C3) supplies charge to the internal node (Vref) to bring it towards or maintain it at the voltage on the external voltage reference signal (Vref) and then secondly, the switching circuitry (Sample, S5) is operated during a second phase of operation, after the first phase, to connect the internal node (Vref_internal) directly to the input node to receive the external voltage reference signal (Vref) directly, and to disconnect the battery capacitor (C3) from the internal node (Vref_internal) wherein the amplifier (Amp1) recharges the battery capacitor (C3) towards the voltage on the external voltage reference signal (Vref).

2. An integrated voltage reference supply circuit according to claim 1, wherein the switching circuitry (Sample, S5) is operable to switch out the output of the low-bandwidth amplifier (Amp1) from the internal node (Vref_internal) during the said first phase and second phase of operation.

3. An integrated voltage reference supply circuit according to claims 1 or 2, wherein the switching circuitry comprises: a first switch (Sample) operable to connect the internal node (Vref_internal) to the input node during the said second phase of operation; and a second single pole double throw switch (S5), operable to connect: (i) the output of the amplifier (Amp1), to the battery capacitor during the second phase of operation; (ii) the internal node (Vref_internal) to the battery capacitor during the said first phase of operation, wherein the said second single pole double throw switch (S5) is further configured to switch out the output of the amplifier (Amp1) from the internal node (Vref_internal) during the first phase and second phase of operation.

4. An integrated voltage reference supply circuit according to any of the preceding claims, wherein the battery capacitor (C3) is located off-chip.

5. An integrated voltage reference supply circuit according to any preceding claim, wherein the battery capacitor (C3) comprises a capacitance of at least 100nF.

6. An integrated voltage reference supply circuit according to any preceding claim, wherein the said first one of the signal inputs of the amplifier (Amp1) is connected in use to the input node to receive the external voltage reference signal (Vref).

7. An integrated voltage reference supply circuit according to any of claims 1 to 5, wherein the said first one of the signal inputs of the amplifier is connected to an on-chip voltage reference (Voltage reference), and wherein the voltage reference signal (Vref_amp) at the first input of the amplifier is different to the voltage of the external voltage reference signal (Vref), at the input node.

8. An integrated voltage reference supply circuit according to claim 7, further comprising a biasing circuit, (R1, R2), configured to adjust the output of the amplifier (Amp1), to the voltage of the external reference signal (Vref).

9. An integrated voltage reference supply circuit according to claim 8, wherein the biasing circuit comprises a resistor attentuator circuit (R1, R2).

10. A method of providing a voltage reference signal for an analog to digital converter, using the integrated voltage reference supply circuit according to any of claims 1 to 9, the method comprising, prior to an operating phase of the ADC that requires a reference signal at the internal node (Vref_internal): receiving, at the input node, the external voltage reference signal (Vref); disconnecting, during the first phase of operation of the switching circuit (Sample, S5), the internal node (Vref_internal) from the input node; connecting, during the first phase of operation of the switching circuit, the internal node (Vref_internal) to the battery capacitor (C3) to supply a charge to the internal node (Vref_internal) using the battery capacitor (C3) to bring the internal node (Vref_internal) towards or maintain it at the voltage of the external reference voltage (Vref); connecting, during the second phase of operation of the switching circuit, following the first phase of operation, the internal node (Vref_internal) directly to the input node to receive the external reference signal voltage (Vref) directly; and disconnecting the battery capacitor (C3) from the internal node (Vref_internal) to recharge the battery capacitor (C3) using the amplifier (Amp1) towards the voltage on the external reference signal (Vref).

11. A method according to claim 10, wherein the method further comprises switching out the output of the amplifier (Amp1), from the internal node (Vref_internal) during the first phase of operation and the second phase of operation.