METHOD FOR PRODUCING AN OPTOELECTRONIC DEVICE

Abstract

The present description relates to a method for producing an optoelectronic device (5) comprising sets of light-emitting diodes (LED) including first and second sets and first blocks (32) made of a first photoluminescent material each covering one of the first sets. The method comprises forming a layer covering the first and second sets, defining first openings in the layer in order to expose the first sets, filling the first openings with the first material and carrying out chemical-mechanical polishing to define the first blocks.

Description

DESCRIPTION METHOD FOR MANUFACTURING AN OPTOELECTRONIC DEVICE This patent application claims priority from French patent application FR19 / 11133, which will be considered as forming an integral part of this description. technical field

[0001] This description generally relates to optoelectronic devices comprising three-dimensional semiconductor elements of nanometer or micrometer size, in particular microwires or nanowires or pyramidal-shaped structures, forming light-emitting diodes and photoluminescent blocks covering these light-emitting diodes. Previous technique

[0002] Optoelectronic devices are defined as devices adapted to convert an electrical signal into electromagnetic radiation or vice versa, and in particular devices dedicated to the detection, measurement, or emission of electromagnetic radiation. Optoelectronic devices with three-dimensional semiconductor elements may include light-emitting diodes coated with photoluminescent blocks.

[0003] A manufacturing process for such optoelectronic devices includes the formation of light-emitting diodes (LEDs) on a substrate and the formation of photoluminescent blocks covering the LEDs. The photoluminescent blocks can be formed by depositing a photoluminescent layer over all the LEDs and etching this photoluminescent layer to delineate the blocks.

[0004] The delimitation of photoluminescent blocks in the photoluminescent layer may involve the deposition of a A resin layer is applied over the photoluminescent layer, and portions of this photoluminescent layer are delineated using photolithography processes at the desired locations of the photoluminescent blocks. These photolithography processes typically use the detection of alignment marks visible on the substrate to correctly position the masks used for exposing the resin layer to the light-emitting diodes.

[0005] One disadvantage of such a process is that the photoluminescent layer may be partially opaque to visible light, so lithography processes using alignment mark detection may be difficult to implement. Summary of the invention

[0006] Thus, one object of an embodiment is to overcome at least in part the disadvantages of the previously described manufacturing processes of optoelectronic devices with light-emitting diodes and photoluminescent blocks.

[0007] Another object of an embodiment is that the materials composing the photoluminescent blocks may not be photosensitive materials suitable for use in photolithography steps.

[0008] Another object of an embodiment is that the ratio between the height and width of the photoluminescent blocks can be important.

[0009] Another objective of one embodiment is that optoelectronic devices can be formed on an industrial scale and at low cost.

[0010] One embodiment provides a method for manufacturing an optoelectronic device comprising assemblies of light-emitting diodes, including first and The process involves forming a layer covering the first and second sets, creating openings in the layer to expose the first sets, filling these openings with the first material, and performing a mechano-chemical polishing to define the first blocks.

[0011] According to one embodiment, the device includes second blocks of a second photoluminescent material, different from the first photoluminescent material, each covering one of the second sets, the delimitation of second openings in the layer to expose the second sets, the filling of the second openings with the second material and the performance of a mechano-chemical polishing to delimit the second blocks.

[0012] According to one embodiment, the device further comprises third sets of light-emitting diodes and third blocks of a third photoluminescent material, different from the first and second photoluminescent materials, each covering one of the third sets, the delimitation of third openings in the layer to expose the third sets, the filling of the third openings of the third material and the performance of a mechano-chemical polishing to delimit the third blocks.

[0013] According to one embodiment, the device further comprises fourth sets of light-emitting diodes, the method comprising the delimitation of fourth blocks in the layer covering each one of the fourth sets of light-emitting diodes.

[0014] According to one embodiment, the layer is at least partially transparent to the radiation emitted by the diodes. light-emitting diodes of the fourth set of light-emitting diodes.

[0015] According to one embodiment, the process includes the delimitation of fourth openings in the layer between the assemblies and the formation of walls with reflective surfaces in the fourth openings.

[0016] According to one embodiment, the process includes depositing a reflective coating in the fourth openings and filling the rest of the fourth openings with a fifth material.

[0017] According to one embodiment, the walls are formed after the first photoluminescent blocks.

[0018] According to one embodiment, the process includes the formation of a barrier layer extending into the fourth openings and covering the first photoluminescent blocks before the formation of the walls.

[0019] According to one embodiment, the walls are formed after the first and second photoluminescent blocks.

[0020] According to one embodiment, the walls are formed before the first and second photoluminescent blocks.

[0021] According to one embodiment, the process includes etching the layer present between the first, second and third photoluminescent blocks, forming a barrier layer extending into the fourth openings and covering the first, second and third photoluminescent blocks before the formation of the walls, and forming the walls in the spaces present between the first, second and third photoluminescent blocks. Brief description of the drawings

[0022] These features and advantages, along with others, will be detailed in the following description of modes of specific implementations carried out, by way of non-exhaustive list, in relation to the attached figures, including:

[0023] Figure 1 is a partial and schematic cross-sectional view of an embodiment of an optoelectronic device with light-emitting diodes and photoluminescent blocks;

[0024] Figure 2 is a partial and schematic cross-sectional view of one embodiment of a light-emitting diode;

[0025] Figure 3 is a cross-sectional view of the structure obtained at one stage of an embodiment of a manufacturing process for the device of Figure 1;

[0026] Figure 4 is a cross-sectional view of the structure obtained at another stage of the process;

[0027] Figure 5 is a cross-sectional view of the structure obtained at another stage of the process;

[0028] Figure 6 is a cross-sectional view of the structure obtained at another stage of the process;

[0029] Figure 7 is a cross-sectional view of the structure obtained at another stage of the process;

[0030] Figure 8 is a cross-sectional view of the structure obtained at another stage of the process;

[0031] Figure 9 is a cross-sectional view of the structure obtained at another stage of the process;

[0032] Figure 10 is a cross-sectional view of the structure obtained at another stage of the process;

[0033] Figure 11 is a cross-sectional view of the structure obtained at another stage of the process;

[0034] Figure 12 is a cross-sectional view of the structure obtained at another stage of the process;

[0035] Figure 13 is a cross-sectional view of the structure obtained at another stage of the process;

[0036] Figure 14 is a cross-sectional view of the structure obtained at another stage of the process;

[0037] Figure 15 is a cross-sectional view of the structure obtained at one stage of another embodiment of a manufacturing process for the device of Figure 1;

[0038] Figure 16 is a cross-sectional view of the structure obtained at another stage of the process;

[0039] Figure 17 is a cross-sectional view of the structure obtained at another stage of the process;

[0040] Figure 18 is a cross-sectional view of the structure obtained at another stage of the process;

[0041] Figure 19 is a cross-sectional view of the structure obtained at another stage of the process;

[0042] Figure 20 is a cross-sectional view of the structure obtained at another stage of the process;

[0043] Figure 21 is a cross-sectional view of the structure obtained at another stage of the process;

[0044] Figure 22 is a cross-sectional view of the structure obtained at another stage of the process;

[0045] Figure 23 is a cross-sectional view of the structure obtained at another stage of the process;

[0046] Figure 24 is a cross-sectional view of the structure obtained at another stage of the process;

[0047] Figure 25 is a cross-sectional view of the structure obtained at another stage of the process;

[0048] Figure 26 is a cross-sectional view of the structure obtained at another stage of the process;

[0049] Figure 27 is a cross-sectional view of the structure obtained at another stage of the process;

[0050] Figure 28 is a cross-sectional view of the structure obtained at one stage of another embodiment of a manufacturing process for the device of Figure 1;

[0051] Figure 29 is a cross-sectional view of the structure obtained at another stage of the process;

[0052] Figure 30 is a cross-sectional view of the structure obtained at another stage of the process;

[0053] Figure 31 is a cross-sectional view of the structure obtained at another stage of the process;

[0054] Figure 32 is a cross-sectional view of the structure obtained at one stage of another embodiment of a manufacturing process for the device of Figure 1.

[0055] Figure 33 is a cross-sectional view of the structure obtained at another stage of the process;

[0056] Figure 34 is a cross-sectional view of the structure obtained at another stage of the process;

[0057] Figure 35 is a cross-sectional view of the structure obtained at another stage of the process;

[0058] Figure 36 is a cross-sectional view of the structure obtained at another stage of the process;

[0059] Figure 37 is a cross-sectional view of the structure obtained at another stage of the process;

[0060] Figure 38 is a cross-sectional view of the structure obtained at another stage of the process;

[0061] Figure 39 is a cross-sectional view of the structure obtained at another stage of the process;

[0062] Figure 40 is a cross-sectional view of the structure obtained at one stage of another embodiment of a manufacturing process for the device of Figure 1;

[0063] Figure 41 is a cross-sectional view of the structure obtained at another stage of the process;

[0064] Figure 42 is a cross-sectional view of the structure obtained at another stage of the process;

[0065] Figure 43 is a cross-sectional view of the structure obtained at another stage of the process;

[0066] Figure 44 is a cross-sectional view of the structure obtained at another stage of the process;

[0067] Figure 45 is a cross-sectional view of the structure obtained at another stage of the process;

[0068] Figure 46 is a cross-sectional view of the structure obtained at another stage of the process;

[0069] Figure 47 is a cross-sectional view of the structure obtained at another stage of the process;

[0070] Figure 48 is a cross-sectional view of the structure obtained at another stage of the process;

[0071] Figure 49 is a cross-sectional view of the structure obtained at another stage of the process;

[0072] Figure 50 is a cross-sectional view of the structure obtained at another stage of the process;

[0073] Figure 51 is a cross-sectional view of the structure obtained at another stage of the process; and

[0074] Figure 52 is a cross-sectional view of the structure obtained at another stage of the process. Description of the implementation methods

[0075] The same elements have been designated by the same reference numerals in the different figures. In particular, the Structural and / or functional elements common to the different embodiments may have the same references and may possess identical structural, dimensional, and material properties. For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0076] In the following description, when referring to absolute positional qualifiers, such as "front," "back," "top," "bottom," "left," "right," etc., or relative positional qualifiers, such as "above," "below," "superior," "inferior," etc., or to orientational qualifiers, such as "horizontal," "vertical," etc., unless otherwise specified, reference is made to the orientation of the figures or to an optoelectronic device in a normal operating position. Unless otherwise specified, the expressions "about," "approximately," "roughly," and "on the order of" mean to the nearest 10%, preferably to the nearest 5%. When the expressions "about," "approximately," "roughly," and "on the order of" are used in relation to directions, they mean to the nearest 10°, preferably to the nearest 5°.Furthermore, here the terms "insulator" and "conductor" are considered to mean "electrically insulating" and "electrically conductive" respectively.

[0077] The transmittance of a layer is the ratio of the intensity of radiation exiting the layer through an exit face to the intensity of radiation entering the layer through an entrance face opposite the exit face. In the following description, a layer or film is said to be opaque to radiation when the transmittance of the radiation through the layer or film is less than 10%. A film is said to be transparent to radiation when the transmittance of the radiation through the layer or film is greater than 10%. In the following description, visible light refers to electromagnetic radiation with a wavelength between 400 nm and 700 nm.

[0078] In the following description, a film or layer is said to be oxygen-tight when the permeability of the film or layer to oxygen at 40 °C is less than 1 x 10⁻¹². 1 cm 3 / (m 2 *day*atm). Oxygen permeability can be measured according to ASTM D3985, "Standard Test Method for Oxygen Gas Transmission Rate Through Plastic Film and Sheeting Using a Coulometric Sensor." In the following description, a film or layer is considered water-tight when its water permeability at 40°C is less than 1 x 10⁻¹⁰ _1 g / (m 2 *day). Water permeability can be measured according to the ASTM F1249 method entitled "Standard Test Method for Water Vapor Transmission Rate Through Plastic Film and Sheeting Using a Modulated Infrared Sensor".

[0079] The present invention relates to the manufacture of optoelectronic devices comprising light-emitting diodes formed from three-dimensional elements of nanometric or micrometric size, in particular microwires, nanowires or pyramids.

[0080] The term "microwire" or "nanofil" designates a three-dimensional structure elongated in a preferred direction, at least two dimensions of which, called minor dimensions, are between 5 nm and 5 pm, preferably between 100 nm and 2 pm, more preferably between 200 nm and 1.5 pm, the third dimension, called major dimension or height, being greater than or equal to 1 times, preferably greater than or equal to 3 times, and even more preferably greater than or equal to 5 times. large of minor dimensions. In some embodiments, the height of each microwire or nanowire may be greater than or equal to 500 nm, preferably between 1 pm and 50 pm. In the following description, the term "wire" is used to mean "microwire or nanowire".

[0081] The cross-section of wires can have various shapes, for example, oval, circular, or polygonal, including triangular, rectangular, square, or hexagonal. It should be understood that the term "average diameter" used in relation to a cross-section of a wire refers to a quantity associated with the area of ​​the wire in that cross-section, corresponding, for example, to the diameter of the disk having the same area as the cross-section of the wire.

[0082] In the following description, the term pyramid refers to a three-dimensional structure, part of which is pyramidal or elongated conical in shape. This pyramidal structure may be truncated, meaning that the apex of the cone is omitted, leaving a flat surface. The base of the pyramid is inscribed within a square with side lengths ranging from 100 nm to 10 pm, preferably between 0.2 pm and 2 pm. The polygon forming the base of the pyramid may be a hexagon. The height of the pyramid, measured from its base to its apex or summit flat surface, varies from 100 nm to 20 pm, preferably between 200 nm and 2 pm.

[0083] In the following description, embodiments will be described for an optoelectronic device with light-emitting diodes (LEDs) comprising microwires or nanowires. However, it is clear that these embodiments can also be applied to an optoelectronic device with LEDs comprising pyramids of micrometer or nanometer size.

[0084] The yarns comprise predominantly, preferably more than 60% by mass, more preferably more than 80% by mass, at least one semiconductor material. The semiconductor material may be silicon, germanium, silicon carbide, a III-V compound, a II-VI compound or a combination of at least two of these compounds.

[0085] Examples of group III elements include gallium (Ga), indium (In), and aluminum (Al). Examples of III-N compounds are GaN, AIN, InN, InGaN, AlGaN, and AlInGaN. Other group V elements can also be used, for example, phosphorus and arsenic. Generally, the elements in the III-V compound can be combined in different mole fractions. Examples of group II elements include group IIA elements, such as beryllium (Be) and magnesium (Mg), and group IIB elements, such as zinc (Zn), cadmium (Cd), and mercury (Hg). Examples of group VI elements include group VIA elements, such as oxygen (O) and tellurium (Te). Examples of II-VI compounds are ZnO, ZnMgO, CdZnO, CdZnMgO, CdHgTe, CdTe, and HgTe. Generally, the elements in II-VI compounds can be combined in different mole fractions.The semiconductor material of the wires may include a dopant, for example silicon providing N-type doping of a III-N compound, or magnesium providing P-type doping of a III-N compound.

[0086] Figure 1 is a partial, schematic cross-sectional view of an embodiment of a nanowire or microwire optoelectronic device 5. The optoelectronic device 5 comprises, from bottom to top in Figure 1: - a substrate 10 comprising opposite faces 12 and 14, the upper face 12 being preferably flat at least at the level of the light-emitting diodes; - a germination layer 16 made of a material promoting the growth of threads and arranged on face 12; - an insulating layer 18 covering the germination layer 16 and comprising openings 20 exposing portions of the germination layer 16; - LEDs (six LEDs are shown), each LED being in contact with the germination layer 16 through one of the openings 20; - an insulating layer 24 extending over the lateral sides of a lower portion of a light-emitting diode LED and extending over the insulating layer 18 between the light-emitting diodes LEDs; - a layer 26 forming an electrode covering each LED and extending further over the insulating layer 24 between the LEDs; - a conductive and reflective layer 28, extending over the layer 26 between the LEDs, the conductive layer 28 being able, as an alternative, to be interposed between the electrode layer 26 and the insulating layer 24 between the LEDs; - a dielectric protection layer 30 extending over layers 26 and 28; - photoluminescent blocks 32, 33 covering certain sets of light-emitting diodes; - blocks 34 transparent to the radiation emitted by the light-emitting diodes and covering other sets of light-emitting diodes, the transparent blocks 34 may not be present; - an insulating layer 36 covering the upper face of each block 32, 33, 34, or only of some of the blocks 32, 33, 34, the insulating layer 36 may not be present; - a protective layer 37 covering the insulating layers 36, the lateral faces of blocks 32, 33, 34 and the electrode layer 26 between blocks 32, 34; - walls 38 between blocks 32, 34, each wall 38 comprising a core 40 surrounded by a reflective coating 42; - one, two or three color filters 44, for example a single yellow filter, two filters, the first being a yellow filter and the second being a red filter, or three filters, the first being a red filter, the second being a green filter and the third being a blue filter, covering at least some of the photoluminescent blocks 32, 33, a single filter 44 covering two blocks being shown as an example; and - a protective layer 46 covering the entire structure.

[0087] Figure 2 shows an embodiment of the LEDs. According to one embodiment, each LED comprises a wire 21 in contact with the seed layer 16 through one of the openings 20 and a shell 22 comprising a stack of semiconductor layers covering the side walls and the top of the wire 21. The assembly formed by each wire 21 and the associated shell 22 constitutes an LED.

[0088] The shell 22 may comprise a stack of several layers, including an active layer 23 and a bonding layer 25. The active layer 23 is the layer from which the majority of the radiation supplied by the light-emitting diode (LED) is emitted. For example, the active layer 23 may incorporate confinement means, such as multiple quantum wells. The bonding layer 25 may comprise a stack of semiconductor layers of the same type. material III-V than wire 21 but of the opposite conductivity type to wire 21.

[0089] The substrate 10 may be a single-piece structure or a layer covering a support made of another material. The substrate 10 is preferably a semiconductor substrate, for example, a silicon, germanium, silicon carbide, III-V compound such as GaN or GaAs, or a ZnO substrate. Preferably, the substrate 10 is a single-crystal silicon substrate. Preferably, it is a semiconductor substrate compatible with the manufacturing processes used in microelectronics. The substrate 10 may be a multilayer silicon-on-insulator (SOI) structure.

[0090] The cross-sectional area of ​​the openings 20 may correspond to the desired cross-sectional area of ​​the wires 21 or may differ from the resulting cross-sectional area of ​​the wires. The average diameter of the wires 21 may be equal to or greater than the average diameter of the openings 20.

[0091] The germination layer 16 is made of a material that promotes wire growth. For example, the material composing the germination layer 16 may be a nitride, carbide, or boride of a transition metal from group IV, V, or VI of the periodic table of elements, or a combination of these compounds. For example, the germination layer 16 may be made of aluminum nitride (AIN), boron (B), boron nitride (BN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), hafnium (Hf), hafnium nitride (HfN), niobium (Nb), niobium nitride (NbN), zirconium (Zr), zirconium borate (ZrB2), zirconium nitride (ZrN), silicon carbide (SiC), tantalum nitride and carbide (TaCN), in magnesium nitride in the form of Mg x N ywhere x is approximately equal to 3 and y is approximately equal to 2, for example magnesium nitride in the form Mg3N2 or gallium magnesium nitride (MgGaN), tungsten (W), tungsten nitride (WN) or a combination thereof. The nucleation layer 16 may have a single-layer structure or correspond to a stack of at least two layers, each layer being, for example, made of one of the materials described previously.

[0092] In another embodiment, the germination layer 16 may not be present. In another embodiment, the germination layer 16 may be replaced by germination pads, for example formed at the bottom of the openings 20.

[0093] Each insulating layer 18, 24, 30, 36, 37, 46 and the filling material 40 can be made of a dielectric material, for example silicon dioxide (SiCp), silicon nitride (Si x N ywhere x is approximately equal to 3 and y is approximately equal to 4, for example S13N4), in silicon oxynitride (notably with the general formula SiO x N y , for example, S12ON2), aluminum oxide (Al2O3), hafnium oxide (HfCu), titanium dioxide (T1O2), or diamond. The insulating layer 18, 24, 30, 36, 37, 46 may have a single-layer structure or correspond to a stack of two or more layers. When the insulating layer 18 corresponds to a stack of at least two layers, the top layer of the stack is insulating, for example, made of a dielectric material.

[0094] The conductive layer 28 or the coating 42 is preferably a metallic layer, for example, aluminum, silver, copper, gold, or zinc. The thickness of the conductive layer 28 or the coating 42 can be between 0.01 µm and 1000 µm. As a Alternatively, the coating 42 may not be present. In this case, the filler material 40 may be a metallic material, for example aluminium, silver, copper or zinc.

[0095] The electrode layer 26 is designed to allow the passage of electromagnetic radiation emitted by the light-emitting diodes. The material forming the electrode layer 26 can be a transparent and conductive material such as indium tin oxide (ITO), aluminum- or gallium-doped zinc oxide, or graphene. The thickness of the electrode layer 26 can range from 0.01 µm to 10 µm.

[0096] In one embodiment, each photoluminescent block 32, 33 is located opposite one or a set of light-emitting diodes (LEDs). Each photoluminescent block 32, 33 comprises phosphors adapted, when excited by the light emitted by the associated LED, to emit light at a wavelength different from that of the light emitted by the associated LED. In one embodiment, the optoelectronic device 5 comprises at least two types of photoluminescent blocks 32, 33.Each photoluminescent block 32 of the first type is adapted to convert the radiation provided by the light-emitting diodes it covers into a first radiation at a first wavelength, and each photoluminescent block 33 of the second type is adapted to convert the radiation provided by the light-emitting diodes it covers into a second radiation at a second wavelength. According to one embodiment, the optoelectronic device 5 comprises at least three types of photoluminescent blocks 32, 33, each photoluminescent block of the third type being... adapted to convert the radiation emitted by the light-emitting diodes it covers into a third radiation at a third wavelength. The first, second and third wavelengths can be different.

[0097] In one embodiment, the light-emitting diodes are adapted to emit blue light, that is, radiation with a wavelength in the range of 430 nm to 480 nm. In another embodiment, the first wavelength corresponds to green light and is in the range of 510 nm to 570 nm. In yet another embodiment, the second wavelength corresponds to red light and is in the range of 600 nm to 720 nm.

[0098] In another embodiment, light-emitting diodes (LEDs) are, for example, adapted to emit radiation in the ultraviolet range. In one embodiment, the first wavelength corresponds to blue light and is in the range of 430 nm to 480 nm. In another embodiment, the second wavelength corresponds to green light and is in the range of 510 nm to 570 nm. In another embodiment, the third wavelength corresponds to red light and is in the range of 600 nm to 720 nm.

[0099] The aspect ratio of blocks 32, 33, that is to say the ratio between the height and the maximum width of the block, can be between 0.01 and 10, preferably between 0.05 and 2.

[0100] According to one embodiment, each photoluminescent block 32, 33 comprises particles of at least one photoluminescent material, for example in a transparent matrix. An example of a photoluminescent material is trivalent cerium ion-activated yttrium aluminum garnet (YAG), also called YAG:Ce or YAG:Ce 3+ . There The average particle size of conventional photoluminescent materials is generally greater than 5 pm.

[0101] According to one embodiment, each photoluminescent block 32, 33 comprises a matrix in which nanometer-sized single-crystal particles of a semiconductor material are dispersed; these particles are also referred to as semiconductor nanocrystals or nanoluminophores hereafter. The internal quantum efficiency QYint of a photoluminescent material is equal to the ratio of the number of photons emitted to the number of photons absorbed by the photoluminescent substance. The internal quantum efficiency QYi nt of semiconductor nanocrystals is greater than 5%, preferably greater than 10%, more preferably greater than 20%.

[0102] In one embodiment, the average size of the nanocrystals is in the range of 0.5 nm to 1000 nm, preferably from 0.5 nm to 500 nm, and even more preferably from 1 nm to 100 nm, particularly from 2 nm to 30 nm. For dimensions smaller than 50 nm, the photoconversion properties of the semiconductor nanocrystals depend essentially on quantum confinement phenomena. The semiconductor nanocrystals then correspond to quantum dots.

[0103] According to one embodiment, the semiconductor material of the semiconductor nanocrystals is chosen from the group comprising cadmium selenide (CdSe), indium phosphide (InP), cadmium sulfide (CdS), zinc sulfide (ZnS), zinc selenide (ZnSe), cadmium telluride (CdTe), zinc telluride (ZnTe), cadmium oxide (CdO), zinc cadmium oxide (ZnCdO), zinc cadmium sulfide (CdZnS), zinc cadmium selenide (CdZnSe), indium silver sulfide (AgInS2), and PbScX3 type perovskites, where X is an atom of halogen, in particular iodine (I), bromine (Br) or chlorine (Cl), and a mixture of at least two of these compounds. According to one embodiment, the semiconductor material of the semiconductor nanocrystals is chosen from the materials cited in the publication on behalf of Le Blevenec et al. of Physica Status Solidi (RRL) - Rapid Research Letters Volume 8, No. 4, pages 349-352, April 2014.

[0104] In one embodiment, the dimensions of the semiconductor nanocrystals are chosen according to the desired wavelength of the radiation emitted by the semiconductor nanocrystals. For example, CdSe nanocrystals with an average size of approximately 3.6 nm are suitable for converting blue light into red light, and CdSe nanocrystals with an average size of approximately 1.3 nm are suitable for converting blue light into green light. In another embodiment, the composition of the semiconductor nanocrystals is chosen according to the desired wavelength of the radiation emitted by the semiconductor nanocrystals.

[0105] The matrix is ​​at least partially transparent to the radiation emitted by photoluminescent particles and / or light-emitting diodes (LEDs), preferably more than 80%. The matrix is, for example, made of silica. The matrix is, for example, made of any polymer that is at least partially transparent, in particular silicone, epoxy, poly(methyl methacrylate) (PMMA) acrylic resin, or polyacetic acid (PLA). The matrix may, in particular, be made of a polymer that is at least partially transparent and used with 3D printers. The matrix may be a spin-on glass (SOG), photosensitive or non-photosensitive. In one embodiment, the matrix contains from 2% to 90% of preference of 10% to 60%, by weight of nanocrystals, for example about 30% by weight of nanocrystals.

[0106] The thickness of the photoluminescent blocks 32, 33 depends on the concentration of nanocrystals and the type of nanocrystals used. The height of the photoluminescent blocks 32, 33 is preferably greater than the height of the wires 21 and less than or equal to the height of the walls 38. In top view, each photoluminescent block 32, 33 can correspond to a square, a rectangle, an "L"-shaped polygon, etc., the area of ​​which can be equal to the area of ​​a square having a side measuring from 1 pm to 100 pm, preferably from 3 pm to 15 pm.

[0107] The walls 38 are at least partially made of at least one reflective material. The reflective material may be a metallic material, in particular iron, copper, aluminum, tungsten, silver, titanium, hafnium, zirconium, or a combination of at least two of these compounds. Preferably, the walls 38 are made of a material compatible with the manufacturing processes used in microelectronics. Preferably, the walls 38 are made of aluminum or silver.

[0108] The height of the walls 38, measured in a direction perpendicular to the face 12, is in the range of 300 nm to 200 pm, preferably from 3 pm to 15 pm. The thickness of the walls 38, measured in a direction parallel to the face 12, is in the range of 100 nm to 50 pm, preferably from 0.5 pm to 10 pm.

[0109] According to one embodiment, the walls 38 can be formed of a reflective material or covered with a coating reflective at the wavelength of the radiation emitted by the photoluminescent blocks 32, 33 and / or the light-emitting diodes.

[0110] Preferably, the walls 38 surround the photoluminescent blocks 32, 33. The walls 38 then reduce crosstalk between adjacent photoluminescent blocks 32, 33.

[0111] The encapsulation layer 46 is at least partially transparent to the radiation emitted by photoluminescent particles and / or light-emitting diodes (LEDs). The encapsulation layer may be made of an inorganic material that is at least partially transparent to the radiation emitted by photoluminescent particles and / or LEDs. By way of example, the inorganic material is chosen from the group including silicon oxides, of the type SiO₂. xwhere x is a real number between 1 and 2 or SiO y N z where y and z are real numbers between 0 and 1, titanium dioxide, aluminum oxides, for example Al₂O₃, and mixtures of these compounds. The encapsulation layer can be made of an organic material that is at least partially transparent. For example, the encapsulation layer is a silicone polymer, an epoxy polymer, an acrylic polymer, or a polycarbonate. The encapsulation layer 46 can have a single-layer or multi-layer structure and may include, for example, a stack of organic and / or inorganic layers.

[0112] Figures 3 to 14 illustrate the structures obtained at successive stages of an embodiment of a manufacturing process for the optoelectronic device 5 shown in Figure 1.

[0113] Figure 3 illustrates the structure obtained after the formation of the germination layer 16 on the face 12 of the substrate 10, the formation of the insulating layer 18 on the germination layer 16, the etching of the openings 20 in the insulating layer 18, and the formation of the light-emitting diodes (LEDs), i.e., the growth of the filaments. in the openings 20, for example by metal-organic chemical vapor deposition (MOCVD) or any other suitable process, and the formation of the shells covering the wires, the formation of the insulating layer 24 at the base of each LED, the formation of the electrode layer 26, the formation of the conductive layer 28, the formation of the dielectric layer 30, and the deposition of a layer 50 of a material transparent to visible light, in particular a dielectric material, filling the spaces between the wires 21 until a substantially flat upper surface 52 is formed above the dielectric layer 30. The layer 50 may be made of a mineral material transparent in the visible spectrum, S1O2, SiN, or Al2O3. The layer 50 may be made of resin, in particular a photosensitive resin.The 50 layer can be deposited by slot-die coating, blade-coating, flexography or screen printing.

[0114] Figure 4 shows the structure obtained after depositing a layer 54, used as an etching mask, onto the transparent layer 50 and, at each desired location of a photoluminescent block 32 of the first type, etching an aperture 56 in the layer 54 and an aperture 58, extending from the aperture 56, in the transparent layer 50 across its entire thickness. The layer 54 can be made of one of the materials described previously for the insulating layer 18, 24, 30, 36, 37, 46. The etching of the insulating layer 54 can be a dry etch, for example, of the ion plasma type, or a wet etch, preferably selective with respect to the material of the transparent layer 50. In the case where the layer 50 is made of S1O2, the layer 54 can be a photosensitive resin and can be removed after the aperture 58 has been created. The etching of the transparent layer 50 maybe an engraving dry, for example of the ionic plasma type, preferentially selective with respect to the protective layer 30.

[0115] Figure 5 shows the structure obtained after completely filling the openings 56, 58 with the material forming the photoluminescent blocks 32 of the first type. This can be achieved by spinning or by coating with a die. The filling step results in the formation of a layer 60 of the material forming the photoluminescent blocks 32 on the insulating layer 54.

[0116] Figure 6 shows the structure obtained after an etching step, specifically chemical-mechanical polishing (CMP), to remove layer 60 and the insulating layer 54, thereby exposing the upper surface 52 of the transparent layer 50. The chemical-mechanical polishing step may include, simultaneously or successively, mechanical polishing and chemical etching steps. In one embodiment, layer 60 may be removed by CMP, with layer 54 then serving as an etching stop layer. Layer 54 may then be removed, for example, by dry etching, such as plasma etching, or by wet etching. The photoluminescent blocks 32 are thus defined. Alternatively, layer 54 may not be removed.

[0117] Figure 7 shows the structure obtained after depositing a layer 62, used as an etching mask, onto the transparent layer 50 and, at each desired location of a photoluminescent block 33 of the second type, etching an aperture 64 in the layer 62 and an aperture 66, extending from the aperture 64, in the transparent layer 50 over the entire thickness of the transparent layer 50. The layer 62 can be made of one of the materials described. previously for the insulating layer 18, 24, 30, 36, 37, 46, 56.

[0118] Figure 8 shows the structure obtained after completely filling the openings 64, 66 with the material forming the photoluminescent blocks 33 of the second type. This can be achieved by spinning or by coating. The filling step results in the formation of a layer 67 of the material forming the photoluminescent blocks 33 on the transparent layer 50.

[0119] Figure 9 shows the structure obtained after a CMP step to remove layer 67 and the insulating layer 62 to expose the upper face 52 of the transparent layer 50. The photoluminescent blocks 33 are thus delineated. Alternatively, layer 67 can be removed by CMP, with layer 62 then serving as a stop layer. Layer 62 can then be removed, for example, by dry etching, in particular plasma etching, or by wet etching. Alternatively, layer 62 may not be removed.

[0120] Figure 10 represents the structure obtained after the deposition of a layer 68, used as an etching mask, on the transparent layer 50 and the photoluminescent blocks 32, 33 and, at each desired location of a wall 38, the etching of an opening 70 in the layer 68.

[0121] Figure 11 shows the structure obtained after engraving, for each aperture 70, an aperture 72 extending from the aperture 70 into the transparent layer 50, across the entire thickness of the transparent layer 50. The layer 68 may then be retained or removed. The remaining portions of the transparent layer 50 form the transparent blocks 34. If the layer 50 is made of S1O2, the layer 68 may be a layer of a photosensitive resin and may be removed after the aperture 72 has been created.

[0122] Figure 12 shows the structure obtained after the insulating layer 37 has been deposited over the entire structure shown in Figure 11. The insulating layer 37 can be deposited by a conformal deposition process, in particular an atomic layer deposition (ALD) process. The insulating layer 37 can, in particular, be a moisture- and / or airtight layer and act as a protective layer for the photoluminescent blocks 32, 33. Advantageously, the layer 37 is deposited immediately after the formation of the photoluminescent blocks 32, 33.

[0123] Figure 13 represents the structure obtained after the deposition, over the whole of the structure shown in Figure 12, of a layer 76 in the material composing the coatings 42 of the walls 38, and after the filling of the openings 72 by the material composing the cores 40 of the walls 38, which leads to the formation of a layer 78 of the filling material on the blocks 32, 33, 34.

[0124] Figure 14 represents the structure obtained after an etching step, to remove the parts of layer 78 of the filling material and the parts of layer 76 located outside the openings 72 until the parts of the insulating layer 37 covering the portions of the insulating layer 68 are exposed, thus delimiting the walls 38, in particular the cores 40 and the coverings 42. As an example, the parts of layer 78 outside the openings 72 can be removed by dry etching and the parts of layer 76 located outside the openings 72 can be removed by wet or dry etching.

[0125] The process includes additional steps of forming the color filters 44 and the protective layer 46.

[0126] Figures 15 to 27 illustrate the structures obtained at successive stages of another embodiment of a manufacturing process for the optoelectronic device 5.

[0127] Figure 15 illustrates the structure obtained after steps identical to those described previously in relation to figures 3, 4, 5 and 6, with the difference that, in the CMP step, the insulating layer 54 is not removed.

[0128] Figure 16 represents the structure obtained after the deposition of layer 62, used as an etching mask, on the whole of the structure and, at each desired location of a photoluminescent block 33 of the second type, the etching of an opening 64 in layer 62, of an opening 79 in layer 54 extending the opening 64 and of the opening 66, extending the opening 64, in the transparent layer 50 over the entire thickness of the transparent layer 50.

[0129] Figure 17 shows the structure obtained after steps similar to those described previously in relation to Figure 8, that is, after completely filling openings 64, 79, and 66 with the material forming the second type of photoluminescent blocks 33. This can be a spinning deposition process. The filling step results in the formation of layer 67 of the material forming the photoluminescent blocks 33 on the insulating layer 62.

[0130] Figure 18 shows the structure obtained after a CMP step to remove layer 67 until reaching the insulating layer 62, which is not removed. The photoluminescent blocks 33 are thus delimited.

[0131] Figures 19 and 20 illustrate steps analogous to those described previously in relation to Figures 10 and 11 and represent the structure obtained after the deposition of layer 68, used as an etching mask, over the entire structure and at each desired location of a wall 38, the engraving of an opening 70 in layer 68, possibly of an opening 80 in layer 62 extending the opening 70, of an opening 81 in layer 54 extending the opening 70, and the engraving of the opening 72, extending the opening 70, in the transparent layer 50 over the entire thickness of the transparent layer 50.

[0132] Figure 21 represents the structure obtained after a CMP step to remove insulating layers 54, 62 and 68. This step may not be present.

[0133] Figure 22 represents the structure obtained after steps analogous to the steps described previously in relation to Figure 13 and including the deposition, over the whole of the structure represented in Figure 21, of the insulating layer 76 in the material composing the coatings 42 of the walls 38 and after the filling of the openings 72 by the material composing the cores 40 of the walls 38, which leads to the formation of the layer 78 of the filling material on the blocks 32, 33, 34.

[0134] Figure 23 represents the structure obtained after a CMP or dry etching step to remove layer 78 of the filling material and the parts of layer 76 located outside the openings 72 until the parts of the insulating layer 37 covering the insulating layers 36 are exposed, thus delimiting the walls 38.

[0135] Figure 24 represents the structure obtained after the deposition of a layer 82, used as an etching mask, over the whole structure and, at each desired location of a photoluminescent block of a third type, the etching of an opening 83 in the layer 82.

[0136] Figure 25 represents the structure obtained after engraving an opening 84, extending the opening 82 in the transparent layer 50 over the entire thickness of the transparent layer 50 and after removing layer 80.

[0137] Figure 26 shows the structure obtained after completely filling the openings 84 with the material forming the third type of photoluminescent blocks. This could be a spin-on deposition. The filling step results in the formation of a layer 88 of the material forming the photoluminescent blocks on the rest of the structure outside the openings 84.

[0138] Figure 27 shows the structure obtained after a CMP step to remove layer 88. Photoluminescent blocks 90 of the third type are thus delineated. In the case where there are no transparent blocks 34, as described previously, covering LEDs, it is not necessary for layer 50 to be made of a highly transparent material, since no portions of this layer 50 will be covering LEDs at the end of the manufacturing process.

[0139] The process includes additional steps of forming the color filters 44 and the protective layer 46.

[0140] Figures 28 to 31 illustrate the structures obtained at successive stages of another embodiment of a manufacturing process for the optoelectronic device 5.

[0141] The initial steps of the process include all the steps described previously in relation to figures 3 to 18.

[0142] Figure 28 shows the structure obtained after the deposition of layer 82, used as an etching mask, over the entire structure and, at each desired location of a third-type photoluminescent block 90, the etching of the opening 83 in layer 82, of an opening 92 in layer 62 extending the opening 83, of an opening 94 in layer 54 extending the opening 83, and the engraving of the opening 84, extending the opening 83 in layer 50 over the entire thickness of layer 50.

[0143] Figure 29 shows the structure obtained after completely filling the openings 84 with the material forming the third type of photoluminescent blocks 90. This could be a spin-on deposition. The filling step results in the formation of the layer 88 of the material forming the photoluminescent blocks 90 on the rest of the structure outside the openings 84.

[0144] Figure 30 represents the structure obtained after a CMP step to remove layer 88. The photoluminescent blocks 90 of the third type are thus delimited.

[0145] In the embodiments described above, the steps for forming apertures 58, 66, 84 in layer 50 involve the use of etching masks. According to another embodiment, the steps for etching the apertures in layer 50 can be performed directly by photolithography steps when layer 50 is made of a photosensitive resin.

[0146] Figure 31 shows the structure obtained after a selective etching step to remove mask layers 54, 62, 82 and remove portions of the transparent layer 50 remaining between the photoluminescent blocks 32, 33, 90.

[0147] The process can then include the steps described previously in relation to figures 13 and 14, in particular for the formation of the walls 38 in the openings freed up between the photoluminescent blocks 32, 33, 90.

[0148] Figures 32 to 39 illustrate the structures obtained at successive stages of another embodiment of a manufacturing process for the optoelectronic device 5.

[0149] The initial steps of the process include all the steps described previously in relation to the figure 3.

[0150] Figure 32 represents the structure obtained after the deposit of layer 68, used as an etching mask, on the transparent layer 50 and, at each desired location of a wall 38, the etching of an opening 70 in layer 68.

[0151] Figure 33 represents the structure obtained after engraving the opening 72, extending each opening 70, in the transparent layer 50 over the entire thickness of the transparent layer 50.

[0152] Figure 34 represents the structure obtained after steps analogous to the steps described previously in relation to Figure 13 and including the deposition, over the whole of the structure represented in Figure 33, of the insulating layer 76 in the material composing the coatings 42 of the walls 38, and after the filling of the openings 72 by the material composing the cores 40 of the walls 38, which leads to the formation of the layer 78 of the filling material on the transparent layer 50.

[0153] Figure 35 represents the structure obtained after an etching step to remove layer 78 of the filling material and the parts of layer 76 located outside the openings 72, thus delimiting the walls 38. As previously described, the parts of layer 78 outside the openings 72 can be removed by dry etching or CMP and the parts of layer 76 located outside the openings 72 can be removed by wet or dry etching.

[0154] Figures 36 to 39 represent the structures obtained in the steps described above in relation to Figures 24 to 27 respectively, and lead to the formation of the first type of photoluminescent blocks 32. These steps are repeated once for the formation of the second type of photoluminescent blocks 33 and possibly once for the formation of the third type of photoluminescent blocks 90.

[0155] Figures 40 to 52 illustrate the structures obtained at successive stages of another embodiment of a manufacturing process for the optoelectronic device 5.

[0156] The initial steps of the process include all the steps described previously in relation to the figure 3.

[0157] Figure 40 represents the structure obtained after the deposition of a layer 100, used as an etching mask, and covering the transparent layer 50, and of a layer 102 of a photosensitive resin covering the layer 100. The layer 100 can be in one of the materials described previously for the insulating layer 18, 24, 30, 36, 37, 46.

[0158] Figure 41 represents the structure obtained after engraving an aperture 104 in layer 102 and an aperture 106, extending the aperture 104, in layer 100 at each desired location of a photoluminescent block 32 of the first type.

[0159] Figure 42 shows the structure obtained after the removal of the photosensitive resin layer 102 and the deposition of an insulating layer 106 over the entire structure. The layer 106 can be made of one of the materials described previously for the insulating layer 18, 24, 30, 36, 37, 46.

[0160] Figure 43 shows the structure obtained after etching the insulating layer 106, resulting in the formation of portions 108 of the insulating layer 106, called spacers, on the sides of each opening 104 and the withdrawal of the insulating layer 106 elsewhere. The engraving can be a dry engraving.

[0161] Figure 44 represents the structure obtained after engraving an opening 110 in the transparent layer 50 over the entire thickness of the transparent layer 50, the opening 110 being delimited by the mask formed by the layer 100 and the spacers 108.

[0162] Figure 45 shows the structure obtained after completely filling the openings 110 with the material forming the photoluminescent blocks 32 of the first type. This could be a spin-on deposition. The filling step results in the formation of the layer 88 of the material forming the photoluminescent blocks 32 on the rest of the structure outside the openings 110.

[0163] Figure 46 represents the structure obtained after a CMP step to remove layer 88. The photoluminescent blocks 32 of the first type are thus delimited.

[0164] Figure 47 represents the structure obtained after repeating the steps described above in relation to Figures 40 to 45 for the delimitation of the photoluminescent blocks 33 of the second type.

[0165] Figure 48 represents the structure obtained after removing the spacers 108, for example a selective etching with respect to the materials composing the photoluminescent blocks 32, 33, the material composing the transparent layer 50 and the material composing the insulating layer 100. It can be a dry etching or a wet etching.

[0166] Figure 49 shows the structure obtained after etching openings 112 in the transparent layer 50, extending from the openings formed by the removal of the spacers 108, over the entire thickness of the transparent layer 50.

[0167] Figure 50 represents the structure obtained after the deposition, over the entire structure shown in Figure 5, of the insulating layer 37.

[0168] Figure 51 represents the structure obtained after filling the openings 102 with the material composing the cores 40 of the walls 38, which results in the formation of layer 78 of the filling material on the blocks 32, 33, 34.

[0169] Figure 52 represents the structure obtained after a CMP step to remove layer 78 of the filling material and the parts of layer 76 located outside the openings 112 until the parts of the insulating layer 37 covering the upper faces of the blocks 32, 33, 34 are exposed, thus delimiting the walls 38.

[0170] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to them. In particular, the manufacturing processes for optoelectronic devices may include additional steps not described, such as transferring the structure onto intermediate supports, also called handles, to allow for manipulation. Finally, the practical implementation of the described embodiments and variations is within the grasp of those skilled in the art, based on the functional specifications given above.

Claims

DEMANDS 1. Method of manufacturing an optoelectronic device (5) comprising assemblies of light-emitting diodes (LEDs) including first and second assemblies and first blocks (32) of a first photoluminescent material each covering one of the first assemblies, the method comprising the formation of a layer (50) covering the first and second assemblies, the delimitation of first openings (58) in the layer to expose the first assemblies, the filling of the first openings of the first material and the performance of a mechano-chemical polishing to delimit the first blocks.

2. Method according to claim 1, wherein the device comprises second blocks (33) of a second photoluminescent material, different from the first photoluminescent material, each covering one of the second assemblies, the delimitation of second openings (66) in the layer (50) to expose the second assemblies, the filling of the second openings with the second material and the performance of a mechano-chemical polishing to delimit the second blocks.

3. Method according to claim 2, wherein the device further comprises third sets of light-emitting diodes (LEDs) and third blocks (90) of a third photoluminescent material, different from the first and second photoluminescent materials, each covering one of the third sets, the delimitation of third openings (84) in the layer (50) to expose the third sets, the filling of the third openings of the third material and the performance of a mechano-chemical polishing to delimit the third blocks.

4. A method according to any one of claims 1 to 3, wherein the device further comprises fourth sets of light-emitting diodes (LEDs), the method comprising the delimitation of fourth blocks (34) in the layer (50) each covering one of the fourth sets of light-emitting diodes.

5. Method according to claim 4, wherein the layer (50) is at least partially transparent to the radiation emitted by the light-emitting diodes (LEDs) of the fourth sets of light-emitting diodes.

6. A method according to any one of claims 1 to 5, comprising the delimitation of fourth openings (72) in the layer (50) between the assemblies and the formation of walls (38) with reflective walls in the fourth openings.

7. Method according to claim 6, comprising depositing a reflective coating (42) in the fourth openings (72) and filling the remainder of the fourth openings with a fifth material.

8. Method according to claim 6, wherein the walls (38) are formed after the first photoluminescent blocks (32).

9. Method according to claim 8, comprising the formation of a barrier layer (37) extending into the fourth openings (72) and covering the first photoluminescent blocks (32) before the formation of the walls (38).

10. Method according to claim 7 in relation to claim 2, wherein the walls (38) are formed after the first and second photoluminescent blocks (32, 33).

11. Method according to claim 6 in relation to claim 2, wherein the walls (38) are formed before the first and second photoluminescent blocks (32, 33).

12. A method according to claim 6 in relation to claim 3, comprising etching the layer (50) present between the first, second and third photoluminescent blocks (32, 33, 90), forming a barrier layer (37) extending into the fourth openings (72) and covering the first, second and third photoluminescent blocks (32, 33, 90) before the formation of the walls (38) and forming the walls (38) in the spaces present between the first, second and third photoluminescent blocks (32, 33, 90).