OPTOELECTRONIC DEVICE

Description

Domaine technique

[0001] The present description relates generally to an optoelectronic device and its method of manufacturing, for example a light-emitting diode image display device and its method of manufacturing. Technique antérieure

[0002] It is known to produce an optoelectronic device comprising at least one light-emitting diode and a control circuit for this light-emitting diode.

[0003] Document US10468452 describes a method for manufacturing such a device comprising the simultaneous manufacturing of several copies of the optoelectronic device on a single substrate and the separation of the optoelectronic devices thus manufactured. A disadvantage of such a method is that it includes the formation of electrodes covering the sides of the optoelectronic devices, which can be a difficult step to carry out.

[0004] US2019 / 139949, US2019 / 165231, US2017 / 179097, US2015362165 and US2017 / 133550 describe an optoelectronic device with a stack of a circuit comprising a light-emitting diode and a circuit for controlling the light-emitting diode. 1

[0005] WO2019180362 describes an optoelectronic device with a stack of a circuit comprising a light-emitting diode and a circuit for driving the light-emitting diode, in which a connection structure, comprising the superposition of a first and second dielectric sub-layer with connection pads, is located at the interface between the circuits. Summary of the invention

[0006] There is a need for improvement of optoelectronic devices and their manufacturing processes.

[0007] An embodiment overcomes all or part of the drawbacks of known optoelectronic devices and their manufacturing methods.

[0008] The invention provides an optoelectronic device according to claim 1.

[0009] According to one embodiment, the device comprises at least two connectors, located on the second circuit, on the side opposite the first circuit, intended to electrically connect the device to an external object.

[0010] According to one embodiment, the first and second conductive pads are separated by said electrical insulation trench.

[0011] According to one embodiment, the second circuit comprises metal oxide gate field effect transistors and comprises two parts electrically separated by said electrical isolation trench.

[0012] According to one embodiment, the parts of the second circuit are electrically connected by connections via electrically conductive tracks located on the side of the metal oxide gate field effect transistors opposite the first circuit.

[0013] According to one embodiment, the electrical insulation trench has a closed shape, in a plane parallel to the second face.

[0014] According to one embodiment, the electrical insulation trench has, in a plane parallel to the second face, an open shape whose two free ends open onto one or more sides of the device.

[0015] According to one embodiment, the first circuit comprises a substrate on the side of the first face.

[0016] According to one embodiment, the substrate is made of sapphire or glass.

[0017] According to one embodiment, the conductive layer is made of metal or a conductive polymer.

[0018] According to one embodiment, the light-emitting diode is wire-shaped or pyramid-shaped.

[0019] One embodiment provides a structure comprising a plurality of optoelectronic devices as described above.

[0020] The invention also provides a method of manufacturing a plurality of optoelectronic devices according to claim 9.

[0021] According to one embodiment, assembly step a) is carried out by bringing the first and second sub-layers of the electrically conductive layer into contact, in the full plate.

[0022] According to one embodiment, each first circuit is partially etched in a step b) prior to step a) so as to define a first cavity located at the location of the second electrode.

[0023] According to one embodiment, each first circuit is partially etched in a step b') prior to step a) so as to produce a second cavity making it possible to define the edges of said light-emitting diode.

[0024] According to one embodiment, the method comprises a step c), between steps a) and b) or b'), in which each light-emitting diode is covered, on the side of the second face of the first circuit, with a dielectric layer open at the level of the first and second electrodes.

[0025] According to one embodiment, between step c) and step a), each light-emitting diode is covered, on the side of the second face of the first circuit, with the first conductive sub-layer.

[0026] According to one embodiment, each second circuit is covered, before step a), with the second conductive sub-layer.

[0027] According to one embodiment, assembly step a) is carried out by non-hybrid bonding of the first conductive sub-layer with the second conductive sub-layer.

[0028] According to one embodiment, step a) is followed by a step d) of etching, for each optoelectronic device, a trench extending in the second plate and in the electrically conductive layer up to the dielectric layer.

[0029] According to one embodiment, step d) is followed by a step of filling the trench with an insulating material in order to create the electrical insulation trench. Brève description des dessins

[0030] These and other features and advantages will be set forth in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which: there figure 1A illustrates a partial and schematic sectional view of an embodiment of an optoelectronic device; the figure 1B illustrates a partial and schematic sectional view of a variant of the optoelectronic device shown in figure 1A ; there figure 2 illustrates a partial and schematic top view of an embodiment of an optoelectronic device; the figure 3 illustrates a partial and schematic top view of another embodiment of an optoelectronic device; the figure 4 illustrates a step of an implementation mode of a manufacturing process of the device illustrated in figure 1A Or 1B ; there figure 5 illustrates another step in the process; the figure 6 illustrates another step in the process; the figure 7 illustrates another step in the process; the figure 8 illustrates another step in the process; the figure 9 illustrates another step in the process; the figure 10 illustrates another step in the process; the figure 11 illustrates another step in the process; the figure 12 illustrates another step in the process; the figure 13 illustrates another step in the process; the figure 14 is a detail view of part of the figure 13 ; there figure 15 illustrates another step in the process; the figure 16 illustrates another step in the process; the figure 17 illustrates a step of another mode of implementation of a method of manufacturing the device illustrated in figure 1A Or 1B ; and the figure 18 illustrates another step in the process. Description des modes de réalisation

[0031] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0032] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the control circuits of the light-emitting diodes of the optoelectronic devices have only been detailed briefly.

[0033] Unless otherwise specified, when referring to two elements connected together, this means directly electrically connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be electrically connected or be electrically connected through one or more other elements.

[0034] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0035] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%. In addition, the terms "insulator" and "conductor" are considered here to mean "electrically insulating" and "electrically conducting", respectively.

[0036] THE figures 1A represents a partial and schematic sectional view of an embodiment of an optoelectronic device 11 and the figure 1B represents a sectional view of a variant of the optoelectronic device 11 of the figure 1B . There figure 2 is a partial and schematic top view of the optoelectronic device 11 of the figure 1A .

[0037] On the figures 1A And 1B , some of the internal elements of the device 11 have been shown.

[0038] Device 11 includes: a first portion 13, also called an optoelectronic circuit, comprising at least one inorganic light-emitting diode LED emitting radiation in particular towards a lower face 13i of the first portion 13, the first portion 13 further comprising an upper face 13s opposite the lower face 13i; and a second portion 15, also called a logic circuit, comprising a control circuit for the light-emitting diode LED, and comprising a lower face 15i and an upper face 15s opposite the lower face 15i, the lower face 15i of the second portion 15 being on the upper face 13s of the first portion 13.

[0039] According to the embodiment illustrated on the figures 1A And 1B, the device 11 comprises, at the interface between the optoelectronic circuit 13 and the logic circuit 15, a layer 17 divided horizontally, that is to say in the plane of the upper face 13s, the layer 17 comprising a stack of a first sub-layer 173 located in the optoelectronic circuit 13 and a second sub-layer 175 located in the logic circuit 15. As described in more detail below, the layer 17 is divided into two parts horizontally in the orientation of the figure 1A , that is to say in the plane of the upper face 13s.

[0040] Layer 17 is made of a conductive material, for example, a metallic material or a conductive polymer. Layer 17 is preferably made of titanium, aluminum, nickel, silver, copper, gold or an alloy or a combination of all or part of these materials.

[0041] The upper face of the sub-layer 173 corresponds to the upper face 13s of the optoelectronic circuit 13 and the lower face of the sub-layer 175 corresponds to the lower face 15i of the logic circuit 15.

[0042] The light-emitting diode LED of the optoelectronic circuit 13 comprises, according to the embodiment illustrated in the figures 1A And 1B , at least two semiconductor layers of opposite conductivity types defining, for example, a PN junction.

[0043] The light-emitting diode LED thus comprises a semiconductor layer 19, of a first conductivity type, for example of type N, and a semiconductor layer 21, of a second conductivity type, for example of type P, different from the first conductivity type. The layer 21 may have a dopant concentration of between 10 15< and 10 20< dopants / cm3 and have a thickness of between 5 nm and 2 µm. The layer 19 may have a dopant concentration of between 10 17< and 10 20< dopants / cm3 and have a thickness of between 50 nm and 2 µm. The layers 19 and 21 are, for example, made of a III-V compound or a II-VI compound, for example GaN (gallium nitride). The layers 19 and 21 may each have a single-layer structure or a multi-layer structure.

[0044] The light-emitting diode LED of the optoelectronic circuit 13 further comprises an active layer 25 located between the layers 19 and 21. The active layer 25 is the layer in which most of the radiative recombinations occur, leading to the light emission of the light-emitting diode LED. The active layer 25 has, for example, a multiple quantum well structure.

[0045] According to the embodiment illustrated on the figures 1A And 1B, the layer 19 rests on a substrate 27. More particularly, the layer 19 completely covers the upper face of the substrate 27. The substrate 27 may correspond to a growth substrate of the material making up the layer 19 and be, for example, made of sapphire. The substrate 27 may, as a variant, correspond to a transfer substrate, for example a glass transfer substrate replacing a silicon growth substrate. Layer 25 preferably covers layer 19 and layer 25 is covered by layer 21. Layer 17 covers layer 21. The lateral edges of layers 21, 25 may have a recess 26 relative to layer 19. Device 11 further comprises a conductive via 28 passing through layers 21, 25, electrically insulated from layers 21, 25, and electrically connecting sub-layer 173 of layer 17 to layer 19. According to another embodiment, conductive via 28 is located on an edge of layers 21 and 25.The sub-layer 173 has, for example, a thickness greater than 1.5 µm. On the . figures 1A And 1B , the via 28 is shown stopping on the upper face of the layer 19. Alternatively, the via 28 can penetrate into the layer 19 over a portion of the thickness of the layer 19.

[0046] The optoelectronic circuit 13 further comprises a first electrode 23, for example the anode of the LED, arranged on and in contact with the layer 21 and a second electrode 24, for example the cathode of the LED, corresponding to the contact between the via 28 and the layer 19.

[0047] The first electrode 23 is, for example, made of a metallic material such as nickel, silver, gold, aluminum, copper, titanium or an alloy or a combination of all or part of these materials. The first electrode 23 has a thickness, for example, between 200 nm and 900 nm. The first electrode 23 may have a single-layer or multi-layer structure.

[0048] According to the embodiment illustrated on the figures 1A And 1B , the optoelectronic circuit 13 further comprises a dielectric layer 29. The dielectric layer 29 preferably covers the periphery of the first electrode 23, a portion of the layer 21 not covered by the first electrode 23, the lateral edges of the layers 21, 25 at the level of the recess 26 and the via 28, and the layer 19 at the level of the recess 26 and only a portion of the layer 19 at the level of the via 28. The dielectric layer 29 serves as electrical insulation, but also as passivation of the lateral edges of the active layer 25 which may in particular comprise quantum wells.

[0049] Layer 29 has, for example, a thickness of between 0.1 µm and 1 µm, and is made of a dielectric material such as silicon nitride or silicon dioxide or a combination of these two materials.

[0050] In the embodiment shown in the figures 1A And 1B, the light-emitting diode has a so-called planar structure insofar as it corresponds to a stack of layers. According to another particular embodiment, the optoelectronic circuit 13 may comprise a light-emitting diode or several three-dimensional light-emitting diodes, for example of wire shape or pyramid shape. In particular, the light-emitting diode LED may comprise a three-dimensional semiconductor element, or several three-dimensional semiconductor elements, for example nanowires or microwires, each three-dimensional semiconductor element being of the first type of conductivity and being covered with an active zone, itself covered with a semiconductor element of the second type of conductivity.The electrode 23 may be in contact with the semiconductor elements of the second conductivity type, while the semiconductor elements of the first conductivity type may rest on a conductive layer in contact with the via 28.

[0051] The logic circuit 15 comprises an area 33, called a MOS circuit, comprising a first part 331 comprising a substrate in and on which insulated gate field effect transistors, also called MOS transistors, are formed. The substrate may correspond to a semiconductor substrate or may have a silicon-on-insulator (SOI) type structure. The MOS circuit 33 further comprises a first interconnection network 333 located between the first part 331 and the layer 17 and comprising a stack of insulating layers between which and through which conductive tracks and conductive vias are arranged. In particular, the first interconnection network 333 comprises electrically conductive pads 31 and 32.

[0052] The logic circuit 15 further comprises a second interconnection network 30, located on the MOS circuit 33, on the side of the MOS circuit 33 opposite the optoelectronic circuit 13 and which can also extend through the MOS circuit 33.

[0053] The pads 32 are intended to electrically connect the MOS circuit 33 and the interconnection network 30. The pads 31 are each intended to be electrically connected to an electrode of the light-emitting diode of the optoelectronic circuit 13 via the layer 17. The electrically conductive pads 31, 32 are preferably made of titanium, aluminum, silver, nickel, copper, gold or an alloy or a combination of all or part of these materials.

[0054] The device 11 further comprises an electrical insulation structure 39 comprising: an electrical insulation trench 391 for ensuring horizontal electrical insulation, i.e. insulation in a plane parallel to the face 15i between two parts of the MOS circuit 33 and between two parts of the layer 17; and optionally, an insulating layer 393 covering the MOS circuit 33 on the side of the MOS circuit 33 opposite the optoelectronic circuit 13 and having the same composition as the insulation trench 391.

[0055] The isolation layer 393 is preferably located in the interconnection network 30 at the interface with the MOS circuit 33. The layer 393 and the trench 391 may have a multi-layer or single-layer structure. All or part of the layer 393 and the trench 391 are preferably made of a dielectric material. For example, the electrical isolation trench 391 may include electrically insulating walls and a core made of a filler material, for example a conductive or semiconductive material. For illustrative purposes, the isolation trench 391 is shown in the figures 2 et 3 .

[0056] Trench 391 extends from the top face of MOS circuit 33 in the orientation of the figure 1A through the MOS circuit 33, and the layer 17 so as to open onto the dielectric layer 29. The trench 391 may be filled with a material having a multi-layer or single-layer structure. The trench 391 is preferably filled with a dielectric material.

[0057] Preferably, there is at least one pad 31 on each side of the trench 391.

[0058] Trench 391 has, according to the embodiment illustrated in figure 2 , an open shape opening onto at least one side of the device 11, here onto two sides of the device 11. The trench 391 insulates in particular a lateral portion of the MOS circuit 33 and a lateral portion of the conductive layer 17 connected to the second electrode 24 of the light-emitting diode. For example, in the orientation of the figure 2 , trench 391 is "L" shaped and opens onto the upper side of device 11 and onto the right side of device 11.

[0059] According to the embodiment illustrated on the figures 1A And 1B , the interconnection network 30 comprises a stack of insulating layers 37 covering the MOS circuit 33 on the side of the MOS circuit 33 opposite the optoelectronic circuit 13, including the layer 393 when it is present, in which and through which conductive elements are formed, in particular conductive tracks 35 and conductive vias 36. According to one embodiment, each conductive via 36 can be connected to one of the tracks of the first interconnection network 333, for example to one of the pads 32, and thus extend through the first part 331.

[0060] According to one embodiment, there are conductive elements 35, 36 on each side of the electrical insulation trench 391. These elements, on either side of the electrical insulation trench 391, can be electrically connected, for example, by one of the conductive tracks 35, as shown in the figure 1B .

[0061] According to the embodiment illustrated on the figures 1A And 1B , the logic circuit 15 further comprises connectors 41 of which at least one of the connectors 41 is connected to the first electrode 23 and at least one other of the connectors 41 is connected to the layer 19.

[0062] For example, the connectors 41 are made of titanium, aluminum, silver, nickel, copper, gold, tin, tin-silver alloy, or an alloy or combination of all or part of these materials.

[0063] According to the embodiment shown in the figure 1A , the connectors 41 may be located on either side of the isolation trench 391. However, the position of the connectors 41 does not depend on the position of the electrical isolation trench 391, the connectors 41 not in particular necessarily being aligned with the conductive vias 36, so that the connectors 41 may be located on the same side of the isolation trench 391 as shown in figure 1B . The electrical conductors 35 may for example connect a connector 41 disposed on one side of the insulation trench 391 and a conductive via 36 disposed on the other side of the trench 391. Furthermore, as illustrated in the figure 1B , an electrical conductor 35 can electrically connect two conductive vias 36 arranged on either side of the isolation trench 391 and electrically connect pads 32 of the first interconnection network 333 of the MOS circuit 33. The conductive tracks 35 can play the role of a redistribution layer, also called RDL (English acronym for ReDistribution Layer), that is to say correspond to an additional metal layer covering the MOS circuit 33 which electrically connects the connectors 41 to other locations of the MOS circuit 33, in particular to release the constraints of positioning the connectors 41. The conductive tracks 35 make it possible in particular to electrically connect a connector 41, located on the part of the MOS circuit 33 located on one side of the trench 391, to the part of the MOS circuit 33 located on the other side of the trench 391.

[0064] According to one embodiment, not shown, the MOS circuit 33 only comprises transistors on one side of the isolation trench 391. The pad 31 located in the part of the MOS circuit 33 not comprising a transistor is then connected to the second interconnection network 30 without intermediate connection by MOS transistors.

[0065] There figure 3 illustrates, by a top view, a variant of the device 11 illustrated in figure 2 .

[0066] According to the embodiment illustrated in figure 3 , the trench 391 follows, in top view, a closed curve, and thus has an annular shape isolating in particular a central island of the MOS circuit 33 and a central island of the conductive layer 17 connected to the second electrode 24 of the light-emitting diode.

[0067] THE figures 4 à 16 illustrate steps of an embodiment of a method of manufacturing the device 11 illustrated in the figures 1A And 1B .

[0068] THE figures 4 à 7 are each partial and schematic sectional views of structures obtained at successive stages of an embodiment of the method for manufacturing a wafer comprising several examples of the optoelectronic circuit 13 illustrated in the figures 1A and / or 1B.

[0069] There figure 4 illustrates a starting structure 45 from which several devices 11 are produced.

[0070] The structure 45 comprises, from bottom to top, in the orientation of the figure 4 : substrate 27; layer 19; active layer 25; and layer 21.

[0071] The substrate 27 corresponds, for example, to a circular semiconductor wafer having a diameter preferably of the order of 150 mm, 200 nm or 300 nm. The layers 19, 25, 21 are all formed as a full wafer so as to cover substantially the entire upper surface of the substrate 27.

[0072] There figure 5 illustrates a structure 47 obtained at the end of the formation, for each device 11, of the first electrode 23 on the upper face of the structure 45 illustrated in figure 4 .

[0073] The material constituting the first electrode 23 is deposited, for example, full plate before being etched in order to keep, for each device 11, the first electrode 23 only in the desired area. The electrode 23 is, for example, produced by the lift-off technique consisting of the deposition of a layer of resin, the formation of patterns in the resin layer, then a deposition of a metal layer on the entire structure and in particular the resin patterns. The resin is then dissolved in a solvent, carrying away the portions of metal covering the resin patterns. The metal deposition is, for example, carried out by physical vapor deposition (PVD) or by chemical vapor deposition (CVD).

[0074] There figure 6 illustrates a structure 49 obtained at the end of a step of etching and depositing the insulating layer 29 on the upper face of the structure 47 illustrated in figure 5 .

[0075] Structure 47 is, during the step illustrated in figure 6 , etched so as to form, for each device 11, openings 261, 281 over a height h1, greater than or equal to the sum of the thicknesses of the layers 21 and 25, for example, of the order of 0.5 µm. During this etching step, a part of the layer 19 opposite the openings 261 and 281 can be etched in addition to the layers 21 and 25. Only two openings 261 and one opening 281 have been shown in figure 6 . The openings 261 are located at the locations at which a cutting operation of the devices 11 will be carried out at a later stage. The openings 281 are located at the locations of the vias 28.

[0076] The openings 261 have, for example, a width l1 of the order of 50 µm and the openings 281 have, for example, a width l2 of the order of 10 µm in the section plane of the figure 6 .

[0077] The insulating layer 29 is preferably deposited on the surface of the structure obtained after etching the openings 261, 281 so that the layer 29 covers the upper face of the layer 21, the upper face of the electrodes 23, the lateral edges of the openings 261, 281 and the bottom of the openings 261, 281. The thickness of the layer 29 is for example of the order of 1 µm.

[0078] The insulating layer 29 is subsequently etched, for example by wet or dry etching, in order to reveal, for each device 11, a part of the electrode 23 and a part of the layer 19. The etching makes it possible to reveal the layer 19 in the openings 281 over a width l3, for example, of the order of 5 µm, in the section plane of the figure 6 .

[0079] There figure 7 illustrates a structure 50 obtained at the end of a step of depositing a conductive layer 51 on the upper face of the structure 49 illustrated in figure 6 so as to form the conductive sub-layer 173 and the vias 28. A wafer comprising several copies of the optoelectronic circuit 13 is thus obtained.

[0080] The conductive layer 51 is preferably deposited over the entire upper face of the structure 49 so that the conductive layer 51 covers the insulating layer 29, comes into contact with the electrodes 23 and comes into contact with the semiconductor layer 19 in the openings 281. The conductive layer 51 further extends into the openings 261.

[0081] At the end of the step of depositing the conductive layer 51, the structure is optionally planarized by chemical mechanical polishing (CMP, Chemical Mechanical Planarization).

[0082] There figure 8 illustrates a structure 52 comprising, from top to bottom in the orientation of the figure 8 : a substrate 53; and the underlayer 175.

[0083] The substrate 53 preferably comprises several copies of the MOS circuit 33 and an area 55 free of all electronic components.

[0084] The substrate 53 is, for example, a semiconductor wafer on and in which electronic components have been formed. The substrate 53 preferably has a diameter of the order of 100 mm, 200 mm or 300 mm. The MOS circuits 33 form the lower part of the substrate 53, in the orientation of the figure 8 and area 55 is the upper part of substrate 53, in the orientation of the figure 8 .

[0085] The 175 sub-layer has, for example, a thickness greater than 500 nm.

[0086] Optionally, in order to planarize the lower face of the structure 52 and, more precisely, of the underlayer 175, the latter can undergo chemical-mechanical polishing CMP.

[0087] There figure 9 illustrates a structure 57 obtained at the end of an assembly step of the structure 50 illustrated in figure 7 and structure 52 illustrated in figure 8 .

[0088] The structure 52 is transferred to the upper face of the structure 50. More precisely, a lower face 175i of the sub-layer 175 of the structure 52 is transferred to an upper face 173s of the sub-layer 173 of the structure 50. The step of transferring the structure 52 to the structure 50 preferably comprises an alignment sub-step so that the MOS circuits 33 are aligned with the openings 261.

[0089] According to one embodiment, the adhesion of the sub-layers 173 and 175 is achieved by non-hybrid conductive bonding, i.e. the faces of the sub-layers coming into contact are flat, continuous and formed from a single material. The materials composing the two sub-layers are identical. Thus, 173 and 175 adhere to each other, without bonding material.

[0090] There figure 10 illustrates a structure 59 obtained at the end of a step of thinning the structure 57 illustrated in figure 9 .

[0091] The thinning of structure 57 illustrated in figure 9 is produced by its upper face so as to remove the zone 55 from the substrate 53 and only keep the MOS circuits 33 in the substrate 53.

[0092] There figure 11 illustrates a structure 61 obtained at the end of a step of forming trenches 63 in the structure 59 illustrated in figure 10 , a single trench 63 being represented in figure 11 .

[0093] The trenches 63 preferably extend from the upper face of the structure 61 into the MOS circuits 33, the sub-layer 175 and the sub-layer 173 so as to expose the upper face of the insulating layer 29.

[0094] The trenches 63 are preferably produced by a succession of two dry or wet etchings, one allowing the different layers of the MOS circuit 33 to be etched and the other allowing the sub-layers 173 and 175 to be etched. The insulating layer 29 can act as an etching stop layer during the formation of the trenches 63.

[0095] Preferably, a single trench 63 is produced per device 11, i.e. each opening 261 surrounds a single trench 63. Each trench 63 is intended to become an isolation trench 391 as shown in the figures 1A , 1B And 2 . The trenches 63 therefore have the same shape as the isolation trenches 391.

[0096] The trenches 63 preferably have a width l4 of the order of 5 µm in the cutting plane of the figure 11 .

[0097] There figure 12 illustrates a structure 65 obtained at the end of a step of forming the insulation structure 39 on the upper face of the structure 61 and in the trenches 63.

[0098] The insulation structure 39 comprising the insulation layer 393 and the insulation trenches 391 is preferably produced by the successive deposition of two layers 67 and 69. The layer 67 is an insulating layer and is, for example, deposited on the upper face of the structure 61 illustrated in figure 11 such that the layer 67 covers the upper face of the MOS circuits 33 and the side faces and the bottom of the openings 63. The layer 67 is preferably conformal and deposited by a vapor deposition technique.

[0099] Layer 69 is preferably deposited so as to completely cover layer 67. Layer 69, for example, fills trench 39. Layer 69 may be an insulating layer or a layer of a filling material, for example polycrystalline silicon.

[0100] There figure 13 illustrates a structure 71 obtained at the end of a step of forming, for each device 11, the stacking of insulating layers 37, conductive tracks 35 and conductive vias 36 on and in the structure 65 illustrated in figure 12 . There figure 13 illustrates very schematically the electronic connection of tracks 35 to one or more metallization levels of the MOS circuit 33, shown schematically in figure 13 by the pads 32, and this by the vias 36. The figure 14 is an enlargement of part 73 of structure 71.

[0101] According to one embodiment, the pad 32 corresponds to a track of any of the metallization levels of the MOS circuit 33, preferably the first level. In order to reach the track 32, each via 36 crosses, for example: layer 37; and the first part 331 of the MOS circuit 33.

[0102] The production of the vias 36 preferably comprises an etching step making it possible to etch the part 331 of the MOS circuit 33 over a thickness of between 3 µm and 5 µm. The vias 36 preferably each have a width 15 greater than 6 µm. Following the etching step, the deposition of an insulating layer 81, for example made of silicon dioxide, is carried out for example by a plasma-enhanced chemical vapor deposition (PECVD) technique. The layer 81 preferably has a thickness of the order of 0.5 µm. Following the step of depositing the layer 81, the latter is etched so as to reveal a part of the upper face of the pads 32 (or of a pad 31 in the event that the MOS circuit 33 does not include a transistor on one side of the isolation trench 391), at the bottom of the openings formed in the MOS circuit 33. The etching of the layer 81 makes it possible to uncover the pads 32 over a width 16 greater than 3 µm.Following the step of etching the layer 81, a metal layer 83 is deposited, for example, made of aluminum, tungsten, copper or a combination or alloy of these two materials. The layer 83 is preferably deposited by a physical vapor deposition technique. The layer 83 thus covers the layer 81 and comes into contact with the pads 32. The layer 83 preferably has a thickness of the order of 1 µm. The layer 83 is subsequently etched in order to preserve it in order to form only the vias 36 and possibly the conductive tracks 35 as illustrated in . figure 13 .

[0103] There figure 15 illustrates a structure 85 obtained at the end of a step of forming the connectors 41 on the upper face of the structure 71 illustrated in figure 13 .

[0104] The connectors 41 are formed in contact with tracks 35. Preferably, for each device, at least one connector 41 is connected to the electrode 23 and at least one connector 41 is connected to the layer 19.

[0105] There figure 16 illustrates a plurality of devices 11 obtained at the end of a cutting step, of the structure 85 illustrated in figure 15 .

[0106] Structure 85 illustrated in figure 15 is, for example, sawn so as to produce trenches 87 by means of a blade having a thickness, for example, of the order of 40 µm.

[0107] The trenches 87 are through-cut and allow the structure 85 to be cut into unitary devices 11. The trenches 87 extend, for example, into the logic circuit 15 and into the optoelectronic circuit 13 in the openings 261. The step of sawing the structure 85 may be preceded by a step of thinning the substrate 27 to a thickness of the order of 300 µm.

[0108] THE figures 17 et 18 are partial and schematic sectional views of structures obtained at stages of another embodiment of a method of manufacturing a variant of the optoelectronic device 11 shown in figure 1A .

[0109] More specifically, the figure 17 illustrates a structure 89 obtained at the end of a step of forming trenches 91 in the structure 61 illustrated in figure 11 . Trenches 91 can be formed simultaneously with trenches 63.

[0110] The trenches 91 preferably extend from the upper face of the structure 89 into the structure 89. The trenches 91 preferably extend through the MOS circuit 33, the underlayer 175 and the underlayer 173 so as to expose the layer 29 in the openings 261. The trenches 91 preferably have, in top view, the same dimensions and shape as the dimensions and shape of the openings 261. In other words, during this step, the layers overlying the layer 29 are removed directly above the openings 261.

[0111] There figure 18 illustrates a structure 93 obtained at the end of a step of depositing an insulating layer 95 and a step of forming conductive regions 97 on the upper face of the structure 93.

[0112] The insulating layer 95 is preferably a silicon dioxide layer. The insulating layer 95 is preferably deposited by PECVD to a thickness of the order of 1 µm. Openings 99 are then etched in the insulating layer 95. The structure 93 preferably comprises at least one opening 99 on each side of the trench 63. The openings 99 have, for example, each a width l7 greater than 3 µm.

[0113] The metal regions 97 are preferably made of aluminum, copper, or a combination or alloy of these two materials. The metal regions 97 may have a single-layer structure or a multi-layer structure. The regions 97 are preferably formed to extend into the openings 99. The regions 97 are preferably formed to a width 18 greater than 10 µm.

[0114] The regions 97 are preferably connected to metal tracks of the MOS circuit 33 in a similar manner, for example in a manner analogous to what has been described previously in relation to the figure 13 .

[0115] At the end of this step, connectors (not shown in figure 18 ), similar to the connectors 41 illustrated in figure 15 , are formed on and in contact with the 97 regions.

[0116] An advantage of the embodiments and implementations described is that they allow the logic circuit 15 and the optoelectronic circuit 13 to be bonded at rather low temperatures (i.e. below 250°C), which limits the risks of damage to the materials making up the optoelectronic circuit.

[0117] Another advantage of the embodiments and implementations described is that they make it possible to increase the reliability of the bonding of the logic circuit 15 and the optoelectronic circuit 13 in comparison, for example, with a hybrid bonding, based on contact pads.

[0118] Yet another advantage of the described embodiments and implementations is that they allow the assembly of the substrate of the light-emitting diodes and the substrate of the control circuits with lower positioning precision constraints than for hybrid bonding.

[0119] Yet another advantage of the described embodiments and implementations is that, compared to US10468452, there are no constraints on the electrical connection between circuits 15 and 13.

[0120] Yet another advantage of the described embodiments and implementations is that they make it possible to maximize the useful surface area of ​​the LED formed on a single growth surface.

[0121] Yet another advantage of the described embodiments and implementations is that they limit the risk of damage to the substrate 27 since the isolation trench 391 does not extend to the substrate 27.

[0122] An advantage of the embodiments and implementations described is that they are compatible with standard production lines for microelectronic components.

[0123] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will be apparent to those skilled in the art. In particular, in the embodiments described above, in order to be able to carry out the molecular bonding of the sub-layer 173 to the sub-layer 175, the flatness of the face 13s of the sub-layer 173 is obtained by a possible planarization step carried out after the deposition of the sub-layer 173 and the flatness of the face 15i of the sub-layer 175 is obtained by a possible planarization step carried out after the deposition of the sub-layer 175.Alternatively, the flatness of the face 13s of the sub-layer 173 may be obtained by depositing, before the formation of the sub-layer 173, an electrically insulating planarization layer, for example an oxide, on the underlying structure, by forming vias passing through this insulating planarization layer (by depositing a conductor in the vias passing through this insulating planarization layer, and by planarizing this conductive material at the same level as the insulating planarization layer), then by depositing the sub-layer 173 on the planarization layer and in contact with the vias, the sub-layer 173 then directly having the desired flatness properties. The formation of the insulating planarization layer may comprise the deposition of at least one insulating layer followed by a planarization step, for example by CMP.Similarly, the flatness of the face 15i of the sub-layer 175 can be obtained by depositing, before the formation of the sub-layer 175, an electrically insulating planarization layer, for example an oxide, on the underlying structure, by forming vias passing through this insulating planarization layer (by depositing a conductor in the vias passing through this insulating planarization layer, and by planarizing this conductive material at the same level as the insulating planarization layer), then by depositing the sub-layer 175 on the planarization layer and in contact with the vias, the sub-layer 175 then directly having the desired flatness properties. Obtaining the flatness of the face 13s of the sub-layer 173 by depositing an electrically insulating planarization layer makes it possible to facilitate plate-to-plate bonding and thus optimize the manufacturing time of the optoelectronic device.In addition, this allows to reduce the thickness of the optoelectronic device.

[0124] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

1. Optoelectronic device (11) comprising a stack: of a first circuit (13) comprising at least one inorganic light-emitting diode (LED) emitting through a first surface (13i) of the first circuit and comprising first and second electrodes (23, 24); and of a second circuit (15) for controlling the light-emitting diode, positioned on a second surface (13s) of the first circuit opposite to the first surface, comprising first and second electrically-conductive pads (31), wherein an electrically-conductive layer (17) comprising the stacking of a first electrically-conductive sub-layer (173) of the first circuit (13) and of a second electrically-conductive sub-layer (175) of the second circuit (15), is located at the interface between the first and second circuits, the electrically-conductive layer (17) being divided into first and second portions orthogonally to the stacking direction of the first and second circuits, the first electrode being electrically coupled to the first conductive pad via the first portion of the conductive layer and the second electrode being electrically coupled to the second conductive pad via the second portion of the conductive layer, the first and second conductive portions of the electrically-conductive layer (17) being separated by an electrical insulation trench (391).

2. Device according to claim 1, comprising at least two connectors (41), located on the second circuit (15), on the side opposite to the first circuit (13), intended to electrically couple the device (11) to an external object.

3. Device according to claim 1 or 2, wherein the first and second conductive pads (31) are separated by said electrical insulation trench (391).

4. Device according to any of claims 1 to 3, wherein the second circuit (15) comprises metal oxide gate field-effect transistors and comprises two portions electrically separated by said electrical insulation trench (391).

5. Device according to claim 4, wherein the portions of the second circuit (15) are electrically coupled by connections by electrically-conductive tracks (35) located on the side of the metal oxide gate field-effect transistors opposite to the first circuit (13).

6. Device according to any of claims 1 to 5, wherein the electrical insulation trench (391) has a closed shape, in a plane parallel to the second surface (13s), or wherein the electrical insulation trench (391) has, in a plane parallel to the second surface (13s), an open shape having its two free ends emerging onto one or a plurality of the sides of the device (11).

7. Device according to any of claims 1 to 6, wherein the first circuit (13) comprises a substrate (27) on the side of the first surface (13i), wherein the substrate (27) can in particular be made of sapphire or of glass.

8. Device according to any of claims 1 to 7, wherein the conductive layer (17) is made of metal or of a conductive polymer.

9. Method of manufacturing a plurality of optoelectronic devices according to any of claims 1 to 8, comprising a step a) of assembly of a first wafer comprising said plurality of first circuits (13) to a second wafer comprising said plurality of second circuits (15).

10. Method according to claim 9, wherein assembly step a) is carried out by placing into contact, full plate, first and second sub-layers (173, 175) of the electrically-conductive layer (17).

11. Method according to claim 9 or 10, wherein each first circuit (13) is partially etched at a step b) prior to step a) to define a first cavity (281) located at the location of the second electrode.

12. Method according to any of claims 9 to 11, wherein each first circuit (13) is partially etched at a step b') prior to step a) to form a second cavity (261) enabling to define the edges of said light-emitting diode (LED).

13. Method according to claim 11 or 12, comprising a step c), between steps a) and b) or b'), where each light-emitting diode (LED) is covered, on the side of the second surface of the first circuit (13), with a dielectric layer (29) open at the level of the first and second electrodes (23, 24).

14. Method according to claim 13, wherein between step c) and step a), each light-emitting diode (LED) is covered, on the side of the second surface of the first circuit (13), with the first conductive sub-layer (173).

15. Method according to claim 14, wherein each second circuit (15) is covered, before step a), with the second conductive sub-layer (175).

16. Method according to claim 15, wherein assembly step a) is carried out by a non-hybrid bonding of the first conductive sub-layer (173) with the second conductive sub-layer (175).

17. Method according to any of claims 9 to 16, wherein step a) is followed by a step d) of etching, for each optoelectronic device (11), of a trench (63) extending in the second wafer (15) and in the electrically-conductive layer (17) all the way to the dielectric layer (29).

18. Method according to claim 17, wherein step d) is followed by a step of filling of the trench (63) with an insulating material to manufacture the electrical insulation trench (391).