Method for producing a region doped with a microelectronic device

Description

TECHNICAL FIELD

[0001] The present invention relates to the field of microelectronics. It finds a particularly advantageous application in the production of sources and drains in transistors requiring low thermal budgets, particularly in the field of monolithic 3D integration. STATE OF THE ART

[0002] Historically, developments in the semiconductor industry have aimed to follow, through a common roadmap, Moore's Law, which predicts that the density of electronic chips will double approximately every eighteen months. The technological nodes along this roadmap are generally defined by the etching fineness of integrated circuit transistors.

[0003] For technology nodes with an etching fineness below 10 nm, the required developments are extremely complex and costly. An alternative solution for the most advanced technology nodes, relaxing some of the constraints related to etching fineness, consists of integrating transistors according to a three-dimensional (3D) architecture. This 3D integration concept is a promising solution for globally improving the relative power / performance / size / cost criteria of integrated circuits, according to an approach known as "More than Moore" (or "beyond Moore's Law" in French) while allowing co-integration of different devices on different levels.

[0004] Among the very large scale 3D integration processes (or 3D VLSI for Very Large Scale Integrationin English), the CoolCube ™ integration process proposes to form transistors one on top of the other sequentially. One issue with this process concerns the management of the thermal budget during the formation of the upper layers of transistors. In order to preserve the optimal electrical characteristics of the transistors in the lower layers of the stack, the temperature rise during the various stages of the process must be kept to a minimum. In particular, the formation of doped zones on either side of the transistor channel, typically the source and drain zones of the transistor, typically requires a dopant activation and / or diffusion step, after ion implantation of doping species.

[0005] A classic solution for dopant activation in planar technology is to perform high temperature thermal annealing, typically at a temperature T > 1000°C, after implantation of the dopants.

[0006] An existing solution for dopant activation in 3D integration technology consists of amorphizing a portion of the semiconductor layer intended to form the source and drain regions, before or during dopant implantation. After dopant implantation, dopant activation occurs during solid-phase recrystallization of the amorphous semiconductor layer. This recrystallization / activation step can be performed at lower temperatures, typically at a temperature T < 600°C.

[0007] THE Figures 1A-1C present the steps of such a recrystallization process called SPER (acronym for "solid-phase epitaxial regrowth" in English terminology). The Figure 1A illustrates a device 1 intended to form a transistor and comprising a gate pattern 10 flanked by a spacer 11 on a substrate 20 of SOI type (acronym for “Silicon on Insulator” or “silicon on insulator” in French). The Figure 1B illustrates an ion bombardment at the edge of the spacer 11, adapted to partially amorphize the upper silicon layer 22 (topSi) of the SOI substrate, and to implant dopants in this amorphous part 22a. A crystalline part 22b of the topSi layer is preserved at the end of this bombardment, so as to form a seed for the future recrystallization. Figure 1C illustrates the partial recrystallization of topSi from this 22b seed. During recrystallization, the dopants are incorporated and activated. This recrystallization allows in fine to obtain a doped zone 13.

[0008] A disadvantage of this solution based on the SPER recrystallization process is that there is an undoped area 22d between channel 15 and doped area 13, under spacer 11. This increases the access resistance of the transistor. Another disadvantage is the presence of the undoped seed 22b underlying the doped area 13. This further increases the access resistance of the transistor. In addition, for small thicknesses of topSi, for example less than 10 nm, good control of the amorphization depth becomes essential. The implementation of the SPER process is therefore complex. Furthermore, the recrystallization of the amorphous part 22a of the topSi is generally not complete. A residual superficial uncrystallized layer 22c remains, it is then necessary to provide an etching to eliminate it.

[0009] Document US 2004 / 0132258 A1 discloses a solution for reducing the access resistance of the transistor, in the case of a substrate having a "recess". This solution is not suitable for 3D integration processes.

[0010] An object of the present invention is to at least partially overcome some of the drawbacks mentioned above.

[0011] In particular, an object of the present invention is to provide a method of forming a doped area improving the access resistance of a microelectronic device.

[0012] Other objects, features, and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other advantages may be incorporated. SUMMARY

[0013] To achieve this objective, a first aspect of the invention relates to a method of forming at least one doped zone intended to form a source or a drain of a transistor, comprising the following steps: Providing a stack comprising, along a z direction, at least one insulating layer, an active layer made of a semiconductor material overlying the insulating layer, and a transistor gate pattern overlying the active layer and having at least one lateral flank extending in a plane substantially perpendicular to an upper face of the active layer, Removing a first portion of the active layer not surmounted by the gate pattern, said first portion extending to the vertical plane of the gate pattern directly at the edge of a second portion of the active layer, said second portion being located under the gate pattern, so as to expose an edge of said second portion, said edge extending substantially in an extension of the lateral flank of the gate pattern, Forming a first spacer made of a first material on the lateral flank and on said edge,said first spacer having an L shape and comprising a basal portion in contact with the insulating layer and a lateral portion in contact with the lateral flank, said basal portion having a thickness in the z direction substantially equal to the thickness of the active layer, Forming a second spacer in a second material on the first spacer, said second spacer having a shape complementary to that of the first spacer, Removing the basal portion of the first spacer by selective etching of the first material with respect to the second material of the second spacer and the semiconductor material, so as to expose the edge of the second portion while retaining at least in part the lateral portion of the first spacer on the lateral flank of the gate pattern, Forming by epitaxy from said exposed edge the doped zone.

[0014] Advantageously, the removal of the first portion of the active layer is carried out before the formation of the first spacer. This makes it possible to remove the first portion as close as possible to the gate pattern. After removal of the first portion, the edge of the second portion extends substantially as an extension of the lateral flank. The formation of the doped zone is carried out from this edge. This edge thus becomes a junction between the second portion, typically the channel of the transistor, and the doped zone, typically the source or drain of the transistor. This junction is preferably abrupt.

[0015] Such a method advantageously eliminates the residual undoped area which is located directly above the spacer(s), between the channel and the doped area, when implementing the known methods. The junction thus obtained makes it possible to reduce the access resistance of the transistor. As indicated previously with reference to the Figure 1Billustrating the prior art, bombardment carried out within the framework of known solutions does not make it possible to make the undoped zone disappear, even if this bombardment were modified so as to tilt the bombardment direction.

[0016] The formation of the doped zone by lateral epitaxy, that is to say from the edge of the second portion, also makes it possible to avoid the need to keep an epitaxy seed underlying a modified portion, as implemented by known methods. Thus, the removal of the first portion can be carried out over the entire thickness of the active layer, up to the insulating layer, so that the doped zone has a thickness at least equal to that of the active layer, under the first and second spacers. It is therefore not necessary to precisely control an implantation depth, unlike known methods. This makes it possible to simplify the process. A doped zone extending along the entire height of the active layer also makes it possible to reduce the access resistance of the transistor.

[0017] Such a process can advantageously be implemented at low temperature, typically for temperatures T < 600°C. This process is thus compatible with 3D integration technology. BRIEF DESCRIPTION OF THE FIGURES

[0018] The aims, objects, as well as the characteristics and advantages of the invention will emerge more clearly from the detailed description of an embodiment thereof which is illustrated by the following accompanying drawings in which: THE Figures 1A to 1C illustrate in section steps of forming a doped zone according to a method of the prior art. The Figures 2A to 2H illustrate in section steps of forming a doped zone according to an embodiment of the present invention.

[0019] The drawings are given as examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily to the scale of practical applications. In particular, the relative dimensions of the different layers, portions and elements of the device (for example spacers, active layer) are not representative of reality. In the drawings, only one side of the grid and only one spacer are shown. It is understood that the method applies symmetrically to the second side of the grid and to the second spacer. Thus, the figures can be extended by symmetry on either side of the z axis. DETAILED DESCRIPTION

[0020] Before beginning a detailed review of embodiments of the invention, optional features that may optionally be used in combination or alternatively are set out below: According to one example, the basal portion of the first spacer has a thickness in the z direction substantially equal to the thickness of the active layer. A basal portion of the first spacer having a thickness less than the thickness of the active layer does not make it possible to optimally reduce the access resistance of the transistor. A basal portion of the first spacer having a thickness greater than the thickness of the active layer does not make it possible to correctly insulate the gate of the transistor. A basal portion of the first spacer having a thickness substantially equal to the thickness of the active layer makes it possible to optimally reduce the access resistance of the transistor.A basal portion thickness “substantially equal” to the active layer thickness means that the basal portion thickness is equal to the active layer thickness within ±10%, preferably ±5%.

[0021] According to one example, the selectivity of the selective etching of the first material with respect to the semiconductor material is greater than or equal to 10:1, and preferably greater than or equal to 20:1.

[0022] According to one example, the selectivity of the selective etching of the first material with respect to the second material is greater than or equal to 5:1, and preferably greater than or equal to 10:1.

[0023] According to one example, the formation of the first spacer comprises a deposition of a first non-conformal layer, such that the first layer has a thickness ey on the lateral flank and a thickness ez on the insulating layer, such that the thickness ey is less than the thickness ez. A first spacer formed from a first non-conformal layer makes it possible to obtain a basal spacer portion that is thicker than the lateral spacer portion, preferably such that the basal spacer portion has a thickness substantially equal to the thickness of the active layer. In addition, a less thick lateral spacer portion makes it possible to more finely and more easily control the “critical dimension” known by the acronym CD (“critical dimension”: it is on this dimension that the dimensional control of the transistors is based).

[0024] In one example, the first material and the second material are dielectric materials.

[0025] In one example, the first material is silicon oxide-based or SiBCN-based.

[0026] According to one example, the second material is different from the first material and is based on silicon nitride SiN or SiCO or another material comprising at least two species among Si, C, O, B, N.

[0027] According to one example, the semiconductor material of the active layer is taken from silicon and silicon-germanium.

[0028] In one example, the doped area is based on silicon or silicon-germanium.

[0029] According to one example, the epitaxy of the doped zone is configured so that said doped zone extends beyond an upper face of the active layer in a direction substantially perpendicular to the active layer.

[0030] In one example, the removal of the first portion is performed by anisotropic dry etching along the z direction.

[0031] According to one example, the epitaxy of the doped zone is a lateral epitaxy mainly directed in a direction normal to the edge of the second portion.

[0032] In one example, the transistor gate pattern serves as an etch mask when removing the first portion.

[0033] In one example, the epitaxy of the doped area is implemented with a doping in situ so that the doped area directly presents doping at the end of said epitaxy.

[0034] It is specified that in the context of the present invention, the term "on", "overcomes", "covers" or "underlying" or their equivalents do not necessarily mean "in contact with". Thus, for example, the deposition of a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but it does mean that the first layer at least partially covers the second layer by being either directly in contact with it or by being separated from it by at least one other layer or at least one other element.

[0035] A layer can also be composed of several sub-layers of the same material or of different materials.

[0036] A substrate, a layer, a device, "based" on a material M, is understood to mean a substrate, a layer, a device comprising this material M only or this material M and possibly other materials, for example alloying elements, impurities or doping elements. Thus, a spacer based on silicon nitride SiN may for example comprise non-stoichiometric silicon nitride (SiN), or stoichiometric silicon nitride (Si3N4), or even a silicon oxynitride (SiON).

[0037] In general, but not limited to, a spacer forms a ring around the grid, with a closed contour; the description of a spacer is preferably understood to mean this single spacer around the grid; however, the sectional illustration drawings, generally along a plane transverse to the longitudinal direction of the grids, show two spacer parts on either side of the sides of the grid. By extension, these two spacer parts are often designated “the spacers”. This latter terminology may optionally be adopted in this application, in this case “the first spacers” and / or “the second spacers”. Furthermore, the invention extends to embodiments in which “the first spacers” and / or “the second spacers” are discontinuous.

[0038] The present invention allows in particular the fabrication of at least one transistor or a plurality of transistors on a substrate. This substrate may be of the semiconductor on insulator type, for example a silicon on insulator SOI substrate (acronym for "silicon on insulator") or a germanium on insulator GeOl substrate (acronym for "germanium on insulator").

[0039] The invention can also be implemented more broadly for different microelectronic devices or components.

[0040] A microelectronic component, device or element is any type of element made using microelectronics. These devices include, in addition to devices for purely electronic purposes, micromechanical or electromechanical devices (MEMS, NEMS, etc.) as well as optical or optoelectronic devices (MOEMS, etc.).

[0041] Several embodiments of the invention implementing successive steps of the manufacturing process are described below. Unless explicitly stated, the adjective "successive" does not necessarily imply, even if this is generally preferred, that the steps follow one another immediately, intermediate steps being able to separate them. Furthermore, the term "step" means the carrying out of a part of the process, and can designate a set of sub-steps.

[0042] The word "dielectric" describes a material whose electrical conductivity is sufficiently low in the given application to serve as an insulator. In the present invention, a dielectric material preferably has a dielectric constant of less than 7. Spacers are typically formed from a dielectric material.

[0043] The terms "grid pattern", "grid stacking", "grid" are used synonymously.

[0044] The term "selective etching with respect to" or "etching exhibiting selectivity with respect to" means etching configured to remove a material A or a layer A with respect to a material B or a layer B, and exhibiting an etching rate of the material A greater than the etching rate of the material B. Selectivity is the ratio of the etching rate of the material A to the etching rate of the material B.

[0045] In this patent application, we will preferentially speak of thickness for a layer, height for a device (transistor or gate for example) and depth for a cavity or an etching. The thickness is taken in a direction normal to the main extension plane of the layer, the height and depth are taken in a direction normal to the base plane of the substrate. The main extension plane of the layer, respectively the base plane of the substrate is generally parallel to a lower face or an upper face of this layer, respectively of this substrate.

[0046] In the present patent application, a preferably orthonormal reference frame formed by the x, y, z axes is shown in the accompanying drawings. The substrate, more precisely its lower face and / or its upper face, extends in the xy basal plane.

[0047] In the following, the length is taken according to the direction carried by the x axis, the width is taken according to the direction carried by the y axis.

[0048] An element located "perpendicular to" or "in line with" another element means that these two elements are both located on the same line perpendicular to the basal plane, or on the same line oriented along the z axis in the figures. An element located "in extension" of another element means that these two elements are both oriented in the same direction or the same plane, and preferably in continuity with each other.

[0049] "Horizontal" or "basal" means an orientation parallel to an xy plane. "Vertical" means an orientation parallel to the z axis.

[0050] The terms "substantially", "approximately", "of the order of" mean "within 10%" or, when it comes to an angular orientation, "within 10°". Thus, a direction substantially normal to a plane means a direction presenting an angle of 90±10° with respect to the plane.

[0051] The invention will now be described in detail through some non-limiting embodiments.

[0052] A first embodiment of the method is illustrated in Figures 2A-2H .

[0053] This method is preferably carried out on an initial structure comprising a grid pattern 10 and a substrate 20, as illustrated in Figure 2A For example.

[0054] The substrate 20 may typically be a semiconductor-on-insulator type substrate, for example a silicon-on-insulator SOI (acronym for “silicon on insulator”) substrate or a germanium-on-insulator GeOl (acronym for “germanium on insulator”) substrate.

[0055] Such an SOI type substrate 20 typically comprises: a bulk silicon support typically having a thickness of several hundred µm (not shown) called bulk Si (meaning bulk silicon), a buried layer 21 of silicon dioxide, called BOX (acronym for “Burried Oxide” meaning buried oxide). This layer 21 typically has a thickness of between 30 nm and 200 nm, for example of the order of 40 nm. an active layer 22 of silicon, called top Si (meaning upper silicon). This active layer 22 preferably has a thickness of between 5 nm and 50 nm, for example of the order of 10 nm.

[0056] The active layer 22 is surmounted by a grid stack or grid pattern 10. Conventionally, the grid pattern 10 may successively have the following layers arranged from the active layer 22: an interface oxide layer (often referred to as grid oxide), a polycrystalline silicon grid called polySi and a hard mask. Alternatively, this grid pattern may comprise a high dielectric constant layer, called a “high k” layer surmounted by a metal grid.

[0057] The grid pattern 10 typically has a height along the z axis of several tens of nanometers to several hundreds of nanometers. The invention also covers an alternative embodiment for which the grid pattern 10 is a sacrificial pattern intended to be removed after the spacers have been produced, then to be replaced by another grid stack forming a grid 10. Such a method is commonly referred to as “gate last” according to English terminology. The grid 10 in the following therefore indifferently designates a grid stack of the “gate first” type (the grid is retained after the spacers have been produced) or of the “gate last” type (the grid is replaced after the spacers have been produced).

[0058] In the remainder of the description, and for the sake of brevity, the gate pattern will simply be referred to as gate 10. The active layer is referred to as topSi 22. The doped area intended to form the source or drain of the transistor is referred to as S / D area 13.

[0059] After structuring or providing the grid 10 and before forming the first spacer 11 on the sides 100 of the grid 10, a first portion 221 of the topSi 22, which is neither masked nor covered by the grid 10 or by spacers, is removed ( Figure 2B). The gate 10 thus forms an etching mask for the removal of the portion 221. The removal of this first portion 221 exposes an edge 150 of a second portion 222 of topSi covered by the gate 10, forming the channel 15 of the transistor. This edge 150 between the first and second portions 221, 222 is substantially parallel to the z axis and is located in an extension of the flank 100 of the gate 10. This makes it possible to subsequently align the junction between the channel and the S / D zone of the transistor directly at the edge of the gate 10. This prevents an undoped portion from remaining between the channel 15 and the subsequently formed S / D zone. The access resistance to the transistor is then reduced.

[0060] The first portion 221 preferably has a thickness ez equal to the thickness of the active layer 22. This prevents an undoped portion from remaining outside the channel 15, under the subsequently formed S / D zone. The access resistance to the transistor is then further reduced. Since the portion 221 to be removed extends along z up to the BOX 21, it is not necessary to precisely control the depth of the removal. The BOX 21 can thus serve as a stop layer for the removal of the topSi.

[0061] The removal of the first portion 221 is preferably carried out by anisotropic dry etching and mainly directed along z. This removal therefore does not affect the second portion 222 masked by the grid 10, along this z direction. In a manner known to those skilled in the art, such anisotropic dry etching can be carried out by plasma, for example using an HBr / O2 or CH2F2 / SF6 / N2 / He etching chemistry, within a capacitively coupled plasma (CCP) reactor or an inductively coupled plasma (ICP) reactor. According to one possibility, the portion 221 is amorphized before removal by etching.

[0062] The first and second spacers 11, 12 are formed after removal of the first portion 221 of the topSi 22.

[0063] A first deposition of a first layer 110 in a first dielectric material on the gate 10 and on the active layer 22 is typically carried out ( Figure 2C). This first deposition is preferably non-conformal, so as to obtain a layer 110 having a thickness ez substantially equal to the thickness of the second portion 222 of the active layer 22, at a basal part of the layer 110 in contact with the BOX 21, and a thickness ey < ez at a lateral part of the layer 110 in contact with the lateral flank 100 of the gate pattern 10. The thickness ey may be between 2 nm and 10 nm. The first dielectric material may be a silicon oxide or based on SiBCN, or based on SiCO (silicon carbon oxygen).

[0064] A second deposition of a second layer 120 of a second dielectric material is then carried out on the first layer 110 ( 2D figure). This second deposition may be conformal. The thickness of the second layer 120 may be between 5 nm and 30 nm. The second dielectric material may be based on silicon nitride SiN. The first and second dielectric materials are different from each other.

[0065] One or more anisotropic etching steps along the z axis then make it possible to remove horizontal portions of the two dielectric layers 110, 120 at the top of the gate 10 and on the BOX 21, while retaining portions 11l, 11b, 12 of dielectric layers on the side 100 of the gate 10 and on the edge 150 of the second portion 222 intended to form the channel 15. These portions 11l, 11b, 12 form the first and second spacers 11, 12, also called double spacer. The first spacer 11 thus typically has an L shape and comprises the basal portion 11b and the lateral portion 11l. The second spacer 12 partially covers the first spacer 11 ( Figure 2E).

[0066] A selective etching configured to remove the basal portion 11b of the first spacer 11 is then carried out, so as to expose the edge 150 of the second portion 222 intended to form the channel 15. This selective etching preferably has a selectivity greater than 5:1 between the first dielectric material and the second dielectric material. This makes it possible to remove the basal portion 11b while retaining the second spacer 12 ( Figure 2F ). This selective etching preferably has a selectivity greater than 10:1 between the first dielectric material and the semiconductor material. This makes it possible to remove the basal portion 11b while preserving the channel 15.

[0067] Such selective etching can be carried out wet, for example from a dilute hydrofluoric acid (dHF) solution. Such selective etching can be carried out dry, in particular by plasma based on at least one species comprising a fluorine or carbon atom. Plasma etching of SiO2 can be carried out selectively with respect to Si, and anisotropically, from the following species or mixtures of species: CHF3 / O2, C2F6, C3F8, C5F8 / CO / O2 / Ar. Typically, high ratios between fluorine atoms and carbon atoms make it possible to obtain high etching selectivity.

[0068] This selective etching makes it possible to expose the edge 150 of the channel 15. This edge 150 is substantially parallel to z, in an extension of the flank 100 of the gate 10. This edge 150 is advantageously used to form by lateral epitaxy, in a direction substantially perpendicular to the edge 150, the doped zone 13. The edge 150 then becomes an interface forming a junction between the channel 15 and the doped zone 13. This junction is advantageously located directly at the edge of the gate 10, directly above the flank 100. The access resistance to the transistor can thus be reduced.

[0069] As illustrated in figures 2G, 2H , the lateral epitaxy is done from the edge 150, preferably only from the edge 150, first and mainly along the y axis (portion 13a of the doped zone 13 on the Figure 2G ). This epitaxy of the 13-doped zone can continue partly along z (portion 13b of the 13-doped zone on the Figure 2H). Such a transistor 1 configuration including raised S / D regions is called RSD, an acronym for "Raised Source / Drain".

[0070] A doped epitaxy process in situ is preferably used to form the doped zone 13. A boron (:B) or phosphorus (:P) doping can thus be obtained. The doped zone 13 can for example be based on SiGe:B, Si:B or Si:P.

[0071] According to one possibility, a cavity is formed between the BOX 21 and the doped area 13, 13b, during lateral epitaxy. Such a cavity improves the electrical insulation between the doped area 13 and the substrate underlying the BOX 21.

Claims

1. Method for forming at least one doped area (13) intended to form a source or drain of a transistor (1), comprising the following steps: • Providing a stack comprising in a direction z at least one insulating layer (21), an active layer (22) made of a semiconductor material overlying the insulating layer (21), and a transistor gate pattern (10) overlying the active layer (22) and having at least one lateral flank (100) extending in a plane substantially perpendicular to an upper face (220) of the active layer (22), • Removing a first portion (221) of the active layer (22) not overlaid by the gate pattern (10), said first portion (221) extending up to vertically in line with the gate pattern (10) directly at the rim of a second portion (222, 15) of the active layer (22), said second portion (222, 15) being located under the gate pattern (10), so as to expose an edge (150) of said second portion (222, 15), said edge (150) extending in an extension of the lateral flank (100) of the gate pattern (10), • Forming a first spacer (11) in a first material on the lateral flank (100) and on said edge (150), said first spacer (11) having an L-shape and comprising a base portion (11b) in contact with the insulating layer (21) and a lateral portion (111) in contact with the lateral flank (100), said base portion (11b) having a thickness along the direction z substantially equal to the thickness of the active layer (22), • Forming a second spacer (12) from a second material on the first spacer (11), said second spacer (12) having a shape complementary to that of the first spacer (11), • Remove the base portion (11b) of the first spacer (11) by selectively etching the first material with respect to the second material of the second spacer (12) and the semiconductor material, so as to expose the edge (150) of the second portion (222, 15) while at least partially retaining the side portion (111) of the first spacer (11) on the lateral flank (100) of the gate pattern (10), • Forming the doped zone (13) by epitaxy from said exposed edge (150).

2. Method according to the preceding claim, wherein the selectivity of the selective etching of the first material with respect to the semiconductor material is greater than or equal to 10:1, and preferably greater than or equal to 20:1.

3. Method according to either one of the preceding claims, wherein the selectivity of the selective etching of the first material with respect to the second material is greater than or equal to 5:1, and preferably greater than or equal to 10:1.

4. Method according to any one of the preceding claims, wherein the formation of the first spacer (11) comprises a deposition of a non-compliant first layer (110), such that the first layer (110) has a thickness ey on the lateral flank (100) and a thickness ez on the insulating layer (21), so that the thickness ey is less than the thickness ez.

5. Method according to any one of the preceding claims, wherein the semiconductor material of the active layer (22) is taken from silicon and silicon-germanium, and wherein the doped zone (13) is based on silicon or silicon-germanium.

6. Method according to any one of the preceding claims, wherein the first material and the second material are dielectric materials.

7. Method according to any one of the preceding claims, wherein the first material is based on silicon oxide or SiBCN, and wherein the second material is different from the first material and is based on silicon nitride SiN or SiCO or another material comprising at least two species from Si, C, O, B, N.

8. Method according to any one of the preceding claims, wherein the epitaxy of the doped zone is configured for said doped zone (13) to extend beyond the upper face (220) of the active layer (22) in a direction substantially perpendicular to the active layer (22).

9. Method according to any one of the preceding claims, wherein the removal of the first portion (221) is performed by anisotropic dry etching along the direction z.

10. Method according to any one of the preceding claims, wherein the epitaxy of the doped area (13) is a lateral epitaxy originating only from the edge (150) of the second portion (222, 15).

11. Method according to any one of the preceding claims, wherein the transistor gate pattern (10) serves as an etch mask when removing the first portion (221).

12. Method according to any one of the preceding claims, wherein the epitaxy of the doped area (13) is implemented with in situ doping so that the doped area (13) shows directly doping at the end of said epitaxy.