Capless voltage regulator with adaptive compensation

Description

BACKGROUND

[0001] Capless voltage regulators (CVRs) supply power to subcircuits (e.g., high speed digital loads, memories, etc.) of integrated circuits (ICs). CVRs are low cost and do not occupy substantial IC substrate area since they do not require external capacitors, external pins, or large internal capacitors.

[0002] US2018 / 0351450 A1 (Pelicia et al.) provides a voltage regulator. A first biassing circuit can provide current to a first capacitor, when the first biassing circuit is triggered. The first capacitor is connected to the gate of a transistor that supplies current to a load. The load is a processor, which may have a widely variable demand for current. The first biassing circuit has a pair of comparison circuits. The comparison circuits trigger, respectively, when the voltage supplied to the processor is above a first threshold, or below a second threshold. A second, separate biassing circuit is controlled by a load current prediction circuit. The load current prediction circuit monitors a processing activity of the processor. The load current prediction circuit is configured to anticipate that a load current demand to the processor is going to increase, based on detected processing activity of the processor. When the load current prediction circuit anticipates that a load current demand to the processor is going to increase, the load current prediction circuit activates the second biassing circuit. The second biassing circuit comprises a precharge capacitor. The precharge capacitor is preloaded with charge. When the load current prediction circuit activates the second biassing circuit, the precharge capacitor is connected to the first capacitor and charges the first capacitor. The second biassing circuit thus provides a temporary voltage boost to the first capacitor. That voltage boost increases the current supplied by the transistor. The temporary voltage boost avoids a situation arising in which the first biassing circuit is too slow to react when the processor's demand for current increases suddenly. US2014 / 0084881A1 (Shih et al.) provides a voltage regulator with hysteretic control. An amplifier drives an output stage. A separate charge pump is provided. The charge pump activates when the output voltage either exceeds a higher trigger voltage plus a first margin, or is below a lower trigger voltage minus a second margin. An LDO regulator is provided in MING XIN et al: 'A capacitor-less LDO regulator with dynamic transconductance enhancement technique', ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, Springer New York LLC, US, vol. 84, no. 3, pp 433-444, 9 July 2015 (2015-07-09). The LDO regulator detects a rate of change of output voltage, in order to detect load transients in a load circuit.SUMMARY

[0003] In a first aspect, the invention provides an integrated circuit in accordance with appended independent claim 1. In a second aspect, the invention provides an integrated circuit in accordance with appended independent claim 13. The dependent claims provide further details of embodiments.BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The present technology may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings. Figure 1 illustrates a prior art voltage regulator. Figure 2 illustrates a voltage regulator according to one embodiment of the present disclosure. Figure 3 illustrates an embodiment of the pass device gate controller employed in the voltage regulator of Figure 2. Figure 4 illustrates an embodiment of the pass device gate controller employed in the voltage regulator of Figure 2. Figure 5 illustrates an embodiment of the pass device gate controller employed in the voltage regulator of Figure 2. Figure 6 illustrates an embodiment of the pass device gate controller employed in the voltage regulator of Figure 2. Figure 7 illustrates an embodiment of the pass device gate controller employed in the voltage regulator of Figure 2. Figures 8a-8c illustrate example responses by the voltage regulator of Figure 6 to various load steps.

[0005] The use of the same reference symbols in different drawings indicates similar or identical items.DETAILED DESCRIPTION

[0006] Figure 1 illustrates an example CVR 100 that supplies load voltage VLOAD and load current ILOAD to a variable load circuit 102, which can be modelled as resistance R and capacitance C coupled in parallel. CVR 100 includes a switched biasing control circuit 104 that is connected to a pass device (e.g., N-channel metal oxide field effect transistor (MOSFET)) M1 and capacitor 106.

[0007] Biasing control circuit 104 controls the conductivity of pass device M1 via gate voltage Vg in response to a changing load that is sensed via the feedback of VLOAD. Switched biasing control circuit 104 includes two comparators 110 and 112 in a window comparison configuration. Comparator 110 receives a reference voltage VREF_LO and VLOAD as feedback, while comparator 112 receives a reference voltage and VREF_HI and VLOAD as feedback. When the load increases, suddenly more current is needed, and load current ILOAD is not supplied fast enough by CVR 100, so VLOAD drops below VREF_LO. When VLOAD is below reference voltage VREF_LO, switch 114 closes and current source 120 starts charging capacitance 106 with constant charging current I1, which in turn increases Vg. VLOAD increases as Vg increases. Because charging current I1 is constant, Vg increases in a linear fashion. When load current ILOAD drops suddenly, the opposite reaction occurs and VLOAD rises above VREF_HI. When VLOAD is above VREF_HI, switch 116 closes and current source 122 starts discharging capacitance 106 with a constant discharge current I2, which in turn lowers Vg. VLOAD decreases as Vg decreases. Because discharge current I2 is constant, Vg decreases in a linear fashion.

[0008] CVRs respond to sudden load fluctuations. A CVR's response is measured by the time it takes for VLOAD to return to a stable voltage within the range defined by VREF_HI and VREF_LO after having fallen or risen. It takes time for biasing control 104 to respond to a change in the load and bring VLOAD back to a stable value. VLOAD can overshoot VREF_HI or undershoot VREF_LO during biasing control 104's response to a sudden change in the load, and this is particularly true as the range defined by VREF_HI and VREF_LO becomes tighter. The overshoot or undershoot can increase the response time for CVR 100.

[0009] A CVR with adaptive compensation is disclosed. The disclosed CVR employs a quasi-adaptive controller, which dynamically adjusts the slew rate of the pass device's gate voltage to follow the slew rate of the CVR output so that voltage overshoot and / or undershoot is largely avoided. The quasi-adaptive controller enhances CVR accuracy and speed in responding to a change in the load, and promotes bonded-in bonded-out stability, i.e. the whole system is kept stable with little to no oscillatory response for all load range.

[0010] Figure 2 illustrates an IC 200 (e.g., a microcontroller) that includes a CVR 202 according to one embodiment of the present disclosure. CVR 202 supplies output voltage VLOAD and output load current ILOAD to variable load circuit 204 (e.g., high speed digital load, memory, or other subcircuit of IC 200), which can be partially modelled as resistance R coupled in parallel with capacitance C.

[0011] CVR 202 includes a switched biasing control circuit 206 connected to pass device M1 and capacitor 210 as shown. Switched biasing control circuit 206 controls pass device M1 via gate voltage Vg, which in turn controls VLOAD. For purposes of explanation only, pass device M1 takes form in an N-channel MOSFET, and capacitor 210 includes, at the very least, the gate capacitance of M1. Figure 2 shows the same supply voltage VDD coupled to switched biasing control circuit 206 and pass device M1. In an alternative embodiment distinct supply voltages are coupled to switched biasing control circuit 206 and pass device M1.

[0012] Switched biasing control circuit 206 includes two comparators 220 and 222 in a window comparison configuration. Comparator 220 receives reference voltage VREF_LO and VLOAD as feedback. Comparator 220 controls switch 224 (e.g., a MOSFET) based on a comparison of VREF_LO with VLOAD. Comparator 222 receives reference voltage VREF_HI and VLOAD as feedback. Comparator 222 controls switch 226 (e.g., a MOSFET) based on a comparison of VREF_HI with VLOAD. Lastly switched biasing control circuit 206 includes a pass device gate controller 230 coupled between switches 224 and 226. The pass device gate controller 230 dynamically adjusts the slew rate of gate voltage Vg to follow the slew rate of the CVR 202 output. In other words, pass device gate controller 230 adjusts the rate at which gate voltage Vg changes. In yet other words, pass device gate controller 230 adjusts gate voltage Vg in a non-linear fashion.

[0013] Reference voltages VREF_HI and VREF_LO set a range for VLOAD. Reference voltage VREF_LO (e.g., 500 mV) is lower than reference voltage VREF_HI (e.g., 600 mV). When output voltage VLOAD falls below reference voltage VREF_LO due to a change in the load, switch 224 closes, and pass device gate controller 230 starts charging capacitor 210 with charging current Icharge, which in turn increases Vg. VLOAD increases with Vg. As VLOAD increases, ILOAD decreases. The rate at which pass device gate controller 230 charges capacitor 210 depends on ILOAD. Thus Icharge varies in magnitude, or in other words Icharge is non-linear. VLOAD should increase as Vg increases until VLOAD exceeds VREF_LO, at which point switch 224 is opened by comparator 220. Since Icharge is non-linear, Vg and VLOAD increases in a non-linear fashion. Vg and VLOAD increase at slowing rates, which prevents an overshoot of VREF_HI. When VLOAD is less than VREF_HI and greater than VREF_LO, both switches 224 and 226 should open, and Vg (and thus VLOAD) should hold steady assuming load 204 remains constant.

[0014] When VLOAD rises above the VREF_HI value, switch 226 closes, and pass device gate controller 230 starts discharging capacitor 210 with discharge current Idischarge, which in turn decreases Vg. VLOAD decreases as Vg decreases. Idischarge may be constant, and as a result Vg decreases linearly or at a constant rate. VLOAD should decrease as Vg decreases until VREF_HI exceeds VLOAD, at which point switch 226 is opened by comparator 222. Alternatively, Idischarge can vary in magnitude, or in other words Idischarge may be non-linear. In this alternative embodiment, Idischarge depends on ILOAD, and as a result the rate at which pass device gate controller 230 discharges capacitor 210 depends on the magnitude of ILOAD. VLOAD should decrease as Vg decreases until VREF_HI exceeds VLOAD, at which point switch 226 is opened by comparator 222.

[0015] As noted, when VLOAD falls below VREF_LO, pass device gate controller 230 increases Vg by charging capacitor 210, which in turn increases VLOAD, and when VLOAD rises above VREF_HI, pass device gate controller 230 decreases Vg by discharging capacitor 210, which in turn decreases VLOAD. Pass device gate controller 230 is configured to change Vg at a rate that is slower than the rate at which VLOAD changes, at least towards the end of the capacitor charging cycle, in order to prevent VLOAD from overshooting VREF_HI. Switched biasing control circuit 206 in general and device gate controller 230 in particular promotes bonded-in bonded-out stability, i.e. the whole system is more stable with less oscillatory response caused by VREF_HI overshoot and / or VREF_LO undershoot for an anticipated load range.

[0016] Figure 3 illustrates one embodiment of the pass device gate controller (hereinafter gate controller) 230. In this embodiment, gate controller 230 includes a variable current source 304 and a constant current source 306 arranged as shown between switches 224 and 226. Current sources 304 and 306 are configured to charge and discharge capacitor 210, respectively. Variable current source 304 charges capacitor 210 with variable current I1 when switch 224 is closed by comparator 220 (i.e., when VREF_LO is greater than VLOAD). Current I1 depends upon load current ILOAD. More particularly, I1=K1·ILOAD, where K1 is a predetermined value. Gate voltage Vg, and thus VLOAD, increases as capacitor 210 is charged by I1. The rate at which Vg increases depends upon the magnitude of ILOAD. K1 is selected so that Vg increases at a rate that is slower than the rate at which VLOAD increases to avoid overshooting VREF_HI and activating switch 226. Constant current source 306 discharges capacitor 210 with constant current I2C when comparator 222 closes switch 226. Gate voltage Vg, and thus VLOAD, decreases as capacitor 210 is discharged by current source 306.

[0017] Figure 4 illustrates an alternative embodiment of gate controller 230 shown in Figure 2. Gate controller 230 in this embodiment is essentially the same as the gate controller 230 shown within Figure 3, but with constant current source 306 replaced by variable current source 404. When switch 226 is closed by comparator 222 (i.e., when VLOAD is greater than VREF_HI), variable current source 404 discharges charge capacitor 210 with variable current I2 that depends upon ILOAD. In the illustrated embodiment, I2=K2·ILOAD, where K2 is a predetermined value. K1 and K2 may be different from each other. For example, K2 can be less than K1. Or K1 and K2 may be equal. Gate voltage Vg, and thus VLOAD, decreases as capacitor 210 is discharged by variable current I2. K2 is selected so that Vg decreases at a rate that is slower than the rate at which VLOAD decreases to avoid undershooting VRER_LO and activating switch 224.

[0018] Figure 5 illustrates yet another embodiment of gate controller 230 shown in Figure 2. Gate controller 230 in this configuration is essentially the same as gate controller 230 shown in Figure 4, but with added constant current sources 504 and 506. Constant current source 504 is connected in parallel with variable current source 304, while constant current source 506 is connected in parallel with variable current source 404. When switch 224 is closed, variable current source 304 and constant current source 504 charge capacitor 210 with variable current I1 and constant current I1C. Constant current source 504 insures capacitor 210 is charged when load current ILOAD approaches 0 A. Gate voltage Vg, and thus VLOAD, increases as capacitor 210 is charged by I1 and I1C. Vg should increase at a rate that is slower than the rate at which VLOAD increases. When switch 226 is closed, variable current source 404 and constant current source 506 discharge capacitor 210 with variable current I2 and constant current I2C. Gate voltage Vg, and thus VLOAD, decreases as capacitor 210 is discharged by I2 and I2C. Constant current source 506 insures capacitor 210 is discharged when load current ILOAD approaches 0 A. Vg decreases at a rate that is slower than the rate at which VLOAD decreases. Current sources 504 and 506 guarantee a minimum amount of current for charging and discharging capacitor 210.

[0019] Figure 6 illustrates still another embodiment of the gate controller 230 shown in Figure 2. In this embodiment gate controller 230 includes the same constant current source 306 shown within Figure 3, which discharges capacitor 210 with constant current I2C when switch 226 is closed. Gate controller 230 includes a constant current source 604, N-channel MOSFET M2 and current mirror 606. The combination of M2 and current mirror 606 implement one embodiment of variable current source 304 shown within Figure 3. M2 transmits a reference current IR, which varies with ILOAD as will be more fully described below. Current mirror 606 has a scaling factor N. Current mirrors are well known in the art. A current mirror is a circuit designed to "copy" a reference current through one active device by controlling the current in another active device. IR is the current being "copied" by current mirror 606. Constant current source 604 and current mirror 606 charge capacitor 210 with constant current I1m and variable current IR / N, respectively, when switch 224 is closed. IR is related to ILOAD. The relationship is defined by the relative sizes of M1 and M2. M1 has a gate with W1 and a gate length L1, while M2 has a gate with W2 and a gate length L2. The gates of M1 and M2 are coupled together, and the sources M1 and M2 are coupled together as shown. In this configuration reference current IR = (ILOAD·W2·L1) / (W1·L2). The lengths and widths of M1 and M2 should be selected so that IR is a fraction of ILOAD. Variable charging current IR / N=(ILOAD·W2·L1) / (W1·L2·N). When switch 224 is closed, current mirror 606 and constant current source 604 charge capacitor 210 with variable current IR / N and constant current I1m. Gate voltage Vg, and thus VLOAD, increases as capacitor 210 is charged by IR / N and I1m. M1, M2, N, and I1m should be selected so that Vg increases at a rate that is slower than the rate at which VLOAD increases to avoid overshooting VRER_HI.

[0020] Figure 7 illustrates another embodiment of the gate controller 230 shown in Figure 2. Similarities exist between the gate controllers 230 shown in Figures 6 and 7. More particularly, gate controller 230 of Figure 7 includes the same constant current source 604, and N-channel MOSFET M2 that transmits reference current IR = (ILOAD·W2·L1) / (W1·L2). However, substantial differences exist between the gate controllers 230 of Figures 6 and 7. The gate controller 230 in Figure 7 includes constant current source 702, current mirror 704, and current mirror 706. Constant current source 604 and current mirror 704 charge capacitor 210 with constant current I1m and variable current IR / N1, respectively, when switch 224 is closed. Gate voltage Vg, and thus VLOAD, increases as capacitor 210 is charged by IR / N1=(ILOAD·W2·L1) / (W1·L2·N1) and I1m. M1, M2, N1, and I1m should be selected so that Vg should increases at a rate that is slower than the rate at which VLOAD increases. Current mirror 704 provides a separate variable current IR / N1 to current mirror 706 as a reference current. Current mirror 706 may be one embodiment of the variable current source 404 shown in Figure 4. Current mirror 704 has a scaling factor N2, which is distinct from scaling factor N1. In one embodiment, N2 is greater than N1. In another embodiment, N1 and N2 may be substantially equal. When switch 226 is closed, constant current source 702 and current mirror 706 discharge capacitor 210 with constant current I2m and variable current IR / (N1·N2)=(ILOAD·W2·L1) / (W1·L2 ·N1 ·N2), respectively. Gate voltage Vg, and thus VLOAD, decrease as capacitor 210 is discharged by IR / (N1·N2) and I2m. M1, M2, N1, N2 and I2m should be selected so that Vg decreases at a rate that is slower than the rate at which VLOAD decreases.

[0021] As noted above, pass device gate controller 230 should be configured to change Vg as fast as possible, but at a rate that is slower than the rate at which VLOAD changes, at least towards the end of the charging or discharging cycle, in order to prevent VLOAD from overshooting VREF_HI or undershooting VREF_LO. M1, M2, N, and I1m in Figure 6 should be selected so that Vg increases at a rate that is slower than the rate at which VLOAD increases. M1, M2, N1, and I1m in Figure 7 should be selected so that Vg increases at a rate that is slower than the rate at which VLOAD increases. And M1, M2, N1, N2 and I2m in Figure 7 should be selected so that Vg decreases at a rate that is slower than the rate at which VLOAD decreases. M2 should be a fraction of the size of M1 (e.g., M2:M1 = 1:1000). N1, N2, I1m and I2m may be selected based on the load transient requirements. For instance, for minimum load (e.g. R → infinite) the regulator loop will only rely on I1m and I2m to control the loop (that is Vg) since the current from mirrored devices are too small.

[0022] Pass device gate controller 230 also promotes a fast and stable response according to the imposed load at a low area cost, while maintaining low power characteristics. For example, Figures 8a - 8c illustrate transient waveforms for CVR 202 shown in Figure 6 with three different load steps and with VREF_LO = 0.9 V. Figure 8a shows the output voltage response to a load step of approximately 10µA from a leakage current of 2µA at t=700µs. Figure 8b shows the output voltage response to a load step of approximately 315µA from a quiescent current of 12µA t=1.083ms. Figure 8c shows the output voltage response to a load step of approximately 315µA from a quiescent current of 12µA at t=1.4667ms. In all three cases, it can be seen that the output voltage presents fast recovery time Δt with a smooth transient behavior.

Claims

1. An integrated circuit, IC (200), comprising: a load circuit (204); a voltage regulator circuit (202) configured to provide a load voltage (VLOAD), and a load current (ILOAD) to the load circuit (204), the voltage regulator circuit (202) comprising: a transistor (M1) comprising a first current electrode coupled to a supply conductor (VDD) a second current electrode coupled to the load circuit (204) and configured to provide the load voltage and the load current to the load circuit (204), and a control electrode for controlling the transistor (M1); a capacitor (210) coupled to the control electrode; a control circuit (230) that charges the capacitor (210) with a charging current (I1; I1 +IC1), changes in the charging current (I1; I1 +IC1) being proportional to changes in the actual load current (ILOAD), the control circuit (230) comprising a variable charging current source (304) for charging the capacitor (210) with the charging current; wherein the voltage regulator (202) circuit further comprises: a first switch (224) coupled between the supply conductor and the variable charging current source (304); a first comparator (220) for comparing a first reference voltage (VREF_LO) to the load voltage, wherein the first comparator (220) is configured to assert a first signal to close the first switch (224) when the first reference voltage (VREF_LO) exceeds the load voltage, thereby coupling the variable charging current source (304) to the supply conductor, whereby the control circuit (230) charges the capacitor (210) with the charging current when the first signal is asserted.

2. The IC (200) of any preceding claim wherein the control circuit (230) discharges the capacitor (210) with a discharging current (I2C) that varies with the actual load current (ILOAD).

3. The IC (200) of any preceding claim wherein the control circuit (230) discharges the capacitor (210) when the load voltage (VLOAD) rises above a second reference voltage (VREF_HI).

4. The IC (200) of any preceding claim wherein the control circuit (230) is coupled to the second current electrode.

5. The IC (200) of any preceding claim wherein the voltage regulator comprises: a second comparator (222) for comparing the second reference voltage (VREF_HI) to the load voltage (VLOAD); a second switch (226) controlled by the second comparator (222), wherein the second switch (226) is coupled between the ground conductor and the control circuit (230); wherein the second comparator (222) closes the second switch (226) to couple the control circuit (230) to the ground conductor when the load voltage (VLOAD) exceeds the second reference voltage (VREF_HI); wherein the control circuit (230) discharges the capacitor (210) with a discharging current when the second switch (226) is closed.

6. The IC (200) of any preceding claim wherein the control circuit (230) comprises: a current mirror (606); a second transistor (M2) comprising a third current electrode coupled to the current mirror (606), a fourth current electrode coupled to the load circuit (204) and configured to transmit a reference current from the current mirror (606) to the load circuit (204), and a second control electrode coupled to the capacitor (210); wherein changes in the charging current (IR +I1m) are proportional to changes in the reference current.

7. The IC (200) of claim 2, wherein: changes in the discharging current (I2C) are proportional to changes in the actual load current (ILOAD).

8. The IC (200) of claim 7 wherein the voltage regulator circuit (202) further comprises a variable discharging current source (404) for providing the discharging current.

9. The IC (200) of claim 7, wherein the variable discharging current source (404) comprises a second current mirror (706) that provides the discharging current.

10. The IC (200) of any preceding claim, wherein: the control circuit (230) is further configured to sense the actual load current (ILOAD); and wherein the control circuit (230) controls a voltage at the control electrode based upon the sensed load current (ILOAD).

11. The IC (200) of claim 7, wherein the discharging current (I2) is proportional (K2) to the actual load current (ILOAD).

12. The IC (200) of any previous claim, wherein the charging current comprises a constant current (I1C) from a constant current source (504) and a variable current (I1) from a variable current source (304), where the variable current (I1) is the load current (ILOAD) multiplied by a first constant (K1).

13. An integrated circuit, IC (200), comprising: a load circuit (204); a voltage regulator circuit (202) configured to provide a load voltage (VLOAD) and a load current (ILOAD) to the load circuit (204), the voltage regulator circuit (202) comprising: a transistor (M1) comprising a first current electrode coupled to a supply conductor (VDD) a second current electrode coupled to the load circuit (204) and configured to provide the load voltage and the load current to the load circuit (204), and a control electrode for controlling the transistor (M1); a control circuit (230) that charges a gate capacitance of the transistor (M1) with a charging current (I1; I1 +IC1), changes in the charging current (I1; I1 +IC1) being proportional to changes in the actual load current (ILOAD), the control circuit (230) comprising a variable charging current source (304) for charging the gate capacitance of the transistor (M1) with the charging current; wherein the voltage regulator (202) circuit further comprises: a first switch (224) coupled between the supply conductor and the variable charging current source (304); a first comparator (220) for comparing a first reference voltage (VREF_LO) to the load voltage, wherein the first comparator (220) is configured to assert a first signal to close the first switch (224) when the first reference voltage (VREF_LO) exceeds the load voltage, thereby coupling the variable charging current source (304) to the supply conductor, whereby the control circuit (230) charges the gate capacitance of the transistor (M1) with the non-linear charging current when the first signal is asserted.

14. The IC (200) of claim 13, wherein the charging current comprises a constant current (I1C) from a constant current source (504) and a variable current (I1) from a variable current source (304), where the variable current (I1) is the load current (ILOAD) multiplied by a first constant (K1).

15. The IC (200) of claim 13, wherein the control circuit (230) discharges the gate capacitance of the transistor, M1, with a discharging current comprising a constant current (I2C) provided by a constant current source (506) and a variable current (I2) from a variable current source (404), where the variable current (I2) is the load current (ILOAD) multiplied by a second constant (K2).