DISPLAY DEVICE

Description

Domaine technique

[0001] This description relates generally to the field of image display devices, and more specifically to an interactive image display device, combining a light emission function and an optical capture function, and a method for manufacturing such a device. Technique antérieure

[0002] Image display devices comprising a plurality of elementary monolithic electronic chips or microchips arranged in an array on a single substrate have already been proposed, for example in the applicant's previous patent applications WO2017089676, EP3401958, and WO2018185433. The elementary chips are mounted directly onto the substrate and connected to electrical connection elements on the substrate for control. Each chip comprises one or more light-emitting diodes (LEDs) and an integrated circuit for controlling said LED(s), and corresponds to one pixel of the device. The control integrated circuit includes a connection face opposite said LED(s), comprising a plurality of electrical connection areas for connection to the substrate for controlling the microchip.The mounting substrate comprises a connection face having, for each microchip, a plurality of electrical connection pads intended to be connected respectively to the electrical connection pads of the microchip. The chips are mounted on the mounting substrate, connection faces facing the connection face of the mounting substrate, and fixed to the mounting substrate so as to connect the electrical connection pads of each microchip to the corresponding electrical connection pads of the mounting substrate.

[0003] This type of display device is particularly suitable for creating large surface display screens, for example computer screens, television screens, tablet screens, etc.

[0004] This paper focuses specifically on the development of an interactive image display device that combines a light emission function with an optical capture function. More precisely, it examines the development of an interactive image display device that combines a visible light emission function for displaying images with a light emission-reception function, for example, infrared, for detection applications. Documents EP 3 958 309 A1 and US 2021 / 265323 A1 describe interactive image display devices incorporating LEDs and laser diodes. Summary of the invention

[0005] One embodiment provides for a device comprising: a substrate for carrying electrical connections; a plurality of first monolithic elementary chips fixed and electrically connected to the substrate, each first elementary chip comprising at least one LED and an integrated electronic circuit for controlling said at least one LED, the device further comprising, associated with at least one of the first elementary chips, a second elementary chip comprising a vertical cavity laser diode emitting through the surface, fixed and electrically connected to the carrier substrate, the first elementary chip comprising an integrated electronic control circuit for said laser diode.

[0006] According to one embodiment, the device further comprises a plurality of photosensitive detectors, and, associated with each photosensitive detector, an integrated electronic circuit for reading the photosensitive detector electrically connected to the reporting substrate.

[0007] According to one embodiment, each photosensitive detector is associated with a first elementary chip, the electronic circuit for reading the photosensitive detector being integrated into said first elementary chip.

[0008] According to one embodiment, each photodetector comprises a photosensitive organic layer.

[0009] According to one embodiment, each photodetector comprises an inorganic photodiode, for example based on type III-V semiconductor materials, for example based on indium-gallium arsenide, or based on amorphous silicon.

[0010] According to one embodiment, each photodetector includes a matrix layer, for example made of resin, in which quantum dots are incorporated.

[0011] According to one embodiment, each photodetector comprises a silicon photodiode in CMOS technology, an avalanche photodiode, or a detection device enabling the acquisition of information as to the distance between the device and the scene observed by direct or indirect measurement of the time of flight of light.

[0012] According to one embodiment, the laser diode is adapted to emit in a range of wavelengths sensitive to photodetectors, for example in the infrared.

[0013] According to one embodiment, in each first elementary chip, the electronic control circuit of said at least one LED and the electronic control circuit of the laser diode comprise MOS transistors formed in and on a single-crystal silicon layer.

[0014] According to one embodiment, in each first elementary chip, said at least one LED is an inorganic LED, for example gallium nitride.

[0015] According to one embodiment, in each first elementary chip, said at least one LED is adapted to emit visible light.

[0016] According to one embodiment, each first elementary chip includes an integrated electronic circuit adapted to control a laser diode of a second elementary chip, and the number of second elementary chips is less than the number of first elementary chips, so that some first elementary chips have their laser diode control circuit not connected to a laser diode.

[0017] According to one embodiment, the second elementary chip comprises two metallic connection areas connected respectively to an anode region and a cathode region of the laser diode, said two metallic connection areas being connected respectively to two metallic connection areas of the first elementary chip via conductive interconnection elements of the carrier substrate. Brève description des dessins

[0018] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the attached figures, among which: there figure 1A , there figure 1B , there figure 1C , there figure 1D , there figure 1E , there figure 1F , there figure 1G , there figure 1H , there figure 1I and the figure 1J are cross-sectional views illustrating successive stages of an example of a manufacturing process for elementary pixel chips of an interactive display device according to one embodiment; the figure 2 is a top view schematically and partially illustrating an example of a substrate for the transfer of an interactive display device according to one embodiment; the figure 3A , there figure 3B and the figure 3C are cross-sectional views illustrating successive stages of an example of a manufacturing process for an interactive display device according to one embodiment; and the figure 4 is a schematic top view of an example of an interactive display device according to one embodiment. Description des modes de réalisation

[0019] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0020] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and detailed. In particular, the various applications that the described interactive display devices can have have have not been detailed, as the described embodiments are compatible with all or most known applications of an emissive display device incorporating a light emission-reception function, for example, motion detection, face recognition, identification, etc.

[0021] Unless otherwise specified, when referring to two connected elements, this means directly connected without any intermediate elements other than conductors, and when referring to two coupled elements, this means that these two elements can be connected or linked through one or more other elements.

[0022] In the description that follows, when referring to absolute positional qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative positional qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientational qualifiers, such as the terms "horizontal", "vertical", etc., unless otherwise specified, it refers to the orientation of the figures.

[0023] Unless otherwise specified, the expressions "approximately", "roughly", "about", and "on the order of" mean within 10%, preferably within 5%.

[0024] According to one embodiment, an image display device is provided comprising a plurality of elementary monolithic electronic chips arranged in an array on a single substrate. As in the examples described in the applicant's previously filed patent applications WO2017089676, EP3401958, and WO2018185433, the elementary chips are mounted directly onto the substrate and connected to electrical connection elements of the substrate. Each chip comprises one or more LEDs and a control circuit for said LED(s) and corresponds to a pixel of the display device. The control circuit includes a connection face opposite said LED(s), comprising a plurality of electrical connection areas (also called terminals or pads) for connection to the substrate for controlling the microchip.The mounting substrate comprises a connection face with, for each microchip, a plurality of electrical connection pads (also called terminals or pads) intended to be connected respectively to the electrical connection pads of the microchip. The chips are mounted onto the mounting substrate with their connection faces facing the connection face of the mounting substrate, and fixed to the mounting substrate so as to connect the electrical connection pads of each microchip to the corresponding electrical connection pads of the mounting substrate.

[0025] According to one aspect of an embodiment, the image display device further includes a function for emitting and receiving light radiation, for example infrared, enabling the detection of elements or variations in the environment of the device.

[0026] For this purpose, the device includes a plurality of photosensitive detectors, for example organic photodetectors, for example arranged in a matrix according to rows and columns, defining an image sensor.

[0027] The display device further includes one or more vertical-cavity surface-emitting laser diodes, also called VCSELs (from the English "Vertical-cavity surface-emitting laser", adapted to emit in a wavelength range of sensitivity of photosensitive detectors.

[0028] VCSELs, for example, are external to the individual pixel chips of the display device and are located on the device's substrate, on the same side of the substrate as the individual pixel chips. VCSELs are connected, for example, to electrical connection terminals on the substrate for control.

[0029] As an example, the device includes one VCSEL diode per pixel chip of the device, positioned in the vicinity of said pixel chip. In other words, the pixel chip array of the display device and the VCSEL diode array are interleaved matrices of the same dimensions and pitch.

[0030] For example, photodetectors are also external to the individual pixel chips of the display device and are located on the device's substrate, on the same side of the substrate as the individual pixel chips. The photodetectors are connected to electrical terminals on the substrate for reading.

[0031] As an example, the device includes one photodetector per pixel chip of the device, positioned in the vicinity of said pixel chip. In other words, the matrix of pixel chips of the display device and the matrix of photodetectors are interlaced matrices of the same dimensions and the same pitch.

[0032] According to one embodiment, each pixel chip of the display device incorporates an electronic control circuit for the corresponding VCSEL diode, i.e., the diode in the same position within the pixel matrix of the device. Each pixel chip of the device comprises two connection terminals linked, for example, to the two electrodes of the VCSEL diode via conductive traces on the substrate.

[0033] Each pixel chip in the display device can also incorporate an electronic circuit for reading an electrical signal representing the light intensity received by the corresponding photodetector—that is, the one in the same position within the pixel matrix of the device. In this case, each pixel chip in the device includes a connection terminal individually connected to an electrode of the associated photodetector via a conductive trace on the signal carrier substrate.

[0034] Examples of the implementation of such an interactive display device will be described in more detail below in relation to the figures.

[0035] THE figures 1A à 1J These are cross-sectional views illustrating an example of a manufacturing process for the device's elementary pixel chips.

[0036] There figure 1A includes a view (a) schematically representing a control structure comprising a first substrate 101 in and on which a plurality of elementary control integrated circuits 103 have been formed, for example identical or similar, corresponding respectively to the control integrated circuits of the future elementary pixel chips of the device.

[0037] In the example shown, the substrate 101 is a SOI (Semiconductor On Insulator) type substrate, comprising a support semiconductor substrate 101a, for example of silicon, an insulating layer 101b, for example of silicon oxide, disposed on and in contact with the upper face of the support substrate 101a, and an upper semiconductor layer 101c, for example of monocrystalline silicon, disposed on and in contact with the upper face of the insulating layer 101b.

[0038] In this example, the elementary control circuits 103 are formed in and on the upper semiconductor layer 101c of the substrate 101. Each elementary control circuit 103 comprises, for example, a plurality of MOS transistors (not detailed in the figures 1A à 1I The elementary control circuits 103 are, for example, implemented using CMOS technology (Complementary Metal Oxide Semiconductor). Each elementary control circuit 103 may include a circuit adapted to control the light emission by the LED(s) of the future pixel chip of the device, and a control circuit adapted to control the light emission by the VCSEL diode associated with the future pixel chip of the device. Each elementary control circuit 103 may also include a readout circuit for the photodetector associated with the future pixel chip of the device.

[0039] In this example, each elementary control circuit 103 includes, on its upper face, one or more metallic connection pads 105a, 105b. For example, the pads 105a, 105b are flush with the upper face of an upper insulating layer, for example of silicon oxide, of an interconnect stack (not detailed in the figures) covering the upper face of the upper semiconductor layer 103c of the substrate 101. Thus, in this example, the upper surface of the control structure of view (a) is a flat surface comprising an alternation of metallic regions (the pads 105a, 105b) and insulating regions.

[0040] For example, each control circuit element 103 includes a specific metal pad 105a for each LED of the future pixel chip of the device, intended to be connected to an anode region of the LED and allowing individual control of the light emission by said LED. Each control circuit element 103 may further include a metal pad 105b intended to be connected to a cathode region of each LED of the future pixel chip of the device. In the case where the chip contains several LEDs, the cathode contact may be common to all the LEDs on the chip. Thus, the control circuit element 103 may include a single metal pad 105b.

[0041] As an example, each elementary pixel chip of the device comprises three individually controllable LEDs adapted to emit blue, green, and red light, respectively. In this case, each elementary control circuit 103 may comprise three separate metal pads 105a intended to be connected respectively to the anode regions of the three LEDs, and a single metal pad 105b intended to be connected collectively to the cathode regions of the three LEDs. On the figure 1A , only two metal pads 105a and one metal pad 105b per electronic circuit have been represented.

[0042] There figure 1A It further includes a view (b) schematically representing a structure comprising a second substrate 111, on the upper surface of which rests an active stack of LEDs 113. The active stack of LEDs 113 is, for example, a stack of inorganic LEDs, for example based on one or more III-V semiconductor materials, for example based on gallium nitride. The substrate 111 is, for example, made of sapphire or silicon.

[0043] The active stack of LEDs 113 comprises, for example, in order from the top face of the substrate 111, an N-type doped semiconductor layer forming a cathode layer, an active layer, and a P-type doped semiconductor layer forming an anode layer (layers not detailed in the figure). The active layer includes, for example, alternating layers of quantum wells in a first semiconductor material and barrier layers in a second semiconductor material, defining a stack of multiple quantum wells.

[0044] The active stack 113 can be formed by epitaxy on the upper face of the substrate 111. As an alternative, the active stack 113 is formed by epitaxy on a growth substrate, not shown, and then transferred to the upper face of the substrate 111.

[0045] At this stage, the stack 113 is not yet structured into individual LEDs. In other words, the layers of the stack 113 extend continuously and with a substantially uniform thickness over the entire upper surface of the substrate 111.

[0046] There figure 1B includes a view (a) illustrating a step of deposition of a metallic layer 107 on and in contact with the upper face of the control structure of view (a) of the figure 1A In this example, layer 107 extends continuously and with a substantially uniform thickness over the entire upper surface of the interconnect stack of the control structure of view (a) of the figure 1A . Thus, layer 107 connects all the metal studs 105a, 105b of the control structure to each other.

[0047] There figure 1B further includes a view (b) illustrating a step of depositing a metallic layer 115 on and in contact with the upper face of the active LED stack 113 of the structure of view (b) of the figure 1A The metallic layer 115 can be a single layer or a stack of several metallic layers. Preferably, the metallic layer 115 comprises, on its upper face, a layer of the same material as the layer 107.

[0048] There figure 1C illustrates the structure obtained after a step of transferring and fixing the active stack of LEDs 113 and the metallic layer 115 onto the structure of view (a) of the figure 1B .

[0049] On the figure 1C , the orientation of the structure of the view (a) of the figure 1B remains unchanged. However, the elements of the view structure (b) of the figure 1B are reversed with respect to the orientation of the figure 1B .

[0050] During this step, the structure of view (b) of the figure 1B is reported on the upper face of the structure of view (a) of the figure 1B using substrate 111 as a handle. The underside (in the orientation of the figure 1C , corresponding to the upper face in the orientation of the figure 1B ) of the metallic layer 115 is fixed to the upper face of the metallic layer 107. The fixing is obtained for example by direct bonding or molecular bonding of the lower face of the layer 115 to the upper face of the layer 107, that is to say without the addition of material between the two layers.

[0051] The substrate 111 is then removed, for example by grinding and / or chemical etching, so as to free access to the top face of the active LED stack 113, i.e., in this example, the top face of the cathode semiconductor layer of the active LED stack 113.

[0052] There figure 1D illustrates a trench formation step 121 extending vertically in the active LED stack from its top face and laterally delimiting, in the stack 113, a plurality of islands 123 corresponding to the individual LEDs of the future elementary chips of the device. The trenches 121 are formed, for example, by plasma etching. In the example of the figure 1D , the trenches 121 are interrupted on the upper face of the metallic layer 115. In top view (not shown), the trenches 121 form a grid separating laterally the elementary diodes 123 from each other.

[0053] There figure 1E This illustrates a subsequent step of vertically extending the trenches 121 through the metallic layers 107 and 115, for example using the same etching mask (not shown) as that used in the previous step. At the end of this step, the trenches 121 emerge onto the upper face of the interconnect stack covering the upper face of the substrate 101.

[0054] The portion of the stack of layers 107 and 115 remaining beneath each LED 123 after this step constitutes an anode electrode of the LED. This anode electrode is in contact, via its lower face, with the upper face of a metal connection pad 105a of the underlying control circuit element 103. Thus, each LED has its anode electrode individually connected to a metal connection pad 105a of a control circuit element 103.

[0055] In this example, a trench 121 is further formed opposite each metal connecting block 105b so as to free access to the upper face of the blocks 105b.

[0056] There figure 1E This further illustrates a subsequent step of passivating the sides of the LEDs 123. For this purpose, a layer 125 of an electrically insulating material, for example silicon oxide or silicon nitride, is deposited by a conformal deposition method on the upper surface of the structure. The layer 125 then coats the upper surface and sides of the LEDs 123, as well as the sides of the portions of the metal layers 107 and 115 located beneath the LEDs 123, and, at the bottom of the trenches 121, the upper surface of the interconnect stack covering the substrate 101. A vertical anisotropic etching step is then carried out to remove the horizontal portions of the layer 125, retaining only the vertical portions of this layer, which coat the sides of the LEDs 123 and the sides of the portions of the metal layers 107 and 115 located beneath the LEDs 123.

[0057] There figure 1F illustrates a subsequent step of filling the trenches 121 with metal 127. As an example, the metal 127 is initially deposited over the entire upper surface of the structure with a thickness greater than the depth of the trenches 121, so as to completely fill the trenches 121. A planarization step, for example by chemical polishing, is then carried out to provide access to the upper face of the LEDs 123. This results in a substantially flat upper surface on which the cathode semiconductor regions of the LEDs 123, the vertical insulation regions 125 of the LEDs, and the metallic regions 127 filling the trenches 121 are flush. In top view (not shown), the metallic regions 127 form a conductive grid separating the LEDs 123 laterally from each other.The metallic regions 127 are electrically connected to the metallic pads 105b at the bottom of the trenches 121, and define a common cathode contact metallization for all the LEDs 123 in the structure.

[0058] There figure 1G illustrates a subsequent step of depositing a conductive layer 129, transparent to the emission wavelengths of the LEDs of the display device, onto the upper surface of the structure. The layer 129 extends, for example, continuously and with a substantially uniform thickness over the entire upper surface of the structure of the figure 1F The 129 layer is, for example, a transparent conductive oxide, such as indium tin oxide (ITO). Alternatively, the 129 layer can be a metallic layer thin enough to be transparent, for example, a silver layer less than 80 nm thick.

[0059] Layer 129 is in contact, by its lower face, with the upper face of the cathode semiconductor regions of the LEDs 123, and defines a common cathode electrode of the LEDs 123. Layer 129 is also in contact, by its lower face, with the upper face of the metallic region 127. Thus, layer 129 electrically connects the cathode semiconductor region of each LED 123 to the common cathode contact metallization 127 of the structure.

[0060] There figure 1H illustrates a later stage in the transfer of the structure of the figure 1G on a temporary support substrate 140. On the figure 1H The orientation of the structure is reversed with respect to the orientation of the figure 1G The temporary support substrate is fixed to the face of the conductive layer 129 opposite the substrate 101, i.e., its lower face in the orientation of the figure 1H (corresponding to its upper face in the orientation of the figure 1G The temporary support substrate 140 is, for example, a silicon substrate. The temporary support substrate 140 can be attached to the conductive layer 129 using an adhesive bonding layer, or by direct bonding.

[0061] There figure 1H further illustrates a subsequent step of removing the support substrate 101a from the starting SOI structure, for example by grinding and / or chemical etching, so as to free access to the upper face of the insulating layer 101b of the SOI structure.

[0062] It should be noted that the embodiments described are not limited to the example described above in which substrate 101 is a SOI-type substrate. As an alternative, substrate 101 can be a bulk semiconductor substrate, for example, silicon. In this case, at the step of the figure 1A , substrate 101 can be thinned from its rear face (upper face in the orientation of the figure 1H ), for example by grinding. An insulating passivation layer, for example of silicon oxide, can then be deposited on the top face of the thinned substrate, replacing layer 101b of the SOI substrate. Alternatively, layer 101b can be omitted.

[0063] There figure 1I This illustrates the structure obtained after the formation of contact re-establishment apertures in layers 101b and 101c, and the formation of contact re-establishment metallizations 131 in and on said apertures. The contact metallizations 131 allow electrical contact to be re-established on metallic levels (not detailed in the figures) of the interconnect stack located on the underside of the semiconductor layer 101c. The metallizations 131 are, for example, electrically connected to transistors in the control circuit, these transistors being themselves connected or electrically linked to contact metallizations 105a, 105b of the LEDs.

[0064] The metallizations 131 form connection terminals for the future elementary pixel chips of the device, intended to be connected to corresponding connection terminals of the device's carrier substrate.

[0065] There figure 1J This illustrates the structure obtained after a step of individualizing the elementary pixel chips of the device. For this purpose, trenches 151 extending vertically through layers 101b, 101c, 127, and 129 are formed from the top face of the structure, along cutting lines. In this example, the trenches open onto the top face of the temporary support substrate 140. From a top view, the trenches 151 form a continuous grid laterally delimiting a plurality of elementary pixel chips 153, for example, identical or similar, each comprising an elementary control circuit 103 and one or more LEDs 123. The trenches 151 are, for example, produced by plasma etching.

[0066] It should be noted that in the example described in relation to the figures 1A à 1J The elementary LEDs 123 are formed from the same active stack of LEDs and all emit at the same wavelength. Where the elementary chips 153 each comprise several LEDs 123, steps for forming differentiated light conversion elements on the different LEDs 123 of each chip can be provided, for example, after the deposition of the conductive cathode layer 129 and before the attachment of the temporary support substrate 140. For the sake of simplicity, the fabrication of the conversion elements has not been detailed in the figures. The fabrication of these elements is within the grasp of a person skilled in the art upon reading this description. Alternatively, each elementary chip may comprise LEDs 123 of different types adapted to emit respectively in different wavelength ranges, in which case the conversion elements can be omitted.

[0067] The 153 pixel elementary chips are intended to be transferred onto a 200 substrate of the display device, as will be described in more detail below in relation to the figures 3A à 3C .

[0068] There figure 2 is a schematic and partial top view of an example implementation of the 200 report substrate of the display device.

[0069] The transfer substrate 200 comprises, for example, a support plate or sheet 201 made of an insulating material, for example, glass or plastic. Alternatively, the support plate or sheet 201 comprises a conductive substrate, for example, metallic, covered by a layer of an insulating material. The transfer substrate further comprises electrical connection elements, and in particular conductive tracks and conductive areas, formed on the upper surface of the support plate 201. These electrical connection elements are formed, for example, by printing a succession of conductive and insulating layers on the upper surface of the support plate 201. The electrical connection elements are formed, for example, by a deposition or printing process such as inkjet printing, screen printing, rotogravure, vacuum deposition, or any other suitable method.

[0070] In the example shown, the carry substrate 200 comprises two conductive metal layers M1 and M2 separated by an insulating layer (not visible in the figure), and metal vias V connecting the two metal layers through the insulating layer. In this example, the carry substrate 200 further comprises metal connection pads formed on the upper metal layer M2, intended to be connected to corresponding connection pads 131 of the pixel element chips 153 of the device.

[0071] Active control circuits for the display device (not shown), adapted to power and control the elementary chips of the device via the electrical connection elements of the transfer substrate, are for example connected to the electrical connection elements of the transfer substrate at the periphery of the transfer substrate 200.

[0072] In the example shown, the fabrication of the transfer substrate includes the following three successive deposition steps.

[0073] In a first deposition step, a plurality of conductive tracks are formed on the upper face of the support plate 201, substantially parallel to the direction of the columns of the display device (vertical direction in the orientation of the figure 2 More specifically, in this example, during the first deposition step, four conductive tracks C1, C2, C3, and C4 are formed for each column of the display device, extending along approximately the entire length of the display device's columns. The C1 tracks are designed to carry a DATA-L signal for adjusting the light intensity emitted by the LEDs 123 of the column's elementary chips 153. Note that in this example—which is not exhaustive—the intensity adjustment signals for the different colors (red, green, blue) are transmitted sequentially via the C1 track. As an alternative, not shown, several separate tracks can be used to transmit the intensity adjustment signals for the different colors in parallel, on separate terminals of each elementary chip. The C2 tracks are designed to carry a DATA-V signal for adjusting the light intensity emitted by the VCSEL diodes of the column's pixels.Traces C3 are designed to carry a DATA-S signal representing the light intensity received by the photodetectors of the column pixels. Traces C4 are designed to distribute a high VDD supply potential to the various 153 pixel elementary chips.

[0074] The conductive elements formed during this first deposition stage define the first conductive level M1 of the transfer substrate.

[0075] In a second deposition step, the first conductive level is covered with an insulating material (not visible in the figure), so as to allow the subsequent deposition of conductive tracks extending above tracks C1, C2, C3 and C4, without creating a short circuit with tracks C1, C2, C3 and C4.

[0076] In a third deposition step, a plurality of conductive tracks, substantially parallel to the direction of the display line lines, are formed on the upper surface of the support plate 201. More specifically, in this example, during the third deposition step, three conductive tracks L1, L2, and L3 are printed for each line of the display, extending over substantially the entire length of the display line. The L1 tracks are intended to carry an SEL-L signal for selecting the corresponding pixel line. The L2 tracks are intended to carry an SEL-V signal for selecting the corresponding VCSEL diode line. The L3 tracks are intended to carry an SEL-S signal for selecting the corresponding photodetector line.

[0077] In this example, during the third deposition step, a metallic region EL1 defining a lower electrode of the photodetector of the display device is also printed for each pixel of the device.

[0078] The conductive elements printed during this third deposition stage define the second conductive level M2 of the transfer substrate.

[0079] After the third deposition step, for each pixel, ten metallic patches P1, P2, P3, P4, P5, P6, P7, P8, P9, and P10 are formed on conductive areas of the metallic layer M2. These patches are designed to receive ten separate connection patches 131 of the pixel's elementary chip 153. In addition, for each pixel, two metallic patches P11 and P12 are formed on conductive areas of the metallic layer M2. These patches are designed to receive two separate connection patches of the pixel's VCSEL diode. Patches P6, P7, and P8 are connected to the pixel's conductive tracks L1, L2, and L3, respectively. Patch P9 is connected to the pixel's electrode EL1. Patches P5 and P10 are connected to the pixel's patches P11 and P12, respectively.The aforementioned connections are made by conductive elements formed in the metallic level M2, and, possibly, by vias V (opened between the second and third deposition stages) and conductive elements formed in the metallic level M1.

[0080] THE figures 3A à 3C are cross-sectional views illustrating successive stages of an example of a manufacturing process for an interactive display device according to an embodiment.

[0081] There figure 4 is a schematic top view of the device obtained at the end of the process of figures 3A à 3C .

[0082] THE figures 3A et 3B illustrate more specifically a collective transfer step of elementary pixel chips 153 onto the transfer substrate 200.

[0083] The individual chips 153 are initially attached to one face of the temporary support substrate 140. The structure comprising the temporary support substrate 140 and the individual chips 153 is, for example, produced by a process of the type described in relation to the figures 1A à 1J In the example shown, the structure is reversed with respect to the orientation of the figure 1J that is to say that the elementary chips 153 are arranged on the underside of the temporary support substrate 140.

[0084] For the sake of simplicity, on the figures 3A à 3C The elementary chips 153 and the carrying substrate 200 have been represented schematically, and many elements have been omitted compared to the representations of the figures 1J And 2 .

[0085] The elementary chips 153 are collectively reported opposite the connection face of the substrate of transfer 200, namely its upper face in the orientation of the figures 3A et 3B using the temporary support substrate 140 as a handle ( figure 3A ).

[0086] The connection terminals 131 of the elementary chips 153, located on the underside of said chips, are then brought into contact with the corresponding connection areas P1, P2, P3, P4, P5, P6, P7, P8, P9 and P10 of the carrier substrate 200, and fixed to said connection areas P1, P2, P3, P4, P5, P6, P7, P8, P9 and P10. The fixing of the connection terminals 131 of the elementary chips 153 to the connection areas of the carrier substrate is carried out, for example, by direct bonding, by heat compression, by brazing, by means of metallic microstructures (for example, micro-pillars) previously formed on the terminals 131, or by any other suitable fixing and connection method.

[0087] Once fixed, by their connection terminals 131, to the transfer substrate 200, the elementary chips 153 are detached from the temporary support substrate 140 and the latter is removed ( figure 3B ), freeing up access to the emitting face of the 123 LEDs (not detailed on the figures 3A à 3C ).

[0088] The spacing of the elementary chips 153 on the transfer substrate 200 can be greater than the spacing of the elementary microchips 153 on the temporary support substrate 140. Preferably, the spacing of the elementary chips 153 on the transfer substrate 200 is a multiple of the spacing of the elementary microchips 153 on the temporary support substrate 140. In this case, only a portion of the chips 153 are taken from the support substrate 140 with each transfer, as illustrated in the figures 3A et 3B The other chips 153 remain attached to the temporary support substrate 140 and can be used in another collective transfer step to populate another part of the transfer substrate 200 or another transfer substrate.

[0089] The method further includes, before or after the step of transferring and fixing the elementary chips 153 onto the transfer substrate 200, a step of transferring and fixing, on the same transfer substrate 200, elementary chips of VCSEL diodes 223 ( figure 4 - not visible on the figures 3A à 3C ), distinct from the elementary chips 153. Each elementary VCSEL diode chip 223 comprises, for example, a single VCSEL diode. Each elementary VCSEL diode chip 223 comprises, for example, two metallic electrical connection areas arranged on the side of its face facing the carrier substrate, called the connection face, and intended to be fixed and electrically connected to the corresponding metallic connection areas P11 and P12 of the carrier substrate 200. Each elementary VCSEL diode chip 223 comprises, for example, only two metallic connection areas to the carrier substrate 200, connected respectively to an anode region and a cathode region of the VCSEL diode.

[0090] Each elementary VCSEL diode chip includes a light-emitting face located on the side of the chip opposite its connection face. The connection face and the emission face are, for example, parallel to the connection face of the substrate in the 200 carryover stage. As an example, each VCSEL diode includes an active emissive layer located between two reflective structures, for example, Bragg mirrors. The VCSEL diodes in the 223 chips are, for example, of the type described in the article entitled "Vertical-cavity surface-emitting lasers for optical interconnects" by Hui Li et al.

[0091] The VCSEL 223 diode element chips are, for example, transferred and fixed onto the transfer substrate 200 by a collective transfer process, for example similar to the collective transfer process for the pixel element chips 153 described in relation to the figures 3A et 3B .

[0092] As an alternative, the VCSEL 223 diode elementary chips are transferred and fixed onto the transfer substrate 200 individually, for example by an automated pick and place process.

[0093] There figure 3C illustrates the device after fixing all the elementary chips 153 and the elementary diode chips VCSEL 223 (not visible in the figure) onto the transfer substrate 200.

[0094] There figure 3C This further illustrates a subsequent step of deposition, within each pixel, of a portion of a photosensitive organic layer 203, for example, sensitive in the infrared or near-infrared, onto and in contact with the upper surface of the pixel's EL1 electrode. The portions of layer 203 are deposited, for example, by a localized printing process, such as screen printing, or by a slot-die coating process. In each pixel, the portion of organic layer 203 extends, for example, over the entire upper surface of the pixel's EL1 electrode.

[0095] There figure 3C This further illustrates a subsequent step of deposition, in each pixel, of an upper electrode EL2 on and in contact with the upper surface of the portion of the photosensitive organic layer 203 of the pixel. The electrode EL2 extends, for example, over the entire upper surface of the portion of the photosensitive organic layer 203 of the pixel. The electrode EL2 is transparent to the sensitivity wavelengths of the layer 203. As an example, the electrode EL2 is made of a transparent conductive oxide, for example, ITO. In this example, in each pixel, the stacking of the layers EL1, 203, and EL2 forms a photodetector 211. The electrodes EL1 and EL2 correspond, for example, to the cathode and anode electrodes of the photodetector, respectively.

[0096] The EL2 electrodes can be deposited locally using a stencil. For example, the top electrode EL2 is common to all pixels of the device. In a top view, the EL2 electrode forms, for instance, a continuous grid covering the portions of the photosensitive layer 203 of all pixels in the device, as illustrated in the schematic top view of the figure 4 The common electrode EL2 can then be connected to a node applying a fixed polarization potential at the periphery of the pixel matrix.

[0097] As an alternative, the photodetectors 211 can be formed before the steps of transferring and fixing the elementary chips 153 and 223 onto the transfer substrate 200, or between the step of transferring and fixing the elementary chips 153 and the step of fixing the elementary chips 223 onto the transfer substrate 200.

[0098] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will become apparent to them. In particular, the embodiments described are not limited to the specific examples of the pixel element chips and the carry substrate described in connection with the figures1A à 1J , 2, 3A has 3C et 4 .

[0099] Furthermore, the described embodiments are not limited to the specific case described above in which the device's photodetectors are organic photodiodes. As an alternative, the organic photodetectors of the described device can be replaced by inorganic photodetectors, for example, based on type III-V semiconductor materials, such as indium gallium arsenide, or amorphous silicon. In another variant, the photodetectors 211 can consist of a matrix layer, for example made of resin, in which quantum dots are embedded.As an alternative, the photodetectors can be silicon photodiodes in CMOS technology, avalanche photodiodes, for example of the SPAD type (from the English "Single Photon Avalanche Diode"), or any other detection device allowing the detection of a light signal backscattered by the scene, for example allowing the acquisition of information as to the distance between the device and the scene observed, for example by direct or indirect measurement of the time of flight of the light.

[0100] Furthermore, the described embodiments are not limited to the specific example described above in which the readout electronic circuit of each photodetector 211 is integrated into the elementary chip 153 of the corresponding pixel. Alternatively, the readout electronic circuit of the photodetector can be integrated into a separate chip. In this case, the photodetector 211 may not be connected to the elementary chip 153 of the pixel. For example, the photodetector 211 and its readout electronic circuit can be integrated into a single monolithic chip, separate from chips 153 and 223, and fixed and electrically connected to corresponding electrical connection areas of the carrier substrate 200. In another embodiment, each photodetector 211 can be integrated into the elementary chip 153 of the corresponding pixel.

[0101] Furthermore, the described embodiments are not limited to the specific examples described above in which the device comprises one VCSEL diode 223 elementary chip and one photodetector 211 per visible pixel 153 elementary chip. Alternatively, the number of VCSEL diode 223 elementary chips may be less than the number of 153 elementary chips. In this case, the VCSEL diode driver circuit is not used in some of the 153 elementary chips. Similarly, the number of photodetectors 211 may be less than the number of 153 elementary chips.

[0102] Furthermore, the embodiments described are not limited to the examples described above of application to interactive display devices, but can be applied more generally to other LED emitting devices that can take advantage of the use of VCSEL type emitting cells, while remaining within the scope of the invention defined by the accompanying claims.

[0103] Finally, the practical implementation of the described methods and variants is within the reach of the person in the trade, based on the functional indications given above.

Claims

1. Device comprising: - a transfer substrate (200) comprising electric connection elements; - a plurality of first elementary monolithic chips (153) bonded and electrically connected to the transfer substrate (200), each first elementary chip (153) comprising at least one LED (123) and one integrated electronic circuit for controlling said at least one LED (123), the device further comprising, associated with at least one of the first elementary chips (153), a second elementary chip (223) comprising a vertical cavity surface-emitting laser diode, bonded and electrically connected to the transfer substrate (200), the first elementary chip (153) comprising an integrated electronic circuit for controlling said laser diode.

2. Device according to claim 1, further comprising a plurality of photosensitive detectors (211), and, associated with each photosensitive detector, an integrated electronic circuit for reading from the photosensitive detector electrically connected to the transfer substrate (200).

3. Device according to claim 2, wherein each photosensitive detector (211) is associated with a first elementary chip, the electronic circuit for reading from the photosensitive detector (211) being integrated to said first elementary chip.

4. Device according to claim 2 or 3, wherein each photodetector (211) comprises an organic photosensitive layer.

5. Device according to claim 2 or 3, wherein each photodetector comprises an inorganic photodiode, for example based on type-III-V semiconductor materials, for example based on indium gallium arsenide, or based on amorphous silicon.

6. Device according to claim 2 or 3, wherein each photodetector comprises a matrix layer, for example made of resin, having quantum dots incorporated therein.

7. Device according to claim 2 or 3, wherein each photodetector comprises a photodiode made of silicon in CMOS technology, an avalanche photodiode, or a detection device enabling to acquire information relative to the distance between the device and an observed scene by direct or indirect measurement of the time of flight of light.

8. Device according to any of claims 2 to 7, wherein said laser diode is adapted to emitting in a wavelengths range of responsivity of the photodetectors (211), for example in infrared.

9. Device according to any of claims 1 to 8, wherein, in each first elementary chip (153), the electronic circuit for controlling said at least one LED and the electronic circuit for controlling the laser diode comprise MOS transistors formed inside and on top of a single-crystal silicon layer (103c).

10. Device according to any of claims 1 to 9, wherein, in each first elementary chip (153), said at least one LED (123) is an inorganic LED, for example with gallium nitride.

11. Device according to any of claims 1 to 10, wherein, in each first elementary chip (153), said at least one LED (123) is adapted to emitting visible light.

12. Device according to any of claims 1 to 11, wherein each first elementary chip (153) comprises an integrated electronic circuit adapted to controlling a laser diode of a second elementary chip (223), and wherein the number of second elementary chips (223) is smaller than the number of first elementary chips (153), so that certain first elementary chips (153) have their laser diode control circuit not connected to a laser diode.

13. Device according to any of claims 1 to 12, wherein said second elementary chip (223) comprises two metal connection areas respectively coupled to an anode region and to a cathode region of the laser diode, said two metal connection areas being connected to respectively two metal connection areas of the first elementary chip (153) via conductive interconnection elements of the transfer substrate (200).