CIRCUIT FOR NON-DESTRUCTIVE READING OF FERROELECTRIC STORAGE

Description

Scope of application

[0001] The invention generally relates to data storage circuits based on ferroelectric non-volatile memory cells. More particularly, the invention relates to a circuit for non-destructive reading of ferroelectric memories. Problem raised

[0002] Non-volatile memories present emerging solutions for implementing data storage means in a computer circuit. Ferroelectric memories with variable electrical polarization exhibit high write endurance and low write energy. Figure 1a presents a structural example of an elementary NVM (Non Volatile Memory) component of a ferroelectric memory cell with variable electrical polarization, more precisely a FeRAM (Ferroelectric Random Access Memory) type component.

[0003] In the illustrated example, the elementary component NVM consists of the stack of thin layers in the following order: a first layer C1 made of an electrically conductive material forming a first electrode EL1; a second layer C2 made of a dielectric and ferroelectric material and a third layer C3 made of electrically conductive material forming a second electrode EL2. The second layer C2 is referred to in the remainder of the description as the “central layer”.

[0004] The stack of thin layers forms a MIM (acronym Metal-Insulator-Metal) type structure acting as a capacitive element with a capacitance C. The ferroelectric character of the central layer C2 induces the following behavior: when a positive electrical voltage is applied to the upper electrode EL2, the polarization of the electric dipoles of the central layer is directed in a so-called "negative" direction. Conversely, when a positive electrical voltage is applied to the lower electrode EL2, the polarization of the electric dipoles is directed in a so-called "positive" direction. The direction of the electrical polarization in the central layer C2 corresponds to a state of equilibrium maintained even in the absence of the electric field induced by the voltage applied to one of the electrodes EL1 or EL2, hence the operation in ferroelectric memory.

[0005] Thus, the following convention is chosen as an example: when an NVM memory component is configured to store binary data in the low logic state (x = 0), a write electrical voltage is temporarily applied to the upper electrode EL2 (illustrated by polarization +) so as to obtain a polarization directed in a “negative” direction in the central layer C2. Conversely, when an NVM memory component is configured to store binary data in the high logic state (x = 1), a write electrical voltage is temporarily applied to the lower electrode EL1 (illustrated by polarization -) so as to obtain a polarization directed in a “positive” direction in the central layer C2.

[0006] However, the read operation of a ferroelectric non-volatile memory is a destructive operation. Indeed, during a read access, the elementary NVM component receives a read electrical voltage on the upper electrode so as to rewrite it to a low logic state (x=0). We then observe the dynamics of the transition following the application of the read voltage. If the electric dipoles of the central layer are previously polarized with an orientation in a "positive" direction (x=1), a relatively large quantity of electric charges will be emitted by the device during the transition. Conversely, if the electric dipoles of the central layer are previously polarized with an orientation in a "negative" direction (x=0), the quantity of charges delivered during the transition is lower.As a result, the reading procedure consists of estimating the quantity of charges emitted during a polarization to a low logic state (x=0) and therefore erases the logic value of the stored data.

[0007] In this context, a technical problem to be solved is the destruction of the logical content of a ferroelectric memory cell with variable electrical polarization following a read operation.

[0008] Moreover, increasing the number of ferroelectric non-volatile memory cells induces an increase in the parasitic capacitance at the bit lines BL (Bit line in English). The increase in the value of said parasitic capacitance induces a drastic reduction in the sensitivity of known reading circuits.

[0009] In addition, the densification of memory matrices used in embedded systems requires a reduction in the surface area occupied by each elementary NVM component. This leads to a reduction in the electrical capacity of each elementary NVM component. This leads to a reduction in the read sensitivity of this type of memory.

[0010] To summarize, several technical problems arise concerning the reading of ferroelectric memories with variable electrical polarization, namely:

[0011] The destruction of the logical content of the memory cell following a read, and more particularly for a high logic stage “x=1”.

[0012] The reduction in reading sensitivity with the enlargement of memory cell matrices and / or the densification of memory matrices by reducing the size of the elementary storage components. Prior Art / State of the Art Restrictions

[0013] The scientific publication entitled "1T1C FeRAM memory array based on ferroelectric HZO with capacitor under bitline" by J. Okuno et al presents a circuit for reading a plurality of FeRAM type memories. The solution presented is based on a capacitive divider bridge connected to the bit line of the memory cell to be read. The voltage variation at the output of the capacitive divider bridge with respect to a reference signal is amplified by a detection amplifier. The amplitude of said variation depends directly on the value of the parasitic capacitance at the bit line, which causes the loss of reading accuracy for the reasons detailed previously. In addition, in Okuno's solution, the amplitude of said variation depends directly on the value of the capacitance of the elementary component, which reduces the reading sensitivity for densified matrices. Another is the reading operation of a memory cell that stores a high logic state.

[0014] The publication of the American patent application US 2021 / 020222 A1 describes another storage circuit based on FeRAM type memories. Response to the problem and provision of a solution

[0015] To address the technical problems discussed above, related to the reading of ferroelectric non-volatile memories, the invention proposes a reading circuit comprising a CTIA capacitive trans-impedance amplifier stage (acronym for Capacitive Trans-Impedance Amplifier). The reading circuit according to the invention thus comprises a capacitive feedback impedance allowing direct reading of the quantity of charges contained in the elementary ferroelectric storage component and not reading of a voltage variation on the bit line. This solution thus makes it possible to carry out a reading operation whose precision is independent of the parasitic capacitances of the bit lines. This thus makes it possible to construct larger matrices without being penalized by a reduction in the memory window.

[0016] Additionally, charge-domain reading allows for limiting variations in electrical potential at the bit lines. This offers the advantage of significantly reducing the dynamic power consumption of the storage circuit.

[0017] In addition, the reading circuit according to the invention makes it possible to rewrite the read data (x=1) in the memory cell after each reading operation so as to perform a non-destructive reading operation. The rereading operation is fully integrated by the reading circuit according to the invention. There is no need to recopy the data into buffer memories before reading, nor to transfer said data to external circuits. This makes it possible to reduce the implementation complexity of the storage circuit. This also makes it possible to reduce the energy consumption of the storage circuit by limiting the data exchanges at the input and / or output of the storage circuit. Summary / Claims

[0018] The subject of the invention is a data storage circuit comprising: a memory cell array such that each memory cell comprises: an elementary storage component of the ferroelectric type with variable electrical polarization and having a first electrode and a second electrode; a first input / output node connected to the second electrode; a second input / output node; a selection node; a selection transistor having a gate connected to the selection node and connecting the first electrode to the second input / output node; in which, each memory cell can have a first or a second logic state corresponding respectively to different levels of charges stored in the associated elementary storage component;a reading circuit associated with at least one memory cell, comprising a capacitive transimpedance amplifier stage configured to read data stored in a selected memory cell via the conduction of the corresponding selection transistor by applying a selection signal to the selection node; said capacitive transimpedance amplifier stage comprising: ∘ an operational amplifier having: a first input connected to the second input / output node of the associated memory cell, a second input for receiving a first reference signal; and an output for providing an analog reading signal;∘ a capacitive feedback impedance mounted between the output and the first input of the operational amplifier. a sequencer circuit configured to, following the reading of data corresponding to the second logic state, apply a control signal to the first input / output node having an amplitude lower than the first reference signal and maintain the selection transistor in an on state so as to restore, in the elementary storage component of the selected memory cell, a charge level corresponding to the second logic state. ;

[0019] According to a particular aspect of the invention, said sequencer circuit is configured to, during reading, apply a control signal to the first input / output node having an amplitude substantially equal to the first reference signal so as to generate a transfer of charges from the elementary storage component of the selected cell to said capacitive transimpedance amplifier stage.

[0020] According to a particular aspect of the invention, said first logic state corresponds to an uncharged state of an elementary storage component. The sequencer circuit is such that, following the reading of data corresponding to a first logic state, said sequencer circuit is configured to make said transistor for selecting the selected memory cell non-conductive before modifying the control signal on the first input / output node to a new value, to maintain the memory cell just read in an uncharged state.

[0021] According to a particular aspect of the invention, the reading circuit further comprises a comparator having a first input connected to the output of the operational amplifier, a second input for receiving a second reference signal; and an output for providing a digital readout signal.

[0022] According to a particular aspect of the invention, the control signal is a first pulse; the selection signal is a second pulse; the sequencer circuit is configured to reduce the duration of the first pulse relative to that of the second pulse following the reading of data corresponding to a high logic state.

[0023] According to a particular aspect of the invention, the reading circuit further comprises a reset switch mounted between the output and the first input of the operational amplifier.

[0024] According to a particular aspect of the invention, the reading circuit further comprises a first feedback activation switch between the capacitive feedback impedance and the first input of the operational amplifier.

[0025] According to a particular aspect of the invention, the data storage circuit further comprises a read activation switch between the first input of the operational amplifier and the second input / output node of the associated memory cell.

[0026] According to a particular aspect of the invention, the reading circuit is configured to further perform, before reading said associated memory cell: a reset step to discharge the capacitive feedback impedance and bias the first input of the operational amplifier to the first reference signal.

[0027] According to a particular aspect of the invention, the amplitude of the first reference signal is comprised in the interval [VDD / 2 - 50%; VDD / 2 + 50%] with VDD a supply voltage of the data storage circuit.

[0028] According to a particular aspect of the invention, the storage circuit comprises at least one elementary storage component configurable according to an operating configuration corresponding to a resistive memory with variable conductive filament; The reading circuit further comprising: a resistive feedback impedance connected between the output and the first input of the operational amplifier; a second feedback activation switch between the resistive feedback impedance and the first input of the operational amplifier.

[0029] According to a particular aspect of the invention, the memory cell matrix is composed of N rows and M columns such that: memory cells belonging to the same column have interconnected first input / output nodes, and interconnected second input / output nodes; memory cells belonging to the same row have interconnected selection nodes.

[0030] According to a particular aspect of the invention, the elementary storage component is of the FeRAM type or of the ferroelectric tunnel junction FTJ type. Brief Description of the Drawings

[0031] Other features and advantages of the present invention will become more apparent upon reading the following description in relation to the following appended drawings. [ Fig. 1a ] illustrates a sectional view of an example of an elementary component of a ferroelectric memory cell with variable electrical polarization compatible with the invention. This figure is already described. [ Fig. 1b] illustrates an electrical modeling of a ferroelectric memory cell with variable electrical polarization compatible with the invention. [ Fig. 2 ] illustrates an electrical diagram of a first embodiment of the reading circuit according to the invention connected to a ferroelectric memory cell with variable electrical polarization. [ Fig. 3a ] illustrates an electrical diagram of the configuration of the reading circuit according to the invention during an initialization step. [ Fig. 3b ] illustrates an electrical diagram of the configuration of the reading circuit according to the invention during a reading step. [ Fig. 3c ] illustrates a flowchart of the memory cell control signals during a reading step by the reading circuit according to the invention. Fig. 4 ] illustrates a flowchart of the memory cell control signals following the reading of a low logic state (x=0) by the reading circuit according to the invention. [ Fig. 5a] illustrates a flowchart of the memory cell control signals following the reading of a high logic state (x=1) by the reading circuit according to the invention. [ Fig. 5b ] illustrates an electrical diagram of a first configuration of the reading circuit according to the invention during a rewriting step. [ Fig. 5c ] illustrates an electrical diagram of a first configuration of the reading circuit according to the invention during a rewriting step. [ Fig. 5d ] illustrates an electrical diagram of a first configuration of the reading circuit according to the invention during a rewriting step. [ Fig. 6a ] illustrates a functional diagram of the architecture of a first embodiment of the data storage circuit according to the invention. [ Fig. 6b ] illustrates a functional diagram of the architecture of a second embodiment of the data storage circuit according to the invention. [ Fig. 7a] illustrates a sectional view of an example of an elementary component of a resistive memory cell with variable conductive filament compatible with the invention. Fig. 7b ] illustrates an electrical diagram of a second embodiment of the reading circuit according to the invention connected to a resistive memory cell with variable conductive filament. [ Fig. 7c ] illustrates a flowchart of the control signals of the resistive memory cell when reading a memory cell by the reading circuit according to the invention.

[0032] There Figure 1a , already described, illustrates an elementary NVM component of the FeRAM type compatible with the invention. We emphasize that it is also possible to implement the invention with elementary components of the ferroelectric tunnel junction FTJ type (acronym for the English term Ferroelectric Tunnel Junction) and any other type of ferroelectric non-volatile memory technology with variable electrical polarization.

[0033] There Figure 1b illustrates an electrical modeling of a ferroelectric memory cell CM ij with variable electrical polarization compatible with the invention. The memory cell comprises CM ij an elementary memory component NVM, a selection transistor T1, a first input / output node SL, a second input / output node BL and a selection node WL. The memory cell CM ij is intended to be integrated in a matrix comprising a plurality of bit lines (bit line in English), a plurality of word lines (word line in English) and a plurality of source lines (source line in English). The first input / output node SL is intended to be connected to a source line associated with the memory cell CM ij . The second input / output node BL is intended to be connected to a bit line associated with the memory cell CM ij . The selection node WL is intended to be connected to a word line associated with the memory cell CM ij

[0034] Within a memory cell CM ij , the first input / output node (SL) is connected to the second electrode EL2 of the elementary memory component NVM. The selection transistor T1 has a gate connected to the selection node WL. The selection transistor T1 connects the first electrode EL1 of the elementary memory component NVM to the second input / output node BL. The elementary component NVM behaves like a capacitive element having a variable capacitance depending on the direction of the electrical polarization of the central ferroelectric layer C2. The memory cell CM ij is thus modeled by a compact 1C1T architecture. This allows a direct action on the electrodes EL1 and EL2 of the capacitive element when the transistor T1 is in the on state.

[0035] There Figure 2illustrates an electrical diagram of a first embodiment of the reading circuit 3 according to the invention connected to a ferroelectric memory cell CM ij with variable electrical polarization.

[0036] The reading circuit 3 is connected to the second input / output node BL of the memory cell to be read CM ij through a read activation switch i3. The read activation switch i3 makes it possible to isolate the node BL from the reading circuit 3 if necessary. As a non-limiting illustrative example, the memory cell CM ij has the same architecture described previously. The parasitic capacitance C BL seen by the second input / output node BL is represented here in order to facilitate understanding of the invention.

[0037] The read circuit 3 comprises a capacitive trans-impedance amplifier stage 31 (translation of the term into English Capacitive Trans-Impedance Amplifier); a comparator 32, a sequencer circuit 33 and a reset switch i1.

[0038] The capacitive transimpedance amplifier stage 31 comprises an operational amplifier AO associated with a capacitive feedback impedance (CCR). The operational amplifier AO has a first input e1_ao connected to the second input / output node BL of the associated memory cell; a second input e2_ao for receiving a first reference signal VREF1; and an output s1_ao for providing an analog read signal Vs1_ao. The capacitive feedback impedance CCR is mounted between the output s1_ao and the first input e1_ao of the operational amplifier. This type of assembly makes it possible to perform a direct reading of the quantity of charges contained in the elementary component NVM and not a reading of a voltage variation on the node BL. This assembly thus makes it possible to perform a read operation whose precision is independent of the parasitic capacitance C BL .

[0039] The operational amplifier AO has a dual function: maintain the BL node at a fixed potential equal to the potential of the first reference signal VREF1 when the read enable switch i3 is on. generate an analog read signal Vs1_ao having an amplitude dependent on the amount of charge transmitted from the elementary component NVM to the capacitive feedback impedance CCR during a read operation.

[0040] The function of the CCR capacitive feedback impedance is to convert the quantity of charges supplied by the NVM elementary component (similar to a capacitive element) into an electrical voltage applied between the s1_ao output and the e1_ao input during a read operation.

[0041] Optionally, the read circuit comprises a first feedback activation switch i2 between the capacitive feedback impedance CCR and the first input e1_ao of the operational amplifier.

[0042] The comparator 32 has a first input e1_cmp connected to the output s1_ao of the operational amplifier; a second input e2_cmp for receiving a second reference signal VREF2; and an output s1_cmp for providing a digital read signal Vs1_cmp resulting from the comparison of the analog read signal Vs1_ao with the second reference signal VREF2.

[0043] The comparator 32 and the operational amplifier AO are each biased by a supply voltage VDD and the electrical ground GND.

[0044] The sequencer circuit 33 is configured to control the application: of a write and read control signal VSL on the first input / output node SL of the associated memory cell; and of a selection signal VWL on the selection node WL of the associated memory cell,

[0045] This is a circuit configured according to a state machine in order to adapt the characteristics of the VSL and WL signals according to the digital read signal Vs1_cmp. The action of the sequencer 33 on the VSL and WL signals will be detailed in a later section. As a non-limiting example, it is possible to implement the sequencer circuit 33 using a microcontroller integrated in the memory circuit. Advantageously, the sequencer 33 makes it possible to set up a feedback loop allowing a rewrite operation to be carried out by the read circuit itself. This makes it possible to overcome the problems of destructive reading without complicating the circuit. In addition, the action of the sequencer makes it possible to carry out the rewrite without transferring the data to external buffer memories.

[0046] The reset switch i1 is connected between the output s1_ao and the first input e1_ao of the operational amplifier. When the reset switch i1 is in the on state, the capacitive feedback impedance CCR is discharged. This discharge also induces the reset of the analog read signal Vs1_ao to a potential equal to that of the first reference signal VREF1.

[0047] Advantageously, closing the reset switch i1 allows the cumulative charges on the second input / output node BL to be dissipated due to leakage currents. Indeed, for advanced technological nodes, there is an increase in leakage currents coming from the selection transistors connected to the second input / output node BL. These leakage currents cause an accumulation of charges at the level of the parasitic capacitance C BL . This induces potential fluctuations at the level of the second input / output node BL. Hence the specific interest of the reset switch i1 in this case.

[0048] All switches i1, i2 and i3 are controlled by control means not shown to simplify the illustration. Switches i1, i2 and i3 are implemented by CMOS transistors as an example. Read circuit 3 is configured to perform the following steps:

[0049] The first step (i) is a reset step obtained by the configuration illustrated by the Figure 3a. The reset switch i1, the feedback enable switch i2 and the read enable switch i3 are closed. The sequencer 33 generates a selection signal VWL so as to put the selection transistor T1 in a blocking state. The sequencer 33 generates a write and read control signal VSL on the first input / output node SL equal to the electrical ground. This step (i) makes it possible to discharge the capacitive feedback impedance CCR and to bias the first input e1_ao of the operational amplifier to the first reference signal VREF1. Thus following the reset, the input / output node BL and the output s1_ao are biased to the first reference signal VREF1 (VBL = Vs1_ao = VREF1); the voltage across the capacitive feedback impedance CCR is zero; and the output of comparator s1_cmp is at a low logic state (Vs1_cmp=0).

[0050] The second step (ii) is a reading step obtained by the configuration illustrated by the Figure 3c . There Figure 3c illustrates a flowchart of the VSL and VWL signals provided by the sequencer 33 during a reading step ii). The reset switch i1 is open and the switches i2 and i3 are closed (on state).

[0051] The sequencer 33 is configured during this step to apply a selection signal VWL to turn on the selection transistor T1 (a rising edge in the case of an NMOS is illustrated here). This results in the creation of a connection path between the elementary component NVM and the capacitive feedback element CCR.

[0052] In addition, the sequencer 33 is configured to apply a positive VSL read control signal to the first input / output node SL. This results in the application of a quasi-zero potential difference across the terminals of the elementary component NVM.

[0053] Thus, the combination of the almost zero voltage across the NVM elementary component and its connection with the CCR feedback capacitive element induces a transfer of the charges previously stored in the NVM elementary component to the CCR feedback capacitive element. The amount of charge transferred depends on the logic state previously stored in the CM ij memory. This induces a variation of the VCCR electrical voltage across the CCR feedback capacitive element. The value of the electrical voltage across the CCR feedback capacitive element depends on the amount of charges supplied by the NVM elementary component to the CCR feedback capacitive element. This induces a variation of the analog output signal Vs1_ao which passes to VREF1-VCCR.

[0054] In the case where x=1 is stored in the NVM elementary component, we obtain Vs1_ao= VREF1-VCCR < VREF2 with VCCR of the order of a few hundred millivolts. We thus obtain Vs1_cmp=VDD corresponding to a high logic level. Conversely, in the case where x=0 is stored in the NVM elementary component, we obtain Vs1_ao= VREF1-VCCR > VREF2 and therefore Vs1_cmp=GND corresponding to a low logic level.

[0055] We emphasize that the charges are transferred completely to the capacitive feedback element CCR during this step. The parasitic capacitance C BL does not receive these charges because it is maintained at a voltage equal to VREF1 thanks to the operational amplifier AO during the entire operation. The reading circuit 3 according to the invention thus makes it possible to carry out a reading operation in the charge domain independent of the value of the parasitic capacitance C BL .

[0056] The third step (iii) consists of rewriting the logical data previously read by the reading circuit 3. We recall that the rewriting operation is only required in the case where the data read corresponds to a high logical state. Figure 4 illustrates a flowchart of the control signals of the memory cell CM ij following the reading of a low logic state (x=0) by the reading circuit 3. In this case, the sequencer 33 receives the digital reading signal Vs1_cmp=0. In response to this result, the sequencer 33 is configured to emit a falling edge simultaneously on the nodes SL and WL. This makes it possible to isolate the elementary component NVM from the node BL and to maintain the logic state of said elementary component at x=0 obtained following the reading operation. (by pumping the charges during reading).

[0057] Alternatively, the Figure 5aillustrates a flowchart of the control signals of the memory cell CM ij following the reading of a high logic state (x=1) by the reading circuit 3. In this case, the sequencer 33 receives the digital reading signal Vs1_cmp=VDD. In response to this result, the sequencer 33 is configured to apply a falling edge to the input / output node SL while maintaining the selection node WL in a high state. This results in the following combination: On the one hand, the first input / output node SL is at a low potential (preferably zero) under the action of the sequencer 33; On the other hand, the second input / output node BL is at a high electrical potential equal to VREF1 under the action of the operational amplifier AO; the transistor T1 being in the on state;

[0058] This corresponds to the application of a SET write voltage on the NVM elementary component as explained in the Figure 1a. Thus, a rewriting operation of the logical value x=1 was carried out via the action of the sequencer 33 allowing a rewriting operation to be carried out by the reading circuit itself. This makes it possible to overcome the problems of destructive reading without complicating the circuit.

[0059] In the following, we will describe, by way of non-limiting illustration, several possible configurations of the reading circuit during a rewriting step following the reading of a logical data item x=1.

[0060] There Figure 5billustrates an electrical diagram of a first configuration of the reading circuit 3 according to the invention during a rewriting step. For this configuration, the feedback activation switch i2 is kept closed during the writing step so as to repatriate the charges accumulated in the feedback capacitor CCR to the elementary component NVM. The charges have not been evacuated downstream of the capacitive transimpedance amplifier 31. The charges transmitted during reading are repatriated into the memory cell for rewriting of the information with lower energy consumption than in the state-of-the-art solution.

[0061] There Figure 5cillustrates an electrical diagram of a second configuration of the reading circuit according to the invention during a rewriting step. In this second configuration, the feedback activation switch i2 is open. This makes it possible to rewrite the memory cell using the potential difference applied between the nodes SL and BL while keeping a copy of the information read in the capacitive feedback impedance CCR.

[0062] There Figure 5dillustrates an electrical diagram of a third configuration of the read circuit according to the invention during a rewriting step. In this second configuration, the feedback activation switch i2 is open and the reset switch i1 is closed. This makes it possible to rewrite the memory cell using the potential difference applied between the nodes SL and BL. This configuration has a particular advantage in the case where the bit line connected to the node BL is capacitive so as to have a potential not equal to the voltage of VREF1. The closure of the reset switch i1 makes it possible to correctly repolarize the node BL to the first reference voltage VREF1 via the capacitive transimpedance amplifier 31. This makes it possible to rewrite a high logic state (x=1) in a more efficient manner.

[0063] There Figure 6aillustrates a first embodiment of the storage circuit 1 according to the invention. The storage circuit 1 according to the invention comprises a matrix of memory cells 2 and a plurality of reading circuits 3. The matrix of memory cells comprises N rows and M columns. The memory cells CM ij belonging to the same column C j have first input / output nodes SL interconnected via a common source line (SL n for the column C n ). In addition, the memory cells CM ij belonging to the same column C j have second input / output nodes BL interconnected via a common bit line (BL n for the column C n ). In addition, the memory cells CM ij belonging to the same row L i have selection nodes WL interconnected via a common word line (WL n for the column L n ). This is then a matrix structure with the bit lines BL j and the source lines SL j parallel in a first direction.The word lines WL i are orthogonal to said first direction. The storage circuit 1 comprises at the foot of each column C j a read circuit 3 according to the invention connected to the bit line BL j of said column. Each read circuit 3 acts via its feedback loop on the memory cells CM ij belonging to the same column C j to perform a non-destructive reading. This configuration makes it possible to perform a writing and a reading of a target memory cell CM ij without disturbing the adjacent memory cells in row or column. To do this, it is sufficient to polarize the bit lines BL j of the adjacent memory cells to the electrical ground GND. In addition, this configuration makes it possible to perform parallel writing / reading of all the memory cells belonging to the same row L i . This parallelization is possible thanks to the independence between the bit lines BL j and the source lines SL j of this set of memory cells.

[0064] The storage circuit 1 further comprises writing means not shown for the sake of simplification. The writing means are distinct from the reading circuit according to the invention. The writing means are configured to carry out data writing operations and do not intervene in the rewriting operations in response to a destructive reading previously illustrated in the context of the invention.

[0065] There Figure 6billustrates a second embodiment of the storage circuit 1 according to the invention. The second embodiment differs from the first by the different orientation of the source lines SL n , SL n-1 , SL n+1 . Indeed, in this embodiment the source lines are common to the memory cells CM ij belonging to the same row L i . Thus, the source lines SL i extend in a direction orthogonal to that of the bit lines BL j and parallel to that of the word lines WL i . This configuration is compatible with the invention provided that inhibition signals are applied to the bit lines BL j of the other columns C j different from that of the memory cell selected for a read operation. This makes it possible to avoid disturbances of the state of the memory cells CM ij belonging to the same row of the target memory cell during its reading.

[0066] In the following section we will describe an embodiment of the invention when the data storage circuit 1 comprises memory cells of the variable conductive filament resistive memory type (OxRAM for example). The variable conductive filament resistive memory cells can be co-integrated with the ferroelectric memory cells in the same matrix 2. Alternatively, the variable conductive filament resistive memory cells can be integrated in a second matrix distinct from the matrix 2. Alternatively, it is possible to reconfigure the ferroelectric memory cells according to a variable conductive filament resistive type operation as described in the Figure 7a .

[0067] There Figure 7aillustrates an elementary NVM component of a variable conductive filament resistive memory cell compatible with the invention. The variable conductive filament resistive operation requires the formation of a conductive filament F through at least a portion of the central electrically insulating layer C2.

[0068] Initially, the NVM elementary component is a MIM (metal, insulator, metal) type structure having an infinite resistance between the two electrodes EL1 and EL2. In order to reconfigure the NVM elementary component according to a resistive memory operation, it is necessary to form the filament F starting from the upper electrode EL2 through at least a part of the volume of the central layer C2. The formation of the filament makes it possible to obtain a variable resistance by modulating the length I of the formed conductive filament. To form the filament, a forming electrical voltage is applied to the upper electrode EL2. The forming electrical voltage has a sufficiently high amplitude and / or duration to cause the generation of oxygen vacancies in the central layer C2.Indeed, the applied formation electrical voltage must exceed a predetermined value so as to tear oxygen ions from the crystal lattice of the central metal oxide layer which will migrate towards the upper electrode EL2 thus forming a conductive filament F through the central layer made up of oxygen vacancies.

[0069] Once the conductive filament F is formed, we obtain the behavior of a resistive element with a variable resistance R depending on the length I of the conductive filament F. When a positive electrical voltage is applied to the lower electrode EL1, the reverse reaction occurs and oxygen ions will fill part of the oxygen vacancies forming the conductive filament. This results in a reduction in the length of the conductive filament. Thus, the resistance of the resistive element increases. This is called a high resistive state and a RESET type write operation. Conversely, when a positive electrical voltage is applied to the upper electrode EL2, the length of the conductive filament F increases by the same mechanism described for the wire formation operation. Thus, the resistance of the resistive element decreases. This is called a low resistive state and a SET type write operation.

[0070] The following convention is chosen as an example: when an NVM memory component is configured to store binary data in the high logic state (x = 1), a write electrical voltage is temporarily applied to the upper electrode EL2 (SET operation) so as to obtain a low resistive state. Conversely, when an NVM memory component is configured to store binary data in the low logic state (x = 0), a write electrical voltage is temporarily applied to the lower electrode EL1 (RESET operation) so as to obtain a high resistive state.

[0071] Reading a resistive NVM memory component involves estimating the resistance between the top electrode and the bottom electrode and comparing it to a threshold value to determine whether the resistive state is a high or low state.

[0072] There Figure 7billustrates an electrical diagram of a second embodiment of the reading circuit 3 according to the invention connected to a resistive memory cell with variable conductive filament. The Figure 7c illustrates a flowchart of the control signals of the resistive memory cell when reading a memory cell by the reading circuit according to the invention.

[0073] In this embodiment, the elementary component NVM behaves like a resistor. The reading circuit 3 further comprises a resistive feedback impedance RCR mounted between the output s1_ao and the first input e1_ao of the operational amplifier AO.

[0074] Advantageously, the reading circuit 3 comprises a second feedback activation switch i4 between the resistive feedback impedance RCR and the first input e1_ao of the operational amplifier A0.

[0075] To read the logic content of the resistive memory cell CM ij, the second feedback activation switch i4 is in the on state and the first feedback activation switch i2 is in the off state. The sequencer 33 is configured to apply a positive read control signal VSL to the first input / output node SL with the transistor T1 in the on state. The amplitude of the positive read control signal VSL is greater than that of the first reference signal VREF1 (potential of the second node BL). The resistive elementary component NVM is then subjected to a non-zero potential difference. This results in the circulation of an electric current I1 through the resistor NVM and the resistive feedback impedance RCR. The intensity of the current I1 depends on the resistive state of the filament of the elementary component NVM. This induces a variation in the voltage VRCR across the resistive feedback impedance RCR which depends on the intensity of the current I1.This results in a variation of the electrical potential at the output node s1_ao of the operational amplifier AO. This voltage variation is an image of the resistive state of the elementary component NVM according to the logical content stored in said component. Reading an elementary component NVM is not destructive to the logical content of the memory cell. There is no need for a rewrite step in this case.

Claims

1. A data storage circuit (1) comprising: - a matrix (2) of memory cells such that each memory cell (CMij) comprises: • an elementary storage component (NVM) of ferroelectric type with variable electric bias and having a first electrode (EL1) and a second electrode (EL2); • a first input / output node (SL) connected to the second electrode (EL2); a second input / output node (BL); a selection node (WL); • a selection transistor (T1) having a gate connected to the selection node (WL) and linking the first electrode (EL1) to the second input / output node (BL); wherein each memory cell can have a first ("0") or a second ("1") logic state corresponding respectively to different levels of charges stored in the associated elementary storage component (NVM); - a read circuit (3) associated with at least one memory cell, comprising: • a capacitive transimpedance amplifier stage (31) configured to read a piece of data stored in a memory cell (CMij) selected via the switching-on of the corresponding selection transistor (T1) by applying a selection signal (VWL) to the selection node (WL); said capacitive transimpedance amplifier stage (31) comprising: ∘ an operational amplifier (AO) having: a first input (e1_ao) connected to the second input / output node (BL) of the associated memory cell, a second input (e2_ao) for receiving a first reference signal (VREF1); and an output (s1_ao) for providing an analogue read signal (Vs1_ao); ∘ a feedback capacitive impedance (CCR) mounted between the output (s1_ao) and the first input (e1_ao) of the operational amplifier; - a sequencer circuit (33) configured to, following the reading of a piece of data corresponding to the second logic state ("1"), apply a control signal (VSL) to the first input / output node (SL) having an amplitude lower than the first reference signal (VREF1) and maintain the selection transistor (T1) in an on state so as to restore, in the elementary storage component (NVM) of the selected memory cell, a level of charges corresponding to a second logic state ("1").

2. The data storage circuit (1) according to claim 1, wherein said sequencer circuit (33) is configured to, during the reading, apply a control signal (VSL) to the first input / output node (SL) having an amplitude substantially equal to the first reference signal (VREF1) so as to create a transfer of charges from the elementary storage component (NVM) of the selected cell to said capacitive transimpedance amplifier stage (31).

3. The data storage circuit (1) according to claim 2, wherein said first logic state ("0") corresponds to a non-charged state of an elementary storage component (NVM), and wherein said sequencer circuit (33) is such that, following the reading of a piece of data corresponding to a first logic state ("0"), said sequencer circuit (33) is configured to switch off said selection transistor (T1) of the selected memory cell (CMij) before modifying the control signal (VSL) on the first input / output node (SL) to a new value, to maintain the memory cell that has just been read in a non-charged state.

4. The data storage circuit (1) according to any one of claims 1 to 3, wherein the read circuit (3) further comprises a comparator (32) having a first input (e1_cmp) connected to the output (s1_ao) of the operational amplifier, a second input (e2_cmp) for receiving a second reference signal (VREF2); and an output (s1_cmp) for providing a digital read signal (Vs1_cmp).

5. The data storage circuit (1) according to any one of claims 1 to 4, wherein: • the control signal (VSL) is a first pulse; • the selection signal (VWL) is a second pulse; the sequencer circuit (33) being configured to reduce the duration of the first pulse with respect to that of the second pulse following the reading of a piece of data corresponding to a high logic state.

6. The data storage circuit (1) according to any one of claims 1 to 5, wherein the read circuit (3) further comprises a reset switch (i1) mounted between the output (s1_ao) and the first input (e1_ao) of the operational amplifier.

7. The data storage circuit (1) according to any one of claims 1 to 6, wherein the read circuit (3) further comprises a first feedback activation switch (i2) between the feedback capacitive impedance (CCR) and the first input (e1_ao) of the operational amplifier.

8. The data storage circuit (1) according to any one of claims 1 to 7, comprising a read activation switch (i3) between the first input (e1_ao) of the operational amplifier and the second input / output node (BL) of the associated memory cell.

9. The data storage circuit (1) according to any one of claims 3 to 8, wherein the read circuit (3) is configured to further perform, before the reading of said associated memory cell: a reset step for discharging the feedback capacitive impedance (CCR) and biasing the first input (e1_ao) of the operational amplifier to the first reference signal (VREF1).

10. The data storage circuit (1) according to any one of claims 1 to 9, wherein the amplitude of the first reference signal (VREF1) lies within the interval [VDD / 2 - 50%; VDD / 2 + 50%] with VDD a power supply voltage of the data storage circuit (1).

11. The data storage circuit (1) according to any one of claims 1 to 10, comprising at least one elementary storage component (NVM) that can be configured according to an operating configuration corresponding to a resistive memory with variable conductive filament; the read circuit (3) further comprising: • a feedback resistive impedance (RCR) mounted between the output (s1_ao) and the first input (e1_ao) of the operational amplifier (AO); • a second feedback activation switch (i4) between the feedback resistive impedance (RCR) and the first input (e1_ao) of the operational amplifier (AO).

12. The data storage circuit (1) according to any one of claims 1 to 11, wherein the matrix (2) of memory cells is composed of N rows and M columns such that: - the memory cells (CMij) belonging to one and the same column have interconnected first input / output nodes (SL), and second interconnected input / output nodes (BL); - the memory cells (CMij) belonging to one and the same row have interconnected selection nodes (WL).

13. The data storage circuit (1) according to any one of the preceding claims, wherein the elementary storage component (NVM) is of FeRAM type or of ferroelectric tunnel junction FTJ type.