METHOD FOR PRODUCING A PHOTONIC CHIP

Description

[0001] The invention relates to a method for manufacturing a photonic chip and to a photonic chip manufactured by this method.

[0002] Photonic chips often contain optical components that are optically or capacitively coupled to each other through a thin layer of dielectric material, also referred to herein as the "dielectric thin layer." The thickness of this dielectric thin layer is less than the thickness of the buried silicon oxide layer of standard SOI (Silicone Insulator) substrates. Therefore, to fabricate such a photonic chip from a standard SOI substrate, it has been proposed to obtain the dielectric thin layer by thinning the buried layer of a standard SOI substrate. Such a fabrication method is disclosed, for example, in patent application US20170237229. This method is advantageous because it uses standard SOI substrates and is therefore easily implemented.

[0003] However, when the thin dielectric layer is obtained by thinning the buried layer of a standard SOI substrate, the accuracy of the thin dielectric layer thickness is low. An error in the thickness of this thin dielectric layer alters the coupling between the two parts of the optical components and therefore the performance of the fabricated photonic chip.

[0004] The following are also known from the state of the art: US2018323575, US2017237229, US20118323575A1, US8358897B1, EP3264541A1 and US2007200144A1.

[0005] It is therefore desirable to propose a manufacturing process for such a photonic chip which allows the use of a standard SOI substrate, while improving the accuracy of the thickness of the thin dielectric layer.

[0006] The invention therefore relates to such a manufacturing process in accordance with claim 1.

[0007] The invention also relates to a photonic chip manufactured by the above manufacturing process.

[0008] The invention will be better understood upon reading the following description, given solely by way of non-limiting example and made with reference to the drawings in which: there figure 1 is a schematic and partial illustration, in vertical cross-section, of a photonic chip comprising parts of optical components coupled together through a thin dielectric layer; the figure 2 is a flowchart of a manufacturing process for the photonic chip of the figure 1 ; THE figures 3 to 11 These are partial schematic illustrations and vertical cross-sections of different manufacturing states encountered during the implementation of the process. figure 2 ; there figure 12 is a flowchart of a first variant of the manufacturing process of the figure 2 ; there figure 13is a schematic and partial illustration, in vertical section, of a manufacturing state obtained by implementing the process of the figure 12 ; there figure 14 is a flowchart of a second variant of the manufacturing process of the figure 2 ; THE figures 15 to 17 are schematic and partial illustrations, in vertical section, of different manufacturing states obtained by implementing the process of the figure 14 .

[0009] In these figures, the same references are used to designate the same elements.

[0010] In the remainder of this description, the well-known characteristics and functions of a person skilled in the art are not described in detail.

[0011] There figure 1represents a photonic chip 2 comprising photonic components that guide and / or modulate the phase or amplitude of an optical signal. Typically, the wavelength of the guided and / or modulated optical signal is between 1250 nm and 1590 nm.

[0012] In practice, such a photonic chip 2 comprises several optical components. For example, each of these optical components is chosen from the group consisting of the following optical components: a waveguide, a laser source, a phase and / or amplitude modulator, an optical filter, a mirror, an interface for connecting the photonic chip to an optical fiber.

[0013] More specifically, the photonic chip 2 includes: at least two parts of optical components optically coupled to each other via optical coupling, or at least two parts of optical components capacitively coupled to each other via capacitive coupling.

[0014] On the figure 1 , the parts of optical components coupled together by optical or capacitive coupling bear the numerical references, respectively, 4 and 6.

[0015] By way of illustration, optically coupled portions of optical components are typically sections of waveguides sufficiently close to each other that at least 50%, and preferably more than 80%, of the optical signal power propagating in one of the two waveguides is transmitted to the other. For example, such optical coupling is adiabatic coupling, as described in detail in the following article: B. Ben Bakir et al., “Hybrid Si / III-V lasers with adiabatic coupling”, 2011.

[0016] Capacitively coupled parts of optical components include, for example, the two electrodes of a phase and / or amplitude modulator. Such a modulator is disclosed, for example, in US patent application US20170237229.

[0017] To achieve such optical or capacitive coupling, the two optical components 4 and 6 are separated from each other by a thin dielectric layer 8. A thin dielectric layer is a layer of dielectric material less than 250 nm thick, and typically less than 150 nm. In the case of optical coupling, the thickness of the thin dielectric layer is often between 100 nm and 250 nm or between 100 nm and 200 nm. In the case of capacitive coupling, the thickness of the thin dielectric layer is generally between 5 nm and 50 nm, and most often between 5 nm and 30 nm or between 5 nm and 20 nm. To remain compatible with the use of a standard SOI substrate for fabricating the photonic chip 2, the thin dielectric layer is a thin layer of silicon oxide.

[0018] To simplify the figure 1and the following, only a portion of the photonic chip 2 comprising the two parts 4 and 6 of optical components coupled together through the thin dielectric layer 8 is shown.

[0019] Here, the description is given for the specific case where parts 4 and 6 are, respectively, the lower and upper electrodes of a phase and / or amplitude modulator 10 of the optical signal. In this particular case, parts 4 and 6 of the optical components are capacitively coupled to each other. For example, the architecture of the modulator 10 is identical or similar to the architecture of the modulator described in US patent application US20170237229. Thus, the precise architecture of the modulator 10 is not described in detail hereafter. However, everything described thereafter for this specific case also applies to the case where parts 4 and 6 are coupled to each other via optical coupling.

[0020] The figures are oriented with respect to an orthogonal XYZ coordinate system. The X and Y directions are horizontal. The X direction is perpendicular to the cutting plane. The Z direction is vertical. In this text, terms such as "above," "below," "superior," and "inferior" are defined with respect to the Z direction.

[0021] Photonic chip 2 comprises, successively from bottom to top: a substrate 18 consisting, from bottom to top, of a support 20 and a layer 22 of dielectric material, a layer 24 of encapsulated semiconductor material, directly located on an upper face of the layer 22 of dielectric material, the thin layer 8 of silicon oxide, and a layer 26 inside which part 6 is encapsulated.

[0022] The thickness of support 20 is typically greater than 200 µm or 400 µm. For example, support 20 is made of silicon or polycrystalline silicon.

[0023] Layer 22 is made of a dielectric material having optical and electrical properties close to or identical to those of silicon oxide. In this embodiment, layer 22 is a silicon oxide layer. The thickness of layer 22 is typically greater than 500 nm or 1 µm or more. In this text, a dielectric material is defined as a material whose electrical conductivity at 20°C is less than 10⁻⁷ S / m and, preferably, less than 10⁻⁹ S / m or 10⁻¹⁵ S / m. Furthermore, its refractive index is lower than the refractive index of the semiconductor material encapsulated in layer 24.

[0024] Layer 24 contains a semiconductor material 30 in which part 4 is encapsulated within a dielectric encapsulating material 32. As with layer 22, the dielectric encapsulating material 32 is a dielectric material whose optical and electrical properties are close to or identical to those of silicon oxide. In this example, the material 32 is silicon oxide.

[0025] In this embodiment, the semiconductor material 30 is monocrystalline silicon. Thus, part 4 is made of monocrystalline silicon. For example, the thickness of the monocrystalline silicon in layer 24 is between 100 nm and 800 nm and, typically, between 300 nm and 500 nm. Also in this embodiment, layer 24 includes remnants 34 of a layer 36 ( figure 5A masking layer 36 is used to structure the single-crystal silicon to create the encapsulated optical component parts within layer 24. These remnants 34 are located within layer 24 and each extends along the interface between layers 22 and 24. Here, such a remnant 34 separates the lower end of part 4 from layer 22. In this embodiment, the masking layer 36 and the remnants 34 are made of a dielectric material other than silicon dioxide. Here, layer 36 is made of silicon nitride.

[0026] The thickness of the remnants 34 and of layer 36 is typically three or five times less than the thickness of monocrystalline silicon 30 encapsulated in layer 24. For example, the thickness of layer 36 is less than 100 nm.

[0027] Layer 26 contains part 6 of an optical component encapsulated within a dielectric encapsulating material 38. Material 38 may be the same as material 32 or a different dielectric material. Here, material 38 is the same as material 32. Therefore, material 38 is silicon oxide. Part 6 of the optical component is made of the same material as part 4 of the optical component or of another semiconductor material, such as InP alloy.

[0028] The thickness of the thin dielectric layer 8 is generally much smaller than the thickness of the buried layer of standard SOI substrates. Indeed, typically, the silicon oxide buried layer of a standard SOI substrate is thicker than 500 nm or 1 µm and generally less than 10 µm or 20 µm. Therefore, during the fabrication of the photonic chip 2, it is necessary to thin the buried layer of a standard SOI substrate while maintaining good accuracy in its thickness to fabricate this thin dielectric layer 8.

[0029] To this end, the photonic chip 2 comprises several pads distributed uniformly across the entire horizontal face of layer 22. For simplicity in the figures, only pad 50 is shown. Here, the other pads of the photonic chip 2 are structurally identical to pad 50 except that they are located in different positions on the upper face of layer 22. Therefore, only pad 50 is described in detail hereafter, and the numerical reference 50 is also used to collectively designate all of these pads of the photonic chip 2.

[0030] The pad 50 extends vertically from a face 52, which is flush with the upper surface of layer 22, to a face 54, referred to in this text as the "buried face." In this embodiment, face 54 is flush with the upper surface of the thin dielectric layer 8. It is therefore located at the interface between layers 8 and 26. Thus, the pad 50 passes completely through layers 8 and 24.

[0031] The pad 50 is a right cylinder with vertical generatrices. Its horizontal cross-section is, for example, rectangular or circular. The surface area of ​​face 54 is typically greater than 1 µm² or 5 µm² and generally less than 50 µm² or 20 µm². The density of the pads 50 in the photonic chip 2 is greater than 10% and, preferably, greater than or equal to 20%. Advantageously, the density of the pads 50 is also less than 40% or 30%. In this embodiment, the density of the pads 50 is 20%. The density of the pads 50 is equal to the ratio C 54 / S 22 × 100, where: C 54 is the sum of the areas of the faces 54 of all the pads 50 of the photonic chip 2, S 22 is the total area of ​​the upper horizontal face of layer 22, the symbol "x" denotes the scalar multiplication operation.

[0032] Face 54 is made of a material that allows it to be used as a stop layer during the thinning of a buried silicon oxide layer. Therefore, face 54 is made of a material other than silicon oxide. For example, in this first embodiment, face 54 is made of silicon nitride. More precisely, in this embodiment, the pad 50 has a silicon oxide core 56 and a thin silicon nitride film 58 covering this core 56.

[0033] The manufacturing process of photonic chip 2 will now be described with reference to the flowchart of the figure 2 and with the help of figures 3 to 11 .

[0034] Initially, during step 80, a standard SOI 82 substrate is provided ( figure 3 ). Substrate 82 comprises a stack of the following three layers immediately superimposed on one another from bottom to top: a support 84, a buried layer 86 of silicon oxide, and a layer 88 of monocrystalline silicon.

[0035] For example, support 84 is made of silicon. Its thickness is typically greater than 400 µm or 700 µm.

[0036] The thickness of the buried layer 86 is classically greater than 500 nm or 1 µm and, generally, less than 10 µm or 20 µm.

[0037] In the particular case where part 4 is an electrode of a phase modulator, during a step 90, one or more localized dopings of the single-crystal silicon layer 88 are carried out at the location where part 4 is to be formed.

[0038] During step 91, the pads 50 are made. Here, for this purpose, during operation 92, a cavity 94 ( figure 4The cavity 94 is made at the location of each pad 50. The cavity 94 passes completely through the single-crystal silicon layer 88 and has a bottom 96 located inside the layer 86. The bottom 96 extends horizontally. It is located at a depth P96 inside the layer 86. The depth P96 is measured from the top face of the layer 86. The depth P96 is less than, and typically two to five times less than, the thickness e86 of the layer 86. Preferably, the depth P96 is less than 150 nm or 100 nm. Here, the depth P96 is equal to the thickness e8 of the thin dielectric layer 8 and therefore less than 30 nm.

[0039] Here, cavity 94 is, for example, hollowed out by implementing one or more chemical etchings.

[0040] Choosing a small P96 depth increases the accuracy at that depth. Indeed, if the etching accuracy of layer 86 is ±5%, then a P96 depth of 100 nm corresponds to a maximum error of ±5 nm. Conversely, if the P96 depth is much greater, for example, 1 µm, the maximum error is then ±50 nm, and therefore ten times greater. Thus, by limiting the P96 depth, the accuracy is increased.

[0041] During operation 100, the masking layer 36 of dielectric material is deposited over the entire upper surface. This layer 36 covers the entire upper surface of the single-crystal silicon layer 88. A portion of this layer 36 also covers the bottom 96 of the cavity 94 and forms the film 58 of the pad 50.

[0042] The thickness of layer 36 along the vertical walls of cavity 94 is more difficult to control than the thickness of layer 36 along the horizontal faces. Therefore, to ensure that core 56 is consistently isolated from layer 86 by film 58, the thickness e36 of layer 36 is chosen to be greater than the depth P96. Under these conditions, core 56, which is formed in the next step, is located entirely above layer 86.

[0043] During operation 104, the center of cavity 94 is filled with a material other than silicon to form core 56. Here, cavity 94 is filled, at this stage, with silicon oxide. For example, a layer of silicon oxide thicker than the remaining depth of cavity 94 is deposited. This layer of silicon oxide is deposited, for example, over the entire upper surface of the masking layer 36 by implementing a chemical vapor deposition process such as the process known by the acronym PECVD (plasma enhanced chemical vapor deposition).

[0044] Next, the top surface is polished using layer 36 as a stop coat for this polishing. The state shown on the figure 6 is then obtained. The construction of plot 50 is then complete.

[0045] During step 110, the single-crystal silicon layer 88 is structured to form, in particular, part 4 of the optical component.

[0046] To achieve this, during operation 112, the masking layer 36 is etched to leave remnants 34 of this layer 36 only above the locations where part of an optical component is to be produced. The state shown on the figure 7 is then obtained at the end of operation 112.

[0047] Preferably, the cumulative surface area of ​​the upper faces of the remnants 34 obtained at the end of operation 112 is greater than 10% and, preferably, greater than or equal to 20% of the horizontal surface of the layer 88. For this purpose, here, remnants 34 are formed around each of the pads 50 made in order to increase the remaining silicon nitride surface area and thus be able to use these remnants 34 as a stop layer in a subsequent step.

[0048] In operation 114, layer 88 is etched through the etching mask formed by the remnants 34. For example, in this operation 114, an etching agent that dissolves monocrystalline silicon is applied to the upper surface of the etching mask. This etching agent can be liquid or gaseous.

[0049] Following operation 114, the state represented on the figure 8 is obtained. Etching layer 88 creates pits at the locations where the monocrystalline silicon has been removed. Step 110 of structuring the monocrystalline silicon is then completed and part 4 of an optical component is obtained.

[0050] In step 120, the structured monocrystalline silicon layer is encapsulated in the encapsulation material 32 to form the encapsulated monocrystalline silicon layer 24. At the end of step 120, the state shown on the figure 9is obtained. In step 120, a layer of the encapsulating material 32 is deposited over the entire upper surface of the etching mask. This layer of material 32 completely fills the voids formed in the single-crystal silicon layer. For this purpose, the thickness of the encapsulating material 32 layer is greater than the depth of the voids to be filled. For example, the encapsulating material 32 layer is deposited using a chemical vapor deposition process. Next, the encapsulating material 32 that is located outside the voids is removed, and the upper surface of layer 24 is prepared for bonding, for example, direct or molecular bonding. For this, the upper surface of layer 24 is polished using a chemical-mechanical polishing (CMP) process. This CMP process is stopped when the upper surface of the remaining material 34 is exposed.

[0051] During step 124, substrate 18 is bonded to layer 24. The state represented on the Figure 10 is then obtained. In the Figure 10 and in the following figure, the stacking of layers 84, 86 and 24 is reversed, so that layer 24 is now at the bottom of this stacking with its face glued to the top face of layer 22 of substrate 18. For example, in step 124, layer 24 is glued to layer 22 by molecular bonding, that is, without the addition of any external material.

[0052] In step 126, the substrate 84 is removed to expose the back face of the buried layer 86.

[0053] Next, in step 128, the buried layer 86 is thinned to leave only a residual layer 129 of silicon oxide deposited on layer 24. This residual layer 129 here forms the entirety of the thin dielectric layer 8. The state represented on the figure 11 is then obtained.

[0054] During step 128, the thinning of layer 86 is stopped by using the buried faces 54 of the pads 50 as a stop layer. In other words, the thinning of layer 86 is stopped as soon as the buried faces 54 are exposed.

[0055] Since the buried faces 54 are located at depth P 96 within the buried layer 86, at the moment the thinning of the buried layer 86 is stopped, the thickness e 129 of the residual layer 129 is precisely equal to the depth P 96. In this first embodiment, the thickness e 129 is equal to the thickness e 8 of the thin dielectric layer 8. Thus, the use of the pads 50 makes it possible to easily produce the thin dielectric layer 8 with high precision in its thickness. For example, the thinning of the buried layer 86 is carried out using a CMP process.

[0056] In step 130, part 6 of an optical component is made on the thin dielectric layer 8.

[0057] Then, in step 132, part 6 of a fabricated optical component is encapsulated in the dielectric material 38 to obtain layer 26. Steps 130 and 132 are carried out, for example, as described in US20170237229.

[0058] At the end of steps 130 and 132, the photonic chip 2 shown on the figure 1 is obtained.

[0059] Next, additional steps are implemented to complete the fabrication of the photonic chip 2. For example, in the particular case where the optical component is a modulator, a step of making electrical contacts on parts 4 and 6 is carried out.

[0060] There figure 12 represents a first variant of the manufacturing process of the figure 2 This first variant is identical to the manufacturing process of the figure 2 except that a step 150 is introduced between steps 128 and 130.

[0061] Step 150 is a step for depositing an additional dielectric layer 152 ( Figure 13 ) directly onto the residual layer 129 obtained at the end of step 128. The state obtained at the end of step 150 is represented on the figure 13In this variant, the superposition of the residual layer 129 and the additional dielectric layer 152 forms a thin dielectric layer 154 through which parts 4 and 6 are coupled. The thin layer 154 is functionally identical to the thin layer 8. However, in this variant, the thin layer 154 is generally thicker than the thin layer 8. Thus, this variant is primarily intended for the fabrication of parts 4 and 6 of optical components that are optically coupled through the thin layer 154. The additional dielectric layer 152 is made of silicon oxide or another dielectric material such as silicon nitride. The deposition of this additional dielectric layer 152 has very little impact on the accuracy of the thickness of the thin layer 154 located between parts 4 and 6 of optical components.Indeed, the accuracy of the thickness of the dielectric layer 152 obtained by depositing dielectric material is much greater than the accuracy of the thickness of a dielectric layer obtained by thinning a thicker dielectric layer. For example, in this variant, the thickness of the residual layer 129 is between 30 nm and 50 nm, and the thickness of the additional dielectric layer 152 is between 50 nm and 150 nm.

[0062] There figure 14 represents a second variant of the process of the figure 2 This second variant is identical to the process of the figure 2 except that steps 91, 110, 128 are replaced, respectively, by steps 160, 162, 164.

[0063] Step 160 is identical to step 91 except that operations 100 and 104 are replaced, respectively, by operations 170 and 174.

[0064] Operation 170 is an oxidation operation of monocrystalline silicon to form a layer 176 ( figure 15 ) of thermal oxide which covers the entire upper face of the layer 88 of monocrystalline silicon as well as the portions of the vertical walls of the cavity 94 made of monocrystalline silicon.

[0065] The resulting layer 176 does not cover the walls of cavity 94, which are made of silicon oxide. Therefore, layer 176 does not cover the bottom 96 of cavity 94 because this bottom is made of silicon oxide.

[0066] Operation 174 is a filling operation for cavity 94 with a filler material other than silicon oxide. In this embodiment, the filler material is polycrystalline silicon. The procedure is the same as described for operation 104, except that: Instead of depositing silicon oxide, polycrystalline silicon is deposited, and the polishing of the top face uses layer 176 as a stop layer.

[0067] At the end of step 160, the state represented on the figure 15 is obtained. On the figure 15 The plot produced bears the numerical reference 180. This plot 180, like the plot 50 previously described, includes: a buried face 184 which extends horizontally inside the layer 86 at depth P 96, a core 186 of polycrystalline silicon, and a film 188 of silicon oxide which covers the portion of the vertical faces of the core 186 located inside the silicon layer 88.

[0068] Step 162 is identical to step 110 except that it includes, before operation 112, an operation 192 of depositing a layer 194 ( Figure 16) of masking on the upper faces of the pads 180 and the thermal oxide layer 176. At the end of operation 194, the state shown on the figure 16 is obtained.

[0069] For example, the masking layer 194 is identical to the masking layer 36 except that in this variant, this layer 194 also covers the upper faces of the pads 180. In addition, during operation 192, the thickness of the layer 194 deposited may be less than the depth P 96.

[0070] During step 112, the masking layer 194 is etched, leaving the remnants 34 only above the locations of the monocrystalline silicon layer 88 that are not to be etched. In this variant, the upper face of each pad 180 is entirely covered with a respective remnant 34 to protect the polycrystalline silicon core 186 during the subsequent etching operation 114. This simply results in a larger cumulative horizontal surface area of ​​remnant 34 than with the process of the figure 2 and therefore to obtain a stop layer used during step 120 with a larger surface area.

[0071] Step 164 is identical to step 128 except that the buried face 184 is used as the arrest layer. At the end of step 164, the state represented on the figure 17 is obtained. On the figure 17, the encapsulated monocrystalline silicon layer bears the numerical reference 198 and functionally corresponds to layer 24 of the photonic chip 2.

[0072] The following steps are identical to those described in the case of the figure 2 . Chapter III: Variants Variations of the process shown in Figure 2 :

[0073] The cavities 94 can be filled with any other filling material other than silicon. For example, the cavities are filled with silicon nitride.

[0074] In the case where the filling material is different from silicon oxide or if the thickness of the masking layer 36 deposited on the vertical walls of the cavity 94 is systematically sufficient to properly isolate the core 56 from the buried layer 86, then the thickness e 36 of the layer 36 can be less than the depth P 96. Variations of the process shown in Figure 14 :

[0075] The polysilicon used to fill cavities 94 can be replaced by any material, other than silicon oxide, that can be polished by a CMP process with a stop on the thermal oxide layer. For example, polysilicon can be replaced by polygermanium or silicon nitride.

[0076] The masking layer 194 can be made of a material other than silicon nitride. For example, alternatively, the masking layer 194 is made of titanium nitride or silicon oxide.

[0077] Alternatively, the masking layer 194 is completely removed after the structuring of layer 88 in semiconductor material. For example, in this case, the masking layer is made of a photosensitive material such as a photoresist. Common variations across all manufacturing processes:

[0078] Other dielectric encapsulation materials can be used instead of silicon dioxide to encapsulate single-crystal silicon. However, preferably, the chosen encapsulation material has optical and electrical properties similar to those of silicon dioxide. Furthermore, preferably, the chosen encapsulation material can be deposited by chemical vapor deposition and, advantageously, by a PECVD process. For example, alternatively, the dielectric encapsulation material is tetraethyl orthosilicate, better known by the acronym TEOS, or silane.

[0079] Other shapes are possible for the pads 50. For example, the horizontal cross-section of the pads 50 can have any shape. It is not necessary for the horizontal cross-sections of all the pads in the photonic chip 2 to be identical. For example, alternatively, some of the pads in the photonic chip may have a rectangular cross-section while others may have a different horizontal cross-section, for example, a circular one.

[0080] In the case where it is not necessary for parts 4 and 6 of optical components to be doped, then step 90 of doping these parts 4 and 6 are omitted.

[0081] Other embodiments of operation 114 for etching the single-crystal silicon layer are possible. For example, to structure a multi-layered part of an optical component within the single-crystal silicon layer, a multi-level etching operation can be implemented.

[0082] Step 128, thinning the buried layer, can be carried out by means other than chemical polishing. For example, alternatively, the thinning is achieved using only chemical etching. In this latter case, the chemical etching is stopped as soon as components resulting from the etching of the buried faces 54 are detected in the etching agent bath used to perform this chemical etching.

[0083] In another variant, step 128 of thinning the buried layer comprises a first and then a second thinning operation. The first thinning operation is a stopping operation on the buried faces 54 of the pads 50. This first thinning operation is identical to that described in the preceding embodiments. This first thinning operation yields the residual layer 129. Following the first thinning operation, the second thinning operation is carried out to thin the residual layer 129. The first and second thinning operations differ from each other in the chemical and / or physical processes employed. For example, typically, the etching agent used in the second thinning operation is different from the etching agent used in the first thinning operation.In particular, during the second thinning operation, the etching agent is a non-selective etching agent that etches the silicon oxide and the buried face 54 of the pads at the same rate. Conversely, during the first thinning operation, it is not necessary for the etching agent used to etch the silicon oxide and the buried faces 54 of the pads at the same rate. For example, the first thinning operation is used to obtain the residual layer 129 with a thickness between 40 nm and 150 nm, and then the second thinning operation is used to obtain a thin dielectric layer with a thickness of less than 30 nm.

[0084] Optical component parts can be coupled optically or capacitively to each other through a thin dielectric layer. In the case of optical coupling, the desired thickness of the thin dielectric layer is generally greater than the desired thickness of the thin dielectric layer in the case of capacitive coupling.

[0085] Electrical contacts and electrical interconnections can be made in the substrate 18 or in an additional interconnection layer deposited on layer 26.

[0086] The semiconductor material used is not necessarily single-crystal silicon. For example, alternatively, the semiconductor material is germanium or silicon carbide. In the case of germanium, the initial stack from which the manufacturing process begins is then known by the acronym GOI ("Germanium On Insulator").

[0087] Several of the embodiments described here can be combined with each other. Chapter III: Advantages of Implementation Methods described:

[0088] Using the buried faces of the pads 50 and 180 as arrest faces during the thinning of the buried layer 86 increases the accuracy of the thickness of the resulting residual layer 129. Ultimately, this limits the dispersion of the characteristics of photonic chips manufactured using the fabrication processes described herein. Furthermore, this fabrication process remains compatible with the use of standard SOI substrates, i.e., SOI substrates in which the buried layer thickness exceeds several hundred nanometers. Finally, the residual layer 129 is obtained without completely removing the buried layer 86 after the substrate is flipped. Such complete removal of the buried layer is disadvantageous because the complete removal of the buried layer 86 is then stopped by using the structured semiconductor material as an arrest layer.This leads to increased roughness of the optical component parts made from the semiconductor material, thus degrading the performance of the manufactured photonic chip. Furthermore, complete removal of the buried layer increases silicon oxide consumption. By avoiding complete removal of the buried layer, the processes described here mitigate these drawbacks.

[0089] The use of a 176 layer of thermal oxide as a stop layer when making the 180 pads avoids the need to deposit another material to form this stop layer.

[0090] Applying the masking layer 194, including over the pads 180, results in a masking layer with a larger surface area than when the process of the figure 2is implemented to fabricate the same photonic chip. In other words, the masking material density on the face to be polished at the end of the encapsulation step is greater. This higher masking material density on the face to be polished results in a flatter encapsulated semiconductor layer, since the masking layer also acts as a polishing stop layer for the encapsulated semiconductor layer. Ultimately, this improves the bonding of the substrate 18 to the encapsulated semiconductor layer 198.

[0091] Using the same layer 36 to form the etching mask and the buried faces 84 of the pads 50 simplifies the manufacturing process. In particular, it offers the possibility of using silicon oxide as a cavity filling material 94.

[0092] The fact that the thickness e 36 of the masking layer 36 is greater than the predetermined depth P 96 allows the core 56 of the pad 50 to be made of silicon oxide, which simplifies the manufacturing process.

[0093] The fact that the etching mask formed on the single-crystal silicon layer 88 covers more than 10% of the horizontal top surface of this layer 88 allows this etching mask to also be used as a stop layer during the polishing of the encapsulated semiconductor material layer 24. This simplifies the manufacturing process.

[0094] The fact that the P96 depth is less than 150 nm increases the accuracy of the thickness of the resulting residual layer 129. Indeed, the margin of error for the P96 depth is typically ±5% with conventional etching processes. The error in the thickness of the residual layer 129 is therefore less than 7.5 nm. This is significantly more accurate than when using known processes to form such a residual silicon oxide layer.

[0095] The fact that the cumulative buried areas 54 represent more than 10% of the surface of the buried layer makes it possible to improve the flatness of the residual layer 129.

Claims

1. Method for manufacturing a photonic chip, this method comprising: - providing (80) a first stack successively comprising a support, a buried silicon oxide layer and a semiconductor material layer, then - structuring (110; 162) the semiconductor material layer to form at least a first part of an optical component in the semiconductor material layer, then - encapsulating (120) the structured semiconductor material layer in a dielectric encapsulation material to obtain a semiconductor material layer encapsulated in a dielectric material, then - bonding (124) a substrate to the encapsulated semiconductor material layer, then - removing (126) the support to expose the buried layer, then - thinning (128; 164) the buried layer to leave a residual silicon oxide layer on the encapsulated semiconductor material layer on the side where the support was removed, then - forming (130) a second part of an optical component on the residual silicon oxide layer, this second part of an optical component being coupled to the first part of an optical component through the residual silicon oxide layer via optical or capacitive coupling, characterized in that: - prior to the bonding of the substrate, the method comprises forming (91; 160) studs pressed into the buried layer, each of these studs comprising a buried face which extends parallel to the interface between the buried layer and the semiconductor material layer to a predetermined depth within the buried layer, each of the buried faces being formed of a material different from the silicon oxide of the buried layer, and - the thinning (128; 164) of the buried layer comprises an operation of thinning the buried layer, with this thinning stopping as soon as the buried face of the studs is exposed.

2. Method according to Claim 1, wherein the forming of the pressed-in studs comprises, prior to the structuring of the semiconductor material layer: - at the location of each stud, forming (92) a cavity which passes through the semiconductor material layer and the bottom of which extends parallel to the interface between the buried layer and the semiconductor material layer to the predetermined depth within the buried layer, then - oxidizing (170) the semiconductor material layer to obtain a thermal oxide layer which covers the semiconductor material layer, then - filling (174) each cavity with a filling material different from the silicon oxide of the buried layer, then - polishing, stopping on the thermal oxide layer, the face from which the cavities were filled with the filling material to dispose of the filling material located outside these cavities.

3. Method according to Claim 2, wherein: - the structuring of the semiconductor material layer comprises: - depositing (192) a masking layer which covers the pressed-in studs formed and the entirety of the semiconductor material layer, this masking layer being formed of a material different from the semiconductor material, then - etching (112) the masking layer and thermal silicon oxide layer at the locations where the semiconductor material layer is to be removed to obtain an etching mask, then - etching (114) the semiconductor material layer through the etching mask obtained, said etching forming recesses in the semiconductor material layer at the locations where the semiconductor material is etched, - the encapsulation (120) of the semiconductor material layer comprises: - filling the recesses with the dielectric encapsulation material, then - polishing, stopping on the masking layer, the face from which the recesses were filled with the dielectric encapsulation material to dispose of the dielectric encapsulation material located outside these recesses.

4. Method according to Claim 1, wherein: - the forming (91) of the pressed-in studs comprises, prior to the structuring of the semiconductor material layer: - at the location of each stud, forming (92) a cavity which passes through the semiconductor material layer and the bottom of which extends parallel to the interface between the buried layer and the semiconductor material layer to the predetermined depth within the buried layer, then - depositing (100) a masking layer which covers the entirety of the semiconductor material layer and the bottom of each cavity, this masking layer being formed of a material different from the silicon oxide of the buried layer and different from silicon, - filling (104) each cavity with a filling material different from the semiconductor material, then - the structuring (110) of the semiconductor material layer comprises: - etching (112) the masking layer at the locations where the semiconductor material layer is to be removed to obtain an etching mask, then - etching (114) the semiconductor material layer through the etching mask obtained, said etching forming recesses in the semiconductor material layer at the locations where the semiconductor material is etched.

5. Method according to Claim 4, wherein the thickness of the masking layer is greater than the predetermined depth.

6. Method according to Claim 4 or 5, wherein: - the etching mask obtained covers at least ten percent of the surface area of the semiconductor material layer before the latter is etched, and - the encapsulation (120) of the semiconductor material layer comprises: - filling the recesses with the dielectric encapsulation material, then - polishing, stopping on the masking layer, the face from which the recesses were filled with the dielectric encapsulation material to dispose of the dielectric encapsulation material located outside these recesses.

7. Method according to any one of the preceding claims, wherein the predetermined depth is less than 150 nm or 100 nm.

8. Method according to any one of the preceding claims, wherein the cumulative sum of the surface areas of the buried faces is greater than 10% of the surface area of the buried layer.

9. Method according to any one of the preceding claims, wherein the semiconductor material is monocrystalline silicon.

10. Method according to any one of the preceding claims, wherein, when encapsulating (120) the semiconductor material layer, the dielectric encapsulation material used to encapsulate the semiconductor material is a silicon oxide.

11. Photonic chip obtained by a manufacturing method according to any one of the preceding claims, wherein the photonic chip comprises, successively stacked one on top of the other: - a substrate (18), - a first layer (24; 198) of encapsulated semiconductor material comprising at least a first part (4) of an optical component formed in the encapsulated semiconductor material, - a dielectric layer (8; 154) comprising a residual layer (129) of silicon oxide, - a second layer (16) of encapsulated semiconductor material comprising at least a second part (6) of an optical component formed in the encapsulated semiconductor material, this second part of an optical component being coupled to the first part of an optical component through the dielectric layer via optical or capacitive coupling, characterized in that the photonic chip comprises studs (50; 180) which each extend from the interface between the substrate and the first encapsulated semiconductor material layer to a buried face (54; 184) located between: - the interface between the dielectric layer (8; 154) and the first encapsulated semiconductor material layer (24; 198), and - the interface between the dielectric layer (8; 154) and the second encapsulated semiconductor material layer (26), the buried face of each stud being formed of a material different from silicon oxide and extending parallel to the interface between the dielectric layer (8; 154) and the first encapsulated semiconductor material layer (24; 198).