Microelectronic device with a sheathing grid and method for manufacturing such a device

Description

DOMAINE TECHNIQUE

[0001] The invention relates to the field of microelectronic technologies. It finds a particularly advantageous application in the manufacture of advanced FET (Field-Effect Transistor) type devices with encapsulated gate and channel based on semiconductor materials, in particular based on two-dimensional (2D) materials or semiconductor oxides. ETAT DE LA TECHNIQUE

[0002] The constant increase in transistor performance was initially made possible by reducing the size of transistors, for a classic silicon-based MOSFET (“Metal-Oxide-Semiconductor Field-Effect Transistor”) architecture.

[0003] This traditional architecture has since given way to other types of architectures better suited to the performance requirements of sub-12 nm technology nodes. The so-called "finFET" architecture, for example, meets the performance standards set by the 7 nm and 5 nm technology nodes. This type of architecture allows, in particular, for easy adjustment of the transistor threshold voltage to prioritize either high performance or low power consumption, depending on the intended application.

[0004] For the next technological nodes, particularly those at 3 nm and below, alternative architectures offering improved electrostatic control are needed. One architecture considered to address the challenges of these next technological nodes incorporates gate-all-around (GAA) transistors. These GAA transistors typically feature very thin channels, in the form of nanowires or nanosheets, stacked on top of each other. However, this type of architecture is less versatile than the finFET architecture. The threshold voltage cannot be easily adjusted.

[0005] The paper "Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications, R. Bao et al., 2019 IEEE International Electron Devices Meeting (IEDM)" discloses a solution for integrating nanosheet GAA transistors with a wide range of threshold voltages. The device and method described in this paper are based on introducing varying nanosheet dimensions within the same stack, with precise gate dimensional control. The different portions of the encapsulating gate thus have varying metal thicknesses. This allows for different threshold voltages to be achieved within the same stack. Four different threshold voltages are therefore achievable with this architecture. To increase the number of achievable threshold voltages, different regions, fabricated with different technological parameters, are still required.

[0006] Document WO 2008 / 023776 A1 describes a transistor comprising a stack of semiconductor layers forming the channel. Each semiconductor layer has its upper face in contact with a first gate electrode via a gate insulating film, and its lower face in contact with a second gate electrode, also through the insulating film. The first and second gate electrodes are each connected to separate contact pads.

[0007] US patent application 2020 / 0176613 A1 discloses a nanowire transistor with two gate electrodes. A first gate is in contact with each nanowire on a horizontal top face, a vertical wall, and a horizontal bottom face, while a second gate is in contact with the other vertical wall of each nanowire.

[0008] A major challenge for the development of these GAA transistor architectures is the ability to finely adjust their threshold voltage.

[0009] A first objective of the invention is to propose a GAA transistor architecture allowing extensive control of the threshold voltage. A second objective of the invention is to propose a method for implementing such a GAA transistor architecture. Another objective of the invention is to overcome, at least partially, the drawbacks of known devices and methods. RESUME

[0010] To achieve these objectives, according to one embodiment, a microelectronic device according to claim 1 is provided, the microelectronic device comprising at least one transistor comprising: at least two channels stacked along a principal direction z, each channel being based on a semiconductor material, a gate surrounding at least one of the channels, a source and a drain on either side of the channels, and source and drain contacts connected respectively to the source and the drain, a dielectric gate layer separating each channel from the gate,

[0011] The grid corresponds to a first grid partially surrounding at least one of the channels.

[0012] According to the invention, at least one transistor comprises a second gate partially surrounding the same channel as that surrounded by the first gate, the first and second gates being electrically isolated from each other so that they can be biased independently of each other.

[0013] Thus, the device comprises two gates surrounding the transistor channels, which can be independently biased. This allows for continuous adjustment of the device's threshold voltage, unlike known solutions that only allow access to a few threshold voltages predetermined by the architectural design. The device according to the invention advantageously offers a wide range of threshold voltages for a GAA architecture. It can be described as a dual-gate device. The gate dielectric layer can exhibit ferroelectric properties, for example, for the fabrication of FeFET (ferroelectric field-effect transistor) memory transistors.

[0014] Another aspect of the invention relates to a method for manufacturing this microelectronic device. The method according to claim 3 comprises the following steps: Provide on a substrate a stack along the principal direction z comprising a plurality of first layers of a first material alternating with a plurality of second layers of a second material alternating with a plurality of third layers of a third material, the first, second, and third materials being different; Form a first etching mask on this stack; Form in this stack first openings defining first patterns perpendicular to the first etching mask; Form a sacrificial grid on either side of the first patterns, in the first openings; Form a second etching mask on the first etching mask and on the sacrificial grid, the second etching mask being transverse to the first etching mask; Form in the first patterns second openings defining second patterns perpendicular to the second etching mask; Partially removeFrom the second openings, the third material of the third layers is selectively removed from the first and second materials of the first and second layers, so as to form third spaces within the third layers. The third spaces are filled with a third dielectric material to form internal third spacers. Partially removed, from the second openings, the first material of the first layers is selectively removed from the second material of the second layers and from the internal third spacers, so as to form first spaces within the first layers, preferably directly above the internal third spacers. The first spaces are filled with a first dielectric material to form internal first spacers. Partially removed from the sacrificial grid so as to form third openings leading to remaining portions of the third layers. Completely removed, from the third openings,the third material from the remaining parts of the third layers, so as to form third cavities, Form a first dielectric layer in the third cavities, Fill the third cavities with a first metallic material, so as to form the first grid partially surrounding the second layers, Completely remove a remaining part of the sacrificial grid so as to form fourth openings leading to remaining parts of the first layers, Completely remove, from the fourth openings, the first material from the remaining parts of the first layers, so as to form first cavities, Form a second dielectric layer in the first cavities, Fill the first cavities with a second metallic material, so as to form the second grid partially surrounding the second layers,Fill the second openings with an electrically conductive material to form source and drain contacts at the interface of the second layers.

[0015] One principle of the method according to the invention consists of selectively replacing certain layers of the initial stack, here the first and third layers, to form two typically interdigitated gate parts surrounding layers based on a semiconductor material forming the transistor channels, here the second layers. The advantages mentioned above for the device apply mutatis mutandis to the process according to the invention.

[0016] In one approach, the second layers are subsequently replaced with a semiconductor material to form the transistor channels. In this case, the initial stack does not include the semiconductor material forming the transistor channels. The subsequent deposition of the semiconductor material aims to better preserve the semiconductor material. In a preferred approach, the semiconductor material is a two-dimensional (2D) material selected from the MX2 transition metal dichalcogenides, with M taken from molybdenum (Mo) or tungsten (W), and X from sulfur (S) or selenium (Se). The process allows, in particular, the introduction of 2D material layers at the end of the process, after the stack has been structured and, specifically, after the formation of the internal spacers. This advantageously limits the risk of degradation of the 2D material during the process. The 2D material is not exposed at all stages of the manufacturing process.The 2D material is thus preserved.

[0017] This late introduction of the 2D material during the manufacturing process also allows the use of standard microelectronic technologies for stack formation and structuring. There is no need to modify or adapt the standard structuring steps to accommodate the constraints of using the 2D material. This significantly reduces process costs and makes the process easier to implement in existing production lines.

[0018] The other objects, features, and advantages of the present invention will become apparent from an examination of the following description and accompanying drawings. It is understood that other advantages may be incorporated. BREVE DESCRIPTION DES FIGURES

[0019] Figures nA (n=1...22) schematically illustrate, in cross-sections xz, the manufacturing steps of a device with superimposed channels, according to a first embodiment of the present invention. Figures nB (n=1...22) schematically illustrate, in cross-sections yz indicated in the corresponding Figures nA, the same manufacturing steps of the device, according to a first embodiment of the present invention. Figures nA (n=23...34) schematically illustrate, in cross-sections xz, the manufacturing steps of a device with superimposed channels, according to a second embodiment of the present invention. Figures nB (n=23...34) schematically illustrate, in cross-sections yz indicated in the corresponding Figures nA, the same manufacturing steps of the device, according to a second embodiment of the present invention.Figures nA (n=35, 36) schematically illustrate, in cross-sections xz, variants of a superimposed channel device according to another embodiment of the present invention. Figures nB (n=35, 36) schematically illustrate, in cross-sections yz indicated in the corresponding figures nA, the same variants of the device according to another embodiment of the present invention.

[0020] In the cross-sectional figures, cutting planes are indicated (A-A', B-B', ..., P-P', ..., Z-Z', α-α', ..., ε-ε', ..., λ-λ') with cross-references to the cutting planes of the corresponding figures. The drawings are provided by way of example and are not intended to limit the invention. They constitute schematic representations of principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications. In particular, in the schematic diagrams, the thicknesses and / or dimensions of the various layers, patterns, and reliefs are not representative of reality. For clarity, not all alphanumeric references are systematically repeated from one figure to another. It is understood that elements already described and referenced, when reproduced on another figure, typically bear the same alphanumeric references, even if these are not explicitly mentioned.A person skilled in the art will easily identify the same element reproduced in different figures. DESCRIPTION DÉTAILLÉE

[0021] Before beginning a detailed review of embodiments of the invention, features of the invention and optional features which may possibly be used in association or alternatively are stated below: According to an example, each channel is partially surrounded by the first grid and is partially surrounded by the second grid.

[0022] According to the invention, the first grid and the second grid are interdigitated.

[0023] According to the invention, each channel is interposed between a finger of the first grid and a finger of the second grid.

[0024] According to the invention, the first grid covers two adjacent sides of one of the channels, and the second grid covers two other adjacent sides of this channel.

[0025] According to one example, the first and second grids have complementary shapes completely surrounding at least one of the channels, in particular surrounding all sides of that channel.

[0026] According to one example, the semiconductor material is a transition metal dichalcogenide MX2 with M taken from molybdenum (Mo) or tungsten (W), and X taken from sulfur (S), selenium (Se) or tellurium (Te).

[0027] According to another example, the semiconductor material is based on a semiconductor oxide, for example based on IGZO (Indium-Gallium Zinc Oxide), In2O3, IWO (Tungsten-Doped Indium Oxide), ITO (Indium Tin Oxide), IAZO (Indium-Aluminum Zinc Oxide), InGaZnO, InGaO, InZnO or an amorphous semiconductor oxide.

[0028] According to another example, the semiconductor material is based on graphene, hexagonal boron nitride "h-BN", phosphorene.

[0029] According to the invention, the stack comprises an alternating first layer with a second layer and a third layer. Preferably, the initial stack does not include the semiconductor material of the transistor channels, nor the materials of the various gates or portions of the surrounding gate. For example, the first layers of the provided stack are in contact only with the second layers, and the third layers of the provided stack are in contact only with the second layers.

[0030] As an example, the first and third internal spacers are silicon nitride-based. The first internal spacers are preferably in contact with the remaining portions of the first layers. The third internal spacers are preferably in contact with the remaining portions of the third layers. Before the formation of the first internal spacers, the partial shrinkage of the first material from the first layers is configured to retain portions of the first layers between the first spaces. These portions are called residual portions. The remaining portions of the first layers are thus located between the first spaces, along a direction in the xy plane. Before the formation of the third internal spacers, the partial shrinkage of the third material from the third layers is configured to retain portions of the third layers between the third spaces. These portions are called residual portions.The remaining parts of the third layers are thus located between the third spaces, along a direction of the xy plane.

[0031] According to one example, the process further includes a sequence of steps configured to replace the second layers, said sequence comprising the following steps: Completely remove, from the second openings, the second material of the second layers, for example selectively from the first material of the first layers, so as to form second spaces, Preferably form a dielectric layer in the second spaces, Deposit a layer based on a semiconductor material in the second spaces, so as to form: ∘ channels based on the semiconductor material above the first and second grids, under the first and second etching masks, and ∘ sources and drains based on the semiconductor material above the first and third internal spacers.

[0032] Typically, in CMOS (MOSFET) applications, the dielectric layer does not possess ferroelectric properties. In memory applications (FeFETs), this dielectric layer does possess ferroelectric properties.

[0033] In one example, the sequence of steps configured to replace the second layers is performed after the formation of the first and third internal spacers, and the formation of the source and drain contacts is performed after this sequence of steps and before the partial removal of the sacrificial gate. This type of process, typically called "gate last," or in this case "dual gate last," involves the formation of the functional gate at the end of the process, replacing the sacrificial gate. This preserves the dimensional characteristics of the first and second gates. This allows for better control of the MOSFET threshold voltage. The thermal budget associated with the deposition of the base layer of semiconductor material does not impact the equivalent gate oxide thickness at the interface with the first and second gates. The structural and electrical characteristics of the two functional gates are better controlled.

[0034] In one example, the sequence of steps configured to replace the second layers is performed after the formation of the first and second gates and before the formation of the source and drain contacts. This type of process, typically called "gate first," or here "dual gate first," or even "channel last," involves forming the functional gate in place of the sacrificial gate at the beginning of the process. The channels are formed at the end of the process. This helps preserve the channel properties, particularly when the transistor channels are made of a temperature-sensitive material.

[0035] According to one example, the process further includes the formation of spacers on the sides of the first and second engraving masks, said spacers resting on an upper face of the first motifs.

[0036] As an example, the semiconductor material base layer is also deposited on flanks of the second motif that are substantially parallel to the principal z-direction, specifically on flanks of the first internal spacers and on flanks of the third internal spacers. This facilitates the re-establishment of source and drain contacts in the device.

[0037] In one example, the semiconductor-based layer is deposited in such a way that lateral portions of the semiconductor-based layer are placed on flanks of the second pattern substantially parallel to the z-direction, and horizontal portions of the semiconductor-based layer are placed in the second pattern, such that the lateral portions are thicker than the horizontal portions. These thicker lateral portions reduce the contact resistance of the source and drain contacts. The transistor channels are formed in the horizontal portions.

[0038] According to one example, the semiconductor material-based layer deposition is configured to form lateral portions of semiconductor material-based layer on the spacers, on the first internal spacers and on the third internal spacers.

[0039] According to one example, the process includes the formation of source and drain contacts in the second openings.

[0040] For example, the semiconductor base layer is deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD). CVD is easy to implement. ALD allows for precise control of the semiconductor base layer thickness. These deposition methods provide excellent conformity for the semiconductor base layer.

[0041] According to one example, the semiconductor material is chosen from the MX2 transition metal dichalcogenides with M taken from molybdenum (Mo) or tungsten (W), and X taken from sulfur (S), selenium (Se) or tellurium (Te).

[0042] According to another example, the semiconductor material is chosen based on a semiconductor oxide, for example based on IGZO (Indium-Gallium Zinc Oxide), In2O3, IWO (Tungsten-Doped Indium Oxide), ITO (Indium Tin Oxide), IAZO (Indium-Aluminum Zinc Oxide), InGaZnO, InGaO, InZnO or an amorphous semiconductor oxide.

[0043] For example, the first material is SiGe with a germanium concentration between 20 at.% and 25 at.%, the second material is Si, and the third material is SiGe with a germanium concentration of approximately 50 at. These materials can be easily epitaxially grown using conventional microelectronics processes. This allows for the use of existing technologies. The cost of the process is reduced. The assignment of the different materials to the different layers can be interchanged.

[0044] In one example, the sacrificial grid is formed so that it extends the full height of the first openings. In another example, the first openings extend the full height of the stack of the first, second, and third layers. The sacrificial grid extends the full height of the stack. The sacrificial grid typically rests on the substrate. This allows access to all layers of the stack via the third and fourth openings.

[0045] In one example, the deposition of the semiconductor material-based layer is configured so that the semiconductor material-based layer completely fills the second spaces.

[0046] In another example, the semiconductor-based layer is deposited in such a way that it partially fills the second gaps. In yet another example, the process further includes, after the semiconductor-based layer is deposited, the deposition of an additional dielectric layer configured to fill the second gaps. This allows for the formation of a thin semiconductor-based layer without constraining the thickness of the second layers in the stack. The semiconductor-based layer can be thinner than the second layers of the initial stack.

[0047] In one example, the substrate is a bulk silicon-based substrate.

[0048] According to one example, the first openings are formed along a longitudinal direction x and the second openings are formed along a transverse direction y perpendicular to the longitudinal direction x, said first and second openings extending to the substrate.

[0049] According to an example, the removal of the first material from the first layers is done selectively at the second material of the second layers with a selectivity S 10:20 of at least 5:1, preferably at least 10:1. According to an example, the removal of the third material from the third layers is done selectively at the second material of the second layers with a selectivity S 30:20 of at least 5:1, preferably at least 10:1.

[0050] According to one example, the removal of the second material from the second layers is done selectively from the first material of the first layers with a selectivity S 20:10 of at least 5:1, preferably at least 10:1. According to another example, the removal of the second material from the second layers is done selectively from the third material of the third layers with a selectivity S 20:30 of at least 5:1, preferably at least 10:1.

[0051] In one example, the deposition of the semiconductor-based layer is configured to form lateral portions of the semiconductor-based layer on the flanks of the second pattern in the second openings. In another example, the process further comprises the formation of source and drain contacts in said second openings and on the lateral portions of the semiconductor-based layer, either before the start of the sacrificial gate removal or after the formation of the first and second gates.

[0052] Unless otherwise required, it is understood that all the optional features described above may be combined to form an embodiment that is not necessarily illustrated or described. Such an embodiment is not excluded from the invention, provided that such a combination includes at least the features of one of the independent claims.

[0053] The characteristics and advantages of an aspect of the invention, for example the device or the method, can be adapted mutatis mutandis to the other aspect of the invention.

[0054] The invention relates generally to a GAA transistor microelectronic device and a manufacturing method. Such a microelectronic device can have a "GAA stacked nanosheet" architecture, i.e., with stacked nanosheets and a partially or fully enclosing gate. An architecture with stacked nanowires and a partially or fully enclosing gate is also possible.

[0055] Nanowires or nanosheets typically each comprise a conduction channel for a transistor. These channels are stacked along a z-direction. This means that each occupies a specific elevation level along the z-direction. A level can be defined between two planes perpendicular to the z-direction.

[0056] In the present invention, each transistor comprises two gates. Each of these two gates comprises portions surrounding the transistor's channels. These portions can typically be complementary so as to completely or almost completely surround at least one of the transistor's channels. These two gates can be described as "all-around" even if each gate does not completely surround the transistor's channel(s). The combination of the two gates can be likened to a single gate completely surrounding the transistor's channel(s). This architecture therefore falls under both the "Gate All Around" and "Dual Gate" designations.

[0057] Advantageously, the process according to the invention can be implemented for the production of GAA MOS transistors for the 5 nm and sub-5 nm technology nodes.

[0058] A microelectronic device comprising GAA stacked channel transistors can be advantageously integrated into logic systems with 3D architectures. These transistors can, in particular, be combined with other structural or functional elements to design complex systems.

[0059] A particular aspect of the invention concerns the implementation of 2D materials to fabricate the nanowires or nanosheets of the device. These 2D materials exhibit semiconductor properties, notably through the presence of an electronic gap.

[0060] 2D materials typically correspond to compounds with a layered structure made up of two-dimensional sheets stacked along the c-axis. The atomic bonds within each sheet are strong and covalent. The bonds between sheets are much weaker and of the Van der Waals type. These two-dimensional sheets are also called monolayers.

[0061] In the context of the present invention, the monolayers are preferably MX2 type semiconductor monolayers where M is molybdenum (Mo) or tungsten (W) and X is sulfur (S) or selenium (Se). Each monolayer consists of a plane of metal cations M sandwiched between two planes of anions X. A monolayer thus typically comprises three atomic planes: the transition metal atoms (Mo or W) form a plane sandwiched between two chalcogen planes (S, Se, or Te, for example). Each transition metal atom is bonded to six chalcogen atoms. These anions are in prismatic trigonal coordination with respect to the metal atoms. The MX2 transition metal dichalcogenide monolayers exhibit a hexagonal atomic lattice.

[0062] MX2 transition metal dichalcogenide monolayers are preferably based on molybdenum disulfide MoS2, MoSe2, MoTe2, WS2, WSe2.

[0063] An alternative possibility involves using semiconductor oxides to fabricate the device's nanowires or nanosheets, for example IWO, IGZO, ITO, InGaZnO, InGaO, InZnO, In2O3, and IAZO. Another possibility involves using graphene, hexagonal boron nitride (h-BN), or phosphorene (also known as black phosphorus, BP), particularly in monolayer form.

[0064] It is specified that, within the framework of the present invention, the terms "on", "overcomes", "covers", "underlying", "opposite" and their equivalents do not necessarily mean "in contact with". Thus, for example, the deposit or application of a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.

[0065] A substrate, film, or layer "based" on a material A is defined as a substrate, film, or layer comprising only that material A, or that material A and possibly other materials, such as dopants or alloying elements. For example, a silicon nitride (SiN)-based spacer might comprise non-stoichiometric silicon nitride (SiN), stoichiometric silicon nitride (Si3N4), or silicon oxynitride (SiON).

[0066] The term "dielectric" describes a material whose electrical conductivity is sufficiently low in a given application to serve as an insulator. In the present invention, a dielectric material preferably has a dielectric constant less than 20. In the present invention, the dielectric layer may exhibit ferroelectric properties.

[0067] Several embodiments of the invention implementing successive steps of the manufacturing process are described below. Unless explicitly stated, the adjective "successive" does not necessarily imply, although this is generally preferred, that the steps follow each other immediately; intermediate steps may separate them.

[0068] Furthermore, the term "step" refers to the completion of a part of the process, and can designate a set of sub-steps.

[0069] Furthermore, the term "step" does not necessarily imply that the actions carried out during a step are simultaneous or immediately successive. Some actions in a first step may be followed by actions related to a different step, and other actions from the first step may be repeated later. Thus, the term "step" does not necessarily refer to unitary actions that are inseparable in time and in the sequence of phases of the process.

[0070] Selective etching, or etching with selectivity, refers to an etching process configured to remove material A or layer A from material B or layer B, where the etching speed of material A is greater than the etching speed of material B. Selectivity is the ratio of the etching speed of material A to the etching speed of material B. It is denoted SA:B. A selectivity SA:B of 10:1 means that the etching speed of material A is 10 times greater than the etching speed of material B.

[0071] The various patterns formed during the manufacturing steps typically have a structure designed to evolve throughout the process. These patterns may include sacrificial layers from the initial stack, layers based on 2D material or semiconductor oxide, and continuous or discontinuous dielectric layers. The aim of these patterns is to form, at the end of the process, "transistor patterns," each comprising at least one conduction channel and two gates surrounding said channel, a dielectric barrier separating the two gates from each other and the channel, and a source and a drain on either side of the channel. The assignment of the first and second layers in the initial stack can be reversed.

[0072] An orthonormal coordinate system, including the x, y, z axes, is shown in the attached figures.

[0073] In this patent application, the terms thickness for a layer or film and height for a device or structure will be preferred. Thickness is measured along a direction normal to the principal extension plane of the layer or film. Thus, a surface layer of silicon (topSi) typically has a thickness along the z-axis. A grid pattern formed on such a surface layer has a height along the z-axis. The relative terms "on," "overtop," "under," and "below" refer to positions along the z-axis. A "lateral" dimension corresponds to a dimension along a direction in the xy-plane. A "lateral" or "lateral" extension is understood to be an extension along one or more directions in the xy-plane.

[0074] An element located "in line with" or "directly above" another element means that these two elements are both located on the same line perpendicular to a plane in which extends mainly a lower or upper face of a substrate, that is to say on the same line oriented vertically on the cross-section figures.

[0075] The terms "approximately," "around," and "in the order of" mean within 10%, and preferably within 5%. Furthermore, the terms "between ... and ..." and equivalents mean that the limits are inclusive, unless otherwise stated.

[0076] The following description presents examples of implementing the method according to the invention in the context of developing a complex 3D device. The scope of this description is obviously not exhaustive of the invention.

[0077] THE figures 1A, 1B has 22A, 22B Figures schematically illustrate the manufacturing steps of a device comprising GAA transistors according to a first embodiment. Figures nA (n=1...22) correspond to first cross-sections, each illustrating a different step in the manufacturing process. Figures nB (n=1...22) correspond to second cross-sections, each illustrating the same step as the corresponding figure nA. This first embodiment can be described as "gate last" or "dual gate last." The first and second gates are formed at the end of the process, after the transistor channels have been formed.

[0078] As illustrated in figures 1A, 1B The first step consists of providing or fabricating a stack E of semiconductor layers 10, 20, 30 on a substrate S. The substrate S can be a SOI (Silicon On Insulator), GeOI (Germanium On Insulator), or SGOI (Silicon-Germanium On Insulator) type substrate. These known substrates comprise, according to the terminology commonly used by those skilled in the art, a thick silicon layer S1 called "Si bulk," a silicon oxide layer S2 called "BOX" (Burn Oxide), and a thin surface layer, respectively based on silicon, germanium, or silicon-germanium. This thin surface layer can advantageously correspond to the first layer 10 of the stack E.

[0079] Alternatively, substrate S can be a massive “Si bulk” substrate.

[0080] The E stacking includes, according to an example, an alternation of first layers 10 in silicon-germanium (SiGe) having a first composition in Ge, second layers 20 in silicon (Si), and third layers 30 in SiGe having a second composition in Ge.

[0081] The Ge concentrations in the SiGe alloy of the first and third layers 10, 30 are chosen to ensure good etching selectivity during the selective etching steps between the different layers. For example, the first 10 layers have a first Ge composition of between 20 at.% and 25 at. For example, the third 30 layers have a second Ge composition of approximately 50 at. This E stack is advantageously formed by epitaxy of the SiGe 10, 30 and Si 20 layers. This E stack formation step is inexpensive and well understood by those skilled in the art. The thicknesses of the Si and SiGe layers can typically be around 10 nm, and more commonly range from 5 nm to 20 nm, for example. As is known in order to avoid the formation of structural defects, the maximum thicknesses allowed for the 10, 30 SiGe layers depend in particular on the Ge concentration chosen.

[0082] In the example illustrated in figures 1A, 1B Two 10-layer SiGe structures alternate with three 20-layer epitaxial Si structures and two 30-layer SiGe structures. This creates a Si / SiGe superlattice. The number of Si and SiGe layers can naturally be increased. This allows in fine to increase the number of stacked channels in the final device. The arrangement of the first, second, and third layers 30 is preferably chosen so that each second layer 20 is sandwiched between a first layer 10 and a third layer 30. In the final device, the first layers are intended to be replaced by fingers of a first gate, and the third layers are intended to be replaced by fingers of a second gate, with the first and second gates interdigitated. The second layers are intended to form transistor channels partially surrounded by the first gate and partially surrounded by the second gate. The arrangement of the different layers 10, 20, 30 is therefore chosen according to the desired design for the final device.According to an example, the first layers 10 are only in contact with the second layers 20 and the third layers 30 are also only in contact with the second layers 20.

[0083] Generally, the first material of the first layers 10, the second material of the second layers 20, and the third material of the third layers 30 are chosen so that some can be selectively etched with respect to others. Thus, other pairs of first, second, and third materials are possible. While respecting this condition of selectivity for etching, the first, second, and third materials can be chosen from among dielectric materials (oxides and nitrides, for example), semiconductor materials, and metallic materials. Particular care must be taken to ensure that the third material can be selectively etched with respect to the first and second materials, and that the first material can be selectively etched with respect to the second material.

[0084] As illustrated in figures 2A, 2B A standard lithography / etching step is performed to define the first 101M motifs and the first 100 apertures. The etching is anisotropic and z-directed. It is configured to etch the E stack, here the Si / SiGe superlattice, along its entire height, stopping at the S substrate, here the BOX S2. It can be performed by plasma using HBr / O2 etching chemistry. The first 101M motifs can have a length L1 along x between 10 nm and 500 nm. Preferably, they have a width l1 along y between 10 nm and 120 nm, for example, on the order of 40 nm. This initial structuring of the E stack in the form of fins or "thins" according to common Anglo-Saxon terminology allows for the definition of a plurality of superimposed nanowires or nanosheets. The "end" 101M patterns are typically surmounted by an engraving mask or hard mask 130 implemented during this first structuring of the E stack.

[0085] As illustrated in figures 3A, 3B Sacrificial grids 150 are then formed between the "fin" motifs 101M. The formation of these sacrificial grids 150 is typically achieved by chemical-mechanical deposition followed by chemical polishing (CMP) with a stop on the hard mask 130. The sacrificial grids 150 typically comprise several independent portions located between the "fin" motifs 101M. This facilitates localized opening of the different portions of the sacrificial grids subsequently. The sacrificial grids 150 typically rest on the substrate S. An etching mask or hard mask 140 is formed transversely to the "fin" motifs 101M. This hard mask 140 then participates in a second structuring of the stacking E, as well as in the structuring of the sacrificial grids 150, as illustrated in the following figures. The sacrificial grids 150 are, for example, based on polycrystalline silicon.A thin layer of SiO2 oxide, for example 7 nm thick, is preferably deposited prior to the formation of the sacrificial grids 150. This thin layer of SiO2 oxide (not shown in the figures) is thus intercalated between the sacrificial grids 150 and the "finish" motifs 101M. This thin layer of SiO2 oxide can form a stop layer for the subsequent etching of the sacrificial grids 150.

[0086] As illustrated in figures 4A, 4B The hard mask 130 is first etched to expose the upper face 321 of the stack E. The portions of the hard mask 130 located beneath the hard mask 140 are retained, as is the hard mask 140 itself. Spacers 170 are then formed on the yz-oriented flanks of the hard masks 130 and 140. In general, in z-projection, these spacers form a continuous ring around the hard masks 130 and 140, with a closed contour. In cross-section, however, along the xz plane illustrated in the figure 4A The spacer 170 has two opposing parts on each side of the hard masks 130 and 140. These two parts are generally referred to as the spacers 170, although they can be considered as belonging to a single spacer. The spacers 170 typically extend to the top face 321 of the E-stack. The spacers 170 are typically based on silicon nitride (SiN) or a dielectric material with a low dielectric constant, for example, SiCO₃.

[0087] As illustrated in figures 5A, 5B After the formation of the 170 spacers by deposition / etching, the anisotropic etching along z is extended to define second 102M motifs and second 200 apertures. The etching is configured to etch the E stack over its entire height, stopping at the S substrate. It can be performed by plasma using an HBr / O2 etching chemistry. A second structuring of the E stack is thus achieved.

[0088] As illustrated in figures 6A, 6B After the formation of the second openings 200, the third layers 30 are partially etched selectively to the second layers 20, the first layers 10, the substrate S, and the spacers 170. The etching of the third material of the third layers 30 typically exhibits a selectivity S 30:20 relative to the second material of the second layers 20 of at least 5:1, preferably at least 10:1. The etching of the third material of the third layers 30 typically exhibits a selectivity S 30:10 relative to the first material of the first layers 10 of at least 5:1, preferably at least 10:1. This partial etching aims to form third spaces 31 directly above the spacers 170. This partial etching is typically time-stopped. It exhibits isotropic characteristics and can be carried out wet or dry, starting from the second openings 200.Following this partial engraving, central parts of the third layers 30 are preserved under the hard masks 130, 140.

[0089] As illustrated in figures 7A, 7B , the third spaces 31 are then filled with a dielectric material, for example with silicon nitride or a low permittivity dielectric, to form internal third spacers 131. These "internal" spacers 131 are integrated into the stack E, preferably directly above the spacers 170. They are in contact with the central parts of the third layers 30. The formation of the internal third spacers 131 typically takes place from the second openings 200.

[0090] As illustrated in figures 8A, 8B The first layers 10 are partially etched selectively to the second layers 20, the substrate S, the spacers 170, and the third internal spacers 131. The etching of the first material of the first layers 10 typically exhibits a selectivity S 10:20 relative to the second material of the second layers 20 of at least 5:1, preferably at least 10:1. This partial etching aims to form first gaps 11 directly above the spacers 170 and the third internal spacers 131. This partial etching is typically time-locked. It exhibits isotropic characteristics and can be performed wet or dry, starting from the second openings 200. Following this partial etching, central portions of the first layers 10 are preserved under the hard masks 130, 140.

[0091] As illustrated in figures 9A, 9B , the first spaces 11 are then filled with a dielectric material, for example with silicon nitride or a low permittivity dielectric, to form first internal spacers 111. These "internal" spacers 111 are integrated into the stack E, preferably directly above the spacers 170 and the third internal spacers 131. They are in contact with the central parts of the first layers 10. The formation of the first internal spacers 111 typically takes place from the second openings 200.

[0092] As illustrated in figures 10A, 10B The second layers 20 are then selectively etched at the central portions of the first layers 10 and the third layers 30, and at the internal spacers 111, 131. The etching of the second material of the second layers 20 typically exhibits a selectivity S 20:10 relative to the first material of the first layers 10, of at least 5:1, preferably at least 10:1. The etching of the second material of the second layers 20 typically exhibits a selectivity S 20:30 relative to the third material of the third layers 30, of at least 5:1, preferably at least 10:1. This complete etching can be stopped at a specific time, possibly after an over-etching time intended to ensure the complete removal of the second material from the second layers 20. This complete etching exhibits isotropic characteristics and can be carried out wet or dry, starting from the second openings 200.Following this engraving, the second layers 20 are completely removed to form second spaces 21. The central parts of the first layers 10 and the central parts of the third layers 30 are held in place by the sacrificial grids 150, as illustrated in the . figure 10B .

[0093] As illustrated in figures 11A, 11B A dielectric layer 70 is then deposited in the second spaces 21. This dielectric layer 70 is typically based on a high-permittivity material, for example, HfO2-based. The dielectric layer 70 is intended to form the gate dielectric layer between the channels of the GAA transistors and their surrounding gates. It can be formed by CVD (Chemical Vapor Deposition), MOCVD (Metal Organic Chemical Vapor Deposition) with organometallic precursors, or ALD (Atomic Layer Deposition). It thus covers at least the central parts of the first layers 10 and the central parts of the third layers 30, and preferably the internal spacers 111, 131, and the spacers 170. The dielectric layer 70 typically has a thickness between 1 nm and 5 nm.As an alternative example, this layer 70 can be based on a ferroelectric material such as HfZrO2, HZO, or Si-doped HfO2. Such a ferroelectric layer 70 can be advantageously used for the fabrication of FeFET (ferroelectric field-effect transistor) type memory transistors. This dielectric layer 70 typically forms a Venetian mesh pattern in each 102M motif.

[0094] As illustrated in figures 12A, 12B A layer 40 made of a semiconductor material is then deposited onto the gate dielectric layer 70 in the second spaces 21. The semiconductor material is deposited in such a way that the layer 40 completely fills the second spaces 21. The portions of the layer 40 located in the second spaces 21 thus have a perfectly controlled thickness, close to the thickness of the initial second layers. This layer 40 is intended to form the channels 41 of the GAA transistors directly above the central parts of the first layers 10 and the central parts of the third layers 30. This layer 40 is also intended to form the sources 42 and the drains 43 of the GAA transistors directly above the spacers 170 and the internal spacers 111, 131.

[0095] Layer 40 is also typically deposited outside the second spaces 21, on the flanks of the spacers 170 and the internal spacers 111, 131. This improves the re-establishment of contact with the sources 42 and drains 43 of the GAA transistors. Layer 40 thus has horizontal portions in the second spaces 21, particularly between the remaining portions of the first and third layers, and vertical portions on the flanks of the spacers 170 and the internal spacers 111, 131. In one possibility, the thickness of the vertical portions of layer 40 is greater than the thickness of the horizontal portions of layer 40. This reduces the contact resistance for the sources 42 and drains 43 of the GAA transistors.The sources 42 and drains 43 of the GAA transistors may include the horizontal portions directly above the spacers 170 and the internal spacers 111, 131, and at least partly the vertical portions on the sides of the spacers 170 and the internal spacers 111, 131.

[0096] The semiconductor material for layer 40 is advantageously a two-dimensional material chosen from among the MX2 transition metal dichalcogenides, with M being molybdenum (Mo) or tungsten (W), and X being sulfur (S), selenium (Se), or tellurium (Te). Such a 2D material can advantageously be deposited as a thin film comprising 1 to 10 atomic layers, preferably 1 to 5 atomic layers. The deposition of this 2D material can be carried out by CVD, MOCVD, or ALD. Alternatively, the semiconductor material for layer 40 is a semiconductor oxide such as ITO (Indium Tin Oxide), IGZO (Indium Gallium Zinc Oxide), IWO (Tungsten-doped Indium Oxide), or indium oxide (In₂O₃).According to another possibility, the semiconductor material of layer 40 is graphene, hexagonal boron nitride "h-BN", phosphorene (also known as "Black Phosphorous" BP), in monolayer or thin film form comprising 1 to 10 atomic layers, preferably 1 to 5 atomic layers.

[0097] As illustrated in figures 13A, 13B The second openings can then be filled with one or more metallic layers 60, for example based on Ti, TiN, W, or other metals providing low contact resistance such as Bi, Ni, Au, Sb, etc., to form the source and drain contacts. A chemical-mechanical polishing (CMP) process is typically performed to remove excess metal deposited on the patterns 102M. The hard masks 140 are thus exposed.

[0098] As illustrated in figures 14A, 14B Protective plugs 61, for example based on SiO2, are preferably formed at the upper ends of the contacts 60. This allows the underlying metal layers to be protected during the subsequent steps of replacing the different portions of sacrificial grid.

[0099] As illustrated in figures 15A, 15B The hard mask 140 is partially open to access certain portions of the sacrificial grid 150 via the openings 300a. The different portions of the sacrificial grid 150 are separated by the "end" patterns. In particular, the openings 300a are configured to access every other portion of the sacrificial grid 150, in an alternating fashion.

[0100] As illustrated in figures 16A, 16B The exposed portions of the sacrificial grid 150 are then removed to form the third openings 300b. This removal can be carried out by wet etching with a stop on the thin SiO2-based stop layer of the sacrificial grid 150. This wet etching typically exhibits high selectivity with respect to the stop layer. This wet etching can be based on a solution of TMAH (tetramethylammonium hydroxide) or TEAH (tetraethylammonium hydroxide) ammonia salts. The SiO2-based stop layer is then typically wet etched to expose one flank of the "end" patterns. The third openings 300b lead to the central parts of the third layers 30 ( figure 16B ).

[0101] As illustrated in figures 17A, 17B The central portions of the third layers 30 are then completely removed by selective etching with respect to the dielectric layer 70 and the central portions of the first layers 10, starting from the third openings 300b. This etching aims to form third cavities 32 in place of the central portions of the third layers 30. This etching is isotropic and can be carried out by wet or dry method, starting from the third openings 300b.

[0102] As illustrated in figures 18A, 18B The third openings 300b and the third cavities 32 are then filled with one or more metallic layers, for example, TiN-based, to form the first gate G1 of the GAA transistors. Before the metallic layers are deposited, a dielectric layer 71 based on a high-permittivity material, for example, HfO2-based, is first deposited to line the third openings 300b and the third cavities 32. This increases the thickness of the gate dielectric layer between the channels 41a, 41b, and 41c of the GAA transistors and the first gate G1. It also isolates the first gate G1 from the central parts of the first layers 10, which are intended to form a second gate section. Chemical-mechanical polishing (CMP) is typically performed to remove excess metal deposited on the patterns 102M.

[0103] As illustrated in figures 19A, 19B , the hard mask 140 is again partially opened to access the remaining portions of the sacrificial grid 150, via openings 400a.

[0104] As illustrated in figures 20A, 20B The remaining portions of the sacrificial grid 150 are then removed to form the fourth 400b openings. This removal can be carried out as before, by wet etching with TMAH or TEAH, stopping on the thin SiO2-based stop layer of the sacrificial grid 150. The SiO2-based stop layer is then typically wet etched to expose a second flank of the "end" patterns. The fourth 400b openings lead to the central parts of the first 10 layers ( figure 20B ).

[0105] As illustrated in figures 21A, 21B The central parts of the first layers 10 are then completely removed by selective etching with respect to the dielectric layers 70, 71, starting from the fourth openings 400b. This etching aims to form first cavities 12 in place of the central parts of the first layers 10. This etching is isotropic and can be carried out by wet or dry method, starting from the fourth openings 400b.

[0106] As illustrated in figures 22A, 22B The fourth openings 400b and the first cavities 12 are then filled with one or more metallic layers, for example, TiN-based, to form a second gate G2 of the GAA transistors. Before deposition of the metallic layers, a dielectric layer 72 based on a high-permittivity material, for example, HfO2-based, is first deposited to line the fourth openings 400b and the first cavities 12. This increases the thickness of the gate dielectric layer between the channels 41a, 41b, 41c of the GAA transistors and the second gate G2. It also isolates the second gate G2 from the first gate G1. Chemical-mechanical polishing (CMP) is typically performed to remove excess metal deposited on the motifs 102M.

[0107] A microelectronic device comprising two transistors T1, T2, each with three channels 41a, 41b, 41c stacked along the z-axis, and two interdigitated encapsulating gates G1, G2, is thus advantageously obtained. The channels 41a, 41b, 41c, the sources 42, and the drains 43 are preferably made of a two-dimensional material. Source and drain contacts 60S, 60, 60D electrically connect these transistors GAA T1, T2.

[0108] THE figures 23A, 23B has 34A, 34B Figures schematically illustrate the manufacturing steps of a device comprising GAA transistors according to a second embodiment. Figures nA (n=23...34) correspond to first cross-sections, each illustrating a different step in the manufacturing process. Figures nB (n=23...34) correspond to second cross-sections, each illustrating the same step as the corresponding figure nA.

[0109] Only the characteristics that differ from the first embodiment of this second embodiment are described below. The other characteristics are assumed to be identical to those of the first embodiment, with reference to the foregoing. This second embodiment can notably be described as "channel last." The transistor channels are formed here after replacing the sacrificial gate portions with the first and second gates.

[0110] As illustrated in figures 23A, 23B After the formation of the internal spacers 111, 131, the second openings are filled with a dielectric material 27, for example based on SiO2. The hard mask 140 is partially opened to access certain portions of the sacrificial grid 150 via the openings 300a, as before.

[0111] As illustrated in figures 24A, 24B The exposed portions of the sacrificial grid 150 are removed to form the third openings 300b, as before. The third openings 300b lead to the central parts of the third layers 30.

[0112] As illustrated in figures 25A, 25B The central portions of the third layers 30 are then completely removed by selective etching with respect to the second layers 20 and the central portions of the first layers 10, starting from the third openings 300b. This etching aims to form third cavities 32 in place of the central portions of the third layers 30. This etching is isotropic and can be carried out wet or dry, starting from the third openings 300b.

[0113] As illustrated in figures 26A, 26B The third openings 300b and the third cavities 32 are then filled with one or more metallic layers, for example, TiN-based, to form the first gate G1 of the GAA transistors. Before the metallic layers are deposited, a dielectric layer 71 based on a high-permittivity material, for example, HfO2-based, is first deposited to line the third openings 300b and the third cavities 32. This forms the dielectric gate layer between the second layers 20, which subsequently form the channels of the GAA transistors, and the first gate G1. This also isolates the first gate G1 from the first layers 10, which subsequently form the fingers of the second gate G2, as before.

[0114] As illustrated in figures 27A, 27B The hard mask 140 is again partially opened to access the remaining portions of the sacrificial grid 150, and the remaining portions of the sacrificial grid 150 are removed to form the fourth openings 400b, as before. The fourth openings 400b lead to the central parts of the first layers 10.

[0115] As illustrated in figures 28A, 28B The central parts of the first layers 10 are then completely removed by selective etching with respect to the dielectric layer 71 and the second layers 20, starting from the fourth openings 400b. This etching aims to form the first cavities 12 in place of the central parts of the first layers 10.

[0116] As illustrated in figures 29A, 29B The fourth openings 400b and the first cavities 12 are then filled with one or more metallic layers, for example, TiN-based, to form a second gate G2 of the GAA transistors. Before the metallic layers are deposited, a dielectric layer 72 based on a high-permittivity material, for example, HfO2-based, is first deposited to line the fourth openings 400b and the first cavities 12. This forms the dielectric gate layer between the second layers 20, which subsequently form the channels of the GAA transistors, and the second gate G2. This also isolates the second gate G2 from the first gate G1, as before.

[0117] As illustrated in figures 30A, 30B The dielectric material 27 is removed so as to reform the second openings 200b. The second openings 200b lead to the second layers 20.

[0118] As illustrated in figures 31A, 31B The second layers 20 are then selectively etched with respect to the dielectric layers 71, 72, starting from the second openings 200b. This complete etching can be stopped at a specific time, possibly after an over-etching period to ensure the complete removal of the second material from the second layers 20. This complete etching is isotropic and can be carried out wet or dry, starting from the second openings 200b. Following this etching, the second layers 20 are completely removed to form second spaces 21, as before.

[0119] As illustrated in figures 32A, 32B Optionally, a dielectric layer 73 is then deposited in the second set of spaces 21. This dielectric layer 73 is typically based on a high-permittivity material, for example, HfO2-based. The dielectric layer 73 can be formed by chemical vapor deposition (CVD) or metal-on-metal vapor deposition (MOCVD), or by atomic layer deposition (ALD). The dielectric layer 73 typically has a thickness between 1 nm and 5 nm. The dielectric layer 73 typically increases the thickness of the gate dielectric layers formed by the dielectric layers 71 and 72.

[0120] As illustrated in figures 33A, 33B The semiconductor-based layer 40 is then deposited onto the dielectric layer 73 in the second spaces 21. The semiconductor material deposition is configured here so that layer 40 completely fills the second spaces 21, as before. This layer 40 is intended to form the channels 41 of the GAA transistors directly above the central portions of the first layers 10 and the gate fingers G1, G2. This layer 40 is also intended to form the sources 42 and drains 43 of the GAA transistors directly above the spacers 170 and the internal spacers 111, 131, as before.

[0121] The semiconductor material of layer 40 is advantageously a 2D material or a semiconductor oxide, as before.

[0122] As illustrated in figures 34A, 34BThe second openings can then be filled with one or more metallic layers 60 to form the source and drain contacts, as before. A chemical-mechanical polishing (CMP) process is typically performed to remove excess metal deposited on the 102M patterns.

[0123] A microelectronic device comprising two transistors T1, T2, each with three channels 41a, 41b, 41c stacked along the z-axis, and two interdigitated encapsulating gates G1, G2, is thus advantageously obtained, as before. This second "channel last" embodiment makes it possible to limit the number of technological steps to which the transistor channels are exposed during device fabrication. The properties of the material forming the transistor channels are thus preserved.

[0124] In light of the preceding description, it is clear that the proposed device and method offer a particularly efficient solution for forming GAA transistors with adjustable threshold voltage. This solution is also advantageously compatible with standard microelectronic processes. However, the invention is not limited to the embodiments described above.

[0125] According to an unillustrated possibility, the semiconductor-based layer 40 does not completely fill the second spaces 21. In this case, the portions of layer 40 located in the second spaces 21 can be significantly thinner than the initial second layers. These horizontal portions can have a thickness corresponding to only a few atomic layers, for example, between 1 and 5 atomic layers of semiconductor material. This allows for a reduction in the dimensions of the channels 41 of the GAA transistors. The performance of the GAA transistors can be improved. A dielectric plug is typically formed between the horizontal portions of layer 40 to fill the second spaces 21. This notably allows operation with a single monolayer of 2D material. Excellent electrostatic control of the device is thus achieved. The gate length can therefore be advantageously reduced.This also improves the device's mechanical strength and / or prevents deformation of the GAA transistor channels, for example, due to overheating during operation. This dielectric plug can be formed by CVD deposition and etching, using conventional methods.

Claims

1. Microelectronic device comprising at least one transistor (T1, T2) comprising: • at least two channels (41a, 41b, 41c) stacked along a main direction (z), each channel being with the basis of a semiconductive material, • a gate (G1, G2) surrounding at least one of the channels (41a, 41b, 41c), • a source (42) and a drain (43) either side of the channels (41a, 41b, 41c), and source and drain contacts (60S, 60, 60D) connected respectively to the source (42) and to the drain (43), • a gate dielectric layer (70, 71, 72) separating each channel (41) of the gate (G1), wherein the gate (G1) corresponds to a first gate (G1) partially surrounding at least one of the channels (41a, 41b, 41c), and in that the at least one transistor (T1, T2) comprises a second gate (G2) partially surrounding the same channel as that surrounded by the first gate (G1), the first and second gates (G1, G2) being electrically isolated from one another, such that they can be biased independently of one another, the first gate (G1) and the second gate (G2) being interdigitated, and each channel (41a, 41b, 41c) being inserted between a finger of the first gate (G1) and a finger of the second gate (G2), the device characterised in that the first gate (G1) covers two adjacent sides of one of the channels (41a, 41b, 41c), and the second gate (G2) covers two other adjacent sides of said channel (41a, 41b, 41c).

2. Device according to the preceding claim, wherein each channel (41a, 41b, 41c) is partially surrounded by the first gate (G1) and is partially surrounded by the second gate (G2).

3. Method for manufacturing a microelectronic device according to any one of the preceding claims, said method comprising the following steps: • Providing, on a substrate (S), a stack (E) along the main direction (z) comprising a plurality of first layers (10) made of a first material, alternated with a plurality of second layers (20) made of a second material, alternated with a plurality of third layers (30) made of a third material, the first, second and third materials being different, • Forming a first etching mask (130) on this stack (E), • Forming, in this stack (E), first openings (100) defining first patterns (101M) in vertical alignment with the first etching mask (130), • Forming a sacrificial gate (150) either side of the first patterns (101M), in the first openings (100), • Forming a second etching mask (140) on the first etching mask (130) and on the sacrificial gate (150), the second etching mask (140) being transverse to the first etching mask (130), • Forming, in the first patterns (101M), second openings (200) defining second patterns (102M) in vertical alignment with the second etching mask (140), • Partially removing, from the second openings (200), the third material of the third layers (30) selectively at the first and second material of the first and second layers (10, 20), so as to form third spaces (31) in the third layers (30), • Filling the third spaces (31) with a third dielectric material to form third internal spacers (131), • Partially removing, from the second openings (200), the first material of the first layers (30) selectively at the second material of the second layers (20) and at the third internal spacers (131), so as to form first spaces (11) in the first layers (10), preferably in vertical alignment with the third internal spacers (131), • Filling the first spaces (11) with a first dielectric material to form first internal spacers (111), • Partially removing the sacrificial gate (150) so as to form third openings (300b) opening onto the remaining parts of the third layers (30), • Totally removing, from the third openings (300b), the third material of the remaining parts of the third layers (30), so as to form third cavities (32), • Forming a first dielectric layer (71) in the third cavities (32), • Filling the third cavities (32) and the third openings (300b) with a first metal material, so as to form the first gate (G1) partially surrounding the second layers (20), • Totally removing a remaining part of the sacrificial gate (150), so as to form fourth openings (400b) opening onto the remaining parts of the first layers (10), • Totally removing, from the fourth openings (400b), the first material of the remaining parts of the first layers (10), so as to form first cavities (12), • Forming a second dielectric layer (72) in the first cavities (12), • Filling the first cavities (12) and the fourth openings (400b) with a second metal material, so as to form the second gate (G2) partially surrounding the second layers (20), • Filling the second openings (200, 200b) with an electrically conductive material, so as to form source and drain contacts in contact with the second layers (20).

4. Method according to the preceding claim, further comprising a sequence of steps configured to replace the second layers (20), said sequence comprising the following steps: • Totally removing, from the second openings (200, 200b), the second material of the second layers (20), so as to form second spaces (21), • Preferably forming a dielectric layer (70, 73) in the second spaces (21), • Depositing a layer (40) with the basis of a semiconductive material in the second spaces (21), so as to form: ∘ channels (41a, 41b, 41c) with the basis of the semiconductive material in vertical alignment with the first and second gates (G1, G2), under the first and second etching masks (130, 140), and ∘ sources (42) and drains (43) with the basis of the semiconductive material in vertical alignment with the first and third internal spacers (111, 131).

5. Method according to the preceding claim, wherein the sequence of steps configured to replace the second layers (20) is carried out after formation of the first and third internal spacers (111, 131), and wherein the formation of the source and drain contacts (60, 60S, 60D) is done after said sequence of steps and before the partial removal of the sacrificial gate (150).

6. Method according to claim 4, wherein the sequence of steps configured to replace the second layers (20) is carried out after formation of the first and second gates (G1, G2) and before formation of the source and drain contacts (60, 60S, 60D).

7. Method according to any one of claims 3 to 6 further comprising a formation of spacers (170) on the flanks of the first and second etching masks (130, 140), said spacers (170) bearing on an upper face (321) of the first patterns (101M).

8. Method according to any one of claims 4 to 7, wherein the semiconductive material is a two-dimensional (2D) material chosen from among MX2 transition metal chalcogenides, with M taken from among molybdenum (Mo) or tungsten (W), and X taken from among sulphur (S), selenium (Se) or tellurium (Te).

9. Method according to any one of claims 3 to 8, wherein the first layers (10) of the stack (E) are only in contact with the second layers (20), and wherein the third layers (30) of the stack (E) are only in contact with the second layers (20).

10. Method according to any one of claims 4 to 9, wherein the deposition of the layer (40) with the basis of the semiconductive material is configured, such that the layer (40) with the basis of the semiconductive material totally fills the second spaces (21).

11. Method according to any one of claims 4 to 9, wherein the deposition of the layer (40) with the basis of the semiconductive material is configured, such that the layer (40) with the basis of the semiconductive material partially fills the second spaces (21), said method further comprising, after deposition of the layer (40) with the basis of the semiconductive material, a deposition of an additional dielectric layer, configured to fill the second spaces (21).

12. Method according to any one of claims 3 to 11, wherein the first openings (100) are formed along a longitudinal direction (x) and the second openings (200) are formed along a transverse direction (y) perpendicular to the longitudinal direction (x), said first and second openings (100, 200) extending to the substrate (S).

13. Method according to any one of claims 4 to 12, wherein the deposition of the layer (40) with the basis of the semiconductive material does not totally fill the second spaces (21), such that two layer horizontal portions (40) with the basis of the semiconductive material are formed in each second space (21), and wherein a dielectric stopper (80) is formed between said two horizontal portions in each second space (21), in order to fill each second space (21).