Logic device and logic computation architecture

Abstract

The present invention relates to a logic device (10) comprising: - a first and a second arm (12) through which a charging current passes; - a channel (16) that connects the arms (12, 14) and comprises a first zone of contact with the first arm (12) and a second zone of contact with the second arm (14), the arms (12, 14) and the channel (16) being able, in the first zone of contact, to convert a charging current into a spin current and, in the second zone of contact, to convert a spin current into a charging current; and - a unit (20) for controlling the direction of the charging current in the second arm (14), the control unit (20) comprising a sub-unit (22) for electrical control of a conversion.

Description

[0001] Logical device and logical computing architecture

[0002] The present invention relates to a logic device and a logic computing architecture.

[0003] The present invention lies in the field of computational architectures and Boolean logic.

[0004] To perform binary information processing, it is beneficial for logic devices to have an output that is either positive or negative. Since the output is usually a current, this property can be termed "bidirectionality," so such a logic device can be termed a bidirectional logic device.

[0005] Binary information processing is currently performed by CMOS components whose output voltage level, low or high, corresponds to a 0 or a 1. The abbreviation CMOS refers to the name "Complementary Metal Oxide Semiconductor" which literally means complementary metal oxide semiconductor. However, according to the terminology introduced previously, these components can be described as "unidirectional" because, since these components only operate with positive voltages, the current always flows in the same direction.

[0006] There is therefore an interest in bidirectional logic devices allowing in particular a concatenation of several devices

[0007] For this purpose, the description describes a logic device comprising:

[0008] - a first arm, the first arm extending in a first direction, the first arm being capable of carrying a charging current,

[0009] - a second arm, the second arm extending in the first direction, the second arm also being capable of carrying a charging current,

[0010] - a channel connecting the first arm to the second arm, the channel being in a second direction, the second direction being perpendicular to the first direction, the channel comprising three zones, a first contact zone with the first arm, a second contact zone with the second arm and a central zone connecting the two contact zones, the first arm, the second arm and the channel being capable of carrying out a first conversion in the first contact zone and a second conversion in the second contact zone, the first conversion being the conversion of a charge current flowing in the first arm into a spin current flowing in the channel, and the second conversion being the conversion of a spin current flowing in the channel into a charge current flowing in the second arm, and

[0011] - a control unit for directing the charging current flowing in the second arm, the control unit comprising at least one electrical control sub-unit for one of the two conversions.

[0012] In this context, a channel has a dimension in the first direction which is less than the dimension of the arms in the first direction.

[0013] Similarly, the channel has a substantially elongated shape in the second direction, such that the dimension of the channel in the second direction is generally greater than the dimension of the arms in the second direction.

[0014] This implies that the channel and the two arms make it possible to define a substantially planar structure and not a stack of layers.

[0015] This allows for a different concatenation than is possible with unidirectional devices such as CMOS components.

[0016] In addition, such a device makes it possible to reduce the power consumption of computing architectures compared to those based on CMOS components, by introducing new computing paradigms and ferroic elements conferring a non-volatile character.

[0017] According to particular embodiments, the logic device has one or more of the following characteristics, taken in isolation or in all technically possible combinations:

[0018] - a control subunit is a control subunit of the first conversion and is capable of controlling the direction of the charge current flowing in the second arm by controlling the direction of the spins of the spin current by electrical control of the first conversion.

[0019] - the first conversion control subunit comprises a voltage source and an electrical contact, the electrical contact being in contact with the first contact area, the voltage source controlling the potential of the electrical contact.

[0020] - a control subunit is a control subunit of the second conversion and is capable of controlling the direction of the charging current by electrical control of the second conversion.

[0021] - the second conversion control subunit comprises a voltage source and an electrical contact, the electrical contact being in contact with the second contact area, the voltage source controlling the potential of the electrical contact. - the electrical contact is a multilayer formed at least of an insulating layer and a metal layer, the insulating layer resting on the arm and the channel and preferably being made of a ferroelectric material, the ferroelectric material being advantageously chosen from the list consisting of BaTiOs, Pb(Zr,Ti)C>3, BiFeOs, (Hf,Zr)C>2, and poly(vinylidene fluoride).

[0022] - the electrical contact rests on the channel part and the arm part.

[0023] - the arms and the channel form an H.

[0024] - the arms and the channel are made of the same material.

[0025] - the arms are made of a first material, the contact zones being made of a second material and the channel being made of a third material distinct from the first material and the second material.

[0026] - each material is chosen from:

[0027] - an oxide, in particular SrTiOs or KTaOs,

[0028] - a III-V semiconductor material, preferably InAs or InSb,

[0029] - an II-VI semiconductor material, preferably HgTe or CdTe,

[0030] - transition metal dichalcogenides, preferably WS2, WSe2, PtSe2, MoTe2 or MoSe2, and

[0031] - topological insulators, preferably (Bi,Sb)2(Se,Te)s.

[0032] - the logic device is capable of performing a logic operation on two logic inputs to obtain a logic output, the state of the logic output being the direction of the current flowing in the second arm, the logic state of a first input being the value of a potential applied to a control sub-unit and the logic state of a second input being the direction of the current flowing in the first arm or the logic state of a first input being the value of a current applied to a control sub-unit and the logic state of a second input being the value of another current applied to a control sub-unit, or the logic state of a first input being the value of the potential applied to the control sub-unit of the first conversion and the logic state of a second input being the value of the potential applied to the control sub-unit of the second conversion.

[0033] The description also relates to a logical computing architecture comprising at least two logical devices as previously described, the logical computing architecture verifying at least one of the following properties:

[0034] - a first property according to which the first arm of one of the two logic devices is merged with the second arm of the other logic device, and - a second property according to which the second arm of one of the two logic devices is connected with an electrical control sub-unit of one of the two conversions.

[0035] Characteristics and advantages of the invention will appear on reading the description which follows, given solely by way of non-limiting example, and made with reference to the appended drawings, in which:

[0036] - Figure 1 is a schematic representation of an example of a logic device with the current directions indicated for two distinct cases (respectively on the left and on the right),

[0037] - Figure 2 is a graph showing the evolution of the resistance variation as a function of the angle formed by the field with respect to the current in the case of two-dimensional gases of SrTiO3,

[0038] - figure 3 is a schematic representation of the different cases corresponding to the different possible values ​​when the logic device of figure 1 performs an XNOR function,

[0039] - Figure 4 is a schematic representation of the different cases corresponding to the different possible values ​​when another logic device performs an XNOR function,

[0040] - Figure 5 is a schematic representation of the different cases corresponding to the different possible values ​​when another logic device performs a NOR function, and

[0041] - Figure 6 is a representation of an example of a logical architecture comprising several concatenated logical devices.

[0042] A logic device 10 is illustrated in Figure 1 for two distinct cases.

[0043] The logic device 10 is capable of performing a logic operation on two logic inputs to obtain a logic output, the logic output then being the result of the logic operation applied to the two logic inputs.

[0044] The logic device 10 comprises a first arm 12, a second arm 14 and a channel 16 connecting the first arm 12 to the second arm 14.

[0045] The first arm 12 extends in a first direction X. The first arm 12 is suitable for carrying a charging current denoted J B1 . This charging current J B1 is indicated in the two cases shown in Figure 1, each case corresponding to an identical direction of flow of the load current.

[0046] By convention, here, when a load current moves in the X direction upwards in Figure 1, the load current is positive (we will adopt the notation according to +X in the following) whereas when a load current moves downwards in Figure 1, the load current is negative (we will adopt the notation according to -X in the following).

[0047] The second arm 14 extends in the first direction X and is therefore parallel to the first arm 12.

[0048] The second arm 14 is also suitable for carrying a charging current denoted J B2This charging current is indicated in the two cases shown in Figure 1, each case corresponding to a direction of flow of the charging current (according to -X or +X).

[0049] Channel 16 is in a second Y direction, the second Y direction being perpendicular to the first X direction.

[0050] The channel 16 has three zones, a first contact zone with the first arm 12, a second contact zone with the second arm 14 and a central zone connecting the two contact zones.

[0051] Since the arms of Figure 1 have the same extent along the second direction Y, the arms and channel 16 form an H.

[0052] However, it is possible that the arms do not have the same extent along the second Y direction as seen in particular in figure 6.

[0053] The first arm 12 and channel 16 are suitable for carrying out a first conversion.

[0054] The first conversion is the conversion of a charging current J B1 circulating in the first arm 12 in a spin current noted J s circulating in channel 16.

[0055] The first conversion is therefore a charge-spin conversion at the intersection between the first arm 12 and the channel 16, i.e. in the first contact zone.

[0056] The generated spin current is shown for each case and has the same direction. However, as will be detailed later, the direction of the spins is opposite in both cases.

[0057] The second arm 14 and the channel 16 are suitable for carrying out a second conversion.

[0058] The second conversion is the conversion of a spin current Js flowing in channel 16 into a charge current J B2circulating in the second arm 14. The second conversion is therefore a spin-charge conversion at the intersection between the channel 16 and the second arm 14, i.e. in the second contact zone.

[0059] To achieve these two conversions, channel 16 has sufficient spin diffusion length.

[0060] Typically, a length between 10 nanometers and 10 microns (pm) is a sufficient spin diffusion length.

[0061] As regards the materials, several cases can be considered. According to a first example, arms 12 and 14 and channel 16 are made of the same material.

[0062] According to another example, the arms 12 and 14 are made of a first material, the contact zones are made of the first material and the central zone is made of a second material distinct from the first material.

[0063] The advantage of such an example is that it becomes possible to separately optimize the conversion efficiency and the spin diffusion length, at the cost of optimizing the interfaces between the two materials involved and in particular their transparency to spin currents.

[0064] Each of the above-mentioned materials are advantageously chosen from the following list:

[0065] - an oxide, in particular SrTiOs or KTaOs,

[0066] - a III-V semiconductor material, preferably InAs or InSb,

[0067] - an II-VI semiconductor material, preferably HgTe or CdTe,

[0068] - transition metal dichalcogenides, preferably WS2, WSe2, PtSe2, MoTe2 or MoSe2, optionally combined with a layer of graphene or other two-dimensional material.

[0069] - topological insulators, preferably (Bi,Sb)2(Se,Te)s or (Bi,Sb).

[0070] In this list, two-dimensional electron gases based on oxides such as SrTiOs or KTaOs, or based on III-V semiconductors such as InAs or InSb are particularly interesting examples.

[0071] The logic device 10 further comprises a control unit 20 for directing the load current flowing in the second arm 14.

[0072] The control unit 20 comprises an electrical control sub-unit of the first conversion 22.

[0073] The control subunit 22 is capable of controlling the direction of the charging current flowing in the second arm 14 by controlling the direction of the spins of the spin current by electrical control of the first conversion.

[0074] For this, according to the example of figure 1, the control sub-unit 22 comprises a voltage source not shown and an electrical contact 24.

[0075] Contact 24 is in contact with the first contact area and the voltage source controls the potential of contact 24.

[0076] The contact 24 is a multilayer formed at least of an insulating layer and a metal layer, the insulating layer resting on the arm 12, and more precisely the first contact zone. It is possible to envisage that the insulating material forming the insulating layer is a simple dielectric material or a ferroelectric material, which provides a non-volatile character to the operation of the device.

[0077] When the insulating material is a ferroelectric material, the contact 24 may be referred to as a ferroelectric contact. The ferroelectric material may advantageously be selected from the list consisting of BaTiOs, Pb(Zr,Ti)Os, BiFeOs, (Hf,Zr)O2, and poly(vinylidene fluoride) (also referred to by the acronym PVDF).

[0078] The control subunit 22 is thus an electrostatic or ferroelectric grid positioned at the intersection between the first arm 12 and the channel 16.

[0079] It is now explained how the control subunit 22 allows to control the direction of the spins of the spin current by an electrical control of the first conversion.

[0080] As seen in Figure 1, the logic device 10 comprises a basic structure which is here an H-shaped Hall bar.

[0081] When applying a load current J B1 in the input arm, the spin-orbit coupling induces the conversion (partial or total) of the charge current into a transverse spin current Js which will circulate in channel 16. The conversion mechanism can typically be of the spin Hall effect type or of the Edelstein effect type.

[0082] Depending on the case, the orientation of the spins in channel 16 can vary (usually the spins are perpendicular to the plane of the layer in the case of the spin Hall effect and in the plane and parallel to Js in the case of the Edelstein effect), but in both cases, a spin current Js flows in channel 16. Arriving at the intersection with the output arm, the spin current Js is reconverted into a charge current by the inverse spin Hall effect or by the inverse Edelstein effect.

[0083] Taking as an example the case of the direct and inverse Edelstein effects, the direction of the (planar) spins carried by J s in channel 16 depends on the sign of the charge current in the first arm 12. The conversion of the spin current into charge current at the second arm 14 depends on the direction of these spins, the output current changing sign with the sign of the current in the first arm 12.

[0084] For a given sign of the current in the first arm 12, the direction of the spins generated in the channel 16 depends on the sign of the conversion coefficient, i.e. the Hall spin angle 0 SHE in the case of the spin Hall effect, or the Edelstein length A IEE in the case of the inverse Edelstein effect. Generally, the magnitude and sign of this conversion coefficient are fixed by the electronic structure and are therefore specific to each material. For example, Pt has a Hall spin angle of 0 SHE positive and Ta a Hall spin angle 0 SHEnegative. The applicant has been able to show that the amplitude and sign of the conversion coefficient can be modified by applying a gate voltage. This leads to an accumulation or depletion of the number of carriers and to a variation in the position of the Fermi level in the band structure. The Fermi level can thus be positioned as desired at bands of different orbital characters, having conversion properties of one sign or another.

[0085] Figure 2 presents magnetotransport results illustrating the modulation of the amplitude and sign of charge-spin conversion by the Edelstein effect in two-dimensional SrTiOs gases.

[0086] In such a case, the application of a charging current generates via the Edelstein effect a transverse spin density which leads to the observation of a unidirectional magnetoresistance effect: the resistance under a magnetic field applied transversely to the current is different depending on whether this transverse field is parallel or antiparallel to the spin density generated by the Edelstein effect.

[0087] If the resistance is measured as a function of the angle formed by the field with respect to the current, we obtain a sinusoidal dependence, with extrema at 90 and 270 degrees corresponding to the two directions of the transverse field with respect to the current.

[0088] As shown in Figure 2, the sign of the dependence changes when applying a gate voltage by using a back gate.

[0089] This sign change reflects the sign change of the charge-spin conversion coefficient.

[0090] This effect makes possible control of spin-charge and / or charge-spin conversion by electrostatic or ferroelectric grids.

[0091] Applying a gate voltage VG leads to a change in the charge-spin conversion coefficient. As a result, without changing the input current, the direction of the spins in channel 16 is changed, and the output current changes sign.

[0092] It is this principle that allows the control subunit of the first conversion 22 to operate.

[0093] As the control is very simple, this allows us to consider very low energy consumption to carry out any type of logic functions as will be shown by describing figures 3 to 5.

[0094] Furthermore, the operation becomes bidirectional so that concatenation of logical devices 10 is possible as will be illustrated in Figure 6.

[0095] With such a control subunit, the logic device 10 can, for example, be used to realize an XNOR logic gate. The XNOR function is the logical complement of the Exclusive OR gate as is schematically represented in Figure 3 which shows the different cases I to IV.

[0096] In this example, the two logic inputs are on the one hand the direction of the load current in the first arm 12 and on the other hand the voltage VG applied to the contact. The logic output is the direction of the load current in the second arm 14.

[0097] This corresponds to the following logical table.

[0098] [Table 1]

[0099] In the configuration just described, the first arm 12 is an input arm and the second arm 14 is an output arm.

[0100] Referring to Figure 4, another example of logic device 10 is provided.

[0101] In addition to the elements of the logic device 10 of FIG. 1, the logic device 10 comprises a sub-unit for controlling the second conversion 26 (more simply second sub-unit control 26 in the following)

[0102] The second control subunit 26 is capable of controlling the direction of the charging current by electrical control of the second conversion.

[0103] Structurally, the second control subunit 26 is similar to the first control subunit (the first conversion control subunit) except that the contact is positioned on the other intersection (that of channel 16 and second arm 14).

[0104] This allows an XNOR function to be implemented in a different way.

[0105] In such a case, the two logic inputs are on the one hand the voltage GI applied to the contact of the first control sub-unit 22 and on the other hand the voltage G2 applied to the contact of the second control sub-unit 26 and the logic output is the direction of the load current in the second arm 14.

[0106] This corresponds to the following logical table:

[0107] [Table 2]

[0108] Referring to Figure 5, another example of logic device 10 is provided.

[0109] In this example, instead of having a single voltage source, the first conversion control subunit 22 has two separate current sources connected to the contact.

[0110] There is no second control subunit in this example.

[0111] In this case, the two logic inputs are on the one hand the current IGI applied to the contact and on the other hand the current IG2 applied to the same contact. The output is the direction of the load current in the second arm 14. It is assumed that the application of at least one of the two input currents induces a change in the sign of the conversion.

[0112] This allows you to perform a NOR function, that is, a “non-Oll” function.

[0113] This corresponds to the following logical table:

[0114] [Table 3]

[0115] It is worth noting that such a NOR gate is a universal gate. In fact, it is possible to realize all other Boolean logic gates by combining NOR gates.

[0116] Figure 6 shows an example of a logical computing architecture 28 that can be obtained by using three concatenated logical devices 10, distinguished in Figure 6 by a reference sign _1, _2 and _3.

[0117] The first logic device 10_1 is a device according to Figure 1 comprising a second conversion subunit 26_1 replacing the first conversion subunit. The second and third logic devices are also devices according to Figure 1 comprising a second conversion subunit 26_2 or 26_3 replacing the first conversion subunit but in which the first arm 12_2 or 12_3 extends only on one side relative to the channel 16 so that these devices have an H shape with a missing branch.

[0118] In this example, the first arm 12-2 and 12-3 of the second and third logic devices is merged with the second arm 14 1 of the first logic device 10_1 .

[0119] It is also possible to concatenate the devices by connecting the second arm 14 of a first device 10 to the electrical contact 24 of a second device 10. This can allow other logic functions to be performed, the output of the first device 10 controlling the sign of the conversion in the second device 10.

[0120] The concatenation of logical devices 10 thus makes it possible to carry out logical operations while maintaining low energy consumption.

Claims

DEMANDS 1. Logic device (10) comprising: - a first arm (12), the first arm (12) extending along a first direction (X), the first arm (12) being suitable for carrying a charge current, - a second arm (14), the second arm (14) extending along the first direction (X), the second arm (14) also being suitable for carrying a charge current, - a channel (16) connecting the first arm (12) to the second arm (14), the channel (16) being in a second direction (Y), the second direction (Y) being perpendicular to the first direction (X), the channel (16) having three zones, a first contact zone with the first arm (12), a second contact zone with the second arm (14) and a central zone connecting the two contact zones, the first arm (12), the second arm (14) and the channel (16) being suitable for carrying out a first conversion in the first contact zone and a second conversion in the second contact zone, the first conversion being the conversion of a charge current flowing in the first arm (12) into a spin current flowing in the channel (16), and the second conversion being the conversion of a spin current flowing in the channel (16) into a charge current flowing in the second arm (14), and - a control unit (20) for the direction of the charging current flowing in the second arm (14), the control unit (20) comprising at least one electrical control subunit (22, 26) for one of the two conversions.

2. Logic device according to claim 1, wherein a control subunit is a control subunit of the first conversion (22) and is adapted to control the direction of the charge current flowing in the second arm (14) by controlling the direction of the spins of the spin current by an electrical control of the first conversion.

3. Logic device according to claim 2, wherein the control subunit of the first conversion (22) comprises a voltage source and an electrical contact (24), the electrical contact (24) being in contact with the first contact area, the voltage source controlling the potential of the electrical contact.

4. Logic device according to any one of claims 1 to 3, wherein a control subunit is a control subunit of the second conversion (26) and is capable of controlling the direction of the charging current by electrical control of the second conversion.

5. Logic device according to claim 4, wherein the control subunit of the second conversion (26) comprises a voltage source and an electrical contact (24), the electrical contact (24) being in contact with the second contact area, the voltage source controlling the potential of the electrical contact.

6. Logic device according to claim 3 or 5, wherein the electrical contact (24) is a multilayer formed of at least an insulating layer and a metallic layer, the insulating layer resting on the arm (12, 14) and the channel (16) and being preferably made of a ferroelectric material, the ferroelectric material being advantageously chosen from the list consisting of BaTiOs, Pb(Zr,Ti)Os, BiFeOs, (Hf,Zr)C>2, and poly(vinylidene fluoride).

7. Logic device according to claim 3 or 5, wherein the electrical contact (24) rests on the channel part (16) and the arm part (12, 14).

8. Logic device according to any one of claims 1 to 7, wherein the arms (12, 14) and the channel (16) form an H.

9. Logic device according to any one of claims 1 to 8, wherein the arms (12, 14) and the channel (16) are made of the same material.

10. Logic device according to any one of claims 1 to 8, wherein the arms (12, 14) are made of a first material, the contact areas are made of a second material and the channel (16) is made of a third material distinct from the first material and the second material.

11. Logic device according to claim 9 or 10, wherein each material is selected from: - an oxide, in particular SrTiOs or KTaOs, - an III-V semiconductor material, preferably InAs or InSb, - a II-VI semiconductor material, preferably HgTe or CdTe, - dichalcogenides of transition metals, preferably WS2, WSe2, PtSe2, MoTe2 or MoSe2, and - topological insulators, preferably (Bi,Sb)2(Se,Te)s.

12. Logic device according to any one of claims 1 to 11, wherein the logic device (10) is suitable for performing a logic operation on two logic inputs to obtain a logic output, the state of the logic output being the direction of the current flowing in the second arm (14), - the logic state of a first input being the value of a potential applied to a control subunit (22, 26) and the logic state of a second input being the direction of the current flowing in the first arm (12) or - the logic state of a first input being the value of a current applied to a control subunit (22) and the logic state of a second input being the value of another current applied to a control subunit (22), or - the logic state of a first input being the value of the potential applied to the control subunit of the first conversion (22) and the logic state of a second input being the value of the potential applied to the control subunit of the second conversion (26).

13. Logic computing architecture (28) comprising at least two logic devices (10) according to any one of claims 1 to 12, the logic computing architecture (28) satisfying at least one of the following properties: - a first property according to which the first arm (12) of one of the two logic devices (10) is coincident with the second arm (14) of the other logic device (10), and - a second property according to which the second arm (14) of one of the two logic devices (10) is connected with an electrical control subunit (22, 26) of one of the two conversions.

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