Method and carrier substrate for producing a semiconductor component

Abstract

The invention relates to a method (600) for producing a semiconductor component (100) with at least one exposed membrane layer, wherein the method (600) comprises the following steps: Providing (610) a semiconductor material (102) having a carrier substrate (104) provided with a passivation layer (108), wherein a membrane layer (110) is arranged on the passivation layer (108), having a material or consisting of a material that can be changed in terms of its structure and / or composition by water, in particular hydrolysable, wherein the membrane layer (110) is covered by a protective layer (114) on a side opposite the passivation layer (108); removing (620) a part of the carrier substrate (104) using a wet-chemical process, in order to obtain an exposed region of the passivation layer (108) in a structured region (130) of the semiconductor material (102); and exposing (630) a section of the membrane layer (110) in the structured region (130) by means of a first dry etching step for etching the passivation layer and a second dry etching step for etching the protective layer, in order to obtain the exposed membrane section (140).

Description

[0001] title

[0002] Method and carrier substrate for producing a semiconductor component

[0003] The present invention relates to a method and an apparatus for producing a semiconductor device according to the main claims.

[0004] With regard to the production of semiconductor components with membranes, DE 10 2011 005 249 A1 discloses a device for converting mechanical energy into electrical energy and a method for its production. The production of a curved piezoelectric membrane is described.

[0005] From JP 2013-160706A a flow detector on a semiconductor substrate with an exposed sensor area is known.

[0006] Modern semiconductor components often require a high degree of flexibility in terms of material properties, so that, for example, good guidance of a light beam can be achieved in optical semiconductor components. For the purposes of this invention, a semiconductor component can be understood as a component that is manufactured on a semiconductor substrate as a carrier substrate, for example a semiconductor wafer, for example a silicon wafer. This can be a mechanical and / or optical component, for which the semiconductor properties of the substrate may be irrelevant for the function. It can be a mechanical component, an optical component, a component for the NIR range, the visible range, the UV range, the EUV range, or the X-ray range of electromagnetic waves.Such semiconductor components can be manufactured using techniques typical of the semiconductor industry. However, the problem is that some advantageous material properties belong to material types that are difficult to process. For example, a material may have a good, desirable material property, such as a certain refractive index, which interacts particularly favorably with another material, such as air, at an interface, thereby enabling particularly good deflection or shaping of electromagnetic radiation. At the same time, however, this very material may also be water-soluble or hydrolyzable, for example, meaning that some process steps used in conventional semiconductor manufacturing processes cannot be used to process such a material.

[0007] Based on this problem, a possibility is now presented that enables improved processing and thus the production of a semiconductor component with improved properties.

[0008] This problem is solved by the subject matter of the main claims.

[0009] The approach presented here presents a method for producing a semiconductor component with at least one exposed membrane section, the method comprising the following steps:

[0010] - Providing a semiconductor material comprising a carrier substrate provided with a passivation layer, wherein a membrane layer is arranged on the passivation layer, which membrane layer comprises or consists of a material whose structure and / or composition can be changed, in particular hydrolyzed, by water, wherein the membrane layer is covered by a protective layer on a side opposite the passivation layer; - Removing a part of the carrier substrate using a wet-chemical process to obtain an exposed region of the passivation layer in a structured region of the semiconductor material; and

[0011] - Exposing a portion of the membrane layer in the structured region by means of a first dry etching step for etching the passivation layer and a second dry etching step for etching the protective layer in order to obtain the exposed membrane portion (140).

[0012] A carrier substrate can be understood, for example, as a conventional substrate, for example made of silicon. This carrier substrate can be provided with a passivation layer which, for example, comprises or consists of silicon nitride. A membrane layer can be understood as a layer which has a particularly advantageous property, for example with regard to its optical behavior, but which comprises or consists of a material whose structure and / or composition can be changed by water, in particular which is hydrolyzable. For example, a mechanical structure of this material can degrade if the material comes into contact with water or if a layer made of this material breaks or tears.Hydrolysis can be understood as the intercalation between water molecules, whereby this material can then precipitate or crystallize upon evaporation or vaporization of the water. However, hydrolysis can also chemically decompose the material through contact with water. Aluminum nitride, for example, can be hydrolyzed with the formation of ammonia. In this case, a protective layer can be understood as a covering of the membrane layer. The protective layer and the passivation layer, which can advantageously consist of a material that is not water-soluble or whose structure and / or composition cannot be changed by water, or contain this material, ensure that the membrane layer is fluid-tightly sealed from the environment of the semiconductor component (except, for example, the lateral edges of the wafer).In this way, it can be ensured that the membrane layer is not damaged during the processing or structuring of regions of the carrier substrate or the semiconductor component, which would otherwise destroy the semiconductor component to be manufactured. A wet-chemical process can be understood as one or more process steps of a wet etching process or a wet cleaning process in which a liquid etching and / or cleaning agent is used to introduce structures into the semiconductor material or to clean a surface of the semiconductor material. A dry etching process can be understood as a process step in which the semiconductor material is structured using a physical or mechanical removal process or using a gaseous etchant.Furthermore, the first and second dry etching steps can, but do not have to, be carried out using an identical dry etching process and / or in a single process step. Two consecutive dry etching steps, each from one side of the semiconductor component, are also advantageous. The sequence of the providing, removing, and exposing steps can also advantageously be carried out in the specified order, with the first and second dry etching steps being able to be implemented as substeps of the exposing step and also being able to be carried out in any desired order.

[0013] The approach proposed here offers the advantage of using different etching or cleaning processes at different processing stages, ensuring that the membrane system, which is made of a material sensitive to an etching or cleaning material used in one of the process steps, remains as undamaged as possible. In this way, a material that is highly favorable for the function of the semiconductor component to be manufactured can now also be used for the membrane layer. The approach proposed here thus enables significant flexibility in the use of different materials, which exhibit highly advantageous properties for a desired target application of the semiconductor component.

[0014] An embodiment of the approach proposed here is advantageous in which, in the providing step, a semiconductor material is provided in which the protective layer forms a layer stack as a protective layer with a cover layer, wherein a material of the protective layer differs from a material of the cover layer, in particular wherein the material of the cover layer comprises a reflective material and / or a metal. Such an embodiment offers the advantage of being able to structure this protective layer very flexibly due to the different materials of the layers of the protective layer, so that a flexible design of the exposed membrane layer can also be achieved in a later process step. By using a reflective material for the cover layer, desired optical properties of the finished semiconductor component can also be realized, for example.According to one embodiment, the method may also comprise a step of structuring the protective layer to be carried out before the second dry etching step, in particular before the step of removing a part of the carrier substrate, in which step the protective layer is exposed, at least in places, by removing the cover layer, in particular using an auxiliary mask by means of one of the etching methods (for example a dry etching method used in the first or second dry etching step) or a further etching method (for example the further or another dry etching method).

[0015] According to a further embodiment of the approach proposed here, a section of the carrier substrate in the structured region can be removed during the structuring step. Such an embodiment of the approach proposed here offers the possibility of preparing the semiconductor material or the semiconductor component using known, efficient processing steps such that the dry etching process can be used exclusively in the subsequent exposure step. In this way, the prior processing of the semiconductor material can prevent damage to a potentially already exposed surface of the membrane layer by an etching or cleaning agent that is too aggressive for the material of the membrane layer.

[0016] Particularly advantageous is an embodiment of the approach proposed here in which the structuring step is carried out such that the membrane layer is sealed against an etching or cleaning agent of the wet-chemical process by the passivation layer and at least part of the protective layer. Such an embodiment offers the advantage of reliably protecting the membrane layer against the etching agent of the wet-chemical process and thus preventing damage to the membrane layer.

[0017] According to a further embodiment of the approach proposed here, the passivation layer and at least part of the protective layer can be removed using the dry etching process in the exposure step. Such an embodiment of the approach proposed here offers the advantage that the dry etching process is already applied when the membrane layer is first exposed, thus allowing the membrane layer to be protected and structured as effectively as possible.

[0018] Semiconductor components designed to be particularly delicate and efficient for a specific application can be manufactured if the membrane layer itself is not only exposed but also structured. For this purpose, through-holes can be introduced into the membrane layer, for example, to enable the implementation of an electromagnetic radiation attenuator or an optical structure, such as a diaphragm structure, in the membrane layer in the exposed membrane section. Such a diaphragm structure can have through-holes with a diameter larger than a design light wavelength of the component, forming conventional diaphragms.According to a particularly advantageous embodiment, the membrane layer can therefore be at least partially removed in the exposure step to obtain a perforated, exposed membrane section, in particular wherein a structured region of the protective layer and / or a resist mask applied to the protective layer and / or to the cover layer can be used as an etching mask. Such a perforation can have perforation holes that have a larger diameter than a design light wavelength of the component in order to form conventional apertures. Perforation holes that have a smaller diameter than a design light wavelength of the component can also be provided in order to produce evanescent light waves or to act as a short-pass filter. The perforated membrane section can represent a diffraction grating.It should be noted that, for the purposes of this invention, light can also include EUV radiation (XUV), UV radiation, visible light, and infrared light. The optical function of the component (design light wavelength) can be provided in any of the aforementioned wavelength ranges.

[0019] Furthermore, according to a further embodiment of the approach presented here, in the step of structuring and exposing, the membrane layer, the carrier substrate, the protective layer, a masking layer, and the passivation layer can be removed in a pass-through region laterally adjacent to the structured region in such a way that an opening is formed into which no portion of the membrane layer protrudes. Such an embodiment of the approach proposed here offers the advantage that other regions of the semiconductor material can also be structured using the method presented here, in which no exposed portions of the membrane layer are required. In this way, the structuring of the semiconductor material or the semiconductor component can be carried out compactly with few work steps, thereby reducing manufacturing costs and manufacturing time.

[0020] A particularly favorable embodiment is furthermore in which, in the structuring step, a holding material is applied to a section of the passivation layer exposed in the passivation region. In the exposure step, after removal of the carrier substrate and the passivation layer in the passivation region, the holding material is removed to form the opening. A holding material can be understood, for example, as a plastic material, such as a photoresist, which can also be used to introduce structures into different layers of the semiconductor material. The holding material can also be applied together with another material to a surface of the semiconductor material or the semiconductor component.By using such a semiconductor material, which is applied, for example, directly to the passivation layer, it is possible to prevent flakes or fragments of a layer to be removed from falling uncontrolled into the processing space and causing defects in a subsequent step. Rather, such fragments, which may arise from a continuous reduction in the thickness of the layer to be removed, can be supported or held firmly in place by the holding material, enabling complete removal or dissolution of these fragments. The holding material can advantageously be applied to the side of the passivation layer facing away from the substrate, in the area of ​​the intended passivation band.

[0021] An embodiment of the approach proposed here can also be used very flexibly, in which the opening is formed in the exposing step such that it has a larger diameter than an opening in the exposed region of the membrane layer. Such an embodiment offers the advantage of being able to introduce differently dimensioned structures into the semiconductor material using a uniform method or process, allowing the efficient implementation of desired functions in a semiconductor element.

[0022] A semiconductor component with particularly favorable properties can be realized specifically by providing a semiconductor material in which the passivation layer and / or a masking layer at least partially comprises a silicon nitride, and / or in which the membrane layer at least partially comprises an aluminum nitride, a germanium oxide, and / or an aluminum oxide, and / or wherein the cover layer comprises a metal, in particular chromium, and / or the protective layer comprises silicon and / or silicon nitride. In this way, semiconductor components designed very advantageously, especially for optical applications, can be realized.

[0023] Particularly advantageously, for the realization of the different steps of the approach proposed here, an embodiment can be used in which, in the structuring step, a wet etching process using potassium hydroxide or tetramethylammonium hydroxide as etchant is carried out as a wet-chemical process and / or a wet-chemical cleaning process and / or wherein, in the exposing step, a dry etching process is carried out using a physical dry etching process, a chemical dry etching process and / or a physico-chemical dry etching process.

[0024] The thickness of the membrane layer can advantageously be between 5 nm and 1000 nm, particularly advantageously between 10 nm and 500 nm, and most advantageously between 50 nm and 200 nm. The lateral extent of the exposed region of the membrane can advantageously be between 50 nm and 5000 nm, particularly advantageously between 100 nm and 500 nm. The membranes can be perforated, for example, with a hole pattern whose lateral hole spacing is between 50 nm and 5000 nm, advantageously between 100 nm and 1000 nm. The membranes can be used, for example, to absorb and / or diffract electromagnetic radiation.

[0025] Another advantageous embodiment of the approach presented here is when the structured region of the semiconductor material has edges whose normals form an angle of less than 60°, in particular 54.7°, to a surface normal of the carrier substrate, in particular where the semiconductor material is monocrystalline and the edges are formed by etch-resistant crystal planes. For example, a silicon wafer with a {100} surface can be used. If the edges are formed by {111} and equivalent crystal planes, the angle can be 54.74°.

[0026] These variants of methods can be implemented, for example, in software or hardware or in a mixed form of software and hardware, for example as control commands in a control unit or device.

[0027] The approach presented here further provides a device designed to perform, control, or implement the steps of a variant of a method presented here in corresponding devices. This embodiment of the invention in the form of a device also allows the problem underlying the invention to be solved quickly and efficiently.

[0028] For this purpose, the device can have at least one computing unit for processing signals or data, at least one memory unit for storing signals or data, at least one interface to a sensor or an actuator for reading sensor signals from the sensor or for outputting data or control signals to the actuator, and / or at least one communication interface for reading or outputting data embedded in a communication protocol. The computing unit can be, for example, a signal processor, a microcontroller, or the like, wherein the memory unit can be a flash memory, an EEPROM, or a magnetic storage unit.The communication interface can be designed to read in or output data wirelessly and / or wired, wherein a communication interface that can read in or output wired data can read this data, for example, electrically or optically from a corresponding data transmission line or output it to a corresponding data transmission line.

[0029] In this case, a device can be understood as an electrical device that processes sensor signals and outputs control and / or data signals depending on them. The device can have an interface, which can be implemented in hardware and / or software. In a hardware implementation, the interfaces can, for example, be part of a so-called system ASIC, which contains a wide variety of functions of the device. However, it is also possible for the interfaces to be separate integrated circuits or to consist at least partially of discrete components. In a software implementation, the interfaces can be software modules that are present, for example, on a microcontroller alongside other software modules.

[0030] Also advantageous is a computer program product or computer program with program code that can be stored on a machine-readable carrier or storage medium such as a semiconductor memory, a hard disk memory or an optical memory and is used to carry out, implement and / or control the steps of the method according to one of the embodiments described above, in particular when the program product or program is executed on a computer or a device.

[0031] Examples of the approach presented here are shown in the drawings and explained in more detail in the following description. It shows:

[0032] Fig. 1A to Fig. 11 show several partial representations, each illustrating a cross-section of a semiconductor component to be manufactured according to an exemplary embodiment in different process steps; a block diagram of a device according to an exemplary embodiment; Fig. 2 shows several partial representations, each illustrating a cross-section of a semiconductor component to be manufactured according to a further exemplary embodiment in different process steps;

[0033] Fig. 3 shows a schematic cross-section of the layer stack used as starting material for the semiconductor component;

[0034] Fig. 4 shows a cross section of a structured wafer as a starting material of a semiconductor material for the semiconductor component;

[0035] Fig. 5 shows an SEM image of a structured AIN membrane prepared using the proposed process flow;

[0036] Fig. 6 is a flowchart of an embodiment of a method for manufacturing a semiconductor device; and

[0037] Fig. 7 is a block diagram of an embodiment of an apparatus for producing a semiconductor component.

[0038] In the following description of advantageous embodiments of the present invention, the same or similar reference numerals are used for the elements shown in the various figures and having a similar effect, whereby a repeated description of these elements is omitted.

[0039] Figure 1 shows, in several partial representations, which are reproduced as Figure 1A to Figure 11, a cross section of a semiconductor component 100 to be produced according to an embodiment after different process steps.

[0040] Figure 1A initially shows a semiconductor material 102 in the form of a stack of multiple layers. The semiconductor material 102 comprises a carrier substrate 104, which is made, for example, of silicon or comprises this material. The semiconductor substrate 104 further comprises a lower masking layer 106 and a passivation layer 108, each of which, for example, comprises a silicon nitride (Si3N4) or comprises this material. The masking layer 106 and the passivation layer 108 can be formed, for example, in a single manufacturing step on the carrier substrate 104. The membrane layer 110, which, for example, comprises a water-soluble material or consists of such a material, is arranged on the passivation layer 108. Alternatively or additionally, the membrane layer 110 can be made of a material whose structure and / or composition can be changed by water, in particular hydrolyzed.A protective layer 112 is arranged on the membrane layer 110, which comprises, for example, a protective layer 114 and a cover layer 116 arranged on the protective layer 114. This protective layer 114 can comprise a silicon-based semiconductor material and be designed as an etch stop layer. The cover layer 116 can, for example, comprise or consist of a reflective material and / or metal, for example, chromium.

[0041] In a first processing step, the cover layer 116 is structured, for example, with the reflective material. For this purpose, a photoresist can be used, for example, which is exposed in accordance with a structure to be introduced into the cover layer 116. A wet etching process or, alternatively or additionally, a dry etching process can be used for structuring the cover layer 116.

[0042] Figure 1 B shows a cross-sectional view through a semiconductor component 100 in a state after execution of the above-mentioned method steps.

[0043] Subsequently, according to this exemplary embodiment, the masking layer 106 is structured, for example again using a photoresist to be exposed and / or using a wet etching process or alternatively a dry etching process.

[0044] Figure 1C shows a cross-sectional view through a semiconductor component 100 in a state after execution of this method step.

[0045] In a further method step, structuring is performed using a photoresist as etching mask 120 to realize different grating types in the semiconductor component 100. This allows a substrate grating type 122 and, in a further region, a membrane grating 124 to be structured. Figure 1D shows a cross-sectional view through a semiconductor component 100 in the state after this method step has been carried out.

[0046] According to the exemplary embodiment for the production of the semiconductor component 100 shown in Figure 1, in a further method step, etching through the carrier substrate 104 takes place using a wet etching process. By using the wet etching process, diagonally sloping flanks instead of trenches can be formed through the openings of the masking layer 106 in the carrier substrate, as is made possible by using the wet etching process with appropriate alignment of the crystal structure of the carrier substrate 104. The formation of such flanks is very advantageous for optical applications, as will be explained in more detail below. The etching then takes place until the rear-side exposure of the passivation layer 108, which serves as a stop layer for the wet etching process, can be avoided.water-sensitive membrane layer 110 is attacked by the wet etching process and thus damaged or destroyed.

[0047] Figure 1E shows a cross-sectional view of a semiconductor component 100 in the state after performing this method step. At the same time, this state of the semiconductor component 100 is the final state in this manufacturing embodiment, which can be processed by a wet etching step. The subsequent steps are performed using the dry etching process to avoid damage or destruction of the membrane layer 110, which consists of or comprises the water-soluble material.

[0048] In a subsequent step, sacrificial layers can be removed, which in the present exemplary embodiment can be the exposed part of the passivation layer 108 from the back side of the carrier substrate 104 as well as the part of the protective layer 114 not covered by the photoresist as etching mask 120 and / or the cover layer 116. A dry etching process is used for this removal, since the membrane layer 110 is now exposed in a structured region 130 and in a transmission region 132. Using a process step of a wet etching process in this state would also attack and damage the membrane layer 110, so that according to the approach presented here, only a dry etching process may be used to process the semiconductor component 100 from this process stage onwards. Figure 1F shows a cross-sectional view through a semiconductor component 100 in the state after execution of this process step.

[0049] Subsequently, in a further method step, for example, the membrane layer 110 in the transmission region 132 can be removed, creating a wide opening 136 through the semiconductor component 100. Furthermore, in the structured region 130, the membrane layer 110 exposed by the structured protective layer 112, specifically the structured protective layer 114 and the structured cover layer 116, can also be removed, which can be achieved, for example, by a dry etching process acting from above. In this way, the membrane layer 110 comprising the water-soluble or water-sensitive material can be structured as desired. At the same time, very fine structures such as holes 138 in the structured region 130 can also be realized in the membrane layer 110, which, for example, makes it possible to form the subsequently produced exposed membrane layer 110 as a movable element.

[0050] Figure 1 G shows a cross-sectional view through a semiconductor component 100 in the state after execution of this method step.

[0051] Furthermore, in a subsequent step, the area of ​​the protective layer 112 not covered by the etching mask 120, i.e., the uncovered part of the protective layer 114 and the cover layer 116, is (dry) etched or removed, creating an exposed membrane section 140 of the membrane layer 110, which, for example, also has fine structures such as through-holes 138. These through-holes 138 can also be significantly smaller in diameter than the opening 236 in the through-hole region 132.

[0052] Figure 1 H shows a cross-sectional view through a semiconductor component 100 in the state after execution of this method step.

[0053] Finally, in a subsequent step, the etching mask 120 is removed or (dry) etched and, if necessary, the individual parts of the semiconductor component 100 are separated.

[0054] Figure 11 shows a cross-sectional view of a semiconductor component 100 in the state after performing this process step. The sub-figures of Figure 1 thus show a schematic of an exemplary embodiment of a process flow for producing free-standing, moisture-sensitive, structured membranes using sacrificial protection layers and standard CMOS process steps. During all critical steps, the sensitive layers, such as membrane layer 110, are protected, enabling the use of wet and thus cost-effective process steps.

[0055] With the approach presented here, the production of ultra-thin, free-standing and structured membranes as membrane layer 110 made of layered material that is sensitive to wet processes can be carried out. In this way, the production of free-standing, ultra-thin membranes, which typically requires many wet-chemical process steps such as lithography and wafer cleaning, can nevertheless be realized efficiently. To produce the free-standing membranes, the entire wafer is typically etched through either by dry or wet etching. While dry etching processes such as DRIE (deep reactive ion etching) produce approximately vertical etch profiles through the wafer, wet etching processes can also produce oblique etch profiles in the etched groove.For optical applications, a sloped V-shaped sidewall with wet etching is preferred to transmit high NA (numerical aperture) light through a membrane without shadowing on the sidewalls of the wafer hole. However, the use of wet etching techniques is difficult or impossible if the application requires a membrane material that is sensitive to wet chemistry. For example, aluminum- or germanium-based materials can even be water-soluble and are therefore not suitable for most wet processes. In contrast, the approach presented here presents a process flow that enables the fabrication of virtually any free-standing membrane material. Furthermore, a method for fabricating structured membranes is described.

[0056] The fabrication of freestanding membranes is a widely used technology for applications such as MEMS products or optical sensors. Typically, robust materials such as SiN or metals are used as the membrane material or material for the membrane layer 110. However, depending on the application, the use of more sensitive materials is also desirable. For example, GeO, AlN, or AlxOy are good candidates for transmissive UV and EUV applications due to their good refractive index match compared to vacuum. However, these materials are soluble even in water, so a wet process step is not directly feasible. Here, a method is presented that can be used to fabricate freestanding membranes made from virtually any structured and moisture-sensitive material, and which also feature a sloped sidewall of the etched hole through the wafer.It consists of various sacrificial layers that protect the sensitive membrane layer 110 from the wet environment. This approach makes it possible to pattern the membranes and create a suitable reflective material for sensor purposes in the VIS range. There are no limitations on the patterning precision other than the resolution limit of the lithography and etching tool used. Here, we demonstrate a minimum feature size of < 200 nm, which is within the resolution limit of the tool.

[0057] The approach presented here can be used particularly advantageously for the production of free-standing ultrathin membranes made of a material particularly suitable for the UV and EUV range. This material, particularly AlN, is water-soluble or hydrolyzable, especially for thin films, and is not robust in the commonly used cleaning chemicals. The proposed process flow circumvents these limitations.

[0058] The proposed process flow also allows, in principle, the use of any depositable and structurable material as a membrane layer, thus opening up a high degree of flexibility in the design of semiconductor devices.

[0059] The proposed process is described based on the processing stages of the semiconductor device shown in the subfigures of Figure 1. It includes various standard process steps such as coating, lithography, cleaning, wet and dry etching. Using the proposed process route, more wet cleaning steps can be performed, thereby improving the overall quality of surface defects. In particular, it is even possible to utilize the critical wet etching step, at least in part, for the production of the membrane.

[0060] An important aspect of the proposal presented here is the use of protective layers below (SiN) and above the moisture-sensitive layers during all wet process steps. These protective layers are ultimately etched away. The layer stack is chosen so that individual layers can be selectively etched without etching the other masking and / or protective layers. A further advantage of the proposed approach or layer stack is the possibility of tuning the optical reflectivity through the selected materials and / or layer thicknesses. The introduction of the protective layer offers the possibility, for example, to bring the reflectivity to almost zero in green light, for example, or to achieve maximum reflectivity simply by changing the layer thickness.

[0061] In the proposed process flow, the step between the processing stages shown in Figures 1F and 1G is challenging. When etching through the last free-standing layer to open large holes, such as in the area of ​​the through-hole 136, this layer is slowly thinned. If the remaining layer is too thin (a few nanometers) to remain intact, the membrane, or in this case, the membrane layer 110, will break before the etching process is complete and curl up into flakes. These shreds, which may consist of the moisture-sensitive material, act as an unwanted masking layer in the following processes. For this reason, a further optimized process flow was developed to avoid these flakes that appear through the large openings.

[0062] Figure 2 shows, in several partial representations, each a cross-section of a semiconductor component 100 to be manufactured according to an exemplary embodiment in different process steps. Starting from the processing state of the semiconductor component 100 shown in Fig. 1C, in a first intermediate step shown on the right, a shading mask 200 is first used, which is used in a dry etching step to remove the protective layer 114 in the through-passage region 132 using a dry etching process. In this way, the membrane layer 110 is exposed in the through-passage region 132. In a subsequent process step, the exposed membrane layer 110 is removed using a wet etching process or a dry etching process. Following this, the procedure according to the illustration in Figure 1D is then continued, but now the etching mask 120 is additionally applied to the now exposed upper passivation layer 108.In the subsequent steps, specifically in the transition from the processing states between the semiconductor components 100 depicted in Figures 1F and 1G, it is thus ensured that the upper passivation layer 108 (and also the previously removed membrane layer 110 in the passband 132) cannot disintegrate into flakes, which could then act as faulty optical masking. Figure 2 thus shows a (partially) optimized scheme for avoiding flakes consisting of moisture-sensitive layers at large openings. Two new process steps are included to selectively etch the layers in the areas of the large membrane openings 136, i.e., the passband 132. All other process steps are the same or very similar to the previous process flow in Figure 1.

[0063] Two additional process steps (shown on the right-hand side of Figure 2) serve to selectively remove the moisture-sensitive layer at the large openings. Various etching methods can be used. In the process diagram, we use a shadow mask as an example to open the buffer layer. All other processes essentially correspond to the sequence previously described in Figure 1. The only difference is the use of a slightly adapted photomask in the step leading to the semiconductor device according to Figure 1D in order to keep the large openings closed by the photoresist as etch mask 120. This improved process flow makes it possible to replace the critical step of etching through the free-standing moisture-sensitive layer with process steps in which etching occurs against a thick (free-standing) photoresist.This can prevent the formation of flakes or flakes during processing, which may consist of, for example, broken ultra-thin and / or moisture-sensitive material.

[0064] As an example of a wet-sensitive membrane material, the feasibility of this process sequence can be demonstrated using aluminum nitride (AIN). AIN can even be soluble in water and / or decompose upon exposure to water, forming ammonia, which poses a significant challenge for wet process steps. To obtain a flat, free-standing AIN membrane, the layer tension is set to a tensile stress of several hundred MPa. In this example, silicon or silicon nitride was used as the protective layer. Chromium was used as the masking and reflection layer, or as the cover layer 116.

[0065] Figure 3 shows a schematic cross-section of the layer stack used as starting material 102 for the semiconductor component 100, specifying an exemplary layer stack for producing free-standing, water-soluble AlN membranes. The AlN layer is subjected to tensile stress. The masking layer 106 and the passivation layer 108 can, for example, be designed as an etch stop layer and comprise, for example, 100 nm thick Si3N4 layers. The membrane layer 110 can comprise AlN with a thickness of, for example, 100 nm. The protective layer 114 can, for example, have a thickness of 50 nm and be formed as SiNx. The cover layer 116 can, for example, be formed as a metal layer, for example made of chromium, with a thickness of, for example, 100 nm.

[0066] The proposed process flow avoids exposing the water-soluble AIN to a liquid process step. The desired V-grooves through the wafers are etched with diluted KOH (potassium hydroxide) or TMAH (tetramethylammonium hydroxide). As a final result, various types of markers can be produced, i.e., gratings patterned in chromium for reflective sensing purposes, as well as gratings patterned in the freestanding AIN membrane for transmission purposes. Furthermore, large openings can also be provided, e.g., for cleaning purposes.

[0067] Figure 4 shows a cross-section of a structured wafer as a semiconductor device 100, consisting of a reflective Cr marker, large openings that allow access to the backside of the wafer, and transmissive markers on the freestanding AIN membrane.

[0068] The lateral dimensions of the Cr markers and the patterned holes of the AlN membrane are limited only by the resolution limit of the lithographic tool in combination with the dry etching tools. Structures with lateral dimensions of ~100 nm can be realized. Similar results were achieved using Al2O3 as the membrane material, which is sensitive to many wet cleaning compounds. A typical SEM (scanning electron microscope) image of a patterned freestanding AlN membrane is shown in the following figure.

[0069] Figure 5 shows an SEM image of a structured AIN membrane 110 fabricated using the proposed process flow. The circles represent holes in the through-hole region 132 in the AIN membrane, which allow a clear optical path through the membrane 110 and the entire wafer 104.

[0070] Figure 6 shows a flow diagram of a method 600 for producing a semiconductor component with at least one exposed membrane section, the method comprising a step 610 of providing a semiconductor material having a carrier substrate provided with a passivation layer, wherein a membrane layer is arranged on the passivation layer, which membrane layer comprises or consists of a material whose structure and / or composition can be changed by water, in particular is hydrolyzed, wherein the membrane layer is covered by a protective layer on a side opposite the passivation layer. Furthermore, the method 600 comprises a step 620 of removing a part of the carrier substrate using a wet-chemical method in order to obtain an exposed region of the passivation layer in a structured region of the semiconductor material.Finally, the method 600 comprises a step 630 of exposing a portion of the membrane layer in the patterned region by means of a first dry etching step for etching the passivation layer and a second dry etching step for etching the protective layer to obtain the exposed membrane portion.

[0071] Figure 7 shows a block diagram of an apparatus 700 for producing a semiconductor component. The apparatus 700 comprises a unit 710 for providing a semiconductor material comprising a carrier substrate provided with a passivation layer, wherein a membrane layer comprising a water-soluble material or consisting of such a water-soluble material is arranged on the passivation layer, wherein the membrane layer is covered by a protective layer on a side opposite the passivation layer. Furthermore, the apparatus 700 comprises a unit 720 for structuring the protective layer using a wet etching process to obtain a structured region of the semiconductor material. Finally, the apparatus 700 comprises a unit 730 for exposing a section of the membrane layer in the structured region using a dry etching process to obtain an exposed membrane section.

[0072] In summary, it should be noted that an advantageous approach for the production of structured, free-standing membranes is presented here. A process flow is presented that enables the use of materials that are not robust in the conventionally used chemicals for cleaning and etching, especially water. The wide range of materials enables the use of membranes with a low refractive index and thus low dispersion. An optimized process flow is also presented to enable large openings without the flakes that usually occur when etching through the membrane. All etching steps can be performed selectively with respect to the respective masking layers and etch stop layers. Despite the use of protective layers, there is an increased risk that small defects will lead to undesired under- or partial etching. Almost any depositable and structurable material can now be used as an alternative.

[0073] membrane layer, which increases the flexibility of the approach presented here compared to conventional process steps.

[0074] The process flow according to the invention can also be advantageously implemented for typical MEMS membranes with sensitive materials. Furthermore, it opens up the possibility of using sensitive materials as membrane layers that are not feasible with conventional methods.

Claims

Patent claims 1. Method (600) for manufacturing a semiconductor device (100) with at least one exposed membrane section, wherein the method (600) comprises the following steps: Providing (610) a semiconductor material (102) comprising a support substrate (104) provided with a passivation layer (108), wherein a membrane layer (110) is arranged on the passivation layer (108) which comprises or consists of a material which is modifiable in its structure and / or composition by water, in particular hydrolyzable, wherein the membrane layer (110) is covered on a side opposite the passivation layer (108) by a protective layer (114); Removing (620) part of the support substrate (104) using a wet chemical process to obtain an exposed area of ​​the passivation layer (108) in a structured region (130) of the semiconductor material (102); and Exposing (630) a section of the membrane layer (110) in the structured area (130) by means of a first dry etching step to etch the passivation layer and a second dry etching step to etch the protective layer in order to obtain the exposed membrane section (140).

2. Method (600) according to claim 1, characterized in that in the provisioning step (610) a semiconductor material (102) is provided in which the protective layer (114) forms a layer stack as a protective layer (112) with a cover layer (116), wherein a material of the protective layer (114) differs from a material of the cover layer (116), in particular wherein the material of the cover layer (116) comprises a reflective material and / or a metal, and the method (600) further comprises a structuring step of the protective layer (112) to be carried out before the second dry etching step, in particular before the step (620) of removing a part of the support substrate, in which the protective layer (114) is exposed, at least locally, by removing the cover layer (116), in particular using an auxiliary mask, by means of an etching process used in the first or second dry etching process or a further etching process. Method (600) according to one of the preceding claims with reference to claim 2, characterized in that in the step of structuring and exposing (630) in a passage area (132) laterally adjacent to the structured area (130) the membrane layer (110), the support substrate (104), the protective layer (114) and the passivation layer (108) are removed in such a way that an opening (136) passing through the semiconductor device (100) is formed, in particular into which no section of the membrane layer (110) projects.Method (600) according to claim 3, characterized in that, to prevent contamination by detachment of material residues from the passivation layer to be removed, a retaining material (210) is applied to a section of the passivation layer (108) exposed in the passage area (132) during the structuring step, wherein, in the exposure step (630), after removal of the support substrate (104) and the passivation layer (108) in the passage area (132), the retaining material (210) is removed to form the opening (136). Method (600) according to claim 3 or 4, wherein, in the exposure step (630), the opening (136) is formed such that it has a larger diameter than an opening (138) in the exposed area (140) of the membrane layer (110).A method (600) according to any one of the preceding claims 2 to 5, characterized in that, in the structuring step, a wet etching process using potassium hydroxide or tetramethylammonium hydroxide as the etchant is carried out, and / or wherein, in the exposure step (630), the first and / or second dry etching step is carried out using a physical dry etching process, a chemical dry etching process, and / or a physicochemical dry etching process. A method (600) according to any one of the preceding claims, characterized in that several semiconductor devices are produced simultaneously on the substrate. A method (600) according to any one of the preceding claims, characterized in that, prior to the exposure step (630), a section of the... Membrane layer (110) at least one cleaning step with a water-containing cleaning agent, in particular a wet chemical cleaning process, is provided.

9. Method (600) according to one of the preceding claims, characterized in that in the exposure step (630) the membrane layer (110) is at least partially removed to obtain a perforated exposed membrane section (140), in particular wherein a structured area (130) of the protective layer (114) and / or a paint mask (120) applied to the protective layer (114) and / or to the cover layer (116) is used as an etching mask.

10. Method (600) according to one of the preceding claims, characterized in that in the step of providing (610) a semiconductor material (102) is provided in which the passivation layer (108) comprises at least partially a silicon nitride, and / or in which the membrane layer (110) comprises at least partially an aluminum nitride, a germanium oxide and / or an aluminum oxide, and / or wherein the cover layer (116) comprises a metal, in particular aluminum or a transition metal, in particular at least one of the transition metals titanium, nickel, chromium, tantalum, tungsten, platinum and / or the protective layer (114) comprises silicon and / or silicon oxide and / or silicon nitride.

11. Method (600) according to one of the preceding claims, wherein the structured region (130) of the semiconductor material (102) has edges whose normals have an angle of less than 60°, in particular 54.7°, to a surface normal of the support substrate, in particular wherein the semiconductor material is single-crystal and the edges are formed by etch-resistant crystal planes.

12. Method (600) according to one of the preceding claims, characterized in that the membrane layer (110) has a thickness between 10nm and 500nm.

13. Device (700) configured to perform and / or control the steps (610, 620, 630) of the method (600) according to any one of the preceding claims 1 to 11 in corresponding units (710, 720, 730). A computer program configured to execute and / or control the steps of the method (600) according to any one of the preceding claims 1 to 11 when the computer program is executed on a computer unit. A support substrate (104) for the production of at least one semiconductor device (100) with at least one exposed membrane section, comprising a passivation layer (108) arranged on a first side, wherein a membrane layer (110) is arranged on the passivation layer (108), the membrane layer comprising or consisting of a material that is modifiable in its structure and / or composition by water, in particular hydrolyzable, wherein the membrane layer (110) is covered on a side opposite the passivation layer (108) by a protective layer (114), the protective layer (114) comprising silicon and / or silicon nitride.wherein the protective layer (114) with a cover layer (116) forms a layer stack as a protective layer (112), wherein a material of the protective layer (114) differs from a material of the cover layer (116) and the cover layer (116) comprises a metal and furthermore an etching mask for wet etching of the substrate is applied on a second side of the support substrate opposite the first side.

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