Method and device for generating a pulse width modulation signal, and arrangement having such a device
Patent Information
- Application Number
- EP2023735245
- Authority / Receiving Office
- EP · EP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-06-20
- Filing Date
- 2023-06-20
- Publication Date
- 2025-04-23
AI Technical Summary
PWM signal period changes cause disruptions in output signals, leading to unwanted electromagnetic and audio emissions, and sudden changes in period duration result in mean value shifts that require compensatory adjustments, risking overshoots and transients in control loops.
Introducing an intermediate state with a changed duty cycle or period duration, allowing for balanced mean value changes during the transition, limiting the effect of period duration changes to the intermediate state duration, and ensuring the output signal returns to its original value without needing further adjustments.
This approach minimizes disruptions to the control loop and reduces the risk of overshoots by maintaining a stable output signal mean value, distributing interference over a broader frequency range and reducing spectral density of unwanted radiation.
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Figure 1.1
Abstract
Description
[0001] Method and device for generating a pulse width modulation signal and arrangement with such a device
[0002] The invention relates to a method for generating a pulse width modulation signal, hereinafter referred to as a "PWM signal" (PWM - pulse width modulation), which changes from a first state with a first predetermined period to a second state with a second predetermined period, wherein the PWM signal has the same predetermined duty cycle in the first and second states. The invention further relates to a device for generating such a PWM signal and an arrangement comprising such a device.
[0003] A PWM signal is a periodic digital signal that initially assumes a first state within a period, then a second state for the remainder of the period. The time ratio with which the two states are assumed within a period is also referred to as the "duty cycle." PWM signals are used to digitally vary an averaged analog output value of a circuit with a digitally controlled circuit by varying the duty cycle of the PWM signal.
[0004] The technology of pulse width modulation is used, for example, in digital-to-analog converters, in voltage converters (boost converters, buck converters), current controllers, in input stages for the power factor adjustment of switching power supplies (PFC - Power Factor Correction) or also in converters, e.g.
[0005] B. inverters.
[0006] In circuits that use a PWM method, the average of an output signal, such as an output voltage or output current, is achieved, for example, by capacitors and / or coils, whose dimensions, together with the resistors in the array (e.g., parasitic resistances of coils or load resistors), define a smoothing time constant. The period of the PWM signal is usually chosen to be significantly smaller than the time constant, usually by more than a factor of 100.
[0007] During operation of a device using a PWM process, disruptive electromagnetic and / or audio emissions may occur, the spectrum of which can be influenced, among other things, by the PWM period. By changing the PWM period during operation, the spectral density of the unwanted interference can be reduced. Such a process is also known as "frequency spread spectrum" and is described, for example, in publications DE 11 2017 004 964 T5 or DE 10 2018 117 014 A1.
[0008] If a period is changed in a PWM process, i.e., shortened or lengthened, the change in the period, with the same duty cycle for the shorter and longer period, leads to a change in the mean value of the output signal due to the change. Systems that use a PWM process typically have a control for the mean value of their output signal, which compensates for this effect after a change in the period. Nevertheless, the change leads to at least temporarily different output values. Furthermore, any disturbance to a control loop, especially a sudden change like the one in this case, poses the risk of overshoots and subsequent transient phenomena.
[0009] It is an object of the present invention to provide a method and a device for generating a PWM signal and an arrangement which uses this PWM signal, in which the effects of a change in the period of the PWM signal are reduced.
[0010] This object is achieved by a method, a device, and an arrangement having the features of the respective independent claim. Advantageous embodiments and further developments are specified in the dependent claims.
[0011] A method according to the invention for generating a PWM signal of the type mentioned at the outset is characterized in that an intermediate state is assumed between the first and the second state for the duration of at least one period, in which intermediate state the PWM signal has a changed duty cycle which differs from the duty cycle in the first and second states and / or has a changed period which differs from the first predetermined period and from the second predetermined period.
[0012] The method according to the invention is based on the fact that when changing from the first to the second state, the intermediate state with the changed duty cycle and / or a changed period is inserted, whereby the change in the mean value that would result from the change in the period is compensated for in advance. In this way, the effect of the change in the period is limited in time to the duration of the intermediate state. After this intermediate state, which preferably only lasts one period, the PWM signal has the desired changed properties, i.e. the second period and the original duty cycle, and the mean value of an output signal is already back at the desired value that it had before the change and does not need to be corrected. The output signal is generated under the control of the pulse width modulation signal and generally changes at least approximately linearly with the passage of time.For example, it can be provided that the output signal increases approximately linearly when the PWM signal is in one of its two digital states and decreases approximately linearly when the PWM signal is in the other of its two digital states. The output signal then has a sawtooth-like curve, with its mean value depending on the duty cycle of the PWM signal.
[0013] For example, it can be provided that in the intermediate state the duty cycle is unchanged compared to the duty cycle in the first and second states, wherein the compensation of the mean value of the output signal then takes place over a period in the intermediate state which deviates from the first and second period.
[0014] Alternatively, the intermediate state can be configured to last for one period of the second period. In this case, the change to a different period occurs already in the intermediate state, with the mean value of the output signal being compensated via a modified duty cycle. The modified duty cycle is selected to be smaller than the duty cycle set before or after the intermediate state if the first period is longer than the second period, and larger if the first period is shorter than the second period.
[0015] It should be noted that, in the context of the application, "equal" (e.g., between duty cycles) is not to be understood in a mathematically precise manner. Often, the device that generates the PWM signal is preceded by a controller that regulates the level of the output signal via the duty cycle. It is therefore conceivable that, in a practical implementation of the method, the duty cycle between the first and second states changes slightly due to the change in the controller's specification. Within a few periods of the PWM signal, such a change will be small compared to the changes resulting from the method according to the application for the duty cycle in the intermediate state.
[0016] Optimal compensation occurs when the following condition for the changed duty cycle is met in the intermediate state: where Ti and T2 indicate the first and second periods, respectively, and d and d' the duty cycle and the changed duty cycle, respectively. This calculation is based on the assumption that the output signal changes at least approximately linearly with time, which is the case in many applications.
[0017] In a further advantageous embodiment of the method, at least one measuring time point is provided within the intermediate state for measuring the output signal for control purposes.
[0018] The influence on the control loop can preferably be further minimized by reading the output signal used for a control loop at suitable times within the intermediate state. In particular, the time of the measurements during the intermediate state can be selected so that at the measurement time the output signal has just the desired mean value. By such a forward-looking selection of the measurement time, control deviations are further minimized. Again, assuming that the output signal changes at least approximately linearly with time, the following advantageously applies for suitable times tma, tmb:
[0019] A device according to the invention is configured to generate a PWM signal according to such a method. An arrangement according to the invention comprises such a device for generating such a PWM signal. This results in the advantages described in connection with the method. For example, the clocked circuit is a voltage converter, a frequency converter, and / or a PFC stage of a switched-mode power supply. The clocked circuit is advantageously operated in a continuous mode when the method according to the invention is implemented.
[0020] The invention is explained in more detail below using an exemplary embodiment and the accompanying figures. The figures show:
[0021] Fig. 1 is a schematic circuit diagram of an arrangement with a device for generating a PWM signal;
[0022] Fig. 2 is a diagram showing signal waveforms of a prior art arrangement;
[0023] Fig. 3 shows a representation of time courses of signals of an application-specific arrangement; and
[0024] Fig. 4 is a schematic circuit diagram of another arrangement with a device for generating a PWM signal.
[0025] In Fig. 1, as a first example of an arrangement in which a PWM signal is used, a current controller 1 is shown which is controlled by a device 10 for generating a PWM signal, hereinafter referred to as “PWM generator 10”.
[0026] The current controller 1 is supplied with an input voltage Uin at input terminals 2. At output terminals 3, the current controller is connected to an inductive load 4. The inductive load 4 can, for example, be a coil 6 of an electromagnetically actuated valve, with the current controller 1 being used to adjust a load current lout flowing through the coil to a desired value. The output current lout thus represents an analog output signal whose magnitude can be varied by the current controller 1.
[0027] For this purpose, the current controller 1 has a semiconductor switch 5, followed by the coil 6. Furthermore, a diode 7 is integrated into the current controller 1 in a known manner as a freewheeling diode to enable current flow through the coil 6 even when the semiconductor switch 5 is open. If the current controller 1 is to supply a non-inductive load 4, a separate coil can be arranged within the current controller. The structure of the current controller would then correspond to that of a buck converter.
[0028] The semiconductor switch 5, which can be, for example, a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor), or a bipolar transistor, is controlled by a PWM signal from the PWM generator 10 via a PWM signal line 11. The control is shown purely schematically in Figure 1.
[0029] The current controller 1 shown in Figure 1 is controlled, for example, to a constant output current lout. For this purpose, a feedback line 12 is provided, which transmits the level of the output current lout to a control circuit 13, which specifies a duty cycle d to be set for the PWM generator 10 at a control output 14. The output current lout is measured by a current measuring sensor 8, which here is formed, for example, by a shunt resistor.
[0030] The current controller 1 or the arrangement shown in Figure 1 represents only an example of a circuit in which a PWM signal is used to vary an output variable, here the output current lout.
[0031] The method according to the application, explained in more detail below, can also be used for other devices, e.g., other voltage converters, inverters, and switching power supplies, particularly for PFC stages. Figure 4 below shows an application of the method according to the application for a switching power supply with a PFC stage.
[0032] The PWM generator 10 is configured to independently vary the period duration of the PWM signal used to control the semiconductor switch 5 on the PWM signal line 11 according to predetermined rules, thereby distributing interference emissions over a larger frequency range and correspondingly reducing the interference signal density. For this purpose, for example, the period duration can be changed after a specific number of periods, possibly also randomly selected from a range, within a certain range of period durations, possibly also randomly selected from a range. In alternative embodiments, the PWM generator 10 can change the period duration not independently, but rather controlled via another input signal. Figure 2 shows the effect of a change in the period duration of a PWM signal on the output current lout according to the prior art.
[0033] Figure 2 shows a schematic diagram of various signal waveforms as a function of time t. The lower part of the diagram shows a time waveform 30 of a PWM signal, where at a time t = 0, the PWM signal changes from a first period Ti to a PWM signal with a second period T2. To the left of the Y-axis in the diagram, one period with the first period Ti is shown, and to the right of the Y-axis, two periods with the second period T2 are shown.
[0034] The PWM signal alternates between two states, e.g., logic "1" and logic "0", wherein in the logic "1" state, the semiconductor switch 5 is switched on in the first part of each period in the arrangement of Figure 1 and the semiconductor switch 5 is not switched on in the remaining part of each period.
[0035] The upper part of Figure 2 shows a time curve 31 showing how the output current lout, for example, of the circuit shown in Figure 1, changes: It increases essentially linearly when the PWM signal is at logic "1" and decreases essentially linearly when the PWM signal is at logic "0." On average, this will result in an average output current with a time curve 32 at the output terminals 3 shown in Figure 1, given a suitable design.
[0036] Due to coil 6, the time characteristic 31 of the output current lout is not exactly linear, but rather exhibits elements of an exponential curve. Since the time constant, which is determined by the inductance values of coil 6 and parasitic resistances and / or capacitances (e.g., coil 6 itself and the shunt resistor used as current sensor 8), is a factor of » 1 greater than the period Ti, the time characteristic 31 can be specified to a good approximation by straight line segments.
[0037] Due to the change in the period duration at time t = 0, the mean value of the output current lout specified in the time characteristic 32 changes. For the time characteristic 32, a computational averaging over one period each has been performed in Figure 2, which is why the change here occurs abruptly at time t = 0. In a real implementation, the mean value changes with the time constant previously mentioned for the arrangement in Figure 1 and determined by the coil 6 and the parasitic resistances and / or capacitances. Nevertheless, the mean value is permanently shifted, which, according to the state of the art, would then have to be compensated for by the control 13.
[0038] In order to prevent or reduce this permanent change in the mean value of the output current lout, which can only be compensated by the control 13, it is provided according to the application to insert an intermediate state of at least one period duration into the signal curve between the first state of the PWM signal with the first period duration T1 and the second state of the PWM signal with the second period duration T2 and the duty cycle d, as shown in Figure 3.
[0039] Figure 3 shows the time courses 30 - 32 of the PWM signal, the output current lout and the mean value of the output current lout in the same way as Figure 2.
[0040] At time t = 0, the PWM signal does not immediately switch to the second state, but rather enters an intermediate state. In the example shown, this has the length of one period of the period duration T2. Unlike in the second state, however, a different duty cycle than the actual duty cycle d is selected, specifically a duty cycle d' = t' / T2.
[0041] In the present case, the time period t' for which the PWM signal is set to the value logical "1" is shorter than the corresponding time period t2 in the subsequent periods. In this way, the mean value of the output current lout is higher in this period of the intermediate state than for times t < 0. The reduction in the mean value that occurs when changing from the intermediate state to the second state just compensates for this increase, so that an average value is then assumed that corresponds to the mean value at times t < 0. The increase or decrease in the mean value introduced when changing the period duration in the prior art is therefore advantageously compensated by the intermediate period. A comparison with Fig. 2 shows that, moreover, the increase in the mean value of the output current lout in the period of the intermediate state is smaller than the permanent increase without the compensation according to the invention.
[0042] Assuming that the output current lout increases or decreases linearly when the PWM signal assumes one or the other logical state, the following equation results from geometric considerations for the necessary changed duty cycle d':
[0043] It should be noted that for an output current lout that does not vary linearly in sections, a corresponding condition for the changed duty cycle can also be specified in individual cases, with the advantage that the mean value does not change permanently. It should also be noted that the duration of the intermediate state, which in this case is one period of the second period duration, can also be selected differently, in which case the changed duty cycle d' will also be different. It is also conceivable to select the duration of the intermediate state such that the "changed" duty cycle d' corresponds exactly to the duty cycle d – i.e., the duty cycle does not change during the entire process.
[0044] An advantage of the method according to the application is that a deviation in the mean value of the output current lout only occurs during the period of the intermediate state of the PWM signal. Since the time constant with which the mean value of the output current lout changes in a circuit arrangement such as that shown in Figure 1 is generally much greater than the period of the intermediate state, disturbance of the control circuit 13 is minimal.
[0045] In an advantageous embodiment of the method, the influence on control loop 13 can be further minimized by reading the output signal—here, in the example, the output current lout, which is used for control loop 13—at suitable times within the intermediate state. Control loop 13 is often implemented digitally, so that the output signal is measured at specific, discrete times and used for control purposes. If the time of the measurements during the intermediate state is selected such that the time profile 31 of the output current lout intersects the actually desired mean value of the output current lout, there is no control deviation caused by the change in the PWM period length.
[0046] As Figure 3 shows, such an intersection point occurs at times tma and tmb, respectively. Mathematically, these two measurement times, tma and tmb, are defined by the following conditions, assuming linear curves of the output current lout:
[0047] If - controlled by the PWM generator 10 - these times tma or tmb are specified to the control loop as measuring times for the output current lout, the control loop 13 is not disturbed during the inserted intermediate state and no control deviations occur.
[0048] Figure 4 shows a switching power supply 20 having a PFC stage 21. This PFC stage 21 represents a further example of an arrangement in which a PWM signal generated by a device 10 in a method according to the application is used.
[0049] A rectifier (also called an AC / DC converter) is connected upstream of PFC stage 21, which converts an AC voltage U~ supplied on the input side into a DC voltage. This voltage is applied to input terminals 2 of PFC stage 21. On the output side, a voltage converter 23, also called a DC / DC converter, is connected downstream of PFC stage 21 at output terminals 3. This converter supplies a load 4.
[0050] The PFC stage 21 reduces reactive power caused by distortion, thereby reducing the ingress of interference signals into the network providing the input AC voltage U. In terms of its basic design, the PFC stage 21 represents a current-controlled converter and is similar in structure to the current controller 1 in Figure 1.
[0051] The PFC stage 21 comprises a series circuit of a coil 6 and a diode 7, which is arranged between one of the input terminals 2 and one of the output terminals 3. A clocked switching element 5 is arranged between a center tap of the series circuit and the other of the input terminals 2 or output terminals 3. A capacitor 9 is connected in parallel with the output terminals 3.
[0052] As in the embodiment of Figure 1, the semiconductor switch 5 is controlled in a clocked manner by the device 10 via a PWM signal line 11, preferably in a continuous operation. A current sensor 8 is also present, which is arranged downstream of the coil 6 here. A signal measured by the current sensor 8 is fed via a feedback line 12 to a control circuit 13, at whose control output 14 a duty cycle d is output. The device 10 generates the PWM signal according to the specified value for the duty cycle d.
[0053] The device 10 is configured to independently change the period of the PWM signal, as also explained in connection with the exemplary embodiment of Figure 1. This distributes interference emissions over a larger frequency range and, accordingly, further reduces the interference signal density during operation of the switching power supply 20.
[0054] List of reference symbols
[0055] 1 current controller
[0056] 2 input ports
[0057] 3 output ports
[0058] 4 Last
[0059] 5 semiconductor switches
[0060] 6 coil
[0061] 7 (freewheeling) diode
[0062] 8 Current measuring sensor
[0063] 9 Capacitor
[0064] 10 Device (PWM generator)
[0065] 11 PWM signal line
[0066] 12 Feedback line
[0067] 13 Control loop
[0068] 14 Control output
[0069] 20 switching power supply
[0070] 21 P FC stage
[0071] 22 rectifiers (AC / DC converters)
[0072] 23 Voltage converters (DC / DC converters)
[0073] 30 Time course of the PWM signal
[0074] 31 Time course of the output current lout
[0075] 32 Time course of the mean value of the output current lout
[0076] Uin input voltage lout output current
[0077] Ti first period duration
[0078] T2second period ti first period t2first period t' changed period d duty cycle d' changed duty cycle tma, tmb measuring time
Claims
Claims: A method for generating a pulse-width modulation signal that transitions from a first state with a first predetermined period (Ti) to a second state with a second predetermined period (T2), wherein the pulse-width modulation signal has the same predetermined duty cycle (d) in both the first and second states, characterized in that an intermediate state is assumed for at least one period between the first and second states, in which the pulse-width modulation signal has a modified duty cycle (d') that differs from the duty cycle (d) in the first and second states and / or has a modified period that differs from both the first predetermined period (Ti) and the second predetermined period (T2). The method according to claim 1, wherein the intermediate state lasts for one period of the second period (T2).A method according to claim 2, wherein the modified duty cycle (d') is smaller than the duty cycle (d) when the first period (Ti) is longer than the second period (T2). A method according to claim 2, wherein the modified duty cycle (d') is larger than the duty cycle (d) when the first period (Ti) is shorter than the second period (T2). A method according to any one of claims 1 to 4, wherein, controlled by the pulse width modulation signal, an output signal is generated which changes at least approximately linearly with time. A method according to claim 5, wherein the modified duty cycle (d') is selected such that the mean value of the output signal is the same in the first and second states. A method according to claims 2 and 6, wherein the following applies to the modified duty cycle (d'):
8. Method according to any one of claims 1 to 7, wherein at least one measurement time (tma, tmb) is provided within the intermediate state for a measurement of the output signal for control purposes.
9. Method according to claims 7 and 8, wherein the following applies to the at least one measurement time (t ma, tmb):
10. Method according to claim 1, wherein in the intermediate state the duty cycle (d) is unchanged compared to the duty cycle (d) in the first and second states.
11. Device for generating a pulse width modulation signal, which is configured to perform a method according to any one of claims 1 to 10.
12. Arrangement for providing an output signal, comprising a device according to claim 11 for generating a pulse width modulation signal and a clocked circuit controlled by the device.
13. Arrangement according to claim 12, wherein the clocked circuit is a voltage converter, an inverter and / or a PFC stage of a switched-mode power supply.
14. Arrangement according to claim 12 or 13, wherein the clocked circuit is operated without gaps.