Substrate comprising nanostructures and nanowires

Abstract

A microstructured substrate comprising a main body and a plurality of elongated elementary microstructures extending from the main body, wherein the microstructured substrate comprises a plurality of nanowires positioned on at least one area of the surface of the main body and on the surface of the elementary microstructures that extend from the main body over said area.

Description

[0001] Description Title of the invention: Substrate comprising nanowires [1]The present invention is in the field of micro-devices for energy storage, and relates more particularly, but not exclusively, to planar and / or microstructured substrates integrating on their surface substructures of dimensions measurable at the nanometric scale. The method for manufacturing said substructures is also an object of the present invention. [2] The bibliographic references in the following text are noted in this way in the text of the description: []; and listed in the table of references. State of the art [3]The substrates used in the manufacture of energy storage devices are for example made from supports made of semiconductor or dielectric materials and may be in the form of a thin disc, also referred to as a “wafer”.Initially, such a support has a flat surface corresponding to a two-dimensional, 2D, topology. However, depending on the destination of the substrate, it is advantageous to dig the surface of the substrate at the microscale or nanoscale so that it has a three-dimensional, 3D, topology, thus defining a microstructured or nanostructured substrate. [4] Such a microstructured substrate has a useful surface, i.e. the developed surface, which is greater than a flat (or smooth) substrate. A microstructured substrate allows, for example, the deposition of a greater quantity of materials on its surface and more particularly on the lateral surfaces of the microstructures, which can, for example, improve the performance of an electrical energy storage device, increase the number of components that can be integrated on a substrate, etc.[5]Microstructured silicon substrates having a surface gain linked to their rough structure are described, as for example in the patent application [1]. Such a microstructured structure is generally produced by a treatment on its surface such as chemical or physical etching, growth of micro-structures, or electrolytic deposition of materials inside micrometric or even nanometric molds, followed by dissolution of the mold.[6]Energy storage devices are not immune to the constant need to miniaturize electronic components and there is a constant need to develop solutions that make it possible to increase the useful surface area visible outside the substrates while retaining the dimensions of the original support from which the substrate is made; and this is all the more so since it has been proven that increasing the useful surface area improves the performance of all-solid-state micro-batteries, micro-capacitors or micro-supercapacitors. [7]To meet this demand, a first objective of the present invention consists in modifying the surface of a microstructured or nanostructured substrate to increase its useful surface area. [8]Furthermore, it is known to use methods for forming thin layers of materials on substrates, for example methods for producing layers of lithiated materials.These layered substrates are used in particular in batteries, for example for the formation of electrodes or electrolytic barriers, or any other electrical storage device. These layers can be deposited by an atomic layer deposition technique (known as ALD) from precursors, by a chemical vapor deposition technique (known as ALCVD), or by an atomic layer epitaxy deposition technique (known as ALE). In particular, the ALD technique is a thin-film deposition technique that relies on gas-surface reactions to expose the surface on which a layer of a material is to be deposited to different successive chemical precursors.[9]The patent application [2] describes a method implementing an atomic layer deposition of a precursor of a first metal, such a precursor being able to be an organometallic complex comprising for example a transition metal (nickel, etc.) or another type of metal such as aluminum; said method making it possible to manufacture a compound containing thin layers of lithiated material. Such layers have thicknesses of 1 nm to 1 µm, made up of complex, electrochemically active materials, and which are, among other things, homogeneous and adapted to conform to the more or less complex reliefs of the surface of a microstructured substrate.

[0010] A second objective of the present invention consists in modifying the surface of a substrate to increase its useful surface by implementing such methods of depositing layers compatible with microstructured substrates whose surface is complex and is difficult to access by all the surface treatment methods of the state of the art.

[0011] Patent application [3] describes a composite substrate consisting of a glass layer coated with a metal layer typically of Molybdenum (Mo), indium (In) micropillars perpendicular to the surface of the substrate and the upper part of which is convex, a layer of Copper (Cu) covering said convex upper part of these In micropillars and copper (I) sulfide (Cu2S) nanowires starting only from the upper part of the micropillars.Description of the invention

[0012] The present invention relates to a microstructured substrate comprising a main body and a plurality of elementary microstructures of elongated shape extending from the main body, characterized in that the microstructured substrate comprises a plurality of nanowires positioned on at least one area of ​​the surface of the main body and on the surface of the elementary microstructures which extend from the main body over said area. Such a configuration of the substrate integrating the nanowires makes it possible to further increase the developed surface by at least a factor of 10, and thus to improve the storage capacity of a storage device integrating the above-mentioned substrate.

[0013] In the context of the present invention, the term "microstructured" or "microstructure" applies indifferently to surfaces having reliefs whose shapes have dimensions which are measurable both at the microscale and at the nanoscale.

[0014] Preferably, the elementary microstructures of elongated shape are micropillars or microtubes (which are micropillars hollowed out in their centers).

[0015] The main body and the elementary microstructures which extend over said main body of the microstructured substrate according to the invention are advantageously made of the same material, preferably a material selected from materials comprising, or even composed exclusively of, silicon Si, silicon dioxide SiO2, gallium arsenide GaAs, silicon nitride Si3N4 and indium phosphide InP.

[0016] Preferably, the elementary microstructures comprise a section chosen from a circular, elliptical, rectangular, square and triangular section.

[0017] Preferably, the nanowires comprise a material selected from oxides, preferably selected from SiO2, ZnO and TiO2, and preferably the nanowires are composed exclusively of SiO2.

[0018] Preferably, the nanowires have a diameter section of 20 to 250 nm, and a length of 100 nm to 10 µm. Advantageously, the nanowires have a diameter section of 50 to 200 nm, and a length of 0.5 to 2 µm. The structure of these nanowires is characterized by an electron microscopy technique and more particularly by scanning electron microscopy (SEM), and the evaluation of the dimensions and structures of the nanowires is carried out from the images collected by this technique.

[0019] Preferably, the area comprising nanowires has a developed surface area of ​​2 to 50 times the developed surface area of ​​said area devoid of nanowires, and advantageously 10 to 40 times, or even 15 to 35 times. The surface gain linked to the presence of nanowires is measured indirectly by electrochemical method via the use of a capacitive, faradic or pseudo-capacitive material whose electrochemical properties are intrinsic to the developed surface.The developed surface is the representation of the total surface introduced via the creation of porosities, cracks through the addition of micro and nano-objects compared to the initial object; which is generally represented by a surface gain which is a numerical value greater than 1 (1 being the representation of the surface gain of the initial object).

[0020] The present invention also relates to a method for manufacturing a planar substrate or a microstructured substrate presented previously within the scope of the invention, comprising the following steps: a- covering a planar or microstructured support with a thin layer of SiO2; b- depositing a layer of a non-oxidized metal by an atomic layer deposition technique; c- carrying out an optical lithography step on at least one area of ​​the surface of the planar or microstructured support having undergone steps a- and b-; d- carrying out an etching treatment; and e- carrying out a thermal annealing, preferably by implementing at least one temperature step.

[0021] Step a- advantageously comprises a deposition of a nanometric thin film of SiO2 by low pressure chemical vapor deposition, also known by the English terminology "low pressure chemical vapor deposition", also designated by the acronym "LP CVD".

[0022] Step b- comprises an atomic layer deposition, better known by the English terminology “Atomic Layer Deposition”, also designated by the acronym “ALD”. The layers deposited by such an atomic layer deposition technique are deposited from precursors, as described in reference [2], by a chemical vapor deposition technique (technique called “Chemical Vapor Deposition” in English and commonly designated by the acronym “ALCVD”), or by an atomic layer epitaxy deposition technique (technique called “Atomic Layer Epitaxy” in English and commonly designated by the acronym “ALE”). In particular, the ALD technique is a thin-film deposition technique which relies on gas-surface reactions in order to expose the surface on which it is desired to deposit a layer of a material to different successive chemical precursors.

[0023] Step c- of optical lithography in order to limit the growth of SiO2 nanowires only on the areas of the substrate on which the presence of the nanowires is desired. Such a step allows the formation of a resin mask which protects these areas of interest of the substrate on which the presence of the nanowires is desired, and which are areas of interest of a few mm2, and leaves “bare” the material resulting from the precursor (the catalyst) on the rest of the surface of the substrate.

[0024] Step d- of dry etching of the catalyst in order to keep it only on the areas of interest is advantageously carried out by reactive thermal etching, also designated by the acronym “RIE”, preferably the RIE etching is an etching using a RIE-ICP device marketed as a reactor by the company Sentech®, for example an apparatus known under the reference Sentech Si500 (ICP-RIE).Such dry etching is based on the generation of a reactive plasma based on a gaseous mixture of Cl2 / Ar (10sccm, 30sccm) in a reactor at a pressure of 5 mTorr, preferably at 10°C.

[0025] Step e- is advantageously an annealing using a vapor-liquid-solid synthesis technique, also designated by the acronym "VLS"; such a technique has the advantage of not requiring the use of a silane precursor in the gas phase as conventionally known in the literature. The growth is directly correlated on the one hand, to the passage into the gas phase of the thin layer of SiO2 generated in step a- and on the other hand, to the presence of the catalyst generated in step b-. Advantageously, step e- comprises at least two stages: the first stage allowing the formation of the metal clusters in order to control the diameter of the future nanowires; the second level allowing the phenomenon of nanowire growth to be triggered.

[0026] Preferably, the non-oxidized metal deposited in step b- is selected from Pt, Ag, Au, Ga, In, Ti, Sn, Zn, Sb, Cu, Ni, Be, Fe, Co, Cr, Al, Ru, Rh and Pd, preferably it is Pt. It should be noted that the precursor of the first metal may be in liquid or powder form. For example, the precursor of the first metal may be selected from the following precursors: MeCpPtMe3, FeCl2, FeCp2, Fe(thd)3, La(thd)3, CoCp2, MnCp2, Mn(thd)3, NiCp2, TiCl4, NbOEt5, Cr(OCl)2, preferably it is MeCpPtMe3.

[0027] Preferably, step e- comprises two temperature levels: a first level of 200 to 1200°C applied for less than 5 min; and a second level of 300 to 1400°C applied for less than 15 min.

[0028] The present invention also relates to a use of a microstructured substrate as presented previously in the context of the invention for the manufacture of a micro-device for storing energy, preferably selected from batteries, supercapacitors and dielectric and electrolytic capacitors of micrometric size, or even nanometric size, of energy harvesting components or of a sensor-type device requiring the use of a large specific surface area.

[0029] The present invention is also described in the detailed description which follows, with the aid of the experimental part which details certain embodiments with the aid of examples, given solely for illustrative purposes and which should not be considered as limiting, and of the figures briefly described in the part which follows. Brief description of the figures

[0030] [Fig.1] – Figure 1 represents an XRR (X-Ray Reflectometry) measurement on a thin NiO layer deposited by ALD on a silicon substrate;

[0031] [Fig.2] – Figure 2 represents a SEM (Scanning Electron Microscopy) view following the synthesis of nanowires by the VLS (Vapor-Liquid-Solid mechanism) technique;

[0032] [Fig.3] – Figure 3 represents the profile of the rapid thermal annealing (RTA) used for the growth of SiO2 nanowires;

[0033] [Fig.4] – Figure 4 represents XRR measurements of Pt thin layers of 5, 10, 15, 20 nm thickness;

[0034] [Fig.5] – Figure 5 represents SEM images for a thickness of the SiO2 layer of 15 nm and of Pt of 10 nm

[0035] [Fig.6] – Figure 6 represents a magnification by SEM on the surface of a substrate having undergone annealing at 900°C for 1 min;

[0036] [Fig.7] – Figure 7 represents a magnification by SEM on the surface of a substrate having undergone annealing at 950°C for 1 min;

[0037] [Fig.8] – Figure 8 represents a SEM magnification on the surface of a substrate having undergone annealing at 900°C for 1 min, followed by annealing at 1050°C for 3 min;

[0038] [Fig.9] – Figure 9 represents a SEM magnification on the surface of a substrate having undergone annealing at 950°C for 1 min, followed by annealing at 1100°C for 3 min; and

[0039] [Fig.10] – Figure 10 represents the normalized surface capacitance as a function of the scanning speed of thin RuO2 films deposited on different types of substrates allowing the estimation of the effective electrochemical gains. Experimental Part

[0040] Materials and methods The reagents used are marketed by the company STREM® Chemical and used without further purification.

[0041] Measurement of surfaces The surface gain (Area Enhancement Factor, AEF) is measured indirectly by cyclic voltammetry in a 3-electrode cell.The electrolyte used is sulfuric acid (H2SO4) diluted to 0.5 M, the reference electrode is an Ag / AgCl electrode, the counter electrode is platinum, the working electrode corresponds to the fabricated sample covered with a thin layer of platinum (30 nm) deposited by ALD (the substrate microstructure, the hierarchical skeleton). The scanning speed is 50 mV / s.

[0042] Measurement of the thicknesses of the deposited thin layers The thickness of the layers is measured by X-ray reflectivity (XRR) which is an interferometry technique that allows to obtain quantitative information on the roughness at the interfaces, the density as well as the thickness of thin layers, amorphous or not. After a phase of alignment of the height and the surface of the sample, the measurement is carried out. Such a measurement consists of directing an X-ray beam onto the surface of a sample at a low theta angle of incidence and collecting the reflected intensity.A measurement allowing the reflected intensity to be plotted as a function of the angle of incidence (2θ) is obtained, as shown in Figure 1. The curve generally describes a plateau for 2θ < θc, where θc corresponds to the critical angle, then a decrease comprising one or more oscillations whose period is related to the thickness of the layer via the following relation: ^^ Θm² = ^ ^^^² + θc² equation 1 With m, the order of the oscillations and θ. mthe corresponding angle in radians as illustrated in Figure 1 and d, the thickness of the layer.

[0043] The slope of the oscillations allows us to go back to the surface roughness. And the change in slope after the oscillations allows us to go back to the density of the layer. X-ray reflectivity is a technique that allows us to precisely measure the thickness of a thin layer (from 5 to 100 nm approximately) precisely using equation 1 provided that the layers are not very rough, which makes it a technique of choice for the ALD deposits that are carried out as part of this work. The X-ray reflectivity measurements were carried out on a SMARTLAB ® copper rotating anode system from Rigaku ®.

[0044] Observation of the surface topography of the samples was carried out by scanning electron microscopy (SEM) in top view, cross-section and grazing incidence using an FEI Magellan 400™.

[0045] The size distribution of the nanowires is carried out using the SEM and the size measurements of the nanowires are carried out using the ImageJ™ software.

[0046] In the context of the invention, a mass percentage expressed in % m / m, defines the mass percentage of an ingredient used in the preparation and taken relative to the total mass of the object considered: a mixture, a material (composite, etc.), a membrane, etc.Examples

[0047] Part 1: Synthesis of a Silicon oxide SiO2 by dry oxidation (LP CVD, Low Pressure Chemical Vapor Deposition) -Wafer cleaning: piranha (mixture of sulfuric acid H₂SO₄ and hydrogen peroxide H₂O₂) 1:1 (20 min), deionized water rinsing, N2 drying, HF 1% (2 min), edi rinsing, N2 drying; -Introduction of the silicon wafer into the oven at 500°C, under 2 slm (standard liter per minute, at T=0°C and P=1bar) of N2; -Temperature rise to 675°C for 30 min (10°C / min); -Temperature rise to 900°C for 1 h (10°C / min); -Pre-oxidation at 900°C for 30 min, with 2 slm of N2 and 0.2 slm of O2; -Oxidation at 900°C for 42 min (15 nm of SiO2 – deposition rate 0.357 nm / min), with 2 slm of O2; -Temperature reduction to 500°C for 1 h, with 2 slm of N2.

[0048] Part 2: Atomic Layer Deposition of a Pt catalyst (ALD)

[0049] A platinum layer is deposited by ALD, the reagents are “Pt” and dioxygen.

[0050] The sample obtained in Part 1 is placed in the ALD enclosure (Beneq model TFS200), the pressure is lowered to 2 mBar and the temperature is adjusted to 300°C.

[0051] To form an atomic monolayer, different steps (corresponding to a cycle) are necessary: ​​nitrogen is injected for 500 ms into the source containing a first reagent (1) which is MeCpPtMe3, i.e. (trimethyl)methylcyclopentadienylplatinum(IV), declared 99% pure from STREM® Chemical) whose temperature is maintained at 54°C, a waiting time of 100 ms is respected in order to increase the pressure of the precursor enclosure and then the source opens for a duration of 500 ms (pulse time). Then a 2-second purge is carried out to expel excess species and reaction products. A second reactant (2) in the form of gaseous O2 is then injected for a duration of 500 ms and then a 1-second purge is carried out.The deposition rate is 0.83Å / cy (Angstroms per cycle) and allows precise control of 5 to 60 nm of the deposited thickness.

[0052] Part 3: Optical lithography to select the areas of interest

[0053] 1-Cleaning and deoxidation of the wafer:

[0054] The plate obtained in part 2 is placed in a beaker of acetone for 5 min then in isopropanol for 5 min, allowing the plate to be degreased. The plate is then dehydrated at 110°C for 10 minutes.

[0055] 2-Resining and insolation:

[0056] Coating with an HMDS adhesion promoter (speed = 2000 revolutions per minute (rpm); acceleration = 1000 revolutions per minute per second (rpm / s); time = 20s).

[0057] Coating with AZ1505 resin (speed = 3000 rpm; acceleration = 1000 rpm per second; time = 20s).

[0058] Annealing 1 min at 110°C, no relaxation time.

[0059] Insolation 3s in Hardcontact, no relaxation time.

[0060] Development 50s in MIF 726 then 30s deionized water.

[0061] This optical lithography allows the formation of a resin mask which protects the areas of interest of a few mm2 and leaves the platinum "bare" on the entire substrate.

[0062] Part 4: Dry etching of the catalyst in order to preserve it only on the areas of interest

[0063] The etching of the platinum is carried out by RIE-ICP (Sentech®), this physicochemical dry etching is enabled by a physical attack of the Cl2 / Ar plasma (10sccm, 30sccm) in a reactor at a pressure of 5 mTorr and at a temperature of 10°C. The ICP source generates a high density plasma thanks to an inductive coupling between the RF antenna and the plasma. The RF antenna creates an alternating RF magnetic field and induces RF electric fields which accelerate the electrons which participate in the ionization of the gas molecules. To etch platinum, the power of the source is set at 600W while that of the RF generator is set at 200W. The etching speed is 2.8 Å / s.(Angstroms per second, or 10-10 meters per second: this is the speed at which platinum is etched to be structured).

[0064] Part 5: Rapid Thermal Annealing (RTA)

[0065] Annealing is carried out in two stages under a nitrogen atmosphere in a Flash annealing furnace marketed by the company Jipelec®.

[0066] The synthesis technique used is called vapor – liquid – solid (VLS). A first stage at 1000°C (10°C / sec) is maintained for 1 min to dewet the Pt catalyst, a step during which small Pt clusters, which are droplets of a few tens of nanometers in diameter, are formed on the surface of the SiO2 and form SiO in vapor phase. The SiO diffuses into the droplets and precipitates at the metal / substrate interface during a second supersaturation / precipitation phase. This results in growth of SiO2 nanowires.The growth is directly correlated to the passage into the gas phase of the SiO2 layer previously synthesized on the substrate in Part 1 and to the presence of the catalyst (here platinum).

[0067] A second stage at 1100°C is maintained for 5 min in order to promote the growth of the SiO2 nanowires. The diameter, length, density (number of nanowires per mm2) of the SiO2 nanowires are controlled by the properties of the initial thin films of SiO2 and Pt as well as by the annealing parameters (T° and holding time of the stages at high temperature, the first stage allowing the formation of Pt clusters in order to control the diameter of the future nanowires; and the second stage in order to provoke the growth phenomenon by controlling the length of the nanowires). A picture obtained by SEM magnification is shown in Figure 2, with a scale to observe the dimensions of the nanowires. Figure 3 shows the temperature profile of the stages as a function of time.Analyses and results

[0068] Different silicon samples were treated after thermal annealing by controlling different parameters of thickness of the SiO2 thin layer and Pt layer (5, 10, 15, 20 nm). The Pt thin layers were measured by XRR, the diagrams are shown in Figure 4.

[0069] The samples are observed by SEM microscopy.

[0070] By varying the thickness of SiO2 from 10 to 15 nm, the inventors observed the presence of very solid nanowires in the form of matches which are strictly perpendicular to the surface with an average length greater than 1 µm and a diameter which can be greater than 80 nm.

[0071] A statistical study of the SEM images makes it possible to determine the average parameters of diameter and length of the nanowires. The general method consists of analyzing images through processing that allows the boundaries of the objects that compose them to be delimited.An analysis of the image then makes it possible to count pixel by pixel the space occupied by each object (length, diameter, intersections with other objects, surfaces etc.).

[0072] The results are shown in Table 2 for a thickness of the Pt layer of 15 nm: [Table 2]

[0073] . Other results are shown in Table 3 for a SiO2 layer thickness of 15 nm and Pt of 10 nm, and the obtained images are shown in Figure 5: [Table 3]

[0074] Study of the phenomena linked to the temperature stages:

[0075] the role of the two annealing stages was determined using SEM images. The first allows the dewetting of the Platinum via the formation of Pt droplets on the surface under which the evaporated SiO2 condenses during the second temperature stage: -figure 6 corresponds to a substrate having undergone annealing at 900°C for 1 min; -figure 7 corresponds to a substrate having undergone annealing at 950°C for 1 ; - Figure 8 corresponds to a substrate having undergone annealing at 900°C for 1 min, then at 1050°C for 3 min; - Figure 9 corresponds to a substrate having undergone annealing at 950°C for 1 min, then at 1100°C for 3 min.

[0076] Figures 6 to 8 show the importance of the first stage in promoting the dewetting of the catalyst (Pt) for the growth of the nanowires. Figure 8 shows in particular that the first stage at 900°C is insufficient to promote growth during the second stage. Figure 9 shows that a first stage at 950°C followed by a second at 1100°C allows the start of growth to be obtained. This figure 9 also shows the importance of the duration of the second stage on the length of the nanowires which is applied here for a duration of 3 min (whereas for the other results described in this experimental part the second stage is applied for 5 min).

[0077] Measurement of the Surface Gain provided by the nanowires:

[0078] The inventors have demonstrated that the high surface capacity of the components integrating the substrates according to the invention was closely linked to their structure, and even when said structure comprises an infinity of structural elements that are complex from the point of view of the architecture of the material, or even highly entangled with each other. The high surface capacity resides in a large surface expressed in relation to the projected surface, this being provided by the presence of micropillars (microstructured substrate) covered by nanowires.The methodology adopted to determine the surface gain consists of using a parameter designated by the English term "Area Enlargement Factor", also known by the acronym "AEF", and comparing the AEF of the different structures and the contribution of each of them, the AEFs being measured independently, first in 2D flat surface, then 3D and 2D with nanowires and 3D with nanowires.

[0079] The different measurements were carried out under the same conditions to calculate the surface gain (AEF) measured by cyclic voltammetry in a 3-electrode cell. The electrolyte used is sulfuric acid (H2SO4) diluted to 0.5M, the reference electrode is an Ag / AgCl electrode, the counter electrode is platinum, the working electrode is platinum (30 nm) deposited by ALD on the sample to be measured (the microstructured "skeleton"). The scanning speed is 50 mV / s. The projected area seen during the measurement is 0.407cm².The results are presented in Table 4 below: [Table 4].

[0080] Thus, Table 4 shows that the measurement method makes it possible to go back to the calculated 3D gains (table entries in lines 3 and 4) from the models of the 3D structures of the micro-tube type. This method demonstrates that the nanowires provide a surface gain of 2 to 19 on the examples cited in the rest of Table 2, respectively at the entries in lines 5 to 8.

[0081] An identical measurement was carried out using a Super-capacitor electrode material (RuO2) which shows a gain of 10 on microstructures having a gain of 50 (i.e. a total surface gain of 50x10 = 500). It was thus shown that the surface gain of the microstructures is between 50 and 70, that of the nanowires between 4 and 10.In Figure 10, the capacitance is represented as a function of the scanning speed of thin layers of RuO2 on different types of substrates, thus the inventors were able to demonstrate in a completely unexpected way, that the cumulative gains do not add up but multiply, making it possible to achieve gains between 200 and 700. In this Figure 10, we find the capacitance of thin layers of RuO2 making it possible to go back to a surface gain of 50 (squares) for a micro-tube type structure and 500 (rounds) on a hierarchical substrate compared to a flat surface (triangles). References

[0082] The following table lists the references cited previously in the text: [Table 1].

Claims

Claims

1. Microstructured substrate comprising a main body and a plurality of elementary microstructures of elongated shape extending from the main body, characterized in that the microstructured substrate comprises a plurality of nanowires positioned on at least one area of ​​the surface of the main body and on the surface of the elementary microstructures which extend from the main body over said area.

2. Microstructured substrate according to claim 1, in which the main body and the elementary microstructures which extend over said main body are made of the same material, preferably a material selected from materials comprising, or even composed exclusively of, Silicon, silicon dioxide SiO2, gallium arsenide GaAs, silicon nitride Si3N4 and indium phosphide InP.

3. Microstructured substrate according to one of claims 1 or 2, wherein the elementary microstructures comprise a section chosen from a circular, elliptical, rectangular, square and triangular section.

4. Microstructured substrate according to one of claims 1 to 3, wherein the nanowires comprise a material selected from oxides, preferably selected from SiO2, ZnO and TiO2, and preferably the nanowires are exclusively composed of SiO2.

5. Microstructured substrate according to one of claims 1 to 4, wherein the nanowires have a diameter section of 20 to 250 nm, and a length of 100 nm to 10 µm.

6. Microstructured substrate according to one of claims 1 to 5, in which the areas comprising nanowires have a developed surface area of ​​2 to 50 times the developed surface area of ​​said area devoid of nanowires.

7. A method of manufacturing a microstructured substrate according to one of claims 1 to 6, comprising the following steps: a- covering a flat or microstructured support with a thin layer of SiO2; b- depositing a layer of a non-oxidized metal by an atomic layer deposition technique; c- performing optical lithography on at least one area of ​​the surface of the flat or microstructured support having undergone steps a- and b-; d- performing an etching treatment; and e- performing thermal annealing, preferably by implementing at least one temperature step.

8. A method of manufacturing a microstructured substrate according to claim 7, wherein the non-oxidized metal deposited in step b- is selected from Pt, Ag, Au, Ga, In, Ti, Sn, Zn, Sb, Cu, Ni, Be, Fe, Co, Cr, Al, Ru, Rh and Pd, preferably it is Pt.

9. Method for manufacturing a microstructured substrate according to claim 8, wherein step e) comprises two temperature levels: a first level of 200 to 1200°C applied for less than 5 min; and a second level of 300 to 1400°C applied for less than 15 min.

10. Use of a microstructured substrate according to one of claims 1 to 6, for manufacturing a micro-device for storing energy, preferably selected from batteries, super-capacitors and dielectric and electrolytic capacitors of micrometric size, or even of nanometric size, energy harvesting components or a sensor-type device requiring the use of a large specific surface area.

Images