Fabrication and operation of quantum processing circuits in a quantum computing system

Abstract

In a general aspect, qubit devices in a quantum computing system are fabricated and operated. In some cases, a method of fabricating a quantum processing circuit, includes forming a protective layer on a surface of a substrate; patterning the protective layer to form a protective structure covering a first region of the surface of the substrate; etching a second region of the surface of the substrate to define a recessed surface outside the first region of the surface of the substrate, the recessed surface residing at a depth in the substrate relative to the surface; revealing the covered first region on the surface of the substrate, the revealing comprising removing the protective layer from the first region of the surface of the substrate; and forming at least a portion of a Josephson junction on the revealed first region.

Description

Fabrication and Operation of Quantum Processing Circuits in a Quantum Computing SystemCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 381,874, filed November 1, 2022, entitled "Fabrication and Operation of Qubit Devices in a Quantum Computing System.” The above-referenced priority document is incorporated herein by reference in its entirety.TECHNICAL FIELD

[0002] The following description relates to fabrication and operation of quantum processing circuits in a quantum computing system.BACKGROUND

[0003] Quantum computers can perform computational tasks by storing and processing information within quantum states of quantum systems. For example, qubits (i.e., quantum bits) can be stored in and represented by an effective two-level sub-manifold of a quantum coherent physical system. A variety of physical systems have been proposed for quantum computing applications. Examples include superconducting circuits, trapped ions, spin systems and others.BRIEF DESCRIPTION OF THE DRAWINGS

[0004] FIG. 1 is a block diagram of an example computing system.

[0005] FIGS. 2A-2B are top-view and cross-sectional-view schematic diagrams of an example quantum processing circuit.

[0006] FIGS. 3A-3C include a flow chart showing aspects of an example fabrication process.

[0007] FIGS. 4A-4B are top-view schematic diagrams of example quantum processing circuits.

[0008] FIG. 4G is a perspective view showing a deposition angle of an angled deposition process relative to an example sidewall of the example quantum processing circuits in FIGS.4A-4B.

[0009] FIG. 5 is a cross-sectional-view schematic diagram of the example quantum processing circuit.

[0010] FIGS. 6A-6B are top-view and cross-sectional-view schematic diagrams of an example quantum processing circuit.

[0011] FIGS. 7A-7F include a flow chart showing aspects of an example fabrication process.DETAILED DESCRIPTION

[0012] In some aspects of what is described here, a quantum computing system includes a quantum processing circuit fabricated on a defect-free surface, or a surface region with low-defect density. The surface region can be protected from contaminations that could introduce two-level systems and negatively affect the device performance, for example, from fabrication steps for creating other circuit elements (e.g., control circuits, drive circuits, conductive through-hole vias, readout resonator devices, etc.]. The protected surface region can be revealed after these fabrication steps; and sensitive devices such as Josephson junctions in a qubit device, a tunable-frequency coupler device or other quantum circuit devices in the quantum processing circuit can be fabricated on the revealed protected surface region. In some implementations, the methods and the systems presented here can improve a Josephson Junction yield and performance.

[0013] In some implementations, superconducting electrodes of a Josephson Junction overlap (e.g., partially overlap) in a plane parallel to the surface of a substrate where the Josephson Junction resides; and the overlapping area has a projected footprint along that plane. In some implementations, the projected footprint has a substantially square shape. For instance, the projected footprint can be a square, with deviations caused by manufacturing imperfections, etc. In some instances, the square shape of the projected footprint of the Josephson Junction can provide advantages. For example, with projected footprints of the same area, the projected footprint of a square shape has a smallerperimeter than the one of a shape distinct from a square shape (e.g., a rectangular shape or another shape). The square shape of the projected footprint of the Josephson Junction with a reduced perimeter can reduce the number of defects associated with the perimeter of the Josephson junction. For another example, with the junction perimeter protected by the top superconducting electrode with a greater size than the bottom superconducting electrode, chances of defect formation over time can be also reduced. The methods and techniques may also enable the use of a thinner barrier between the superconducting electrodes and a smaller junction area, which can reduce the number of two-level systems that the junction can be coupled to. The methods and techniques presented here may improve reproducibility with improved junction area targeting especially at smaller junction areas to obtain accurate device characteristics (e.g., operating frequency, anharmonicity, etc.). In some cases, the methods and techniques described here do not require extra leads, contact patches, etc. to be separately formed to contact respective superconducting electrodes of a Josephson junction with the respective superconducting circuits and thus allows a simplified fabrication process improving the yield of Josephson junctions in qubit devices, coupler devices, or other quantum circuit devices. In some cases, a combination of these and potentially other advantages and improvements may be obtained.

[0014] FIG. 1 is a block diagram of an example computing environment 100. The example computing environment 100 shown in FIG. 1 includes a computing system 101 and user devices 110A, HOB, HOC. A computing environment may include additional or different features, and the components of a computing environment may operate as described with respect to FIG. 1 or in another manner.

[0015] The example computing system 101 includes classical and quantum computing resources and exposes their functionality to the user devices 110A, 110B, HOC (referred to collectively as "user devices 110”). The computing system 101 shown in FIG. 1 includes one or more servers 108, quantum computing systems 103A, 103B, a local network 109, and other resources 107. The computing system 101 may also include one or more user devices (e.g., the user device 110A) as well as other features and components. A computing system may include additional or different features, and the components of a computing system may operate as described with respect to FIG. 1 or in another manner.

[0016] The example computing system 101 can provide services to the user devices 110, for example, as a cloud-based or remote-accessed computer system, as a distributed computing resource, as a supercomputer or another type of high-performance computing resource, or in another manner. The computing system 101 or the user devices 110 may also have access to one or more other quantum computing systems (e.g., quantum computing resources that are accessible through the wide area network 115, the local network 109 or otherwise).

[0017] The user devices 110 shown in FIG. 1 may include one or more classical processor, memory, user interfaces, communication interfaces, and other components. For instance, the user devices 110 may be implemented as laptop computers, desktop computers, smartphones, tablets, or other types of computer devices. In the example shown in FIG. 1, to access computing resources of the computing system 101, the user devices 110 send information (e.g., programs, instructions, commands, requests, input data, etc.) to the servers 108; and in response, the user devices 110 receive information (e.g., application data, output data, prompts, alerts, notifications, results, etc.) from the servers 108. The user devices 110 may access services of the computing system 101 in another manner, and the computing system 101 may expose computing resources in another manner.

[0018] In the example shown in FIG. 1, the local user device 110A operates in a local environment with the servers 108 and other elements of the computing system 101. For instance, the user device 110A may be co-located with (e.g., located within 0.5 to 1 km of) the servers 108 and possibly other elements of the computing system 101. As shown in FIG. 1, the user device 110A communicates with the servers 108 through a local data connection.

[0019] The local data connection in FIG. 1 is provided by the local network 109. For example, some or all of the servers 108, the user device 110A, the quantum computing systems 103A, 103B and the other resources 107 may communicate with each other through the local network 109. In some implementations, the local network 109 operates as a communication channel that provides one or more low-latency communication pathways from the server 108 to the quantum computer systems 103A, 103B (or to one ormore of the elements of the quantum computer systems 103A, 103B). The local network 109 can be implemented, for instance, as a wired or wireless Local Area Network, an Ethernet connection, or another type of wired or wireless connection. The local network 109 may include one or more wired or wireless routers, wireless access points (WAPs), wireless mesh nodes, switches, high-speed cables, or a combination of these and other types of local network hardware elements. In some cases, the local network 109 includes a software-defined network that provides communication among virtual resources, for example, among an array of virtual machines operating on the server 108 and possibly elsewhere.

[0020] In the example shown in FIG. 1, the remote user devices HOB, HOC operate remotely from the servers 108 and other elements of the computing system 101. For instance, the user devices 110B, HOC may be located at a remote distance (e.g., more than 1 km, 10 km, 100 km, 1,000 km, 10,000 km, or farther) from the servers 108 and possibly other elements of the computing system 101. As shown in FIG. 1, each of the user devices 110B, 110C communicates with the servers 108 through a remote data connection.

[0021] The remote data connection in FIG. 1 is provided by a wide area network 115, which may include, for example, the Internet or another type of wide area communication network. In some cases, remote user devices use another type of remote data connection [e.g., satellite-based connections, a cellular network, a virtual private network, etc.) to access the servers 108. The wide area network 115 may include one or more internet servers, firewalls, service hubs, base stations, or a combination of these and other types of remote networking elements. Generally, the computing environment 100 can be accessible to any number of remote user devices.

[0022] The example servers 108 shown in FIG. 1 can manage interaction with the user devices 110 and utilization of the quantum and classical computing resources in the computing system 101. For example, based on information from the user devices 110, the servers 108 may delegate computational tasks to the quantum computing systems 103A, 103B and the other resources 107; the servers 108 can then send information to the user devices 110 based on output data from the computational tasks performed by the quantum computing systems 103A, 103B and the other resources 107.

[0023] As shown in FIG. 1, the servers 108 are classical computing resources that include classical processors 111 and memory 112. The servers 108 may also include one or more communication interfaces that allow the servers to communicate via the local network 109, the wide area network 115 and possibly other channels. In some implementations, the servers 108 may include a host server, an application server, a virtual server or a combination of these and other types of servers. The servers 108 may include additional or different features, and may operate as described with respect to FIG. 1 or in another manner.

[0024] The classical processors 111 can include various kinds of apparatus, devices, and machines for processing data, including, by way of example, a microprocessor, a central processing unit [CPU], a graphics processing unit [GPU], an FPGA (field programmable gate array), an ASIC (application specific integrated circuit), or combinations of these. The memory 112 can include, for example, a random-access memory (RAM), a storage device (e.g., a writable read-only memory (ROM) or others), a hard disk, or another type of storage medium. The memory 112 can include various forms of volatile or non-volatile memory, media, and memory devices, etc.

[0025] Each of the example quantum computing systems 103A, 103B operates as a quantum computing resource in the computing system 101. The other resources 107 may include additional quantum computing resources (e.g., quantum computing systems, quantum virtual machines (QVMs) or quantum simulators) as well as classical (nonquantum) computing resources such as, for example, digital microprocessors, specialized co-processor units (e.g., graphics processing units (GPUs), cryptographic co-processors, etc.), special purpose logic circuitry (e.g., field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), etc.), systems-on-chips (SoCs), etc., or combinations of these and other types of computing modules.

[0026] In some implementations, the servers 108 generate programs, identify appropriate computing resources (e.g., a QPU or QVM) in the computing system 101 to execute the programs, and send the programs to the identified resources for execution. For example, the servers 108 may send programs to the quantum computing system 103A, the quantum computing system 103B or any of the other resources 107. The programs mayinclude classical programs, quantum programs, hybrid classical / quantum programs, and may include any type of function, code, data, instruction set, etc.

[0027] In some instances, programs can be formatted as source code that can be rendered in human-readable form (e.g., as text] and can be compiled, for example, by a compiler running on the servers 108, on the quantum computing systems 103, or elsewhere. In some instances, programs can be formatted as compiled code, such as, for example, binary code (e.g., machine-level instructions] that can be executed directly by a computing resource. Each program may include instructions corresponding to computational tasks that, when performed by an appropriate computing resource, generate output data based on input data. For example, a program can include instructions formatted for a quantum computer system, a quantum virtual machine, a digital microprocessor, co-processor or other classical data processing apparatus, or another type of computing resource.

[0028] In some cases, a program may be expressed in a hardware-independent format. For example, quantum machine instructions may be provided in a quantum instruction language such as Quil, described in the publication "A Practical Quantum Instruction Set Architecture,” arXiv:1608.03355v2, dated Feb. 17, 2017, or another quantum instruction language. For instance, the quantum machine instructions may be written in a format that can be executed by a broad range of quantum processing units or quantum virtual machines. In some cases, a program may be expressed in high-level terms of quantum logic gates or quantum algorithms, in lower-level terms of fundamental qubit rotations and controlled rotations, or in another form. In some cases, a program maybe expressed in terms of control signals (e.g., pulse sequences, delays, etc.] and parameters for the control signals (e.g., frequencies, phases, durations, channels, etc.]. In some cases, a program may be expressed in another form or format.

[0029] In some implementations, the servers 108 include one or more compilers that convert programs between formats. For example, the servers 108 may include a compiler that converts hardware-independent instructions to binary programs for execution by the quantum computing systems 103A, 103B. In some cases, a compiler can compile a program to a format that targets a specific quantum resource in the computer system 101. Forexample, a compiler may generate a different binary program (e.g., from the same source code) depending on whether the program is to be executed by the quantum computing system 103A or the quantum computing system 103B.

[0030] In some cases, a compiler generates a partial binary program that can be updated, for example, based on specific parameters. For instance, if a quantum program is to be executed iteratively on a quantum computing system with varying parameters on each iteration, the compiler may generate the binary program in a format that can be updated with specific parameter values at runtime (e.g., based on feedback from a prior iteration, or otherwise). In some cases, a compiler generates a full binary program that does not need to be updated or otherwise modified for execution.

[0031] In some implementations, the servers 108 generate a schedule for executing programs, allocate computing resources in the computing system 101 according to the schedule, and delegate the programs to the allocated computing resources. The servers 108 can receive, from each computing resource, output data from the execution of each program. Based on the output data, the servers 108 may generate additional programs that are then added to the schedule, output data that is provided back to a user device 110, or perform another type of action.

[0032] In some implementations, all or part of the computing environment operates as a cloud-based quantum computing (QC) environment, and the servers 108 operate as a host system for the cloud-based QC environment. The cloud-based QC environment may include software elements that operate on both the user devices 110 and the computer system 101 and interact with each other over the wide area network 115. For example, the cloud-based QC environment may provide a remote user interface, for example, through a browser or another type of application on the user devices 110. The remote user interface may include, for example, a graphical user interface or another type of user interface that obtains input provided by a user of the cloud-based QC environment. In some cases the remote user interface includes, or has access to, one or more application programming interfaces [APIs), command line interfaces, graphical user interfaces, or other elements that expose the services of the computer system 101 to the user devices 110.

[0033] In some cases, the cloud-based QC environment may be deployed in a “serverless” computing architecture. For instance, the cloud-based QC environment may provide on-demand access to a shared pool of configurable computing resources (e.g., networks, servers, storage, applications, services, quantum computing resources, classical computing resources, etc.) that can be provisioned for requests from user devices 110. Moreover, the cloud-based computing systems 104 may include or utilize other types of computing resources, such as, for example, edge computing, fog computing, etc.

[0034] In an example implementation of a cloud-based QC environment, the servers 108 may operate as a cloud provider that dynamically manages the allocation and provisioning of physical computing resources (e.g., GPUs, CPUs, QPUs, etc.). Accordingly, the servers 108 may provide services by defining virtualized resources for each user account. For instance, the virtualized resources may be formatted as virtual machine images, virtual machines, containers, or virtualized resources that can be provisioned for a user account and configured by a user. In some cases, the cloud-based QC environment is implemented using a resource such as, for example, OPENSTACK ®. OPENSTACK ® is an example of a software platform for cloud-based computing, which can be used to provide virtual servers and other virtual computing resources for users.

[0035] In some cases, the server 108 stores quantum machine images (QMI) for each user account. A quantum machine image may operate as a virtual computing resource for users of the cloud-based QC environment. For example, a QM1 can provide a virtualized development and execution environment to develop and run programs (e.g., quantum programs or hybrid classical / quantum programs). When a QMI operates on the server 108, the QMI may engage either of the quantum processor units 102A, 102B, and interact with a remote user device (110B or HOC) to provide a user programming environment. The QMI may operate in close physical proximity to and have a low-latency communication link with the quantum computing systems 103A, 103B. In some implementations, remote user devices connect with QMls operating on the servers 108 through secure shell (SSH) or other protocols over the wide area network 115.

[0036] In some implementations, all or part of the computing system 101 operates as a hybrid computing environment. For example, quantum programs can be formatted ashybrid classical / quantum programs that include instructions for execution by one or more quantum computing resources and instructions for execution by one or more classical resources. The servers 108 can allocate quantum and classical computing resources in the hybrid computing environment, and delegate programs to the allocated computing resources for execution. The quantum computing resources in the hybrid environment may include, for example, one or more quantum processing units (QPUs), one or more quantum virtual machines (QVMs), one or more quantum simulators, or possibly other types of quantum resources. The classical computing resources in the hybrid environment may include, for example, one or more digital microprocessors, one or more specialized coprocessor units (e.g., graphics processing units [GPUs], cryptographic co-processors, etc.), special purpose logic circuitry (e.g., field programmable gate arrays (FPGAs), applicationspecific integrated circuits (ASICs), etc.), systems-on-chips (SoCs), or other types of computing modules.

[0037] In some cases, the servers 108 can select the type of computing resource (e.g., quantum or classical) to execute an individual program, or part of a program, in the computing system 101. For example, the servers 108 may select a particular quantum processing unit (QPU) or other computing resource based on availability of the resource, speed of the resource, information or state capacity of the resource, a performance metric (e.g., process fidelity) of the resource, or based on a combination of these and other factors. In some cases, the servers 108 can perform load balancing, resource testing and calibration, and other types of operations to improve or optimize computing performance.

[0038] Each of the example quantum computing systems 103A, 103B shown in FIG. 1 can perform quantum computational tasks by executing quantum machine instructions (e.g., a binary program compiled for the quantum computing system). In some implementations, a quantum computing system can perform quantum computation by storing and manipulating information within quantum states of a composite quantum system. For example, qubits (i.e., quantum bits) can be stored in and represented by an effective two-level sub-manifold of a quantum coherent physical system. In some instances, quantum logic can be executed in a manner that allows large-scale entanglement within the quantum system. Control signals can manipulate the quantum states of individual qubitsand the joint states of multiple qubits. In some instances, information can be read out from the composite quantum system by measuring the quantum states of the qubits. In some implementations, the quantum states of the qubits are read out by measuring the transmitted or reflected signal from auxiliary quantum devices that are coupled to individual qubits.

[0039] In some implementations, a quantum computing system can operate using gatebased models for quantum computing. For example, the qubits can be initialized in an initial state, and a quantum logic circuit comprised of a series of quantum logic gates can be applied to transform the qubits and extract measurements representing the output of the quantum computation. Individual qubits may be controlled by single-qubit quantum logic gates, and pairs of qubits may be controlled by two-qubit quantum logic gates (e.g., entangling gates that are capable of generating entanglement between the pair of qubits). In some implementations, a quantum computing system can operate using adiabatic or annealing models for quantum computing. For instance, the qubits can be initialized in an initial state, and the controlling Hamiltonian can be transformed adiabatically by adjusting control parameters to another state that can be measured to obtain an output of the quantum computation.

[0040] In some models, fault-tolerance can be achieved by applying a set of high-fidelity control and measurement operations to the qubits. For example, quantum error correcting schemes can be deployed to achieve fault-tolerant quantum computation. Other computational regimes may be used; for example, quantum computing systems may operate in non-fault-tolerant regimes. In some implementations, a quantum computing system is constructed and operated according to a scalable quantum computing architecture. For example, in some cases, the architecture can be scaled to a large number of qubits to achieve large-scale general-purpose coherent quantum computing. Other architectures may be used; for example, quantum computing systems may operate in small- scale or non-scalable architectures.

[0041] The example quantum computing system 103A shown in FIG. 1 includes a quantum processing unit 102A and a control system 105A, which controls the operation of the quantum processing unit 102A. Similarly, the example quantum computing system103B includes a quantum processing unit 102B and a control system 105B, which controls the operation of a quantum processing unit 102B. A quantum computing system may include additional or different features, and the components of a quantum computing system may operate as described with respect to FIG. 1 or in another manner.

[0042] In some instances, all or part of the quantum processing unit 102A functions as a quantum processor, a quantum memory, or another type of subsystem. In some examples, the quantum processing unit 102A includes a quantum circuit system. The quantum circuit system may include qubit devices, readout devices, and possibly other devices that are used to store and process quantum information. In some cases, the quantum processing unit 102A includes a superconducting circuit, and the qubit devices are implemented as circuit devices that include Josephson junctions, for example, in superconducting quantum interference device [SQUID] loops or other arrangements, and are controlled by radiofrequency signals, microwave signals, and bias signals delivered to the quantum processing unit 102A. In some cases, the quantum processing unit 102A includes an ion trap system, and the qubit devices are implemented as trapped ions controlled by optical signals delivered to the quantum processing unit 102A. In some cases, the quantum processing unit 102A includes a spin system, and the qubit devices are implemented as nuclear or electron spins controlled by microwave or radio-frequency signals delivered to the quantum processing unit 102A. The quantum processing unit 102A may be implemented based on another physical modality of quantum computing. In some implementations, the quantum processing unit 102A includes a quantum processing circuit that can be implemented as the example quantum processing circuit 200, 400, 430, 500, 600 shown in FIGS. 2A-2B, 4A-4B, 5, 6A-6B, or in another manner. In some implementations, the example quantum processing unit 102A includes a quantum processing circuit that can be fabricated according to operations in the example process 300, 700 shown in FIGS. 3, 7, or in another manner.

[0043] The quantum processing unit 102A may include, or may be deployed within, a controlled environment. The controlled environment can be provided, for example, by shielding equipment, cryogenic equipment, and other types of environmental control systems. In some examples, the components in the quantum processing unit 102A operatein a cryogenic temperature regime and are subject to very low electromagnetic and thermal noise. For example, magnetic shielding can be used to shield the system components from stray magnetic fields, optical shielding can be used to shield the system components from optical noise, and thermal shielding and cryogenic equipment can be used to maintain the system components at controlled temperature, etc.

[0044] In some implementations, the example quantum processing unit 102A can process quantum information by applying control signals to the qubits in the quantum processing unit 102A. The control signals can be configured to encode information in the qubits, to process the information by performing quantum logic gates or other types of operations, or to extract information from the qubits. In some examples, the operations can be expressed as single-qubit quantum logic gates, two-qubit quantum logic gates, or other types of quantum logic gates that operate on one or more qubits. A quantum logic circuit, which includes a sequence of quantum logic operations, can be applied to the qubits to perform a quantum algorithm. The quantum algorithm may correspond to a computational task, a hardware test, a quantum error correction procedure, a quantum state distillation procedure, or a combination of these and other types of operations.

[0045] The example control system 105A includes controllers 106A and signal hardware 104A. Similarly, control system 105B includes controllers 106B and signal hardware 104B. All or part of the control systems 105A, 105B can operate in a roomtemperature environment or another type of environment, which may be located near the respective quantum processing units 102A, 102B. In some cases, the control systems 105A, 105B include classical computers, signaling equipment (microwave, radio, optical, bias, etc.), electronic systems, vacuum control systems, refrigerant control systems or other types of control systems that support operation of the quantum processing units 102A, 102B.

[0046] The control systems 105A, 105B maybe implemented as distinct systems that operate independent of each other. In some cases, the control systems 105A, 105B may include one or more shared elements; for example, the control systems 105A, 105B may operate as a single control system that operates both quantum processing units 102A, 102B. Moreover, a single quantum computer system may include multiple quantumprocessing units, which may operate in the same controlled (e.g., cryogenic) environment or in separate environments.

[0047] The example signal hardware 104A includes components that communicate with the quantum processing unit 102A. The signal hardware 104A may include, for example, waveform generators, amplifiers, digitizers, high-frequency sources, DC sources, AC sources, etc. The signal hardware may include additional or different features and components. In the example shown, components of the signal hardware 104A are adapted to interact with the quantum processing unit 102A. For example, the signal hardware 104A can be configured to operate in a particular frequency range, configured to generate and process signals in a particular format, or the hardware may be adapted in another manner.

[0048] In some instances, one or more components of the signal hardware 104A generate control signals, for example, based on control information from the controllers 106A. The control signals can be delivered to the quantum processing unit 102A during operation of the quantum computing system 103A. For instance, the signal hardware 104A may generate signals to implement quantum logic operations, readout operations, or other types of operations. As an example, the signal hardware 104A may include arbitrary waveform generators (AWGs) that generate electromagnetic waveforms (e.g., microwave or radio-frequency) or laser systems that generate optical waveforms. The waveforms or other types of signals generated by the signal hardware 104A can be delivered to devices in the quantum processing unit 102A to operate qubit devices, readout devices, bias devices, coupler devices, or other types of components in the quantum processing unit 102A.

[0049] In some instances, the signal hardware 104A receives and processes signals from the quantum processing unit 102A. The received signals can be generated by the execution of a quantum program on the quantum computing system 103A. For instance, the signal hardware 104A may receive signals from the devices in the quantum processing unit 102A in response to readout or other operations performed by the quantum processing unit 102A. Signals received from the quantum processing unit 102A can be mixed, digitized, filtered, or otherwise processed by the signal hardware 104A to extract information, and the information extracted can be provided to the controllers 106A or handled in another manner. In some examples, the signal hardware 104A may include adigitizer that digitizes electromagnetic waveforms (e.g., microwave or radio-frequency) or optical signals, and a digitized waveform can be delivered to the controllers 106A or to other signal hardware components. In some instances, the controllers 106A process the information from the signal hardware 104A and provide feedback to the signal hardware 104A; based on the feedback, the signal hardware 104A can in turn generate new control signals that are delivered to the quantum processing unit 102A.

[0050] In some implementations, the signal hardware 104A includes signal delivery hardware that interfaces with the quantum processing unit 102A. For example, the signal hardware 104A may include filters, attenuators, directional couplers, multiplexers, diplexers, bias components, signal channels, isolators, amplifiers, power dividers, and other types of components. In some instances, the signal delivery hardware performs preprocessing, signal conditioning, or other operations to the control signals to be delivered to the quantum processing unit 102A. In some instances, signal delivery hardware performs preprocessing, signal conditioning, or other operations on readout signals received from the quantum processing unit 102A.

[0051] The example controllers 106A communicate with the signal hardware 104A to control the operation of the quantum computing system 103A. The controllers 106A may include classical computing hardware that directly interfaces with components of the signal hardware 104A. The example controllers 106A may include classical processors, memory, clocks, digital circuitry, analog circuitry, and other types of systems or subsystems. The classical processors may include one or more single- or multi-core microprocessors, digital electronic controllers, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit), or other types of data processing apparatus. The memory may include any type of volatile or non-volatile memory or another type of computer storage medium. The controllers 106A may also include one or more communication interfaces that allow the controllers 106A to communicate via the local network 109 and possibly other channels. The controllers 106A may include additional or different features and components.

[0052] In some implementations, the controllers 106A include memory or other components that store quantum state information, for example, based on qubit readoutoperations performed by the quantum computing system 103A. For instance, the states of one or more qubits in the quantum processing unit 102A can be measured by qubit readout operations, and the measured state information can be stored in a cache or other type of memory system in one or more of the controllers 106A. In some cases, the measured state information is subsequently used in the execution of a quantum program, a quantum error correction procedure, a quantum processing unit (QPU) calibration or testing procedure, or another type of quantum process.

[0053] In some implementations, the controllers 106A include memory or other components that store a quantum program containing quantum machine instructions for execution by the quantum computing system 103A. In some instances, the controllers 106A can interpret the quantum machine instructions and perform hardware-specific control operations according to the quantum machine instructions. For example, the controllers 106A may cause the signal hardware 104A to generate control signals that are delivered to the quantum processing unit 102A to execute the quantum machine instructions.

[0054] In some instances, the controllers 106A extract qubit state information from qubit readout signals, for example, to identify the quantum states of qubits in the quantum processing unit 102A or for other purposes. For example, the controllers may receive the qubit readout signals (e.g., in the form of analog waveforms) from the signal hardware 104A, digitize the qubit readout signals, and extract qubit state information from the digitized signals. In some cases, the controllers 106A compute measurement statistics based on qubit state information from multiple shots of a quantum program. For example, each shot may produce a bitstring representing qubit state measurements for a single execution of the quantum program, and a collection of bitstrings from multiple shots may be analyzed to compute quantum state probabilities.

[0055] In some implementations, the controllers 106A include one or more clocks that control the timing of operations. For example, operations performed by the controllers 106A may be scheduled for execution over a series of clock cycles, and clock signals from one or more clocks can be used to control the relative timing of each operation or groups of operations. In some implementations, the controllers 106A may include classical computer resources that perform some or all of the operations of the servers 108 described above.For example, the controllers 106A may operate a compiler to generate binary programs (e.g., full or partial binary programs) from source code; the controllers 106A may include an optimizer that performs classical computational tasks of a hybrid classical / quantum program; the controllers 106A may update binary programs (e.g., at runtime) to include new parameters based on an output of the optimizer, etc.

[0056] The other quantum computer system 103B and its components (e.g., the quantum processing unit 102B, the signal hardware 104B, and controllers 106B) can be implemented as described above with respect to the quantum computer system 103A; in some cases, the quantum computer system 103B and its components may be implemented or may operate in another manner.

[0057] In some implementations, the quantum computer systems 103A, 103B are disparate systems that provide distinct modalities of quantum computation. For example, the computer system 101 may include both an adiabatic quantum computer system and a gate-based quantum computer system. As another example, the computer system 101 may include a superconducting circuit-based quantum computer system and an ion trap-based quantum computer system. In such cases, the computer system 101 may utilize each quantum computing system according to the type of quantum program that is being executed, according to availability or capacity, or based on other considerations.

[0058] FIGS. 2A-2B are top-view and cross-sectional-view schematic diagrams showing aspects of an example quantum processing circuit 200. In some instances, the example quantum processing circuit 200 may include quantum circuit devices, e.g., qubit devices, coupler devices, resonator devices, capacitors, inductors, bonding bumps, control signal lines, flux bias devices, or another circuit component. The example quantum processing circuit 200 may be part of a quantum processing unit of a quantum computing system (e.g., the quantum processing unit 102A of the quantum computing system 103A in FIG. 1). The quantum processing unit may be mounted in a dilution refrigerator at the lowest- temperature thermal stage of a cryostat, e.g., at a temperature of 20 milli Kelvin (mK); and may operate at the same temperature as the quantum processing unit, e.g., the lowest- temperature thermal stage of a cryostat.

[0059] In certain instances, the substrate 220 may be an elemental semiconductor, for example silicon (Si), germanium (Ge), selenium (Se), tellurium (Te) or another elemental semiconductor. In some instances, the substrate 220 may also include a compound semiconductor such as aluminum oxide (sapphire), silicon carbide (SiC), gallium arsenic (GaAs), indium arsenide (InAs), and indium phosphide (InP). In certain instances, the substrate 220 may include a compound semiconductor such as magnesium oxide (MgO), silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenic phosphide (GaAsP), and gallium indium phosphide (GalnP). In some instances, the substrate 220 may also include a superlattice with elemental or compound semiconductor layers. In one embodiment, the substrate 220 includes an epitaxial layer. In some examples, the substrate 220 may have an epitaxial layer overlying a bulk semiconductor or may include a semiconductor-on-insulator (SOI) structure. In some instances, the substrate 220 may be an insulating material, a ceramic material, or another type of material. In some instances, the substrate 220 includes a low-dielectric-loss thin film on the surface. For example, a low dielectric-loss thin film is a thin film that exhibits a dielectric film loss tangent in a range of equal to or less than 20E-5, equal to or less than 50E-5, or in a different range at a cryogenic temperature where the quantum processing unit operates. For example, a low- dielectric-loss thin film includes a dielectric layer with a low density of two-level systems (e.g., imperfections). In some implementations, a low dielectric loss thin film includes amorphous Ge, AI2O3 (PLD and MBE deposited), amorphous Si:H (hydrogenated Si), amorphous SiNx, or another dielectric material.

[0060] As shown in FIGS. 2A-2B, the quantum processing circuit 200 includes a qubit device 202 at a first region 204 of the top surface 232 of the substrate 220 includes two Josephson junctions 212A, 212B. The first region 204 of the top surface 232 is a region that has been protected during fabrication operations such as fabrication of control circuit 208A, 208B, and other potentially contaminating operations. In some implementations, the first region 204 of the top surface 232 is defined and protected by a protective structure (e.g., the protective structure 312 in FIGS. 3A-3B) during the fabrication process until the qubit device is ready to be formed.

[0061] In some implementations, the top surface 232 of the substrate 220 at the first region 204 has a root-mean-square (RMS) surface roughness in a range of 0.15 and 0.75 nm. In some implementations, the top surface 232 of the substrate 220 at the first region204 has an RMS surface roughness in a range of 0.15 and 2.75 nm. In some implementations, the density of two-level systems on the at least a portion of the Josephson junction 212A, 212B is less than 2.5 two-level systems per square micrometer. In some implementations, a total coupling strength of two-level systems to the qubit device 202, which includes the Josephson junctions 212A, 212B on the revealed first region 204 after removing the protective structure 312, is less than 40 MHz per qubit device. In some implementations, the qubit devices of the quantum processing unit that have less than 15 MHz total coupling strength per qubit device to two-level systems is equal to or greater than 75% of the total number of the qubit devices in the quantum processing unit. In some instances, other criteria based on TLS measurement can be used to evaluate the quality of the qubit devices on the revealed first region 204.

[0062] As shown in FIG. 2A, the two Josephson junctions 212A, 212B are connected in parallel, for example, forming a superconducting circuit loop. Each of the Josephson junctions 212A, 212B is formed between two superconducting electrodes, e.g., a superconducting bottom electrode 214A and a superconducting top electrode 214B, which are separated by a barrier 216. The two superconducting electrodes 214A, 214B are electrically connected to respective control circuits 208A, 208B at a second, distinct region205 on the top surface of the substrate 220 through respective superconducting circuits 218A, 218B. The two superconducting electrodes 214A, 214B are partially overlapping in the XY plane. The overlapping area has a footprint over the top surface of the substrate 220 in the XY plane. In the example quantum processing circuit 200 shown in FIG. 2A, the overlapping region of the two superconducting electrodes 214A, 214B has a rectangular shape in the XY plane, oriented along the extension direction of the superconducting circuits 218A, 218B (e.g., along the X-axis). In some instances, the two superconducting electrodes 214A, 214B may have another distinct shape or may be arranged along another orientation or in another manner.

[0063] In some implementations, each of the Josephson junctions 212A, 212B in the qubit device 202 may have an identical design. In some implementations, the Josephson junctions 212A, 212B may have distinct characteristics, e.g., junction inductance values or another parameter. In some implementations, the example quantum processing circuit 200 may include additional and different features or components and components of the example quantum processing circuit 200 may be implemented in another manner.

[0064] In some implementations, the control circuits 208A, 208B are part of a control circuit. In some instances, the control circuits 208A, 208B include a superconducting material, e.g., Al, niobium ( Nb), tantalum (Ta), vanadium (V), tungsten (W), zirconium (Zr), or another superconducting metal. In some implementations, the control circuit 208A, 208B may include a superconducting metal alloy, such as molybdenum-rhenium (Mo / Re), niobium-tin (Nb / Sn), or another superconducting metal alloy. In some implementations, the control circuits 208A, 208B may include a superconducting compound material, including superconducting metal nitrides and superconducting metal oxides, such as titanium-nitride (TiN), niobium-nitride (NbN), zirconium-nitride (ZrN), hafnium-nitride (HfN), vanadium-nitride (VN), tantalum-nitride (TaN), molybdenum-nitride (MoN), yttrium barium copper oxide (Y-Ba-Cu-O), or another superconducting compound material. In some instances, the control circuit 208A, 208B may include multilayered superconductorinsulator heterostructures, multilayered superconductor heterostructures, or other types of heterostructures.

[0065] In some implementations, the two superconducting electrodes 214A, 214B are fabricated in the first region 204 on a top surface 232 of the substrate 220 and patterned using a microfabrication process or in another manner. For example, the two superconducting electrodes 214A, 214B may be formed by performing at least some of the following fabrication steps: using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-on coating, and / or other suitable techniques to deposit respective superconducting layers on the substrate 220; and performing one or more patterning processes (e.g., a lithography process, a dry / wet etching process, a soft / hard baking process, a cleaning process, etc.) to form openings in the respective superconducting layers. In some instances, the two superconductingelectrodes 214A, 214B are formed using a single shadow mask followed by an angled deposition. For example, a shadow mask can be formed using a Controlled Undercut Technique (CUT) to create a controlled amount of undercut on either side of the Josephson junction. In some examples, a shadow mask can be also created using a Niemeyer-Dolan technique, during which a free-standing resist bridge is created in the middle of the Josephson junction. A shadow mask from a CUT or a Niemeyer-Dolan technique can be created using an MMA / PMMA resist bilayer or another type of multi-layer resist structure. In some cases, the angled deposition may be a double-angled metal deposition, a shadow evaporation technique, or another type of angled deposition process. In some instances, the two superconducting electrodes 214A, 214B may be formed using another type of fabrication process. For example, the two superconducting electrodes 214A, 214B may be formed using separate lithography / deposition processes (e.g., two distinct patterned resist masks). For another example, the two superconducting electrodes 214A, 214B may be formed using a subtractive method (e.g., metal etching). In some instances, the Josephson junction 212 may have a different structure or be configured in another manner. For example, the superconducting electrodes 214A, 214B may have a different shape or arranged relative to one another in a different manner. In some instances, the superconducting circuits 218A, 218B are fabricated together with the respective superconducting electrodes 214A, 214B. Alternatively, the superconducting circuits 218A, 218B may be fabricated separately, for example, before or after the fabrication of the qubit devices 202.

[0066] In some implementations, the barrier 216 may include a thin layer of an insulating material, a non-superconducting metal, or another material. When the barrier 216 includes an insulating material, the barrier 216 may have a thickness less than 3 nanometers (nm) in some cases. When the barrier 216 includes a non-superconducting metal, the barrier 216 may have a thickness in a range of a few hundred nanometers to micrometers. In some implementations, the barrier 216 may be fabricated using thermal oxidation, atomic layer deposition, or another fabrication technique.

[0067] As shown in the example quantum processing circuit 200, the superconducting circuits 218A, 218B are electrically coupled to respective portions of the control circuit208A, 208B via respective superconductive patches ("bandaid”) 222A, 222B. The respective superconductive patches 222A, 222B can enable electrical connection between the superconducting circuits 218A, 218B and the respective portions of the control circuit 208A, 208B. In some implementations, the superconductive patches 222A, 222B contain the same superconductive material as the control circuit 208A, 208B, the superconducting circuits 218A, 218B, the superconducting electrodes 214A, 214B, or another superconducting material. Such configuration shown in FIGS. 2A-2B using a method described above does not require extra leads to be formed to contact the respective superconducting electrodes of a Josephson junction and thus allows a simplified fabrication process.

[0068] In some implementations, the second region 205 is separated from the first region 204 by the third region 206. As shown in FIG. 2B, the third region 206 includes a recessed surface 228 located at a depth in the substrate 220 relative to the top surface 232. One or more sidewalls 230 are defined between the top surface 232 at the first or second region 204, 205 and the recessed surface 228 at the third region 206. As shown in FIG. 2B, the one or more sidewalls 230 are perpendicular to the top surface 232 and the recessed surface 228. In some instances, the one or more sidewalls 230 may define a slope from the top surface 232 at the first or second region 204, 205 to the recessed surface 228 at the third region 206. An example of sloped sidewalls 230 are shown in FIG. 5. An angle 8 is defined by the sloped sidewall 230 and the recessed surface 228. The angle 8 is in a range of, 20-80 degrees, 30-70 degrees, or in another range.

[0069] As shown in FIGS. 2A-2B, each of the superconducting circuits 218A, 218B has a first portion on the top surface 232 of the substrate 220 at the first region 204, a second portion on the recessed surface 228, and a third portion on the second region 205. Furthermore, the superconducting circuits 218A further includes a first sidewall portion on the sidewall 230 between the top surface 232 at the first region 204 and the recessed surface 228 at the third region 206; and a second sidewall portion on the sidewall 231 between the top surface 232 at the second region 205 and the recessed surface 228 at the third region 206.

[0070] In some implementations, each of the Josephson junction 212A, 212B extends in along a first direction (e.g., the X-axis) on the first region of the surface of the substrate 220; and the sidewall 230 extends in a second direction in the XY plane, and an angle cr is defined between the firstand second directions. In some implementations, the angle is in a range of 10 and 80 degrees, or another range that is greater than 0 degree and less than 90 degrees for improved coverage of the superconducting circuit on the sidewalls 230. For example, the sidewalls (e.g., the sidewalls 424A, 424B of FIG. 4A, and the sidewalls 434A, 434B, 434C, 434D of FIG. 4B) that are not perpendicular to the extending direction of the Josephson junction 212A, 212B are shown in FIGS. 4A-4B.

[0071] In some implementations, each of the two superconducting electrodes 214A, 214B and the superconducting circuits 218A, 218B may include a superconducting metal, such as aluminum (Al) or another type of superconducting material. The superconducting electrodes 214A, 214B, the Josephson junctions 212A, 212B, the superconducting circuits 218A, 218B, the control circuit 208A, 208B, the superconductive patches 222A, 222B, the recessed surface 228 in the third region 206 may be formed and fabricated according to the operations in the example process 300 or in another manner.

[0072] As shown in FIG. 2B, the substrate 220 comprises electrically conductive through-hole vias 226 that connect the control circuits 208A, 208B on the top surface 232 of the substrate 220 with additional circuitry 224 on a bottom surface 234 of the substrate 220. In some implementations, the conductive through-hole vias 226 are filled with superconductive materials.

[0073] FIGS. 3A-3C include a flow chart showing aspects of an example fabrication process 300. In some implementations, the example process 300 may be used for fabricating quantum processing circuits in a quantum processing unit (e.g., the quantum processing circuit 200, 400, 430, 500 in FIGS. 2A-2B, 4A-4B and 5). In some implementations, the example process 300 presented here is compatible with the fabrication process of superconducting qubits in a quantum processing unit and can allow a high yield of Josephson junctions with high performance. The example process 300 is performed on a crystalline silicon substrate or another type of substrate 220. The example process 300 may include additional or different operations, including operations tofabricate additional or different components, and the operations may be performed in the order shown or in another order. In some cases, operations in the example process 300 can be combined, iterated or otherwise repeated, or performed in another manner.

[0074] At 302, a protective structure 312 is formed. In some implementations, the protective structure 312 covering a first region of the surface of the substrate (e.g., the first region 204 of the top surface 232 of the substrate 220 in FIGS. 2A-2B] is formed according to the design of the quantum processing circuit. The first region 204 is a region on the surface of the substrate 220 on which quantum circuit devices (e.g., qubit devices 202 with one or more Josephson junctions 210 or other types of quantum circuit devices] reside. The protective structure 312 at the first region of the top surface of the substrate 220 protects first regions of the surface of the substrate 220 from contamination during the subsequent operations of the fabrication process. In some instances, contamination can be caused by physical diffusion of metal to the substrate and chemical combination between metal and the substrate, which are detrimental for qubit devices that are formed on the contaminated surface. In some instances, contamination and / or structural damage can be caused due to plasma and substrate reaction during etching of metal layers, and such contamination and / or damage may be detrimental for qubit devices later formed on such a substrate surface.

[0075] The protective structure 312 can be formed by forming and patterning a protective layer on the top surface of the substrate 220. For example, a protective layer can be formed on the top surface of the substrate 220 using physical vapor deposition, chemical vapor deposition, atomic layer deposition, or other types of deposition techniques. In some cases, the type of protective layer, the deposition condition, and the physical thickness of the protective layer are determined according to the type of the substrate that needs to be protected, the deposition condition of the superconducting material that are to be used in a later operation, and other factors.

[0076] In some instances, to pattern the protective layer, a first photoresist layer can be deposited and patterned on the protective layer on the top surface of the substrate 220. The first photoresist layer may include a negative or positive tone photoresist layer that is patternable in response to a photolithography light source. In some instances, the firstphotoresist layer may include an e-beam (electron beam resist layer (e.g., poly methyl methacrylate, methyl methacrylate, or another e-beam resist material) that is patternable in response to an e-beam lithography energy source. In some examples, before patterning, the first photoresist layer is formed directly on the top surface of the substrate220 using a deposition process such as spin-coating, spray-coating, dip-coating, roller-coating, or another deposition method. After deposition, the first photoresist layer is then patterned using a lithography process that may involve various exposure, developing, baking, stripping, etching, and rinsing processes. As a result, the first photoresist layer is patterned such that openings in the first photoresist layer expose at least a portion of the protective layer on the top surface of the substrate 220. In some implementations, positions of the openings are determined according to the positions and arrangement of quantum circuit devices on the surface of the substrate 220 (e.g., the qubit device 202 in the quantum processing circuit 200 shown in F1G.2) such that the exposed portion of the protective layer can be removed from and the protective structure 312 can be defined on the top surface of the substrate 220. In some instances, the exposed protective layer may be etched using a dry etching technique, a wet etch technique, or another type of etching technique. After removing the exposed protective layer, the portion of the top surface of the substrate 220 at the opening become exposed.

[0077] In some implementations, the substrate is a float-zone undoped silicon wafer with a high-resistivity or another type of substrate. In some instances, the top surface of the substrate 220 prior to the formation of the protective structure 312 may be cleaned to remove the native oxide at a metal / substrate interface between the protective structure 312 and the substrate 220 in order to reduce dielectric loss. For example, the substrate 220 can be etched using an HF etching process and rinsed in DI water. In some instances, cleaning of the top surface of the substrate 220 is performed to remove contaminants including organic contaminants and another type of contaminants. In some implementations, the substrate 220 after cleaning may be loaded into deposition chamber to minimize reformation of the native oxide. In some implementations, another type of cleaning process may be used according to the type of substrate used.

[0078] In some instances, the substrate 220 may include other materials and may be cleaned in another manner according to the type of materials. In some implementations, prior to forming the protective structure 312, a low-dielectric-loss thin film layer is deposited on the top surface of the substrate 220. For example, a low dielectric-loss thin film is a thin film that exhibits a dielectric film loss tangent in a range of equal to or less than 20E-5, equal to or less than 50E-5, or in a different range at a cryogenic temperature where the quantum processing unit operates. For example, a low-dielectric-loss thin film includes a dielectric layer with low density of two-level system (e.g., imperfections]. In some implementations, a low dielectric loss thin film includes amorphous Ge, AI2O3 (PLD and MBE deposited], amorphous Si:H (hydrogenated Si], amorphous SiNx, or another dielectric material.

[0079] The protective structure 312 does not affect the substrate 220 structurally. For example, the protective structure 312 does not physically diffuse or chemically combine with the substrate material causing damage to the crystallinity of the substrate at least during the operation 302. In some implementations, the protective layer on a silicon substrate includes silicon oxynitride [SiOxNy], which can be formed using plasma-enhanced chemical vapor deposition [PECVD]. The deposition is performed using a silane [SiH4] precursor along with a mixture of nitrous oxide (N2O] and nitrogen (N2] gas. During the deposition, the silicon substrate is resting by gravity at the unbiased plate at an elevated temperature (e.g., 350 degrees Celsius]. Gas flows of these precursors are tuned to tune the film stress. In some implementations, the SiOxNy protective layer has a thickness in a range of few hundreds of nanometers to a few micrometers um]. For example, the SiOxNy protective layer has a thickness in a range of 300 nm -10 / rm, 3-7 / rm, or another range. The protective structure 312 is formed by wet etching the photoresist-masked SiOxNyprotective layer using wet etching in Buffered Oxide Etch (BOE] at room temperature. In some instances, the SiOxNy protective structure may be formed in another manner.

[0080] In certain instances, the protective layer may include an insulating material which can be removed selectively from the surface of the substrate 220 and which can withstand intermediate downstream operations like reactive ion etching (RIE] of superconducting material layers (e.g., Nb, Ta, TiN, NbN, etc]. For example, the protectivelayer may include silicon oxide (SiOz), aluminum oxide (AI2O3), or another type of insulating material. The protective layer can be deposited via chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and other deposition techniques. The minimum thickness of the protective layer is defined by the amount of over-etch protection needed during the RIE etching of the control circuitry metal layers. For example, a silicon oxide thin film having a thickness about ~0.5 / zm can be a protective layer for a silicon substrate. Other types of protective layers with other thicknesses (e.g, > 0.3 .m) can be used for other substrate materials. In some implementations, polymers like polytetrafluoroethylene (PTFE) or dry films may be used. Depending on the material of the protective layer, other wet etch chemistries may be used including those containing hydrofluoric acid (HF), SCI (NH4OH:HzOz:HzO), and ammonium hydroxide (NH4OH).

[0081] At 304, a superconducting layer 314 is deposited. The superconducting layer 314 is deposited on the exposed portion of the top surface of the substrate 220. As shown in FIG. 3A, the superconducting layer 314 is also conformally deposited on the top surface and sidewalls of the protective structure 312. In some implementations, the superconducting layer 314 includes niobium. The superconducting layer 314 having a thickness of 160 nm can be sputter deposited using DC sputtering (continuous power) or using high power impulse magnetron sputtering (HiPIMS). In some instances, the sputtering can be performed with or without intentional heating applied to the substrate. Prior to the formation of the superconducting layer 314 on the substrate 220, the substrate 220 can be cleaned in acid, followed by de-ionized (DI) water rinse, and spin rinse drying. In some instances, the substrate 220 may be processed for additional surface treatment, and then loaded into the sputter tool, and heated in the load lock chamber of the sputter tool prior to deposition. In some implementations, the substrate may be prepared and cleaned in another manner; and the Nb superconducting layer 314 may be prepared in another manner.

[0082] In some instances, the superconducting layer 314 may include one or more superconducting material, e.g., aluminum (Al), niobium (Nb), tantalum (Ta), or their bilayer stacks, molybdenum-rhenium (Mo-Re) alloy, titanium nitride (TiN) and niobiumnitride (NbN), or other superconducting nitrides. In some instances, the thickness of the superconducting layer 314 may be in a range of 100 nanometers (nm) and 1000 nm, or in another range.

[0083] In certain instances, the superconducting layer 314 may be deposited using techniques such as, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or other deposition techniques. The superconducting layer 314 may be arranged on the top surface of the substrate 220 in another manner. For example, the superconducting layer 314 may be deposited through a hard mask and formed on the top surface of the substrate 220 on defined areas.

[0084] At 306, a superconducting circuit 208 is formed. In some implementations, the superconducting circuit 208 is formed by patterning the superconducting layer 314. In particular, the portion of the superconducting layer 314 that is conformally coated on the protective structure 312 is removed such that the protective structure 312 is revealed; and the portion of the superconducting layer 314 at a second region 206 surrounding the protective structure 312 are also removed such that the top surface of the substrate 220 in the second region 206 is also revealed. The second region 206 is outside of the protective structure 312. The superconducting circuit 208 is defined in a third region 205; and the third region 205 is separated from the protective structure 312 at the first region 204 by the second region 206. In some implementations, the top surface of the substrate 220 at the second region 206 can be contaminated by the superconducting layer 314 and can be etched by performing an etching process. After etching of the substrate 220 at the second region 206, a recessed surface 228 in the substrate 220 can be formed. In some implementations, the recessed surface 228 resides at a depth in the substrate 220 relative to the top surface of the substrate 220. In some instances, the depth is less than 10 nanometers (nm). In some implementations, the depth is in a range of 10 to 200 nm. In some instances, the depth may be in a different range.

[0085] In some implementations, when the substrate 220 at the second region 206 is etched, at least one sidewall 230 is created between the first and second regions 204, 206 and between the third and second regions 205, 206. The etching conditions can be tuned totune the slope of the sidewalls 230 in the X-Z plane. For example, the at least one sidewall is perpendicular to the top surface 232 and the recessed surface 228. In some implementations, the at least one sidewall is sloped and the angle of the sidewall relative to the recessed surface 228 may be in a range of 20-80 degrees, 30-70 degrees, or in another range.

[0086] In some implementations, a second photoresist layer can be deposited and patterned to create a mask to protect the superconducting layer 314 at the third region 205. In some instances, the second photoresist layer may be patterned according to the operation 302 or in another manner.

[0087] When the superconducting layer 314 includes Nb, a reactive ion etching with the substrate being heated (e.g., at a temperature at 50 degrees Celsius] can be used to pattern the superconducting circuit 208. In some implementations, the substrate is over-etched in the same R1E process. In some instances, the Nb superconducting layer 314 can be etched using Fluorine or Chlorine chemistries, e.g., CI2 and BCI3. In some instances, other etching techniques can be used including 1CP (inductively coupled plasma], 1BE (ion beam etching], chemically assisted ion beam etching (CA1BE], and other dry etching techniques. In some instances, the substrate 220 at the second region 206 may be etched in another manner.

[0088] At 308, the first region covered by the protective structure is revealed. After the superconducting circuit 208 is formed, the protective structure 312 is removed to expose the covered first region on the surface of the substrate 220. For example, when the protective structure 312 includes silicon oxynitride, the protective structure 312 can be removed using BOE wet etching at room temperature or at another temperature to minimize damage to the substrate 220. Depending on the material of the protective structure 312, other etching chemistries or techniques may be used including those containing hydrofluoric acid (HF], SCI (NH4OH:H2O2:H2O , ammonium hydroxide (NH4OH], and other etching methods.

[0089] In some implementations, the revealed first region after removing the protective structure 312 has a root-mean-square (RMS] surface roughness in a range of 0.15 nm and 0.75 nm, 0.15-2.75 nm, or in another range. In some implementations, the density of two-level systems on the at least a portion of the Josephson junction 212A, 212B is less than 2.5 two-level systems per square micrometer. In some implementations, a total coupling strength of two-level systems to the qubit device 202, which includes the Josephson junctions 212A, 212B on the revealed first region 204 after removing the protective structure 312, is less than 40 MHz per qubit device. In some implementations, the qubit devices of the quantum processing unit that have less than 15 MHz total coupling strength per qubit device to two-level systems is equal to or greater than 75% of the total number of the qubit devices in the quantum processing unit. In some instances, other criteria based on TLS measurement can be used to evaluate the quality of the qubit devices on the revealed first region 204.

[0090] At 310, a qubit device is formed on the revealed first region 204 of the substrate 220. In some implementations, the qubit device includes one or more Josephson junctions. For example, a bilayer resist stack consisting of MMA copolymer and PMMA can be written with a high voltage electron-beam lithography tool, and superconducting layers (e.g., Aluminum] can be deposited using physical vapor deposition (PVD] at opposite substrate angles (e.g., as described in FIGS. 4A-4B] with an intervening controlled oxidation to form tunnel junctions. In some instances, ion-mill pre-deposition cleaning can be applied in the PVD chamber.

[0091] The bilayer resist stack for JJ fabrication processes requiring an undercut (CUT, Dolan bridge) can use resists besides MMA / PMMA. For the imaging layer, ZEP, C-SAR, AR- P, can all be used instead of PMMA for potential improvements in either resolution, line edge roughness (LER), and / or resistance to ion mill. For the undercut layer, LOR and PGMI can both be used instead of MMA for improvements in adhesion / undercut robustness as well as improvements to the imaging layer (by developing both resists separately]. The Manhattan JJ fabrication method, which also utilizes angle evaporation and has potential benefits in JJ resistance uniformity and less fabrication steps, can also potentially benefit from the above resist stacks. The overlap JJ process which breaks vacuum and consists of two EBL and deposition steps and can be performed either with lift off or via reductive etch has various potential benefits including improved resistance uniformity, smaller JJ sizes, cleaner interfaces, as well as better design and metal stack compatibility. In tri-layermethod, without breaking vacuum, a metal trilayer stack is deposited in one vacuum step, patterned via negative resist followed by etch, where the bottom electrode is then separated by the subsequently deposited top electrode via anodic oxidation.

[0092] In some implementations, a superconducting bottom electrode of a Josephson junction is formed. The superconducting bottom electrode (e.g., the superconducting bottom electrode 214A) can be patterned using an electron beam lithographical process on the top surface of the substrate and between two adjacent segments of the segmented central superconducting circuits. In some instances, the superconducting bottom electrode contains a superconducting material such as a superconducting metal, a superconducting metal alloy, or a superconducting metal compound. For example, the superconducting bottom electrode includes aluminum (Al), niobium (Nb), molybdenum-rhenium (Mo-Re), titanium-nitride (TiN), or niobium-nitride (NbN). In some instances, the thickness of the superconducting bottom electrode is in a range of 10 nm and 300 nm, or in another range. In some instances, the superconducting bottom electrode may be formed on the substrate by performing at least some of the following processing steps: performing one or more of the depositing processes (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), etc.); and performing one or more patterning processes (e.g., a lithography process, a dry / wet etching process, a soft / hard baking process, a resist removing process, a cleaning process, etc.).

[0093] In some implementations, a shadow mask can be formed and used to form and pattern the superconducting bottom electrode. In some examples, the shape of the opening on the shadow mask determines the shape of the superconducting bottom electrode on the surface of the substrate. The opening on the shadow mask may have a tapered shape, for example a triangular shape or another tapered shape. In some instances, a shadow mask may be formed on the surface of the substrate using a photolithographic process, an electron-beam lithographic process, or another lithographic process. In some instances, one or more resist layers may be used to form a shadow mask using a controlled undercut technique (CUT). For example, an electron-beam lithography may be performed using at least two electron-beam resist layers (e.g., a top imaging resist layer and a bottom undercut resist layer) to create the shadow mask, in which the bottom undercut resist layer is etchedand removed creating a suspended, patterned top imaging resist layer. In some instances, processing conditions during the electron-beam lithography can be optimized to increase production yield by reducing photoresist residues at the metal / substrate interface and reducing aging of the Josephson junction. For example, soft bake temperatures of electronbeam resist layers can be optimized in order to increase dose contrast between the top imaging and bottom undercut resist layers to reduce electrical shorts and opens either via collapse of the top imaging resist layer, underexposure of the bottom undercut resist layer, or unintended leads due to overexposure of the bottom undercut resist layer. Additionally, resist development time can be optimized to further remove resist residue on the top surface of the substrate, which - in addition to potential reduction in aging - can also improve metal adhesion to the top surface of the substrate and improve chip yield. The development time can also be optimized to improve pattern fidelity and thus resistance targeting by yielding pattern features close to the intended size. In some instances, ethanol and oxygen plasma ashing, can also be used in the process after the development of the resist layers to assist the removal of resist residue, which can reduce aging of the Josephson junction. In some implementations, another type of shadow mask may be used, for example, a dielectric mask, a metal mask, or a metal alloy mask.

[0094] In some instances, after the formation of the shadow mask, the superconducting bottom electrode can be deposited using a first angled deposition process. In some instances, the first angled deposition process may use an angled physical vapor deposition (PVDJ, such as electron-beam evaporation, sputtering, epitaxial growth, or another type of deposition process. In certain examples, the formation of the superconducting bottom electrode using an angled PVD process through a shadow mask is performed at a first fixed angle (e.g., +(p as shown in FIG. 4CJ. In some instances, prior to the first angled deposition of the superconducting bottom electrode, the surface of the substrate may be etched and cleaned to remove the native oxide layer as described in operation 302 or in another manner. In some implementations, a first superconducting circuit 218A, electrically connecting the superconducting bottom electrode 214A of a Josephson junction 212A and a respective superconducting circuit 218A can be formed using the shadow mask and the same first angled deposition process.

[0095] In some implementations, a barrier layer is formed on the superconducting bottom electrode. In some implementations, the barrier layer (e.g., the barrier layer 216) may be formed by oxidizing the superconducting bottom electrode. For example, an oxidation of the superconducting bottom electrode may be performed in air, oxygen, or another type of oxidizing environment, and at room temperature or at another elevated temperature. In certain instances, the barrier layer may have a thickness in a range of 0.5 nm and 10 nm. For example, when aluminum is used as the superconducting bottom electrode, the oxidation process allows the formation of a stable, repeatable aluminum oxide barrier layer on the surface of the superconducting bottom electrode.

[0096] The oxidation of the superconducting bottom electrode may be performed immediately after the formation of the superconducting bottom electrode in the same vacuum chamber. The oxidation process that forms the barrier layer (e.g., tunneling barrier) can also be optimized for more accurate resistance targeting. Improvements in quality of the barrier layer can also reduce / prevent resistance aging in the Josephson junction, for example by making the oxide more thermodynamically stable and resistant to further oxidation. In some instances, these improvements may be achieved by optimizing parameters, such as the temperature, pressure, or time, through the addition of a catalytic agent - such as ultraviolet light, or through another parameter of the oxidation process.

[0097] In some implementations, the barrier layer may be formed using another type of deposition method, for example, atomic layer deposition (ALD), molecular beam epitaxy (MBE) or chemical vapor deposition (CVD). In certain instances, the barrier layer is formed on exposed surfaces of the superconducting bottom electrode, including the top surface along the XY plane and sidewalls perpendicular to the XY plane.

[0098] In some cases, the formation process of the barrier layer may cause the formation of an oxide layer or a formation of the barrier layer on any exposed surfaces through the opening in the shadow mask. For example, the oxidation process may also cause an oxidation on the exposed surface of the substrate, the segmented central conductive strip of the coplanar waveguide, or another circuit component.

[0099] In some implementations, a superconductingtop electrode is formed. In some implementations, the superconducting top electrode (e.g., the superconductingtop electrode 214B] may be formed using the same shadow mask which is used for the formation of the superconducting bottom electrode using a second angled deposition process. In some instances, the second angled deposition process for the formation of the superconducting top electrode may be implemented as the first angled deposition process with respect to the operation 310. In certain examples, the second angle deposition for the formation of the superconducting top electrode 214B is performed at a second, distinct angle (e.g., — ) relative to a direction normal to the recessed surface in the XZ plane. The difference between the two angles and the thickness of the shadow mask, and directionality of the deposition technique used in the angled deposition process may determine the overlapping area between the two superconducting bottom and top electrodes. The operations for the formation of the superconducting bottom and top electrodes 214A, 214B is known as a double-angled metal deposition method. In some instances, prior to the second angled deposition of the superconducting top electrode, the surface of the substrate may be etched and cleaned to remove the oxide layer that is formed during the formation of the barrier layer as described in operation 302 or in another manner. In some implementations, a second superconducting circuit 218B, electrically connecting the superconducting top electrode 214B of a Josephson junction 212A and a respective control circuit 208B can be formed using the shadow mask and the same first angled deposition process.

[0100] In some implementations, during the first angled deposition process, one or more sidewall portions of the superconducting circuit (e.g., the superconducting circuit 418A and the superconducting bottom electrode 414A to the Josephson junction 412A, 412B of the qubit 402 in FIG. 4A) is formed on one or more sidewall (e.g., the side wall 424A in FIG. 4AJ. by depositing along the first deposition direction in the XZ plane. The first deposition direction has an x-component. The angle in the XY plane is defined between the x-component of the first deposition direction and the extension direction of the first sidewall 418A in the XY plane. In some implementations, the angle is in a range of 10 and 80 degrees, 20 and 70 degrees, or in another range.

[0101] In some implementations, during the second angled deposition process, one or more sidewall portions of the superconducting circuit (e.g., the superconducting circuit 418B and the superconducting top electrode 414B to the Josephson junction 412A, 412B of the qubit 402 in FIG. 4AJ is formed on one or more sidewall (e.g., the sidewall 424B in FIG. 4AJ. by depositing along the second deposition direction in the XZ plane. The second deposition direction has an x-component, which is opposite to the x-component of the first deposition direction. The angle cr2in the XY plane is defined between the x-component of the second deposition direction and the extension direction of the second sidewall 418B in the XY plane. In some implementations, the angle tr2is inarange of 10 and 80 degrees, 20 and 70 degrees, or in another range.

[0102] In some implementations, the superconducting top electrode 214B includes the same superconducting material as or a different superconducting material from the superconducting bottom electrode 214A. For example, the thickness of the superconducting top electrode may be increased to reduce self-shadowing effects from the superconducting bottom electrode and to improve the chip yield. The thicknesses of the superconducting bottom and top electrodes 214A, 214B in the Josephson junction 212 may be further optimized according to the design / layout of the qubit device.

[0103] In some implementations, superconductive patches are formed. In some implementations, the superconductive patches 222A, 222B are formed to electrically connect the superconducting circuits 218A, 218B to the two respective control circuits 208A, 208B. Particularly, as shown in FIG. 3C, a first superconductive patch 222A covers a portion of the top surface of the control circuit 208A and a portion of the superconducting circuit 218A; and in some instances, the first superconductive patch 222Amay also cover a portion of the top surface of the substrate 220 in the second region 205. Similarly, a second superconductive patch 222B covers a portion of the top surface of the control circuit 208B and a portion of the superconducting circuit 218B; and in some instances, the second superconductive patch 222B may also cover a portion of the top surface of the substrate 220 at the second region 205. In some examples, the first and second superconductive patches 222A, 222B have dimensions that are large enough for making reliable electricalconnection with the respective superconducting circuits 218A, 218B and the respective control circuit 208A, 208B.

[0104] In some instances, the superconductive patches 222A, 222B may be formed by performing at least some of the following processing steps: performing one or more of the depositing processes (e.g., chemical vapor deposition [CVD], physical vapor deposition [PVD], atomic layer deposition [ALD], molecular beam epitaxy [MBE], etc.]; and performing one or more patterning processes (e.g., a lithography process, a dry / wet etching process, a soft / hard baking process, a resist removing process, a cleaning process, etc.]. In some instances, the superconductive patches may have a thickness in a range of 100 to 1000 nm, or in another range.

[0105] Prior to the formation of the superconductive patches, the shadow mask used for the formation of the superconducting bottom and top electrodes 214A, 214B and the superconducting circuits 218A, 218B can be removed. In some implementations, the top surfaces of the control circuits 208A, 208B and the superconducting circuits 218A, 218B may also be cleaned prior to the formation of the superconductive patches 222A, 222B. For example, a native oxide layer may form on the top surface of the superconducting circuits 218A, 218B due to their exposure to atmosphere in between lithographic and deposition steps. For another example, the barrier layer 216 may be formed on the entire top surface of the superconducting bottom electrode 214A and the superconducting circuit 218A. In some instances, a portion of the native oxide and the barrier on the superconducting bottom electrode 214A and the superconducting circuit 218A can be removed prior to the formation of the superconductive patches 222A, 222B in order to form reliable ohmic contacts between superconductors, providing low DC-resistance and high-quality factor at microwave frequencies. In certain examples, the native oxide is removed to reduce dielectric losses at various interfaces. In some implementations, techniques and conditions for removing the native oxide layer and the barrier layer may be different according to the superconducting materials used, geometries of the superconducting electrodes (e.g., thickness], nature of the native oxide layer, and instruments that are available.

[0106] FIGS. 6A-6B are top-view and cross-sectional-view schematic diagrams showing aspects of an example quantum processing circuit 600. As shown in FIGS. 6A-6B, thequantum processing circuit 600 includes a Josephson Junction 602 including two superconducting electrodes 604A.604B separated by a barrier 612. The two superconducting electrodes 604A, 604B are galvanically connected to respective superconducting circuits 606A, 606B on a top surface 614 of a substrate 610. In some instances, the Josephson junction 602 may reside at the first region 204 of the top surface 232 of the substrate 220 as shown in FIGS. 2A-2B. The example quantum processing circuit 600 may be part of a quantum processing unit of a quantum computing system (e.g., the quantum processing unit 102A of the quantum computing system 103A in FIG. 1). The quantum processing unit may be mounted in a dilution refrigerator at the lowest- temperature thermal stage of a cryostat, e.g., at a temperature of 20 milli Kelvin (mKJ; and may operate at the same temperature as the quantum processing unit, e.g., the lowest- temperature thermal stage of a cryostat. In some implementations, the example quantum processing circuit 600 may include additional and different features or components and components of the example quantum processing circuit 600 may be implemented in another manner. For example, the example quantum processing circuit 600 includes additional qubit devices, coupler devices, resonator devices, capacitors, inductors, bonding bumps, conductive vias, control signal lines, flux bias devices, and other quantum circuit devices.

[0107] In some implementations, each of the two superconducting electrodes 604A, 604B and the respective superconducting circuits 606A, 606B include a superconducting metal, such as aluminum (Al). In some instances, the superconducting electrodes 604A, 604B of the Josephson Junction 602 and respective superconducting circuits 604A, 604B of the quantum processing circuit 600 may include other superconducting material, e.g., niobium (Nb), tantalum (Ta), vanadium (V), tungsten (W), zirconium (Zr), or another superconducting metal. In certain instances, the quantum processing circuit 600 may include a superconducting metal alloy, such as molybdenum-rhenium (Mo / Re), niobiumtin (Nb / Sn), or another superconducting metal alloy. In some implementations, the quantum processing circuit 600 may include a superconducting compound material, including superconducting metal nitrides and superconducting metal oxides, such as titanium-nitride (TiN), niobium-nitride (NbN), zirconium-nitride (ZrN), hafnium-nitride(HfN), vanadium-nitride (VN), tantalum-nitride (TaNJ, molybdenum-nitride (MoN), yttrium barium copper oxide (Y-Ba-Cu-O), or another superconducting compound material. In some instances, the quantum processing circuit 600 may include multilayered superconductor-insulator heterostructures, multilayered superconductor heterostructures, or other types of heterostructures.

[0108] In some implementations, the superconducting electrodes 604A, 604B and the respective superconducting circuits 606A, 606B are fabricated on the top surface 614 of the substrate 610 and patterned using a microfabrication process or in another manner. For example, the two superconducting electrodes 604A, 604B may be formed by performing at least some of the following fabrication steps: using chemical vapor deposition (CVDJ, physical vapor deposition (PVDJ, atomic layer deposition (ALDJ, spin-on coating, and / or other suitable techniques to deposit respective superconducting layers on the substrate 610; and performing one or more patterning processes (e.g., a lithography process, a diy / wet etching process, a soft / hard baking process, a cleaning process, etc.) to form openings in the respective superconducting layers. In some instances, the two superconducting electrodes 604A, 604B are formed using a single shadow mask followed by an angled deposition process. For example, a shadow mask can be formed using a Controlled Undercut Technique [CUT] to create a controlled amount of undercut on either side of the Josephson junction 602. A shadow mask from a CUT technique can be created using an PMMA imaging layer on top of a copolymer MMA / PMMA support layer or using another type of multi-layer resist structure. In some cases, the angled deposition process may be a double-angled metal deposition, a shadow evaporation technique, or another type of angled deposition process. For example, the superconducting electrodes 604A, 604B may have a different shape or arranged relative to one another in a different manner. In some instances, the superconducting circuit 606A, 606B are fabricated together with the respective superconducting electrodes 604A, 604B according to the operations in the example process 700 shown in FIGS. 7A-7F or in another manner.

[0109] In some implementations, the barrier 612 includes a thin layer of an insulating material. In some implementations, the barrier 612 may be fabricated using thermal oxidation, atomic layer deposition, or another fabrication technique. In someimplementations, the barrier 612 is formed on exposed surfaces of the superconducting electrode 604A, including top surfaces and sidewalls of the superconducting electrode 604A. As shown in FIGS. 6A-6B, the size of the superconducting electrode 604B is greater than that of the superconducting electrode 604A, which is configured to protect three sides of the perimeter of the Josephson junction 602 to reduce the exposure of the barrier 612 to the ambient environment; and thus to reduce coupling to defects and aging of the Josephson junction 602. In some instances, the barrier 612 may be implemented as the barrier 216 in FIGS. 2A-2B or in another manner.

[0110] As shown in FIG. 6A-6B, the two superconducting electrodes 604A, 604B are partially overlapping along the XY plane; and the overlapping area has a projected footprint over the top surface 614 of the substrate 610 in the XY plane. In some implementations, the projected footprint of the two superconducting electrodes 604A, 604B has a substantially square shape, oriented along the extension direction of the superconducting electrodes 604A, 604B (e.g., along the X-Y plane).

[0111] In certain instances, the substrate 610 may be an elemental semiconductor, for example silicon (Si), germanium (Ge), selenium (Se), tellurium (Te) or another elemental semiconductor. In some instances, the substrate 610 may also include a compound semiconductor such as aluminum oxide (sapphire), silicon carbide (SiC), gallium arsenic (GaAs), indium arsenide (InAs), and indium phosphide (InP). In certain instances, the substrate 610 may include a compound semiconductor such as magnesium oxide (MgO), silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenic phosphide (GaAsP), and gallium indium phosphide (GalnP). In some instances, the substrate 610 may also include a superlattice with elemental or compound semiconductor layers. In one embodiment, the substrate 610 includes an epitaxial layer. In some examples, the substrate 610 may have an epitaxial layer overlying a bulk semiconductor or may include a semiconductor-on-insulator (SOI) structure. In some instances, the substrate 610 may be an insulating material, a ceramic material, or another type of material. In some instances, the substrate 610 includes a low-dielectric-loss thin film on the surface. For example, a low dielectric-loss thin film is a thin film that exhibits a dielectric film loss tangent in a range of equal to or less than 20E-5, equal to or less than 50E-5, or in a different range at acryogenic temperature where the quantum processing unit operates. For example, a low- dielectric-loss thin film includes a dielectric layer with a low density of two-level systems (e.g., imperfections]. In some implementations, a low dielectric loss thin film includes amorphous Ge, AI2O3 (PLD and MBE deposited], amorphous Si: H (hydrogenated Si], amorphous SiNx, or another dielectric material. In some instances, the substrate 610 may be implemented as the substrate 220 in FIGS. 2A-2B or in another manner.

[0112] FIGS. 7A-7F illustrate a flow chart showing aspects of an example fabrication process 700. In some implementations, the example process 700 may be used to fabricate quantum processing circuits of a quantum processing unit (e.g., the quantum processing circuit 600 in FIGS. 6A-6B]. In some implementations, the example process 700 presented here is compatible with fabrication processes that are used to manufacture superconducting quantum circuit devices and can allow a reproducible production of Josephson junctions with high performance. The example process 700 is performed on a crystalline silicon substrate or another type of substrate (e.g., the substrate 610 as shown in FIGS. 6A-6B]. The example process 700 may also be performed in a protected region on a surface of a substrate (e.g., in the first region 204 on the substrate 220 as shown in FIGS. 2A-2B]. The example process 700 may include additional or different operations, including operations to fabricate additional or different components, and the operations may be performed in the order shown or in another order. In some cases, operations in the example process 700 can be combined, iterated or otherwise repeated, or performed in another manner.

[0113] At 702, a bilayer resist stack 726 is formed. In some implementations, the bilayer resist stack 726 includes a first resist layer 722 and a second resist layer 724. In some instances, each of the first and second resist layers 722, 724 may include a negative or positive tone resist layer that is patternable in response to a lithography light source. In some instances, the each of the first and second resist layers 722, 724 may include an e- beam (electron beam] resist layer, e.g., poly methyl methacrylate (PMMA], methyl methacrylate (MMA], or another e-beam resist material, that is patternable in response to an e-beam lithography energy source. In some implementations, the first resist layer 722 and the second resist layer 724 have distinct sensitivity to the electron beam to allow aformation of respective types of patterns in the respective layers without affecting one another. In some instances, the first resist layer 722 may include materials such as Polyfmethyl methacrylate] [PMMA], ZEP polymer (Zeon electron beam polymer], C-SAR polymer, Arylsulfone-Arylene-Phenolic photoresist [AR-P] polymer, or other polymer; and the second resist layer 724 may include materials such as PMMA / MMA copolymer, LOR, PGMI, or other copolymer. In some instances, the first resist layer 722 has a thickness in a range of 25-300 nanometers [nm]; and the second resist layer 724 has a thickness in a range of 100-1300 nm.

[0114] As shown in FIG. 7A, the second resist layer 724 of the bilayer resist stack 726 is formed directly on the top surface 614 of the substrate 610; and the first resist layer 722 is formed on the top surface of the second resist layer 724, such that the second resist layer 724 is sandwiched between the first resist layer 722 and the substrate 610. In some implementations, the sensitivity of the first resist layer 722 is lower than that of the second resist layer 724. In some instances, each of the first resist layer 722 and the second resist layer 724 of the bilayer resist stack 726 may be formed using a deposition process such as spin-coating, spray-coating, dip-coating, roller-coating, or another deposition method.

[0115] In some implementations, the substrate 610 is a float-zone undoped silicon wafer with a high-resistivity or another type of substrate. In some instances, prior to the formation of the bilayer resist stack 726, the substrate 610 can be etched using an HF etching process and rinsed in DI water. In some instances, cleaning of the top surface of the substrate 610 is performed to remove contaminants including organic contaminants and another type of contaminants. In some implementations, the substrate 610 after cleaning may be loaded into deposition chamber to minimize reformation of the native oxide. In some implementations, another type of cleaning process may be used according to the type of substrate used. In some instances, the substrate 610 may include other materials and may be cleaned in another manner according to the type of materials.

[0116] At 704, the bilayer resist stack 726 is patterned. In some implementations, the bilayer resist stack 726 can be written with a high voltage electron-beam lithography tool. In particular, after the bilayer resist stack 726 is formed on the top surface 614 of the substrate 610, the bilayer resist stack 726 is patterned using a controlled undercuttechnique [CUT], In some implementations, a CUT method is used to create controlled undercuts in the bilayer resist stack 726. In some instances, the CUT method may include a lithography process that may involve various exposure, developing, baking, stripping, etching, and rinsing processes. In some implementations, the CUT method includes defining openings 728, 730A, 730B in the first and second resist layers 722, 724 by exposing the first and second resist layers 722, 724 using a first exposure from the electron-beam source followed by defining respective undercut regions 732A, 732B in the second resist layer 724 by exposing the second resist layer 724 using a second exposure from the electron-beam source. In some implementations, the first exposure is an exposure with a first dose level; and the second exposure is an exposure with a second dose level. In some instances, the first and second dose levels used to perform the first and second exposure depends on the type and thickness of the respective firstand second resist layers 722, 724, and the energy of the electron beam. In some instances, the first dose level used in the first exposure is in a range of 250 microcoulombs per square centimeter (pC / cm2) to 2500 pC / cm2; and the second dose level used in the second exposure is in a range of 50-1200 pC / cm2. In some implementations, the second dose level used during the second exposure does not impact the first resist layer 722.

[0117] After exposure, the bilayer resist stack 726 can be developed and rinsed to create the openings 728, 730A, 730B in the first and second resist layers 722, 724 and the undercut regions 732A, 732B in the second resist layer 724. As shown in FIG. 7B, the undercuts regions 732A, 732B defined by the second exposure are formed in the second resist layer 724 around respective openings 728, 730A, 730B in the firstand second resist layers 722, 724.

[0118] In some implementations, the width of the undercut regions 732A, 732B in the second resist layer 724 from the edges of the respective openings 728, 730A, 730B in the first and second resist layers 722, 724 are asymmetric particularly at the opening 730A and 730B, e.g., the width of the undercut regions on one side of a respective opening is much greater than that on the other side of the respective opening. The width of the undercut regions 732A, 732B is determined by the angle of deposition used in later deposition processes of superconducting materials, thickness of the second resist layer 724,dimensions of the superconducting circuits at the undercut regions 732A, 732B, deposition method / conditions, etc. In some instances, the width of the undercut regions 732A, 732B may have the same value or be distinct from one another. In some instances, the width of the undercut regions 732A, 732B may be in a range of 0.1-1.5 pm.

[0119] As shown in FIG. 7B, the undercut regions 732A, 732B in the second resist layer 724 extend along the X axis from the edge of the openings 728, 730A, 730B, e.g., width (w) of the undercut regions 732A, 732B along the X axis. The undercut regions 732A, 732B associated with the opening 728 in the first and second resist layers 722, 724 may be symmetric along the X axis (as shown in the cross-sectional view along the A-A’ plane); the undercut region 732A associated with the opening 730A (as shown in the cross-sectional view along the C-C’ plane) and the undercut region 732B associated with the opening 730B (as shown in the cross-sectional view along the B-B’ plane) are asymmetric. In particular, the undercut region 732B from the left edge of the opening 730B has a width w along the X axis, while the undercut region from the right edge of the opening 730B is negligible or less than a threshold value. Similarly, the undercut region 732A from the right edge of the opening 730A has a width w along the X axis, while the undercut region from the left edge of the opening 730A is negligible or less than the threshold value. The threshold value of the width of the undercut region is determined by the angle of deposition used in later deposition processes of superconducting materials, thickness of the second resist layer 724, deposition method / conditions, etc.

[0120] As a result, the bilayer resist stack 726 is patterned such that the openings 728, 730A, 730B in the first and second resist layers 722, 724 and the associated undercut regions 732A, 732B expose at least part of the top surface 614 of the substrate 610. In some implementations, positions of the openings 728, 730A, 730B are determined according to the positions and arrangement of quantum circuit devices and superconducting circuits on the top surface 614 of the substrate 610 (e.g., the Josephson junction 602 and the superconducting circuits 606A, 606B shown in FIGS. 6A-6B).

[0121] In some instances, soft bake temperatures of the bilayer resist stack 726 can be tuned in order to increase dose contrast between the first and second resist layers 722, 724 to reduce electrical shorts and opens either via collapse of the first resist layer 722,underexposure of the second resist layer 724, or unintended leads due to overexposure of the second resist layer 724. Additionally, resist development time can be tuned to further remove resist residue on the top surface 614 of the substrate 610, which - in addition to potential reduction in aging - can also improve metal adhesion to the top surface 614 of the substrate 610 and improve production yield. The development time can also be tuned to improve pattern fidelity and thus resistance targeting by yielding pattern features close to the intended size.

[0122] At 706, a first superconducting layer 742 is deposited. In some instances, prior to the deposition of the first superconducting layer 742, an ion-mill pre-deposition cleaning process, an oxygen plasma R1E cleaning process, an ethanol and oxygen plasma ashing process, a short buffered oxide etch or HF etch, or other cleaning process can be applied in the PVD chamber to remove resist residue on the surface of the substrate 610, which can enhance the adhesion of the first superconducting layer 742 to the surface of the substrate 610; reduce aging of the Josephson junction; and reduce two level system defects; and improve coherence of the Josephson junction. A combination of the afore-mentioned cleaning processes in various possible sequences may also be applied.

[0123] In some implementations, the first superconducting layer 742 is deposited using a first angled deposition. The first superconducting layer 742 is deposited on the exposed portion of the top surface 614 of the substrate 610. As shown in the cross-sectional views A-A’ and B-B’ in FIG. 7C, the direction of the first angled deposition relative to the Z axis in the X-Z plane has a first deposition angle of +(p. In particular, the first superconducting layer 742 is deposited on the exposed portion of the top surface 614 in the undercut regions 732B associated with the respective openings 728, 730B, which correspond to the superconducting electrode 604A and the respective superconducting circuit 606A in FIGS. 6A-6B. As shown in FIG. 7C, the first superconducting layer 742 is also deposited on the sidewall of the second photoresist layer 724 associated with the opening 730 and on the top surface of the first resist layer 724. Because of the deposition angle used in the deposition of the first superconducting layer 742, there is no deposition of the first superconducting layer 742 on the exposed portion of the top surface 614 in the undercutregions 732A associated with the respective openings 730A as shown in the cross-sectional view C-C' in FIG. 7C.

[0124] In certain instances, the first superconducting layer 742 may be deposited using deposition techniques such as, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition [ALD], molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or other deposition techniques. The first superconducting layer 742 may be arranged on the top surface 614 of the substrate 610 in another manner. In some instances, the first superconducting layer 742 includes a superconducting material such as a superconducting metal, a superconducting metal alloy, or a superconducting metal compound. For example, the first superconducting layer 742 includes aluminum Al], niobium (Nb), tantalum Ta], or their bi-layer stacks, molybdenum-rhenium [Mo-Re] alloy, titanium nitride (TiN) and niobium nitride (NbN), or other superconducting nitrides. In some instances, the thickness of the first superconducting layer 742 may be in a range of 10 nm and 300 nm, 100 nm and 1000 nm, or in another range.

[0125] In some instances, prior to the deposition of the first superconducting layer 742, a cleaning technique may be used to clean the top surface 614 of the substrate 610. For example, an oxygen plasma reactive ion etching (RIE J can be used to lightly clean the exposed portion on the top surface 614 to remove resist residue. In certain instances, the substrate 610 may be processed for additional surface treatment, and then loaded into the deposition tool, and heated in the load lock chamber of the deposition tool prior to deposition. In some implementations, the substrate 610 may be prepared and cleaned in another manner; and the first superconducting layer 742 may be prepared in another manner.

[0126] In some examples, shapes of the superconducting electrode 604A and the superconducting circuit 606A that the superconducting electrode 604A is galvanically connected to are determined by the shapes of the openings 728, 730A, 730B and the undercut regions 732A, 732B. The first superconducting layer 742 is deposited on the surface of the substrate 610 only at the undercut region 732B through the opening 730B; and the first superconducting layer 742 is formed on the sidewall of the second resist layer 724 through the opening 730A. In this case, the superconducting electrode 604A and thesuperconducting circuit 606A that the superconducting electrode 604A is galvanically connected to are fabricated during operation 706.

[0127] At 708, a barrier layer 744 is formed. In some implementations, a barrier layer 744 is formed on the surface of the first superconducting layer 742. In some implementations, the barrier layer 744 may be formed by oxidizing the first superconducting layer 742. For example, an oxidation of the first superconducting layer 742 may be performed in air, oxygen, or another type of oxidizing environment, and at room temperature or at another elevated temperature. In certain instances, the barrier layer 744 may have a thickness in a range of 0.5 nm and 10 nm, or in another range. For example, when aluminum is used as the superconducting electrode 604A, the controlled oxidation process allows the formation of a stable, repeatable aluminum oxide barrier layer 744 on the surface of the first superconducting layer 742 to form a tunnel junction.

[0128] In some instances, the oxidation of the first superconducting layer 742 may be performed immediately after the formation of the first superconducting layer 742 in the same vacuum chamber. In some instances, the oxidation of the first superconducting layer 742 may be performed in a separate vacuum chamber. The oxidation process that forms the barrier layer 744 (e.g., tunneling barrier) can also be optimized for more accurate resistance targeting. Improvements in quality of the barrier layer 744 can also reduce / prevent resistance aging in the Josephson junction, for example by making the oxide more thermodynamically stable and resistant to further oxidation. In some instances, these improvements may be achieved by optimizing parameters, such as the temperature, pressure, or time, through the addition of a catalytic agent - such as ultraviolet light, or through another parameter of the oxidation process.

[0129] In some implementations, the barrier layer 744 may be formed using another type of deposition method, for example, atomic layer deposition (ALDJ, molecular beam epitaxy (MBEJ or chemical vapor deposition (CVD). In certain instances, the barrier layer 744 is formed on all the exposed surfaces of the first superconducting layer 742. In some cases, the formation process of the barrier layer 744 may cause the formation of an oxide layer or a formation of the barrier layer 744 on any exposed surfaces through the openings 728, 730A, 730B. For example, the oxidation process may also cause an oxidation on theexposed surface of the substrate 610, the superconducting circuit 606A (e.g., as shown in FIG. 7Ds], or another circuit component.

[0130] At 710, a second superconducting layer 746 is formed. In some implementations, the second superconducting layer 746 is formed using a second angled deposition process through the same shadow mask (e.g., the openings 728, 730A, 730B and the undercut regions 732A, 732B]. In some instances, the second angled deposition process for the formation of the superconducting electrode 604B may be implemented as the first angled deposition process with respect to the operation 706. In certain examples, the second angled deposition is performed at a second, distinct angle (e.g., — ] relative to the Z axis in the XZ plane. The difference between the two angles, the thickness of the resist layers 722, 724, the geometry of the openings 728, 730A, 730B and the undercut regions 732A, 732B, and the directionality of the deposition technique used in the angled deposition process may determine the junction area and shape (e.g., overlapping area between the two superconducting electrodes 604A, 604B as shown in FIGS. 6A-6B], As shown in FIG. 7E, the second superconducting layer 746 is also formed on the surfaces of the barrier layer 744. As shown in the cross-sectional view A-A’ and C-C’ in FIG. 7E, the asymmetric undercut created in the second resist layer 724 allows the formation of the superconducting circuit 606B on the surface of the substrate 610 only at the undercut region 732A through the opening 730A. In this case, the superconducting electrode 604B and the superconducting circuit 606B that the superconducting electrode 604B is galvanically connected to are fabricated during operation 708. The portion of the second superconducting layer 746 on the surface 614 of the substrate 610 (e.g., corresponding to the superconducting circuit 606B in FIGS. 6A-6B] is electrically separated from (e.g., not galvanically connected to] the portion of the first superconducting layer 742 on the surface 614 of the substrate 610 (e.g., corresponding to the superconducting circuit 606A in FIGS. 6A-6B.

[0131] In some implementations, the second superconducting layer 746 includes the same superconducting material as or a different superconducting material from the first superconducting layer 742. The thicknesses of the second superconducting layer 746 may be tuned according to the design / layout of the qubit device.

[0132] In some implementations, the footprint of the Josephson junction 602 in the XY plane has a substantially square shape relative to the top surface 614 of the substrate 610. The shape of the footprint of the Josephson junction 602 is determined by the shape and size of the opening 728, the width of the undercut region 732A, 732B, and the deposition directions of the double angled deposition. In some instances, the methods and systems presented here provide a simplified fabrication process of a quantum processing circuit. In other words, the overlapping area between the superconducting electrodes and thus the junction area and the squared shape of the projected footprint of the junction area in the XY plane can be designed and tuned by tuning the geometry of the respective openings 728, 730A, 730B and the undercut regions 732A, 732B, the thickness of the first and second resist layers 722, 724, the angles of the angled depositions. Josephson junctions with a junction area of 1118 nm x 1118 nm, 500 nm x 500 nm, 354 nm x 354, 158 nm x 158 nm, 112 nm x 112 nm, 90 nm x 90 nm, 70 nm x 70 nm, 50 nm x 50 nm, or another squareshaped junction area.

[0133] At 712, the patterned bilayer resist stack 726 is removed from the surface of the substrate 610. In some instances, the patterned bilayer resist stack 726 and the superconducting layers 742, 746 and the barrier layer 744 formed on the first and second resist layers 722, 724 may be removed using a resist remover. In some implementations, techniques and conditions for removing the bilayer resist stack 726 may be different according to the superconducting materials used, geometries of the superconducting electrodes (e.g., thickness) 742, 746, nature of the barrier layer 744, and instruments that are available. In some instances, prior to the removal of the patterned bilayer resist stack 726 in operation 712, another oxidation of the second superconducting layer 746 can be performed to form a controlled "encapsulation" oxide on the surface of the second superconducting layer 746. In some instances, the oxidation of the second superconducting layer 746 may be implemented as the operation 708 or in another manner.

[0134] In a general aspect, qubit devices in a quantum computing system are fabricated and operated.

[0135] In a first example, a method of fabricating a quantum processing circuit includes forming a protective layer on a surface of a substrate; patterning the protective layer toform a protective structure covering a first region of the surface of the substrate; etching a second region of the surface of the substrate to define a recessed surface outside the first region of the surface of the substrate, the recessed surface residing at a depth in the substrate relative to the surface; revealing the covered first region on the surface of the substrate, the revealing comprising removing the protective layer from the first region of the surface of the substrate; and forming at least a portion of a Josephson junction on the revealed first region.

[0136] Implementations of the first example may include one or more of the following features. The protective layer comprises an oxynitride material. The protective layer comprises a superconducting nitride. The protective layer comprises an insulating material. The protective layer has a thickness equal to or greater than 300 nanometers. The depth is in a range of 10 nanometers (nm) and 200 nm. The depth is less than 10 nm. The revealed first region has a root-mean-square (RMS) surface roughness in a range of 0.15 nm and 0.75 nm. The revealed first region has an RMS surface roughness in a range of 0.15 nm and 2.75 nm. The density of two-level systems on the at least a portion of the Josephson junction is less than 2.5 two-level systems per square micrometer. A total coupling strength of two-level systems to a qubit device, which includes the Josephson junction and is formed on the revealed first region, is less than 40 MHz per qubit device. The quantum processing circuit includes qubit devices, and a subset of the qubit devices of the quantum processing circuit has less than 15 MHz total coupling strength per qubit device to two-level systems. A number of the subset of the qubit devices is equal to or greater than 75% of the total number of the qubit devices in the quantum processing circuit.

[0137] Implementations of the first example may include one or more of the following features. The method includes prior to etching the second region, forming a superconducting structure on a third, distinct region of the surface of the substrate, wherein the recessed surface resides between the superconducting structure and the revealed first region. Forming the superconducting structure includes depositing a superconducting layer, the superconducting layer disposed on the second and third regions of the surface of the substrate and the protective structure; and patterning the superconducting layer by removing the superconducting layer from the second region andthe protective structure. The superconducting layer comprises Niobium metal. The superconducting layer is a first superconducting layer. The superconducting structure on the third region of the substrate is a first superconducting structure. Forming the Josephson junction includes patterning a second superconducting layer to form a second superconducting structure on the revealed first region. The second superconducting structure includes a qubit electrode of a qubit device.

[0138] Implementations of the first example may include one or more of the following features. The method includes prior to etching the second region, forming a superconducting structure on a third, distinct region of the surface of the substrate. The recessed surface resides between the superconducting structure and the revealed first region. Forming the superconducting structure includes depositing a superconducting layer, the superconducting layer disposed on the second and third regions of the surface of the substrate and the protective structure; and patterning the superconducting layer by removing the superconducting layer from the second region and the protective structure. The superconducting layer includes Niobium metal. The superconducting layer is a first superconducting layer. The superconducting structure on the third region of the substrate is a first superconducting structure. Forming the Josephson Junction includes patterning a second superconducting layer to form a second superconducting structure on the revealed first region, wherein the second superconducting structure comprises a qubit electrode of a qubit device.

[0139] Implementations of the first example may include one or more of the following features. Etching the second region forms one or more sidewalls between the recessed surface and the first region of the surface of the substrate, and the one or more sidewalls are perpendicular to the first region of the surface and the recessed surface. The superconducting layer is a first superconducting layer. Forming the Josephson Junction includes forming a first superconducting circuit to the Josephson Junction on a first sidewall by depositing a second superconducting layer along a first deposition direction in the XZ plane; and forming a second superconducting circuit to the Josephson Junction on a second sidewall by depositing a third superconducting layer along a second deposition direction in the XZ plane. , A first x-component of the first deposition direction and theextension direction of the first sidewall in the XY plane on the recessed surface define a first angle in the XY plane. A second x-component of the second deposition direction and the extension direction of the second sidewall in the XY plane on the recessed surface define a second angle in the XY plane. The second x-component of the second deposition direction is opposite to the first x-component of the first deposition direction. Each of the first and second angles is in a range of 10 and 80 degrees.

[0140] Implementations of the first example may include one or more of the following features. Etching the second region forms one or more sidewalls between the recessed surface and the first region of the surface of the substrate. The one or more sidewalls define a slope from the first region of the surface to the recessed surface. The slope is in a range of 30 and 70 degrees relative to the recessed surface.

[0141] In a second example, a quantum processing circuit includes a Josephson junction disposed on a first region of a surface of a substrate; control circuitry disposed on a third region of the surface of the substrate. The surface of the substrate includes a second region that resides between the first region and the third region. The second region resides at a depth in the substrate relative to the first region. The quantum processing circuit further includes a superconducting circuit that provides a galvanic connection between the Josephson junction and the control circuitry. The superconducting circuit includes a first portion on the first region, a second portion on the second region, and a sidewall portion on a sidewall between the first region and the second region. The sidewall portion connects the first portion and the second portion.

[0142] Implementations of the second example may include one or more of the following features. The control circuitry includes Niobium metal and superconducting circuit comprises aluminum. The sidewalls include a sloped sidewall. The quantum processing circuit includes a qubit device that includes the Josephson junction. The substrate includes electrically conductive through-hole vias that connect the control circuitry on a first side of the substrate with additional circuitry on a second, opposite side of the substrate. The Josephson junction extends in a first direction on the first region of the surface of the substrate along the XY plane. The side wall extends in a second directionalong the XY plane, and an angle is defined between the firstand second directions. The angle is in a range of 10 and 80 degrees.

[0143] While this specification contains many details, these should not be understood as limitations on the scope of what may be claimed, but rather as descriptions of features specific to particular examples. Certain features that are described in this specification or shown in the drawings in the context of separate implementations can also be combined. Conversely, various features that are described or shown in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable sub-combination.

[0144] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single product or packaged into multiple products.

[0145] A number of embodiments have been described. Nevertheless, it will be understood that various modifications can be made. Accordingly, other embodiments are within the scope of the following claims.

Claims

CLAIMSWhat is claimed is:

1. A method of fabricating a quantum processing circuit, the method comprising: forming a protective layer on a surface of a substrate; patterning the protective layer to form a protective structure covering a first region of the surface of the substrate; etching a second region of the surface of the substrate to define a recessed surface at least partially outside the first region of the surface of the substrate, the recessed surface residing at a depth in the substrate relative to the surface; revealing at least a portion of the covered first region on the surface of the substrate, the revealing comprising removing at least some of the protective layer from the first region of the surface of the substrate; and forming at least a portion of a Josephson junction on the revealed portion of the covered first region.

2. The method of claim 1, comprising: prior to etching the second region, forming a superconducting structure on a third, distinct region of the surface of the substrate, wherein the recessed surface resides between the superconducting structure and the revealed first region.

3. The method of claim 2, wherein forming the superconducting structure comprises: depositing a superconducting layer, the superconducting layer disposed on the second and third regions of the surface of the substrate and the protective structure; and patterning the superconducting layer by removing the superconducting layer from the second region and the protective structure.

4. The method of claim 3, wherein the superconducting layer comprises Niobium metal.

5. The method of claim 3, wherein the superconducting layer is a first superconducting layer, the superconducting structure on the third region of the substrate is a first superconducting structure, and forming the Josephson junction comprises: patterning a second superconducting layer to form a second superconductingstructure on the revealed first region, wherein the second superconducting structure comprises a qubit electrode of a qubit device.

6. The method of claim 1, wherein etching the second region forms one or more sidewalls between the recessed surface and the first region of the surface of the substrate, and the one or more sidewalls define a slope from the first region of the surface to the recessed surface.

7. The method of claim 6, wherein the slope is in a range of 30 and 70 degrees relative to the recessed surface.

8. The method of claim 3, wherein the superconducting layer is a first superconducting layer, and forming the Josephson junction comprises: forming a first superconducting circuit to the Josephson junction on a first sidewall by depositing a second superconducting layer along a first deposition direction in the XZ plane, wherein a first x-component of the first deposition direction and the extension direction of the first side wall in the XY plane on the recessed surface define a first angle in the XY plane; and forming a second superconducting circuit to the Josephson junction on a second sidewall by depositing a third superconducting layer along a second deposition direction in the XZ plane, wherein a second x-component of the second deposition direction and the extension direction of the second sidewall in the XY plane on the recessed surface define a second angle in the XY plane, and the second x-component of the second deposition direction is opposite to the first x-component of the first deposition direction.

9. The method of claim 8, wherein each of the first and second angles is in a range of 10 and 80 degrees.

10. The method of claim 1, wherein the quantum processing circuit comprises qubit devices, and each qubit device in a subset of the qubit devices has a total coupling strength of two-level systems to the qubit device equal to or less than 15 MHz per qubit device.

11. The method of claim 10, wherein a number of qubit devices in the subset is equal to or greater than 75% of the total number of the qubit devices in the quantum processing circuit.

12. The method of any one of claims 1-11, wherein the protective layer comprises an oxynitride material.

13. The method of any one of claims 1-11, wherein the protective layer comprises a polymer material.

14. The method of any one of claims 1-11, wherein the protective layer comprises a superconducting nitride.

15. The method of any one of claims 1-11, wherein the protective layer comprises an insulating material.

16. The method of any one of claims 1-11, wherein the protective layer has a thickness equal to or greater than 300 nanometers (nm).

17. The method of any one of claims 1-11, wherein a density of two-level systems on the at least a portion of the Josephson junction on the revealed first region is less than 2.5 two- level systems per square micrometer.

18. The method of any one of claims 1-11, wherein a total coupling strength of two-level systems to a qubit device comprising the Josephson junction on the revealed first region is equal to or less than 40 MHz per qubit device.

19. The method of any one of claims 1-11, wherein a projected footprint of the Josephson junction in the first region along the surface of the substrate has a substantially square shape.

20. The method of any one of claims 1-11, wherein the revealed first region has a rootmean-square [RMS] surface roughness in a range of 0.15 nm and 0.75 nm.

21. The method of any one of claims 1-11, wherein the revealed first region has an RMS surface roughness in a range of 0.15 nm and 2.75 nm.

22. The method of any one of claims 1-11, wherein the depth is in a range of 10 nm and 200 nm.

23. The method of any one of claims 1-11, wherein the depth is equal to or less than 10 nm.

24. The method of any one of claims 1-11, wherein etching the second region forms one or more sidewalls between the recessed surface and the first region of the surface of the substrate, and the one or more sidewalls are perpendicular to the first region of the surface and the recessed surface.

25. A quantum processing circuit comprising: a Josephson junction disposed on a first region of a surface of a substrate; control circuitry disposed on a third region of the surface of the substrate, wherein the surface of the substrate comprises a second region that resides between the first region and the third region, wherein the second region resides at a depth in the substrate relative to the first region; and a superconducting circuit that provides a galvanic connection between the Josephson Junction and the control circuitry, wherein the superconducting circuit comprises: a first portion on the first region, a second portion on the second region, and a sidewall portion on a sidewall between the first region and the second region, wherein the sidewall portion connects the first portion and the second portion.

26. The quantum processing circuit of claim 25, wherein the Josephson Junction extends in a first direction on the first region of the surface of the substrate along the XY plane, and the sidewall extends in a second direction along the XY plane, and an angle is defined between the firstand second directions.

27. The quantum processing circuit of claim 26, wherein the angle is in a range of 10 and 80 degrees.

28. The quantum processing circuit of any one of claims 25-27, wherein a projected footprint of the Josephson junction in the first region along the surface of the substrate has a substantially square shape.

29. The quantum processing circuit of any one of claims 25-27, wherein the control circuitry comprises Niobium metal and superconducting circuit comprises aluminum.

30. The quantum processing circuit of any one of claims 25-27, wherein the sidewalls comprise a sloped sidewall.

31. The quantum processing circuit of any one of claims 25-27, comprising a qubit device that comprises the Josephson junction.

32. The quantum processing circuit of any one of claims 25-27, wherein the substrate comprises electrically conductive through-hole vias that connect the control circuitry on a first side of the substrate with additional circuitry on a second, opposite side of the substrate.

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