Methods for fabrication of graphene field-effect transistors with a liquid top-gate and associated componentry

Abstract

The present invention broadly relates to the fabrication and processing of graphene electronic devices on silicon and in particular graphene field effect transistors (gFETs) with a liquid top-gate.

Description

[0001] METHODS FOR FABRICATION OF GRAPHENE FIELD-EFFECT TRANSISTORS WITH A LIQUID TOP-GATE AND ASSOCIATED COMPONENTRY

[0002] FIELD

[0003] The present invention broadly relates to the fabrication and processing of graphene electronic devices on silicon and in particular graphene field effect transistors (gFETs) with a liquid top-gate.

[0004] BACKGROUND

[0005] Field effect transistors (FET) are the basis of modem electronics. Since the discovery and isolation of graphene, its electronic properties have made it a desired material to integrate into silicon FET architecture. So-called gFETs (or graphene field effect transistors) have been fabricated and researched since graphene was isolated in 2004.

[0006] Graphene is a highly promising material for use in electronic devices, specifically graphene field effect transistors (gFETs). Since graphene is essentially a 1 atom thick surface layer, its electronic properties are incredibly sensitive to the surrounding media above and below it. As such, graphene, when integrated into an electronic device, could detect changes in that media through changes in the electronic state of the graphene. Due to this, it is promising for analogue applications, such as gas and biological molecule sensors, and digital applications at certain low dimensional sizes. Graphene and related devices, including transistors, electronically integrating graphene, are yet to go beyond lab-scale applications, which is in-part due to a lack of process integration into traditional silicon (Si) wafer production lines. The main issues with graphene processing and integration with Si are: transferring graphene from growth substrates, protecting the graphene during fabrication, and degradation of electrical performance of graphene caused by the processing of polymer resists used in lithography.

[0007] Graphene is not typically grown on SiO2 substrates. This is an issue in the fabrication of graphene-based semiconductor devices as many electronic devices integrated into silicon technology (i.e., integrated circuits and sensors) require a thin layer of SiO2 to act as an insulating layer. This layer is imperative in activating the field-effect which is responsible for allowing materials to function as transistors. Since direct growth of graphene on silicon substrates is not easily realisable, graphene is usually synthesised and then transferred to the SiC surface. This includes graphene layers removed from graphite, graphene synthesised via chemical vapour deposition (CVD) and chemically synthesised and separated graphene dispersed in solution. Of these, exfoliated graphene from graphite typically produces the best quality of graphene, however, the methods are not industrially scalable and are mostly confined to research applications. Both CVD and chemically synthesised graphene are more suitable to fabrication scale-up. CVD generally involves growth on a metallic catalyst (either copper or nickel) and transfer to the Si wafer. Many transfer processes are in use, which either leave chemical residues or defects (sometimes both) negatively effecting the electronic properties. Despite this, CVD is widely regarded as a process advantageous in graphene fabrication as it results in the repeatability and reproducibility of homogenous mono-to-few layer graphene batch-to-batch.

[0008] To effectively integrate CVD grown graphene into gFETs, a method needs to be developed to prevent undesirable defects and delamination of graphene while retaining electronic properties. These two properties are inextricably linked, as broken sp2bonds in graphene (either through vacancy or sp3bond defects) will result in decreased electronic transport through the graphene surface. Therefore, a decrease in defects can be directly measured electronically as an improvement in carrier mobility (i.e., lower sheet resistance).

[0009] There are a few methods of quantifying the number of defects on a graphene sheet. The most powerful is Raman spectroscopy. In addition to determining the number of graphene sheets on the surface, this technique can determine whether defects are present and in what form. The standard spectrum of graphene shows a graphitic peak at approx. 1600cm1and a 2D band at approx. 2650cm1. Additional peaks at approx. 1360 cm1(D) and approx. 1610cm1(D’) carry information about the population type of defect (the intensity of the peaks indicating number of defects, and the ratio between the intensities of D / D’ demonstrating the nature of defects).

[0010] X-ray photoelectron spectroscopy (XPS) is another method of determining the number of defects in graphene. This can be done through examination of the core carbon Is spectra. Carbon to carbon sp2bonds found in graphene have lower binding energies, approx. 284 eV, when compared to sp3bonds (284.8 eV for carbon-carbon / hydrogen and between approx. 286 and 289 eV for carbon to other elements). Additionally, XPS can determine and quantify the presence of other elements on the sample, providing a higher degree of precision in isolating what the chemical defects are, and how many are present. XPS of the valence band can be used to calculate information about the bandgap, allowing direct linking of the chemical and electronic properties of the graphene.

[0011] Direct observation and quantification of defects is also possible through microscopy of the graphene surface. At high magnifications, defects can be observed with optical microscopes as changes in colour. These defects can be countered in terms of the ratio of the defective area of graphene to the total area of graphene.

[0012] There exist some strategies to reduce defects and delamination, including patterning with metals (specifically Ti and Au) and cleaning graphene (using vacuum heating and laser and electron beams). While metallic protection is effective in protection during processing, post process packaging including plasma and laser dicing require further photoresist-based lithography, which cannot be protected against using these processes post fabrication. Simultaneously, the energy intensive based cleaning methods tend to induce more undesirable defects while removing residue.

[0013] For full integration of gFETs into silicon technology, fabrication of gFETs must be compatible with cleanroom environments. This means developing lithography methods compatible with photo or electron polymer resists, and using pristine graphene with in-plane crystallinity on Si (i.e. CVD). Further developing gFETs into sensing platforms (particularly biosensors utilising liquid gating) requires electrode passivation and isolation to reduce crosstalk. This introduces another layer of complexity (and lithography) beyond just fabricating graphene electrodes. Therefore, even if sacrificial metal layers are used to protect graphene during fabrication, the issue of reliably removing polymer resist and residue will also need to be solved. gFET fabrication on a large scale remains difficult as the transferring of graphene onto silicon substrates and processing the graphene into devices typically damages the graphene. There remains a need for a process which increases the yield of graphene devices.

[0014] The present invention seeks to overcome one or more of the current shortcomings in the art.

[0015] SUMMARY OF THE INVENTION

[0016] The present invention is a process for the fabrication of a gFET which has been developed to function with a liquid top-gate at room temperature.

[0017] A distinguishing feature of the gFET device is the multiple parallel graphene strips (parallelised circuit, taken in combination with a biocompatible encapsulation layer). Most current gFETs use a continuous graphene sheet between and source and drain. In current transfer and fabrication processes, the graphene leads to large areas of the graphene becoming damaged. This process aims to reduce the effect of damage on the device by reducing the total graphene footprint necessary. Simultaneously, by using multiple graphene strips in parallel, it aims to produce a device which has multiple layers of redundancy if some strips are damaged.

[0018] The present invention relates to processes for the fabrication of a gFET which is developed to function with a liquid top-gate at room temperature. Experiments by the present inventors have focused on the electronic properties of the completed gFET in a O.lx Phosphate buffered solution. Specific experiments include current vs voltage curve, and the gating effect measured as a function of the bias applied to the gate vs the current across the source and drain of the graphene. The gFET developed by the process of the present invention may be a foundational underlying technology of a biosensor. The liquid-gated transistor design of the gFET disclosed herein will allow the biosensor to detect biomolecules in liquid samples. The biosensor in certain embodiments of the present invention could function as part of a larger biochip. The design allows the gFET to function in liquid environments, requiring certain components being isolated from the liquid, while others need to be exposed. The technology also enables the building of the gFET device into a chip that can be packaged nto a more compact readout device. As disclosed herein the inventors have fabricated a gFET with unique in-house processing methodology and parameters, verifying its electronic operation using liquid gating. The gFET is specially fabricated to prevent the liquid shorting the circuit, while, simultaneously attaining electronic signals using the liquid as a part of the device.

[0019] The present invention provides methods of gFET fabrication suitable in an ISO 5 cleanroom environment and includes three cleaning processing steps. SiO2 / Si covered with a complete mono-to-few layer graphene film (produced from CVD) was used for fabrication. First, the graphene on SiO2 / Si (for example graphene on a 300nm SiO2 passivation layer on a layer of the Si) is rinsed with a methylbenzene (in one case xylene), second rinsed with a ketone (in one case acetone), and finally rinsed in an alcohol (in one case isopropyl alcohol (IPA)). Additionally, the methylbenzene is used in the removal of the polymer resist (eg PMMA) following deposition of gold or etch of graphene (eg lithography), followed by the cleaning with ketone and alcohol. The present inventors have found that first cleaning with a methylbenzene such as xylene, is beneficial in preventing graphene delamination during resist removal post lithography. This is primarily attributed to the removal of defects related to amorphous carbon deposit during CVD.

[0020] In certain embodiments the invention contemplates the use of the methods to construct multiple graphene pieces to create 16 or more parallel source-drains. Most gFETs feature a single graphene sheet between the source and drain. The reason for the smaller strips is to reduce any effect of graphene damage from the processing and transfer. Tears in a large single sheet of graphene in series with a source-drain will ruin the gFET. In the case of the parallel graphene there is less graphene on the surface and more redundancy (that is, if some of the graphene strips are damaged, the current can still move through the remaining undamaged sheets). The current methods allows for very small (on the nanoscale) graphene channels of arbitrary aspect ratio or shape.

[0021] According to one aspect the invention provides a method of fabricating a gFET device or componentry thereof which minimises or prevents graphene delamination, damage, and / or reducing defects, said gFET device or componentry characterised by at least one drain, source and gate electrode, said method comprising the steps of at least one graphene deposition step, at least one lithography step, and at least one O2 plasma etching step, and wherein after each one of the aforementioned steps the graphene layer is cleaned with a methylbenzene, followed by a ketone, and then followed by an alcohol.

[0022] According to another aspect the invention provides a method of fabricating a gFET device or componentry thereof which minimises or prevents graphene delamination, damage, and / or reducing defects, said gFET device or componetry characterised by at least one drain, source and gate electrode, said method comprising the steps of at least one graphene deposition step, at least one lithography step, and at least one O2 plasma etching step, and wherein after each one of the aforementioned steps the graphene layer is cleaned with a methylbenzene, followed by a ketone, and then followed by an alcohol, and wherein the method further comprises at least one polymer resist coating layer which is developed using a methyl isobutyl ketone (MiBK): isopropanol (IPA) mixture in a ratio of about 3: 1.

[0023] According to another aspect the invention provides a method of fabricating a gFET component which minimises or prevents graphene delamination, damage, and / or reducing defects on the graphene layer, said method comprising the steps of: a) providing a S 1O2 / S i wafer substrate characterised with a graphene layer; b) cleaning the graphene deposited layer with a methylbenzene; c) cleaning the layer after step b) with a ketone; and d) cleaning the layer after step c) with an alcohol; e) depositing a polymer resist on the graphene layer after step d); f) defining areas where graphene will remain on wafer substrate using lithography; g) removing any unneeded graphene using O2 plasma etching; h) cleaning off any remaining polymer resist using a methylbenzene; i) cleaning the remaining graphene layer with a ketone; j) cleaning the graphene layer after step i) with an alcohol; k) depositing an adhesive layer comprising Ti or Cr unto the graphene surface layer after step j); l) depositing a metal electrode material layer unto the adhesive layer after step k); m) stripping the metal layer of step 1) to form the gFET component which comprises at least one drain, source and gate electrodes.

[0024] According to another aspect the invention provides a method of fabricating a gFET device which minimises or prevents graphene delamination, damage, and / or reducing defects on the graphene layer, said method comprising the steps of: a) providing a SiCE / Si wafer substrate characterised with a graphene layer; b) cleaning the graphene deposited layer with a methylbenzene; c) cleaning the layer after step b) with a ketone; and d) cleaning the layer after step c) with an alcohol; e) depositing a polymer resist on the graphene layer after step d); f) defining areas where graphene will remain on wafer substrate using lithography; g) removing any unneeded graphene using O2 plasma etching; h) cleaning off any remaining polymer resist using a methylbenzene; i) cleaning the remaining graphene layer with a ketone; j) cleaning the graphene layer after step i) with an alcohol; k) depositing an adhesive layer comprising Ti or Cr unto the graphene surface layer after step j); l) depositing a metal electrode material layer unto the adhesive layer after step k); m) stripping the metal layer of step 1) and n) depositing an encapsulation layer to form the gFET device which comprises at least one drain, source and gate electrodes, and wherein only the source and drain metallic electrode is encapsulated to prevent shorting, while the graphene and at least part of the gate electrode is unencapsulated and therefore exposed.

[0025] In still a further aspect the invention provides a method of fabricating a graphene field effect transistor (gFET) component comprising a graphene layer deposited on SiCh / Si substrate and wherein said gFET is characterised with at least one drain, source and gate electrodes, said method comprising the steps of: i) providing a S 1O2 / S i wafer substrate; ii) depositing a CVD (chemical vapour disposition) grown graphene layer to the surface of said wafer substrate by polymer deposition transfer; iii) cleaning the graphene deposited later with a methylbenzene; iv) cleaning the layer after step iii) with a ketone; v) cleaning the layer after step iv) with an alcohol; vi) depositing a polymer resist on the layer after step v) wherein the layer is developed using a methyl isobutyl ketone (MiBK): isopropanol (IPA) mixture in a ratio of about 3:1. vii) defining areas where graphene will remain on wafer substrate using e-beam lithography; viii) removing unneeded graphene using O2 plasma etching; ix) cleaning off any remaining PMMA resist using a methylbenzene; x) cleaning the remaining graphene layer with a ketone; xi) cleaning the graphene layer after step x) with an alcohol; xii) depositing an adhesive layer comprising Ti or Cr unto the graphene surface layer after step xi); xiii) depositing a metal electrode material layer unto the adhesive layer after step xii); and xiv) stripping the metal layer of step xiii) to form the gFET component which comprises at least one drain, source and gate electrodes.

[0026] In still a further aspect the invention provides a method of fabricating a graphene field effect transistor (gFET) device comprising a graphene layer deposited on SiCE / Si substrate and wherein said gFET is characterised with at least one drain, source and gate electrodes, said method comprising the steps of: i) providing a SiCh / Si wafer substrate; ii) depositing a CVD (chemical vapour disposition) grown graphene layer to the surface of said wafer substrate by polymer deposition transfer; iii) cleaning the graphene deposited later with a methylbenzene; iv) cleaning the layer after step iii) with a ketone; v) cleaning the layer after step iv) with an alcohol; vi) depositing a polymer resist on the layer after step v) wherein the layer is developed using a methyl isobutyl ketone (MiBK): isopropanol (IPA) mixture in a ratio of about 3:1. vii) defining areas where graphene will remain on wafer substrate using lithography; viii) removing unneeded graphene using O2 plasma etching; ix) cleaning off any remaining PMMA resist using a methylbenzene; x) cleaning the remaining graphene layer with a ketone; xi) cleaning the graphene layer after step x) with an alcohol; xii) depositing an adhesive layer comprising Ti or Cr unto the graphene surface layer after step xi); xiii) depositing a metal electrode material layer unto the adhesive layer after step xii); and xiv) stripping the metal layer of step xiii); and xv) depositing an encapsulation layer to form the gFET device which comprises at least one drain, source and gate electrodes, and wherein only the source and drain metallic electrode is encapsulated to prevent shorting, while the graphene and at least part of the gate electrode is unencapsulated and therefore exposed.

[0027] In certain embodiments and with reference to all aspects, the method further involves a step of depositing an encapsulation layer.

[0028] In respect to all of above aspects, in certain embodiments the methylbenzene is selected from xylene (ortho-xylene, meta-xylene, or para-xylene), toluene, hemellitene (1,2,3- trimethylbenzene), mesitylene (1,3,5-trimethylbenzene), pseudocumene (1,2,4- trimethylbenzene), prehnitene (1,2,3,4-tetramethylbenzene), isodurene (1, 2,3,5- tetramethylbenzene), durene (1,2,4,5-tetramethylbenzene), and hexamethylbenzene.

[0029] In respect to all aspects, in certain embodiments the ketone is selected from acetone, ethyl acetate, cyclohexanone, methyl ethyl ketone, or diacetone. In respect to all aspects, in certain embodiments the alcohol is selected from isopropanol (IPA), n-propanol, n-butanol, isobutanol, tert-butanol, or n-pentanol,

[0030] FIGURES

[0031] Figure 1. A microscope image of the gFET before encapsulation, showing a) the bond pads (which are where the device is connected to an external electronic circuit), b) the graphene is between the interdigitated electrodes (centre of the device) and the gate electrodes (The gates are the larger electrodes on above and below the interdigitated electrodes).

[0032] Figure 2. a) Zoomed up images of the interdigitated electrodes showing the graphene strips. The graphene is in a parallel circuit, b) shows a better image of the larger graphene strips while c) shows the thinnest. Each graphene channel is 37.5um wide. In b) the graphene is roughly lOum across, while in c) the graphene is lum across.

[0033] Figure 3. a) Image of the electrodes covered with and SU-8 encapsulation layer, with open wells above the graphene and gate electrodes (the wells, which are the areas that do not have the cloudy grey colour, are where the liquid contacts the electronic components of the gFET). In b) the graphene strips clearly remain and show no tearing or visible residues. The bond pads have also been effectively exposed as seen in c).

[0034] Figure 4. The device on the probe station. In the foreground the PDMS well for containing the PBS in the device can be seen in a), with needles in the background connecting the device to the semiconductor parameter analyser (the electronic measurement device). As seen in b), the needles contact the device through the bond pads (which also have had wells made in the SU-8 layer so the needles could create a gold-metal contact. The needles are tungsten).

[0035] Figure 5. a) The normalised source-drain current of the device measured at increasing gate voltages for 10 separate source-drain biases (Ids vs Vg). Graphene is an ambipolar conductor. This means it can transfer current via hole or electron charge carriers. As the voltage applied to gate approaches the charge neutrality or Dirac point the number of holes and electrons come to an equilibrium resulting in a decrease in current, reaching an absolute minimum at said point. On both sides of this point the conduction increases back to a steady state, which leaves the (Ids vs Vg) plot for graphene having a characteristic shape. This shape is much more apparent in the normalised data. These curves are evidence that this device if a graphene transistor. The position of the minimum in this plot is generally evident of the electrical characteristics of graphene. Undoped graphene with no charge trapping should have this minimum at OV. If this point is located at positive gate voltage values (such as here) it is usually evidence of p- or hole doping (while negative values are n- or electron doping). Dirac points at positive values such as these are common in most fabricated gFETs due to surface contaminants from the processing, particulates from the atmosphere, and charge trapping between the graphene and substrate). The Dirac point for the device at each drain-source bias is shown in b). This was repeated with the Dirac Point showing a rightward shift (figure 6). Overall b) shows a shape which is roughly linear over range of 0.1 to IV, consistent with previously reported behaviour of gFETs when the drain bias is shifted. Between 0 and 0.1V is a large jump (figure 6c), once again typical with the rest of the reported gFETs. This behaviour is due to changes in the field surrounding the graphene as a result of the different biases applied across the graphene, and the subsequent effect it has on the charge population with the graphene. This is similar to how the prospective sensor would change the field around the graphene while it is kept at on constant drain source bias.

[0036] Figure 6. The Dirac point shifts over time as the gFET is exposed to the liquid. The graphs a) and b) were taken on the same day (a) is the raw data shown in figure 5 a). As you can see the Dirac point is shifting rightward which would indicate the presence of p-doping. This has been plotted in c) with the points between 0.1 and 1 being linear. The relationship in peak shift remains the same as while the Dirac point is at different voltages, the co-efficient of each trend line is similar.

[0037] Figure 7. The same measurement as figure 6 taken approximately 3 weeks later. The Dirac point has continued to shift to the right. Measurements of the point with the liquid gate beyond 1.6 V will cause the gold to electrolyse (the gate electrode will be destroyed).

[0038] Figure 8. Shows the encapsulation layer for a gFET chip design according to an embodiment of the present invention. The concept would be realised using photo-lithography to pattern the purple part of the pattern, and higher resolution electron beam or deep UV to pattern the brown areas.

[0039] Figure 9. Illustrates that the process could be used to make a chip containing multiple integrated gFETs. An example of such a design of an exemplary chip is shown. This chip requires a mixture of photo, electron beam or deep UV lithography steps to pattern the different scale of feature sizes.

[0040] Figure 10. Design of a final gFET according to an embodiment of the present invention zoomed in on the critical area of the gFET.

[0041] Figure 11. An I-V curve of the gFET while it is immersed in the liquid gate media at room temperature. The resistance is found to be IkQ.

[0042] Figure 12. The drain-source currents (at drain source bias from 0-1V in 0.1V steps) against voltage applied to the gate. The gFET shows a minimum in each curve between 0.8V and 1.1 V which is related to the Dirac point of graphene (the point at which transport in graphene switches from holes to electrons). In undoped graphene this point is 0V, with this position the graphene is slightly p-doped (more holes than electrons). The device described herein can be run on a 3V battery (a lithium button cell or watch battery). Assuming the maximum current draw recorded in the experiments (-O.lmA) the whole time, a CR2032H (230mAh) button cell could run for 23 hours continuously at room temperature. This is based on Maxell’s datasheet for the CR2032.

[0043] DESCRIPTION

[0044] Presently in the art one of the most basic cleaning methods used in cleanrooms is the use of ketones and alcohols. The present inventors have found that the additional cleaning with a methylbenzene (e.g., xylene) is able to improve the graphene layer in terms of minimising delamination and / or defects. In an embodiment the SiCh / Si wafer substrate comprises a SiC insulation layer of about lOOnm to 400nm, for instance, about lOOnm, 150nm, 200nm, 250nm, 300nm, 350nm, or about 400nm (or any range between any two of the recited thicknesses).

[0045] Chemical vapour disposition (CVD) grown graphene is deposited on said wafer in a cleanroom environment (such as ISO5 / Class 100 type).

[0046] As used herein "CVD grown graphene" refers to the technique of depositing graphene as a thin film onto a substrate (e.g., Cu or Ni foil) from vapour species through chemical reactions. The process and types of the various possible chemical reactions that occur in a CVD reactor are governed by many complex factors, including the system setup, reactor configuration, gas feedstock, gas ratios, both reactor pressure and gas partial pressures, reaction temperature, growth time, temperature, etc. CVD is an extensively used bottom-up approach for the synthesis of few-layer and single-layer graphene films. A variety of different CVD methods are available that can be employed to synthesise graphene-based materials. According to the characteristics of the processing parameters (pressure, temperature, precursor nature, gas flow state, wall / substrate temperature, depositing time, and activation manner), these methods can be categorised into seven main types based on temperature, pressure, wall / substrate, nature of precursor, depositing time, gas flow state and activation / power source.

[0047] While the CVD grown graphene is often regarded as high-quality graphene, which implies single crystalline material without contamination, wrinkle, cracks, or other defects. There is a required transfer step to deposit the graphene from the CVD grown graphene substrate unto the desired technological substrate, in the present case the S i O2 / S i wafer substrate.

[0048] It will be appreciated however that the present method is amenable to standard commercially available graphene deposited SiCh / Si wafer substrate using and technique.

[0049] The transfer maybe facilitated by polymer deposition transfer, with the aid of a polymer transfer agent such as polymethyl methacrylate (PMMA) or poly (bisphenol A carbonate). After graphene transfer, delamination and / or defects are commonly observed on the deposited graphene layer which degrade the quality of the graphene available for the application.

[0050] The sources of the above most often come from sacrificial CVD grown graphene substrate (e.g., Cu foil); etchant used to dissolve the sacrificial substrate (e.g., ammonium persulfate (APS)); and the support layer (usually organic polymers such as polymethyl methacrylate (PMMA)) that also favours defect formations and produces the most undesirable type of residue owing to the compatible interaction of the polymers with graphene. These defects have a detrimental effect on graphene, mainly related to undesired doping that degrades the electrical and catalytic properties of graphene by creating charge-scattering centres and charge gradients.

[0051] Graphene layers are usually one atom or two atom thick and as such cracking and delamination can easily occur as a result of mechanical strain applied during cleaning and repeated transfer, and damage from sharp tools. Such damage degrades the electrical properties and mechanical stability of the graphene, resulting in subsequent operational inefficiency or even failure. In addition, analysis of impure and damaged graphene makes it challenging to develop correct structure-property relationships.

[0052] The present inventors have found that the amount of defects and / or delamination can be minimised or avoided by cleaning the graphene deposited layer with a three step method comprising a methylbenzene; a ketone; and finally an alcohol. With specific reference to the use of xylene the inventors have recognized that it has been only typically used as a developer in cleanrooms, as most polymers used are not as soluble in xylene as compared to other cleaners (e.g. acetone) and strippers (e.g. n-methyl-2-pyrrolidone). As such, using xylene as a cleaner and solvent has been overlooked. The inventors have identified xylene as being excellent for removing amorphous carbon deposits and being effective in the dissolution of polymer resists (particularly at thicknesses around and below a micron).

[0053] The present inventors have identified the following advantages of the defined methods: • a reduction in the degradation (i.e., delamination and / defects) to graphene when patterned with polymer resists;

[0054] • less complex (with less process steps and solvents) then methods using metal sacrificial layers;

[0055] • current methods of residue removal take more time and energy than this method;

[0056] • easier to integrate into post fabrication processing (i.e., dicing);

[0057] • xylene is not as strong a solvent as traditional removers / cleaners, so less risk of damage of graphene;

[0058] • reduces the importance of perfecting the graphene synthesis and transfer methods, as defective additives can be removed.

[0059] The invention thus provides: a) cleaning the graphene deposited layer with a methylbenzene;

[0060] This may involve washing the layer in the methylbenzene (e.g., xylene) by dispersion and gentle agitation for 1 to 5 minutes. The cleaning may also be achieved by mechanical means such as wiping or aspirating the surface with the methylbenzene through pressure with an inert gas. b) then cleaning the layer with a ketone;

[0061] This may involve washing the layer in ketone (e.g., acetone) by dispersion and gentle agitation for 1 to 7 minutes. c) and then subsequently cleaning the layer after with an alcohol.

[0062] This may involve washing the layer in alcohol (e.g., IPA) by dispersion and gentle agitation for 1 to 5 minutes.

[0063] After each of these cleaning steps, or after all three cleaning steps, the graphene deposited layer is optionally dried with an inert gas such as nitrogen.

[0064] As stated above Raman spectroscopy may be used to quantifying the number of defects on the deposited graphene layer. In this respect the intensity of the graphitic peak at approx. 1600cm1(such as between 1605-1590 cm1) is increased by at least 5% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g., acetone and IPA). In another embodiment the intensity of the graphitic peak at approx. 1600cm1is increased by at least 10% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g., acetone and IPA).

[0065] In another embodiment the intensity of the graphitic peak at approx. 1600cm1is increased by at least 15% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g., acetone and IPA).

[0066] In another embodiment the intensity of the graphitic peak at approx. 1600cm1is increased by at least 20% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g., acetone and IPA).

[0067] In another embodiment the intensity of the graphitic peak at approx. 1600cm1is increased by at least 25% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g., acetone and IPA).

[0068] In another embodiment the intensity of the graphitic peak at approx. 1600cm1is increased by at least 30% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g., acetone and IPA).

[0069] In this respect the intensity of the graphitic peak at approx. 2650cm1(such as between 2655- 2645 cm1) is increased by at least 5% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (eg acetone and IPA).

[0070] In another embodiment the intensity of the graphitic peak at approx. 2650cm1is increased by at least 7% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g., acetone and IPA).

[0071] In another embodiment the intensity of the graphitic peak at approx. 2650cm1is increased by at least 10% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g., acetone and IPA).

[0072] In another embodiment the intensity of the graphitic peak at approx. 2650cm1is increased by at least 12% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g., acetone and IPA).

[0073] In another embodiment the intensity of the graphitic peak at approx. 2650cm1is increased by at least 15% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g., acetone and IPA). In another embodiment the intensity of the graphitic peak at approx. 2650cm1is increased by at least 17% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g., acetone and IPA).

[0074] In certain embodiments intensity of the graphitic peaks at approx. 1600cm1and approx. 2650cm1are both increased by at least 5% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g., acetone and IPA).

[0075] In certain embodiments intensity of the graphitic peaks at approx. 1600cm1and approx. 2650cm1are both increased by at least 7% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g., acetone and IPA).

[0076] In certain embodiments intensity of the graphitic peaks at approx. 1600cm1and approx. 2650cm1are both increased by at least 10% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g., acetone and IPA).

[0077] In certain embodiment's the electrical resistance measurements taken of the graphene deposited layer cleaned with methylbenzene (after PMMA removal), shows electrical resistance in a range close to graphene while when xylene is not included in the processing steps the resistance is over 100MQ.

[0078] The method also contemplates the depositing of an encapsulation layer. The purpose of the layer is to ensure that the gate(s) and the graphene layer are in contact with the gating liquid, but the other parts of the device are not in contact with the liquid. This will prevent shorting between the source and the drain and ensure that the field runs through the liquid only. In certain embodiments the encapsulation layer is a SU-8 photoresist which is a commonly used epoxy-based negative photoresist, characterised by 8-epoxy groups of the following formula:

[0079]

[0080] Many of the reported gFETs (devices and componentry) use alumina as an encapsulation layer. Some previous designs also used polymers such as SU-8. SU-8 is useful as an encapsulation layer because it can be directly patterned by lithographic means. Therefore, there is no etching or lift-off required to remove another di-electric encapsulation layer (i.e. alumina). SU-8 is active in both photo and electron beam lithography. Due to this, it may be possible that on a chip, a single layer of SU-8 can be exposed to both forms of lithography. Large areas which need to be encapsulated can be dealt with by photo-lithography, while smaller more delicate features can be addressed with electron beam.

[0081] In certain embodiments the encapsulation layer is developed by a glycol ether or acetate such as propylene glycol methyl ether acetate (PGMEA).

[0082] Reference will now be made to experiments that embody the above general principles of the present invention. However, it is to be understood that the following description is not to limit the generality of the above description.

[0083] EXPERIMENTAL

[0084] METHODS

[0085] CVD grown graphene on a Si wafer (with a 300nm SiO2 insulation layer) was introduced to the cleanroom (ISO 5 / Class 100). The wafer was diced using a diamond scribe into roughly 1cm x 1cm squares for all experiments. First the die was washed in xylene for 3 minutes with gentle agitation. Following this, the die was placed in acetone for another 5 minutes with gentle agitation to remove any organic residues. Finally, isopropanol (IPA) was used for a 3-minute rinse (again with gentle agitation) to remove any further residues. The die was then dried with a N2 flow. An electron beam resist of 950 A4 polymethyl methacrylate (PMMA) was spin coated (Polos spin coater SPIN 150i) on top of the graphene on the die.

[0086] To demonstrate the effect of the xylene in cleaning, a separate process was also conducted involving only washing with acetone and IPA (for the same time and same conditions), before spin coating with a similar layer of PMMA.

[0087] Lithography was carried out with an Elionix F-125 electron beam lithography system. Electron beam voltage was set to 125keV, while the dose for patterns varied from 1250uC.cm’2for electrodes and markers (InA beam size), and 1250uC.cm’2for the graphene patterns (lOnA beam size). Development of the PMMA was conducted using methyl isobutyl ketone (MiBK) in IPA in a ratio of 1:3 (MiBKJPA). PMMA was developed first in MiBKJPA (for 40s) before being rinsed in IPA (20s). The die is then dried in an N2 stream.

[0088] The design of the markers, graphene and electrode layout was completed with Klayout and converted into a .con file using the Beamer software.

[0089] Graphene rectangles were formed via lithographically defining the areas, then etching the exposed graphene from the surface. Once this was achieved, graphene was etched using O2 plasma with a reactive ion etcher (Southbay Technologies). Plasma was generated in 30mT of O2 with an RF power of 50W, for a time of 1 min. This process was performed before Au marker deposition (ensuring Au deposition directly on SiO2 layer), and to separate graphene sheet into multiple devices (following lithography for the graphene pattern).

[0090] Deposition of Au layer for markers and electrodes was achieved using an electron beam evaporator (AJA international). Au layers of 30nm thickness (deposition rate of 2A / s) were deposited on the marker (post plasma etching) and electrode lithography patterns. A Ti adhesion layer of lOnm (deposition rate of lA / s) was first deposited prior to Au deposition.

[0091] The present invention will now be described with reference to the following non-limiting examples. Examples

[0092] Graphene on a silicon wafer was purchased from Graphenea. The device was made using multiple (four) lithographic processes, with each step requiring electron beam lithography. Before each step graphene was cleaned with the method using xylene, acetone and then isopropanol (IPA). The fabrication of electronic components of the gFET occurred across three lithographic layers in the RPF cleanroom (using the Elionix F-125 EBL). First layer is defining and depositing alignment markers (E-beam evaporator). The second layer is defining and etching the appropriate shape of the graphene (Using an oxygen plasma generated in a reactive ion etcher). The graphene is etched into 16 strips of different sizes. The size differences at this stage are mostly demonstrational. Further optimisation is required to see whether which size and number of strips is the best in terms of function. There is also room to attempt to determine whether differences in sizes of the strips assist or hinder the signal. The strips act together as one single conductor in parallel (i.e. there is no way to differentiate which strip the signal is coming from). The strips are situated between the interdigitated source and drain electrodes. If one strip is damaged during the processing then the other strips can still make an effective connection, providing redundancy. The other positive is that less graphene is required to make the gFET, meaning that there is a higher tolerance for damages which occur to the larger graphene sheet during processing and transfer. The third step is the definition and deposition of electrodes (markers and electrodes are gold due to conductivity and chemically inert nature. In the case of the markers, gold is also highly important as it provides a significant contrast when imaged with an electron beam for the alignment process required in the following layers). The results of this can be seen in figure 1 and 2.

[0093] Finally, a layer of lithography is required to encapsulate and thus insulate most of the device, except electric contacts, the “gate” electrodes (which are used to generate an electric field around the graphene) and the graphene itself. This encapsulation layer prevents the liquid from electrically shorting the chip, while ensuring that sensitive graphene areas are exposed to the liquid solvent, which would be carrying biomarkers in a biological sample. The results can be seen in figure 3. The encapsulating layer was a polymer known as SU-8, which is a standard encapsulant for electronics which interface with liquids. Additionally, it is a biocompatible polymer which has been used in biomedical applications like implants. SU- 8’s unique properties mean it can be utilised as a functional (encapsulating) component as well as a structural component with a potential to shape microfluidic channels or other microstructures. SU-8 is used as an encapsulant dielectric rather than a more commonly used oxide materials (i.e. AI2O3) as it can be directly fabricated through lithography. In the case of SU-8, a pattern is directly made in the polymer, then developed leaving behind the structure. To effectively pattern the other materials, lithography is still required, but there is then a lift-off or etching step adding to the complexity. SU-8 is also a flexible polymer as it can be effectively patterned with electron beam, deep UV and UV photo sources, meaning a single layer can be patterned to different resolutions, using different lithography techniques. With microfluidic channels, large pressures can prevent the liquid from reaching the bottom of a well like this. Without any means to “force” the droplet into the channel, the SU-8 requires a critical dimension (as the depth of the well is fixed, this critical dimension is between the 2D length and width of the channel) on the order of 10 microns (in this case, 25 microns).

[0094] The gFET was measured with a semiconductor parameter analyser (The Keithley 4200A- SCS set-up shown in figure 4), using O.lx phosphate buffered saline (PBS, a common biological solvent) as the liquid gate. The resistance of the graphene in the channels was in the kQ range. Single run measurements of the drain source current vs the gate voltage was taken using a source drain bias of 0.2V, 0.5V and 0.7V. Each bias showed a notable Dirac Voltage (typically between 0.8V- IV). This voltage is the point at which the conduction mode of the graphene turns from conducting via electrons rather than holes, and it is highly sensitive to surfaces charges. Following this, an 11 step drain source to gate voltage measurement was made measuring for biases from 0V to IV (in 0.1V) the normalised data is shown in figure 5, demonstrating the Dirac point across all biases.

[0095] At maximum operational power, this system required a maximum of 2.5V with a maximum current draw of -0.1mA. Based on the Maxell datasheet for the CR2032 watch battery (3V, ~230mAh), the device could be powered with one battery for 23 hours of continuous operation at this level. At the current transistor size (which we aim to reduce), operating one million of these transistors for 1 second at this maximum power draw would require -100 W. This is in the same range as a home game console system. Further device operation specifically in terms of size reduction can reduce these requirements.

[0096] Photoresist removal

[0097] • Inspect the photoresist covered chip. Tears in the graphene can be visible through the photoresist. If the graphene is intact in places where the graphene is needed, then the chip can be used.

[0098] • Place the chip in Xylene and leave in the fume hood (at least overnight).

[0099] • After removal from the xylene, the chip is rinsed in acetone for 3 minutes with gentle agitation, followed by 3 minutes in isopropanol (IP A) (also gentle agitation) before the chip is dried in an N2 steam.

[0100] Lithography layers were patterned using KLayout

[0101] Marker layer - Purpose is to align the following layers. Since this is a multilayer lithographic process, each layer must be aligned with the previous one. The markers will allow this process.

[0102] Notes: Marker layer is always first, and at present is deposited alone. This is because it requires graphene to be removed before depositing Au on the surface (as there are tearing issues if Au is removed directly from graphene), which will break electrical contact if electrodes are deposited at the same time. Later deposition of graphene would be an ideal solution but at present this is the best path.

[0103] • After cleaning the chip (this should be done immediately after the photoresist removal. If the chip had the photoresist removed and then was stored for more than 1 hr before the marker layer was started, then perform the cleaning step again, this time cleaning in xylene for 3 min, followed by the acetone / IPA washes and rinses described above), A4 PMMA is deposited, and spin coated at a speed of 500rpm on the Polos spinner.

[0104] • The coated chip is pre-baked at 180°C for 90 seconds. • The chip is then exposed with an Elionix F-125 lithography system. A beam of InA is used, with a .con file of set to dose at 1250uC / cm2.

[0105] • The PMMA is developed using 3:1 MiBKJPA. PMMA is immersed in the developer for 40 seconds before being rinsed in IPA for 20s. The sample is then dried using N2 steam.

[0106] • The chip is then plasma cleaned using an O2 plasma (at a pressure of 30mTorr, and power of 50W) in the Southbay reactive ion etcher (RIE) for 25 seconds.

[0107] • A Ti layer (lOnm at a rate of lA / s) is deposited using an E-beam evaporation system (AJA). Au is then deposited (30nm at 2A / s) without breaking the vacuum.

[0108] • Following this, the chip is immersed in xylene at least overnight to lift-off the PMMA and Au.

[0109] • When removing the chip from the xylene, clean the chip in acetone and IPA, following the same method as the photoresist process.

[0110] Graphene Layer - Graphene is not required to be everywhere on the surface, just to exist between source and drain electrodes. Any further graphene can cause shorts.

[0111] • On a recently cleaned chip with markers, deposit, and spin coat PMMA A4 at 5000rpm (with the Polos once again).

[0112] • Bake the PMMA covered chip at 180°C for 90 seconds.

[0113] • The chip is then exposed with an Elionix F-125 lithography system. A beam of lOnA is used, with a .con file of set to dose at 1250uC / cm2. This layer requires global registration with the alignment markers. Use BSED rather than SED for alignment.

[0114] • The PMMA is developed using 3:1 MiBKTPA. PMMA is immersed in the developer for 40 seconds before being rinsed in IPA for 20s. The sample is then dried using N2 steam.

[0115] • Graphene is the removed in the RIE using an O2 plasma (at a pressure of 30mTorr, and power of 50W) for 60 seconds.

[0116] • Following this, the chip is immersed in xylene at least overnight to lift-off the PMMA.

[0117] • When removing the chip from the xylene, clean the chip in acetone and IPA, following the same method as the photoresist process. Electrode Layer - Four electrodes, two of which are the source and drain (the connecting to the ends of the graphene, these supply a current to the graphene), and the other two being gates (these electrodes supply an electric field through the liquid by the application of a voltage bias).

[0118] • On a recently cleaned chip with markers, deposit, and spin coat PMMA A4 at 5000rpm (with the Polos once again).

[0119] • Bake the PMMA covered chip at 180°C for 90 seconds.

[0120] • The chip is then exposed with an Elionix F-125 lithography system. A beam of InA is used, with a .con file of set to dose at 1250uC / cm2. This layer requires global registration with the alignment markers. Use BSED rather than SED for alignment.

[0121] • The PMMA is developed using 3:1 MiBKTPA. PMMA is immersed in the developer for 40 seconds before being rinsed in IPA for 20s. The sample is then dried using N2 steam.

[0122] • A Ti layer (lOnm at a rate of lA / s) is deposited using an E-beam evaporation system (AJA). Au is then deposited (30nm at 2A / s) without breaking the vacuum.

[0123] • Following this, the chip is immersed in xylene at least overnight to lift-off the PMMA and Au. The lift off from the area where the graphene has been removed will be much cleaner than previous lift-offs.

[0124] • When removing the chip from the xylene, clean the chip in acetone and IPA, following the same method as the photoresist process.

[0125] Encapsulation layer - The purpose of this layer is to ensure that the gates and the graphene are in contact with the gating liquid, but the rest of the device is not. This prevents shorts between the source and drain and ensures that the field runs through the liquid only (Note: As the thickness of the SU-8 was set by the dilution of the polymer, the 2D dimensions were critically important in allowing the liquid into the cell. In microfluidics, the pressure required to force liquid into a well is much higher than at the macroscale. In the current set-up, the mass of the liquid is what forces it down, and the surface tension of the contacting materials also play a role. In these conditions, the smallest dimension in either the length or the width must be in the order of magnitude of tens of microns. For this reason, the well was made long, with a width of ~28um. The chip design to follow this will be integrated into a device allowing more force which means this feature size can be changed in those designs).

[0126] • On a recently cleaned chip with markers, deposit, and spin coat SU-8 2005 at 4000rpm (with the Polos once again).

[0127] • Bake the SU-8 covered chip at 100°C for 180 seconds.

[0128] • The chip is then exposed with an Elionix F-125 lithography system. A beam of 500pA is used, with a .con file of set to dose at 2uC / cm2. This layer requires global registration with the alignment markers. Use BSED rather than SED for alignment.

[0129] • The chip is then post baked at 100°C for 180 seconds. The pattern should be partially visible at this point.

[0130] • The SU-8 is developed using PGMEA. SU-8 is immersed in the developer for 60 seconds before being rinsed in IPA for 30s. The sample is then dried using N2 steam.

[0131] Measurement of gFET

[0132] • Conducted using a Keithley 4200A-SCS Parameter Analyser. A PDMS well (~ 5mm) was placed around the gate and graphene area of the gFET, and 20uE of O.lx PBS was pipetted into the well.

[0133] • Measurements were taken at room temperature, measuring the current between the source-drain as a function of the voltage applied to the liquid gate. These measurements were taken at over a series of different biases applied to the sourcedrain electrodes (from 0V to IV with 0.1V increments).

[0134] An I-V (current vs voltage) curve of the gFET (from the drain to source) at room temperature while the liquid gate was immersing the gFET was taken. The figure can be seen in figure 7. The resulting resistance of the device was found to be IkQ.

[0135] The reference in this specification to any prior publication (or information derived from it), or to any matter which is known, is not, and should not be taken as an acknowledgment or admission or any form of suggestion that that prior publication (or information derived from it) or known matter forms part of the common general knowledge in the field of endeavour to which this specification relates. Throughout this specification and the claims which follow, unless the context requires otherwise, the word "comprise", and variations such as "comprises" and "comprising", will be understood to imply the inclusion of a stated integer or step or group of integers or steps but not the exclusion of any other integer or step or group of integers or steps.

[0136] Throughout this specification and the claims which follow, unless the context requires otherwise, the phrase "consisting essentially of", and variations such as "consists essentially of" will be understood to indicate that the recited element(s) is / are essential i.e. necessary elements of the invention. The phrase allows for the presence of other non-recited elements which do not materially affect the characteristics of the invention but excludes additional unspecified elements which would affect the basic and novel characteristics of the method defined.

Claims

THE CLAIMS DEFINING THE INVENTION ARE AS FOLLOWS:

1. A method of fabricating a gFET device or component thereof which minimises or prevents graphene delamination, damage, and / or reducing defects, said gFET device or component characterised by at least one drain, source and gate electrode, said method comprising the steps of at least one graphene deposition step, at least one lithography step, and at least one O2 plasma etching step, and wherein after each one of the aforementioned steps the graphene layer is cleaned with a methylbenzene, followed by a ketone, and then followed by an alcohol.

2. A method of fabricating a gFET device or component thereof which minimises or prevents graphene delamination, damage, and / or reducing defects, said gFET device or component characterised by at least one drain, source and gate electrode, said method comprising the steps of at least one graphene deposition step, at least one lithography step, and at least one O2 plasma etching step, and wherein after each one of the aforementioned steps the graphene layer is cleaned with a methylbenzene, followed by a ketone, and then followed by an alcohol, and wherein the method further comprises at least one polymer resist coating layer which is developed using a methyl isobutyl ketone (MiBK): isopropanol (IPA) mixture in a ratio of about 3:1.

3. A method of fabricating a gFET component which minimises or prevents graphene delamination, damage, and / or reducing defects on the graphene layer, said method comprising the steps of: a) providing a SiCF / Si wafer substrate characterised with a graphene layer; b) cleaning the graphene deposited layer with a methylbenzene; c) cleaning the layer after step b) with a ketone; and d) cleaning the layer after step c) with an alcohol; e) depositing a polymer resist on the graphene layer after step d); f) defining areas where graphene will remain on wafer substrate using lithography; g) removing any unneeded graphene using O2 plasma etching;h) cleaning off any remaining polymer resist using a methylbenzene; i) cleaning the remaining graphene layer with a ketone; j) cleaning the graphene layer after step i) with an alcohol; k) depositing an adhesive layer comprising Ti or Cr unto the graphene surface layer after step j); l) depositing a metal electrode material layer unto the adhesive layer after step k); m) stripping the metal layer of step 1) to form the gFET component which comprises at least one drain, source and gate electrodes.

4. A method of fabricating a gFET device which minimises or prevents graphene delamination, damage, and / or reducing defects on the graphene layer, said method comprising the steps of: a) providing a SiCE / Si wafer substrate characterised with a graphene layer; b) cleaning the graphene deposited layer with a methylbenzene; c) cleaning the layer after step b) with a ketone; and d) cleaning the layer after step c) with an alcohol; e) depositing a polymer resist on the graphene layer after step d); f) defining areas where graphene will remain on wafer substrate using lithography; g) removing any unneeded graphene using O2 plasma etching; h) cleaning off any remaining polymer resist using a methylbenzene; i) cleaning the remaining graphene layer with a ketone; j) cleaning the graphene layer after step i) with an alcohol; k) depositing an adhesive layer comprising Ti or Cr unto the graphene surface layer after step j); l) depositing a metal electrode material layer unto the adhesive layer after step k); m) stripping the metal layer of step 1) and n) depositing an encapsulation layer to form the gFET device which comprises at least one drain, source and gate electrodes, and wherein only the source and drain metallic electrode is encapsulated to prevent shorting, while the graphene and at least part of the gate electrode is unencapsulated and therefore exposed.

5. A method of fabricating a graphene field effect transistor (gFET) component comprising a graphene layer deposited on SiCh / Si substrate and wherein said gFET is characterised with at least one drain, source and gate electrodes, said method comprising the steps of: i) providing a SiCE / Si wafer substrate; ii) depositing a CVD (chemical vapour disposition) grown graphene layer to the surface of said wafer substrate by polymer deposition transfer; iii) cleaning the graphene deposited later with a methylbenzene; iv) cleaning the layer after step iii) with a ketone; v) cleaning the layer after step iv) with an alcohol; vi) depositing a polymer resist on the layer after step v) wherein the layer is developed using a methyl isobutyl ketone (MiBK): isopropanol (IPA) mixture in a ratio of about 3:

1. vii) defining areas where graphene will remain on wafer substrate using lithography; viii) removing unneeded graphene using O2 plasma etching; ix) cleaning off any remaining PMMA resist using a methylbenzene; x) cleaning the remaining graphene layer with a ketone; xi) cleaning the graphene layer after step x) with an alcohol; xii) depositing an adhesive layer comprising Ti or Cr unto the graphene surface layer after step xi); xiii) depositing a metal electrode material layer unto the adhesive layer after step xii); and xiv) stripping the metal layer of step xiii) to form the gFET component which comprises at least one drain, source and gate electrodes.

6. A method of fabricating a graphene field effect transistor (gFET) device comprising a graphene layer deposited on SiCE / Si substrate and wherein said gFET is characterised with at least one drain, source and gate electrodes, said method comprising the steps of: i) providing a SiCE / Si wafer substrate;ii) depositing a CVD (chemical vapour disposition) grown graphene layer to the surface of said wafer substrate by polymer deposition transfer; iii) cleaning the graphene deposited later with a methylbenzene; iv) cleaning the layer after step iii) with a ketone; v) cleaning the layer after step iv) with an alcohol; vi) depositing a polymer resist on the layer after step v) wherein the layer is developed using a methyl isobutyl ketone (MiBK): isopropanol (IPA) mixture in a ratio of about 3:

1. vii) defining areas where graphene will remain on wafer substrate using lithography; viii) removing unneeded graphene using O2 plasma etching; ix) cleaning off any remaining PMMA resist using a methylbenzene; x) cleaning the remaining graphene layer with a ketone; xi) cleaning the graphene layer after step x) with an alcohol; xii) depositing an adhesive layer comprising Ti or Cr unto the graphene surface layer after step xi); xiii) depositing a metal electrode material layer unto the adhesive layer after step xii); and xiv) stripping the metal layer of step xiii); and xv) depositing an encapsulation layer to form the gFET device which comprises at least one drain, source and gate electrodes, and wherein only the source and drain metallic electrode is encapsulated to prevent shorting, while the graphene and at least part of the gate electrode is unencapsulated and therefore exposed.

7. A method according to any one of claims 1 to 3 and claim 5, further involving a step of depositing an encapsulation layer.

8. A method according to anyone of claims 1 to 7 wherein the methylbenzene is selected from xylene (ortho-xylene, meta-xylene, or para-xylene), toluene, hemellitene (1,2,3-trimethylbenzene), mesitylene (1,3,5-trimethylbenzene), pseudocumene (1,2,4-trimethylbenzene), prehnitene (1,2,3,4-tetramethylbenzene),isodurene (1,2,3,5-tetramethylbenzene), durene (1,2,4,5-tetramethylbenzene), and hexamethylbenzene.

9. A method according to anyone of claims 1 to 7 wherein the methylbenzene is xylene.

10. A method according to anyone of claims 1 to 9 wherein the ketone is selected from acetone, ethyl acetate, cyclohexanone, methyl ethyl ketone, or diacetone.

11. A method according to anyone of claims 1 to 10 wherein the ketone is acetone.

12. A method according to anyone of claims 1 to 11 wherein the alcohol is selected from isopropanol (IPA), n-propanol, n-butanol, isobutanol, tert-butanol, or n- pentanol.

13. A method according to anyone of claims 1 to 12 wherein the alcohol is isopropanol (IPA).

14. A gFET device or component thereof produced by the method according to anyone of claims 1 to 13.

15. A method according to anyone of claims 1 to 14 wherein the intensity of the graphitic peak at approx. 2650cm1is increased by at least 17% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g., acetone and IPA).

16. A method according to anyone of claims 1 to 14 wherein the intensity of the graphitic peaks at approx. 1600cm1and approx. 2650cm1are both increased by at least 5% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g., acetone and IPA).

17. A method according to anyone of claims 1 to 14 wherein the intensity of the graphitic peaks at approx. 1600cm1and approx. 2650cm1are both increased by at least 7% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g., acetone and IPA).

18. A method according to anyone of claims 1 to 14 wherein the intensity of the graphitic peaks at approx. 1600cm1and approx. 2650cm1are both increased by at least 10% after the three cleaning steps compared to an equivalent graphene deposited layer which has only been cleaned by a ketone and alcohol (e.g., acetone and IPA).

19. A method according to claim 7 wherein the encapsulation layer is developed by a glycol ether or acetate such as propylene glycol methyl ether acetate (PGMEA).

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