Method for producing an electrical line arrangement, and electrical line arrangement

Abstract

The invention relates to a method for producing an electrical line arrangement, primarily for the microwave and / or millimetre wave frequency range, and an electrical line arrangement preferably produced by said method. The method for producing an electrical line arrangement comprises the following steps: a) producing a support structure (20), wherein at least a first subregion (120) of the support structure (20) is created by means of a freeform microstructuring method, wherein at least a second subregion (220) of the support structure (20) comprises an electrically insulating material, and wherein the support structure (20) has at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h) with respect to a projection direction (100); and b) producing at least one electrical line structure (1) by coating the support structure (20) with at least one electrically conductive material, wherein the coating comprises at least one spatially directed coating process, which is oriented along the projection direction (100) aligned with at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h). The present invention makes it possible to provide a support structure (20) with integrated undercuts (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h), in particular to produce electrical line structures (1) on substrates (40, 41) of high-frequency (HF) chips, or to produce electrical line transitions (60a-60c, 61a-61c) to already existing electrical line structures (50a-50c, 51a-51c).

Description

[0001] Method for producing an electrical line arrangement and electrical line arrangement

[0002] Field of the invention

[0003] The present invention lies in the field of microwave technology and relates to a method for producing an electrical conductor arrangement, especially for the microwave and / or millimeter-wave frequency range, as well as an electrical conductor arrangement preferably produced using this method. The present invention makes it possible to provide a carrier structure with integrated undercuts, in particular for producing electrical conductor structures on substrates of radio-frequency (RF) chips, or electrical conductor transitions to existing electrical conductor structures. By appropriately designing the carrier structure, a multitude of differently designed electrical conductor arrangements can be produced.

[0004] State of the art

[0005] Standaert et al., Three techniques for the fabrication of high precision, mm-sized metal components based on two-photon lithography, applied for manufacturing horn antennas for THz transceivers, J. Micromech. Microeng. 28, 035008, 2018, describe the current state of the art in the production of RF components using two-photon lithography. In one of the processes presented therein, support structures are first produced using two-photon lithography, the entire surfaces of which are then vapor-deposited using a PVD process. A thicker copper layer is then formed using electroplating. This process cannot be used to produce isolated electrically conductive structures because the vapor deposition covers the entire surface of the structure, in particular to uniformly wet the entire structure by providing a seed layer for the subsequent electroplating.After production, the structures are positioned manually or mechanically; this does not allow the production of corresponding components on substrates with different conductive structures.

[0006] M. Sterner et al., "Electrochemically Assisted Maskless Selective Removal of Metal Layers for Three-Dimensional Micromachined SOI RF MEMS Transmission Lines and Devices," J. Microelectromechanical Systems 20 (4), pp. 899-908, 2011, describe a method for producing an electrical line arrangement by vapor deposition of a silicon cover layer that is first selectively etched using a mask, and by subsequent under-etching of a silicon dioxide intermediate layer that is arranged between a silicon wafer and the silicon cover layer. In this process, the electrical line arrangements are formed on the surfaces of the silicon cover layer with direct "line of sight" to the vapor deposition source and remain electrically insulated from one another, since the under-etching of the intermediate layer can create a shadow of the silicon cover layer on the silicon wafer.While this makes it possible to produce electrically conductive structures that are insulated from one another, the conductive structures still unintentionally created on the surface of the silicon wafer due to the direct "line-of-sight" to the vapor deposition source are located in close proximity to the actual conductive structures on the surfaces of the silicon capping layer due to the fixed and low height of the silicon dioxide intermediate layer and can, for example, cause electrical cross-coupling. It is therefore imperative to remove these unwanted structures to ensure the electrical insulation of the electrically conductive structures. Furthermore, due to the use of a planar layer structure consisting of silicon and silicon dioxide and subsequent selective etching of the silicon capping layer using a mask, this process is limited to planar conductive arrangements and, in particular, cannot provide conductive transitions.

[0007] AQ Liu et al., "Low-loss lateral micromachined switches for high frequency applications." Journal of Micromechanics and Microengineering 15.1, 2004, pp. 157-167, presents two lateral RF MEMS switches. These switches are implemented in a quasi-finite coplanar waveguide (FGCPW) configuration and driven by applying an electrostatic force to a high-aspect-ratio cantilever. The lateral switches are fabricated by deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer using shadow mask technology.

[0008] EP 511360 A1 discloses an electron source comprising, on a substrate, a dielectric layer having at least one cavity in which a cathode electrode in the form of a projection is arranged, a first gate electrode lying on top of the dielectric layer and at least partially surrounding the cavity, and at least one second gate electrode lying on the same side as the first gate electrode with respect to the top of the dielectric layer, wherein the first gate electrode lies between the cavity and the second gate electrode and the two electrodes are insulated from each other and wherein both gate electrodes are arranged on top of the dielectric layer, wherein the second gate electrode is thicker than the first gate electrode.US 2002 / 0167009 A1 discloses a thin-film transistor for a liquid crystal display and a method for its fabrication, which allows for a reduction in the number of photomasks used in a photolithography process compared to conventional processes. A passivation film is formed as a single-layer organic insulating film, and the number of required exposure steps is reduced to reduce the number of photomasks required, thereby improving the efficiency of the production process.

[0009] DE 10 2007 010 462 A1 discloses a method for producing a micromechanical particle beam source having at least one field emitter tip for emitting particles, the method comprising the following steps: - applying at least one surface layer made of an electrically semiconducting or conductive material to the surface of a substrate, - structuring the at least one surface layer applied to the substrate in such a way that a track as narrow as possible and of low height is produced, - partially removing exposed regions of the electrically insulating substrate surface lying between the tracks in such a way that the covering of the regions of the newly created electrically insulating substrate surface by the overlying surface layers is prevented, - applying a further conductive layer to the surface thus created,and - applying the field emitter tip to the narrow track and precisely positioning the field emitter tip with an accuracy of a few nm in the center of the optical axis of the micromechanical particle beam source.

[0010] DE 10 2020 102 372 A1 discloses a component carrier comprising a stack having at least one electrically conductive layer structure and / or at least one electrically insulating layer structure, a tapered blind hole formed in the stack, and an electrically conductive plating layer extending along at least a portion of a horizontal surface of the stack outside the blind hole and along at least a portion of a surface of the blind hole, wherein a minimum thickness of the plating layer at a bottom of the blind hole is at least 8 pm.

[0011] Object of the invention

[0012] Based on this, the object of the present invention is to provide a method for producing an electrical line arrangement and an electrical line arrangement which at least partially overcome the disadvantages and limitations of the prior art. The object of the present invention is, in particular, to enable the production of a component which has electrically conductive structures which are insulated from one another within a cross-sectional plane, without the need to remove the additional conductive structures undesirably created by the direct "line-of-sight" to a vapor deposition source in order to ensure the electrical insulation of the line arrangement. Furthermore, the present invention is not intended to be limited to the production of planar line arrangements.

[0013] Disclosure of the invention

[0014] This object is achieved by a method for producing an electrical cable arrangement and an electrical cable arrangement having the features of the independent patent claims. Advantageous further developments, which can be implemented individually or in any combination, are presented in the dependent claims.

[0015] In a first aspect, the present invention relates to a method for producing an electrical line arrangement. The steps of the method are as follows: a) producing a support structure, wherein at least a first partial region of the support structure is produced by means of a freeform microstructuring method, wherein at least a second partial region of the support structure comprises an electrically insulating material, and wherein the support structure has at least one undercut with respect to a projection direction; and b) producing at least one electrical line structure by coating the support structure with at least one electrically conductive material, wherein the coating comprises at least one spatially directed coating process that is oriented along the projection direction aligned with the at least one undercut.

[0016] The term "electrical conduction arrangement" refers to an arrangement configured for transporting and / or modifying electromagnetic waves. The electrical conduction arrangement proposed herein comprises a carrier structure which, in at least a first partial region of the carrier structure, was produced using a freeform microstructuring process, consists of an electrically insulating material in at least a second partial region of the carrier structure, and wherein an electrical conduction structure is applied to the carrier structure. The electrical conduction structure comprises one or more electrically conductive structures, which may in particular also be designed as electrical lines or as waveguides.A set or a subset of the electrically conductive structures, which are electrically separated from one another or electrically connected to one another in a defined manner within one or more cross-sectional planes, forms the desired electrical conduction structure. By specifically designing the majority of the electrically conductive structures, in particular by connecting them outside a specific cross-sectional plane, a plurality of different electrical conduction structures can be produced on the support structure, which, together with the electrical conduction structure, form the electrical conduction arrangement.

[0017] The present invention relates to any type of electromagnetic waves, as long as they can be guided in an electrical line designed as a waveguide. However, electromagnetic waves having a wavelength X of 3 pm < k < 1 m are preferred. Electromagnetic waves

[0018] - of 3 pm < < 3 mm, also known as ‘terahertz waves’ or ‘THz waves’; and / or

[0019] - of 300 pm < X < 1 cm, which are called “millimeter waves”; and / or

[0020] - of 1 mm < k < 1 m, which are called ‘microwaves’.

[0021] According to process step a), the carrier structure is manufactured at least in a first partial area by means of a freeform microstructuring process. Here, the term “freeform microstructuring process” refers to a three-dimensional structuring process that comprises a subtractive or additive manufacturing process by means of which three-dimensional structures, preferably freeform structures, can be manufactured. In this context, a “freeform structure” is understood to mean a structure that – within the framework of technical limitations regarding resolution and accuracy – can have arbitrarily curved surfaces, at least in certain areas. A freeform structure therefore differs in particular from structural geometries that can be produced by classic planar microstructuring processes, i.e. in particular by a combination of thin-film deposition processes, two-dimensional lithography processes (e.g.Projection lithography) and etching processes on flat substrates. A combination of these processes generally leads to prism-like three-dimensional structural geometries, each of which has a base and top surface essentially parallel to the substrate surface, which are identical or very similar in shape to one another, and which - depending on the deposition and etching processes used - are connected to one another by side walls that are perpendicular or inclined to the substrate surface and / or curved inwards or outwards. The shape of the base and top surfaces is essentially predetermined by a mask used for local etching or deposition, often lithographically structured. By repeatedly repeating the deposition and etching processes with different masks, multilayer structures comprising several prism-like substructures can be constructed.However, the additional effort associated with this repetition is considerable and, in many cases, limited by the overlay accuracy, so that in practice the number of layers that can be produced is often limited to a few, for example, only three. This leads to geometric limitations of the structures that can be produced with reasonable effort using known microstructuring processes and thus to functional limitations of the resulting components.

[0022] In contrast, freeform structures produced by freeform microstructuring processes are not subject to these limitations, or not to the same extent, because their structural geometry is not restricted to a combination of a comparatively small number of flat, prism-like substructures. This makes it possible, in particular, to use the partial area of ​​the support structure defined by a freeform structure to design an electrical wiring arrangement that no longer necessarily has to be planar. It should be noted that in many cases, freeform structures are also produced from a multitude of individual layers—in particular, by means of multilayer material deposition in 3D printing or by curing different layers in 3D lithography processes.Freeform microstructuring processes, however, make it possible to select the number of these layers with a reasonable manufacturing effort so large that a good approximation of the freeform structure is achieved and that discretization into individual layers no longer represents a practically functionally relevant limitation of the producible structural geometries. The structures are preferably constructed from more than 10, particularly preferably from more than 20, in particular from more than 40 or 50 layers. When producing an electrical line arrangement designed for a vacuum operating wavelength of approximately 1 mm, the thickness of a layer is preferably between 100 nm and 10 pm, particularly preferably between 500 nm and 5 pm, in particular between 100 nm and 1 pm. This makes it possible to produce electrical line structures with an accuracy of preferably better than 10 pm, particularly preferably better than 5 pm, in particular better than 1 pm.The resolution of the freeform microstructuring process is preferably better than 20 pm, particularly preferably better than 5 pm, and especially better than 1 pm. The above-mentioned numerical values ​​refer to the production of an electrical conductor arrangement configured for a vacuum operating wavelength of approximately 1 mm. For other vacuum operating wavelengths, the dimensions of the structures and thus the requirements for the accuracy and resolution of the microfabrication process used for production can be scaled accordingly, particularly taking into account the refractive indices of the materials used.Depending on the design, different or the same freeform microstructuring processes can be used to produce the partial area of ​​the support structure produced by a freeform microstructuring process, optional additional shading structures and optional mechanical protective structures or protective layers, whereby all structures can be produced in a common operation when using the same freeform microstructuring process.

[0023] In a preferred embodiment, the freeform microstructuring process and / or a freeform microstructuring unit configured for such a process can be based on a lithographic process, which in particular uses stereolithography or direct-writing, preferably three-dimensional direct-writing, lithography processes. Additive or subtractive manufacturing processes can be used. The term "additive manufacturing process" refers to a manufacturing process in which material is gradually added to or applied to a structure, while the term "subtractive manufacturing process" describes an alternative manufacturing process in which material is gradually removed from a structure.In a preferred embodiment, the material deposition or material removal can be achieved with lithographic processes using suitable photoresists, in particular negative or positive resists. In a preferred embodiment, area light modulators, which allow rapid structuring, can be used in a stereolithography process. In a preferred embodiment, multi-photon lithography processes, in particular using pulsed laser sources, can be used as direct-writing lithography processes. Light pulses with a pulse duration of at most 10 ps, ​​preferably of at most 1 ps, particularly preferably of at most 200 fs, in particular of at most 100 fs, at a repetition rate of preferably at least 1 MHz, preferably of 10 MHz, particularly preferably of at least 25 MHz, in particular of at least 80 MHz, can be used.Laser light sources selected from fiber-based femtosecond lasers or pulsed solid-state lasers, preferably titanium:sapphire lasers or diode lasers, are particularly suitable for this purpose. These can be combined with frequency conversion units, which are particularly designed for frequency multiplication, sum frequency generation, or difference frequency generation. Depending on the lithography process used, wavelengths in the near-infrared, visible, or ultraviolet spectral range, or in the extreme UV radiation (EUV) or X-ray wavelength range, can preferably be used. In a particularly preferred embodiment, the wavelengths can be in a range from 150 nm to 1700 nm, in particular in a range from 300 nm to 1100 nm. In the case of pulsed lasers, two-, three-, or multi-photon absorption effects can be achieved by selecting the pulse duration and pulse energy.For lithography processes based on single-photon absorption using continuous-wave lasers or LEDs, emission wavelengths between 360 nm and 550 nm are suitable, especially around 365 nm, 385 nm, 405 nm, 550 nm and 532 nm. To increase the resolution of lithography processes, the principle of "stimulated emission depletion" (STED) can be used with suitable photoinitiators, similar to corresponding microscopy techniques.

[0024] In a specific embodiment, it may happen that the partial area of ​​the support structure produced by a freeform microstructuring process, the additional shading structures, the mechanical protection structures, or the protective layers are larger than the available write field size of the machine used for production by means of the freeform microstructuring process. In these cases, the structures in question can be divided into individual sections, each located within a write field, and produced by precisely stitching these sections together. The selection of the write field size can be made, in particular, by considering the achievable resolution, which typically improves with smaller write fields, and stitching errors at write field boundaries, the number of which can be reduced with large write fields. The write field size is preferably between 50 x 50 μm 2 and 5 x 5 mm2 , particularly preferably between 100 x 100 m 2 and 3 x 3 mm 2 , and most preferably between 200 x 200 pm 2 and 1 x 1 mm 2 The alignment accuracy of the individual writing fields relative to one another is preferably better than 5 pm, particularly preferably better than 1 pm, in particular better than 500 nm or 100 nm. In a particular embodiment, a two-photon lithography system is used for production. In this case, the available writing field for lenses with a numerical aperture of 1.4 and a magnification of 40x can, for example, take the form of a circular area with a diameter of 400 pm.

[0025] In certain embodiments, the first partial region of the support structure produced by a freeform microstructuring process can also comprise conductive materials. In this case, methods for 3D printing metals can preferably be used, which can be based in particular on material extrusion, powder bed fusion, material jetting, binder jetting, replica molding, selective laser melting, laser metal deposition or electron beam melting. In a particularly preferred embodiment, a polymer with a high proportion of particles (slurry), selected from e.g. copper, stainless steel or other conductive materials, can be produced. By subsequently baking the component in an oven, the polymer bonds are opened and burned out.debinding and sintering), leaving behind a conductive workpiece that closely reflects the properties of the material from which the particles are made.

[0026] In addition to the partial area created by the freeform microstructuring process, the support structure can also comprise further partial areas that are not structured or are structured by other processes. Cases are thus possible in which the support structure comprises an essentially flat substrate on which a further partial area of ​​the support structure is created by the freeform microstructuring process, which partial area of ​​the support structure, either on its own or together with the substrate, has the undercut defined below. Suitable substrates are particularly silicon (Si), gallium arsenide (GaAs), indium phosphide (InP), aluminum oxide (Al2O3), beryllium oxide, quartz glass, sapphire, (woven) PTFE / glass, polyolefin, ferrite / granite or a ceramic. Furthermore, the substrate can also comprise an electrically conductive partial area.When coating a carrier structure comprising a substrate, it may be possible in particular for the at least one free surface defined by the at least one undercut in the carrier structure, which is designed to insulate the electrically conductive structures adjacent thereto, to be arranged on the substrate and, for example, not to be arranged on the partial region produced by the freeform microstructuring process or the partial region of the carrier structure consisting of an insulating material.

[0027] The carrier structure produced according to method step a) further comprises at least a second partial region comprising an electrically insulating material, which

[0028] - on the one hand, it provides a mechanically stable and at least partially electrically insulating base for a subsequent coating with the at least one electrically conductive material according to process step b); and

[0029] - on the other hand, it can be brought into a desired geometric, not necessarily planar, shape, on which the desired electrical conduction structure is formed by the coating carried out according to process step b).

[0030] For the purposes of the present invention, “electrically insulating material” is defined as a substance whose electrical conductivity G is at most 10' 4 S / m, preferably no more than 10' 7 S / m, in particular not more than 10' 10S / m. In addition, the electrically insulating material preferably has a high dielectric strength and preferably low losses, in particular in the form of a low loss factor tan<5 of at most 0.1; preferably at most 0.05; in particular at most 0.01 at the respective operating frequency of the electrical line structure. Here, the term “operating frequency” refers to a frequency of the electromagnetic wave for which a selected electrical line arrangement is preferably designed. Analogously, the term “operating wavelength” is specified as the wavelength of the electromagnetic wave for which a selected electrical line arrangement is preferably designed.Suitable materials for the at least one electrically insulating partial region of the support structure are preferably ceramics, glasses, polymers or other organic compounds or appropriately doped semiconductors as well as composite materials made of the aforementioned materials. In particular, materials that can be three-dimensionally structured using appropriate methods are suitable, wherein in a preferred embodiment the methods and the associated materials are selected such that the production of free-form structures is possible. In a preferred embodiment, polymer-based materials are used to produce the support structure, which materials preferably contain an optically additively or subtractively structurable polymer, e.g. from the class of acrylates, an epoxy resin or a fluoropolymer.If a lithography process is used in process step a) to structure a polymer-based material, polymers can preferably be used which can in particular be fluorinated or can have polysiloxane-based components.

[0031] In a particularly preferred embodiment, the first partial region produced in method step a) by a freeform microstructuring process can be identical to the second partial region comprising the electrically insulating material. However, the two regions can also be disjoint or non-overlapping, or they can fully or partially encompass each other. An example in which the second partial region completely encompasses the first partial region arises when an electrically conductive region of the substrate is replaced by an insulating substrate, so that only the insulating second partial region was produced by 3D printing. In a further example in which the two regions are disjoint, the carrier structure has a metallic core comprising a metallic substrate and an insulating coating.The core filling the first sub-area is created in the first sub-area of ​​the support structure using a freeform microstructuring process, while an insulating coating can be applied independently in the second sub-area of ​​the support structure subsequently, particularly using an isotropic coating process. In this example, the two sub-areas are thus disjoint.

[0032] According to method step a), the support structure is produced in such a way that it has at least one undercut with respect to a projection direction. The terms “undercut”, “undercutting”, “undercut” or “undercutting” each refer to an overhang defined with respect to a projection direction, which is introduced into the surface of the support structure. A geometric definition of the term “undercut” is illustrated by way of example in Figure 3, which shows a support structure with an undercut defined with respect to a projection direction p, with an associated shaded area. The shaded area comprises the totality of all points P on the surface of the support structure for which a half-line g starting from point P and oriented opposite to the projection direction p intersects the support structure.The totality of the sections of all such half-lines g located inside the support structure defines the sub-area of ​​the support structure referred to as the overhang. The overhang defines a shaded area, which includes the totality of the connecting lines PP ' of the points P located outside the support structure with the entry point P ' of the corresponding half-line g into the support structure that is closest to the projection direction p.

[0033] The at least one undercut is designed to create a shadow when the support structure is spatially coated with at least one electrically conductive material along the projection direction. The term "shadow" refers to a result of the coating of the support structure with the at least one electrically conductive material, whereby at least one free area on the surface of the support structure remains uncoated and is not covered by the electrically conductive material. Depending on the design of the coating process according to method step b) and depending on the directionality of the spatially anisotropic material flow, the uncoated area can be identical to the geometrically shaded area, at least partially encompass the shaded area, or be part of the shaded area.

[0034] According to process step b), the electrical conduction structure is produced by coating the support structure with at least one electrically conductive material. In a particular embodiment, the coating of the support structure can comprise multiple coating processes and / or materials, wherein at least one coating process is spatially directed and wherein at least one material must be electrically conductive in the sense defined herein. In a preferred embodiment, the at least one electrically conductive material is applied using a directed coating process.

[0035] For coating the support structure, a coating process suitable for this purpose can be used. The coating process can preferably be selected from a physical vapor deposition (PVD) process, in particular thermal evaporation, electron beam evaporation, laser beam evaporation, arc evaporation, molecular beam epitaxy, ion plating, or sputter deposition, wherein the sputter deposition comprises DC sputtering, RF sputtering, magnetron sputtering, reactive sputtering, ion beam sputtering, or atom beam sputtering; or from a chemical vapor deposition (CVD) process, including plasma-enhanced chemical vapor deposition (PECVD), thermal spraying, or electroplating.In these processes, the degree of spatial anisotropy, i.e. the directionality of the material transport during the coating process, can be adjusted using various parameters, in particular the pressure under which the coating takes place. In addition to spatially anisotropic, i.e. directed, coating processes, isotropic processes can also be used, in which the structures are coated on all sides. A variety of processes are conceivable here, such as dipping or spraying processes, spin coating, atomic layer deposition (ALD) or galvanic processes. In a special embodiment, an isotropic coating with an inert protective material can be applied after a directed coating with a metal, in particular to prevent oxidation of the metal areas.In a particular embodiment, the thickness of the electrically conductive structures of the electrical conduction structure applied from the at least one electrically conductive material can be increased by galvanic growth in order to increase the robustness of the coating, particularly under mechanical stress. The achieved thickness of the electrical conduction structure can preferably be greater than 1 μm, particularly preferably greater than 10 μm, in particular greater than 20 μm or 50 μm. The achieved thickness can be adapted for the respective material, in particular by adjusting the process parameters such as current density, temperature, and time.

[0036] For the purposes of the present invention, “electrically conductive material” refers to a substance whose electrical conductivity G is preferably at least 10 6 S / m, particularly preferably at least 10 7 S / m, in particular at least 5* 10 7S / m. Materials particularly suitable for this purpose include silver, copper, gold, and aluminum; however, the use of other metals is also possible. The electrical conduction structure can comprise a uniform region of a single electrically conductive material, a mixed phase of at least two different electrically conductive materials, in particular an alloy of at least two different metals, and / or a layer structure of at least two different layers, each comprising a uniform phase or a mixed phase.

[0037] In a preferred embodiment, a sequence of layers in the layer structure can be selected in a preferred manner. A preferred layer sequence can, in particular, comprise a first layer directly or indirectly adjacent to the support structure, which has an adhesion promoter with good adhesion properties with respect to a substrate arranged underneath and / or a layer arranged above, wherein the first layer can, in particular, comprise titanium, a core made of a material with high conductivity, preferably copper or gold, and an outer layer adjacent to the environment for passivation made of a chemically resistant material not prone to oxidation, preferably gold, silicon nitride, or silicon dioxide. In addition, at least one further layer, preferably titanium, can be introduced between the material of the core and the passivation to provide diffusion protection. The use of other materials is also possible.This allows the electrical conduction structure to be simultaneously configured for particularly high charge transport and particularly high resistance to the environment, in which aggressive substances, particularly oxygen, may be present in the electrically conductive material. The application of these layers does not necessarily have to be performed using a spatially directed process. For example, it can be particularly helpful for the passivation layer to use an isotropic process that protects the electrical conduction arrangement from multiple sides, preferably from all sides, such as atomic layer deposition or high-pressure vapor deposition.

[0038] A conductive layer thickness y of the electrical conduction structure can be estimated approximately in many cases, based on the skin effect and taking into account the vacuum operating frequency, particularly using equation (1):

[0039] Here, the conductive layer thickness y is defined as the resulting wall thickness of a fictitious round conductor, which has the same resistance to direct current as a solid conductor due to the skin effect at a frequency f. The absolute permeability g = g0)J. r consists of the permeability constant g0= 1.256 • 10 -6 N / A 2 and the relative permeability jj. r of the electrically conductive material used for the round conductor. The electrical conductivity of the electrically conductive material is <J bezeichnet. Zum Beispiel ergibt sich für Kupfer bei einer Vakuum-Betriebswellenlänge von ca. 1 mm und einer elektrischen Leitfähigkeit er = 5,8 • 10 6S / m, a conductive layer thickness of y = 0.12 pm. Therefore, when using the coating process, the layer thickness of the electrically conductive material is preferably selected to be at least three times, particularly preferably five times, and especially ten times, the conductive layer thickness at the desired operating frequency or the desired operating wavelength. For other operating wavelengths, the layer thicknesses can be scaled proportionally to the square root of the wavelength, particularly taking into account the conductivity of the electrically conductive materials used.

[0040] According to method step b), the coating of the support structure comprises at least one spatially directed coating process oriented along the projection direction aligned with the at least one undercut. This results in the application of the electrically conductive material to the support structure as an electrically conductive structure in the form of one or more electrically conductive structures that are electrically separated from one another or electrically connected to one another in a defined manner within a cross-sectional plane, wherein the direction of the coating corresponds to a projection direction related to the undercut.The at least one undercut introduced into the support structure, as already described above, causes at least one uncoated open area to form on the surface of the support structure, which provides electrical insulation between the electrically conductive structures adjacent to the at least one open area at desired locations on the surface of the support structure. In this way, the desired electrical conduction structure is formed on the surface of the support structure, comprising the majority of electrically conductive structures that are electrically separated from one another or electrically connected to one another in a defined manner within a cross-sectional plane.In this case, it is particularly advantageous if the at least one undercut is already produced during method step a) in such a way with knowledge of the projection direction desired during method step b), in particular that the final shape of the desired electrical conduction structure, which comprises the majority of electrically conductive structures that are electrically separated from one another or electrically connected to one another in a defined manner, is freely defined in space via the shape of the carrier structure and the at least one undercut introduced therein, taking into account the direct line of sight between each point E to be coated on the carrier structure and the location of the vapor deposition source from which the electrically conductive material used to coat the carrier structure is provided.

[0041] In a preferred embodiment, the process of physical vapor deposition (PVD), in particular electron beam or laser beam evaporation, can be used. By selecting a sufficient working distance between the location of the vapor deposition source and the support structure to be coated, a vapor deposition direction defined by the connecting line between the vapor deposition source and the support structure to be coated can be set to a good approximation, which corresponds to the desired projection direction related to the undercut according to the invention.The distance between the vapor deposition source and the support structure to be coated is preferably more than 25 cm, particularly preferably more than 50 cm, in particular more than 75 cm or 100 cm, so that the flow of the vapor deposition rays emanating from the vapor deposition source around the defined projection direction at the location of the support structure to be coated has a divergence of preferably less than 10°, particularly preferably less than 5°, in particular less than 2°. The term “divergence” at the location of the support structure to be coated refers to the variance or standard deviation of the directions in which the rays emanating from a vapor deposition source strike a specific point on the support structure. The variance can be determined in particular from a ratio of the lateral extent of the vapor deposition source to a distance of the vapor deposition source from the support structure to be coated.A high variance in the direction of the incident rays can generally lead to a corresponding blurring of the edge of the shadow created by the at least one undercut, which can have adverse effects on the properties of the electrical line arrangement to be created. A deviation between the actual vapor deposition direction and a desired projection direction related to the undercut according to the invention can preferably be at most 20°, particularly preferably at most 10°, and in particular at most 5° or 2°. A working pressure in the chamber of the coating system can preferably be selected such that a mean free path of the particles transferred during vapor deposition exceeds the distance between the vapor deposition source and the carrier structure to be coated.The term "mean free path" refers to the average path length traveled by a particle, particularly one selected from an atom, molecule, ion, or electron, in a given material before colliding with another particle. If a particle stream in a material has traversed the mean free path, a fraction 1 / e of the particle stream has not yet collided with another particle. The mean free path preferably exceeds the distance between the vapor deposition source and the support structure to be coated by a factor of at least 3, particularly preferably by a factor of at least 8 or 20, in particular by a factor of at least 100 or 200. The pressure in this case can typically have a value of 10'. 7 Pa to 10' 3 Pa, especially depending on the material chosen.

[0042] In a particular embodiment, when carrying out method step b), not only the desired electrical conduction structure can be formed, but also at least one further electrically conductive structure can be produced, which is not necessarily a functionally relevant component of the desired electrical conduction structure. It is therefore desirable for the at least one undercut to be designed such that the at least one further electrically conductive structure can be arranged at a sufficiently large distance from the desired electrical conduction structure. In such an arrangement, the influence of the additionally produced electrically conductive structure on the electromagnetic wave guided in the desired electrical conduction structure, which can also be referred to as a "mode", can preferably be minimized.In particular, in order to avoid coupling of a mode guided in the desired electrical conduction structure with at least one further electrically conductive structure, a distance can be specified between the two structures which is selected to be at least large enough that it exceeds a penetration depth E of the electromagnetic wave guided in the desired electrical conduction structure into the surrounding spatial area, preferably by at least twice, particularly preferably five times, in particular ten times, the penetration depth E. The term “penetration depth E” here refers to a depth at which an evanescent electric field associated with a mode guided in an electrical conduction structure has dropped by a factor of 1 / e.

[0043] The method described here can be used to create a variety of different electrical conductor structures on a carrier structure.

[0044] In a preferred embodiment, the electrical line structure can comprise a single microstrip line formed from an electrically conductive structure that is electrically insulated from the environment in all cross-sectional planes along the electrical line structure. Electrical insulation of the electrically conductive structure from the environment can preferably be achieved by the at least one open area on the surface of the carrier structure, which remains uncoated due to the shadow cast by the at least one undercut during the coating step. The electrically conductive structure can be designed, in particular, as an electrical line or as a waveguide on the carrier structure.

[0045] In a further preferred embodiment, the electrical line structure can have at least two electrically conductive structures which, spatially separated from one another, can be arranged at a distance on the support structure and at the same time can be electrically insulated from one another in all cross-sectional planes along the electrical line structure. In this case, the at least two electrically conductive structures can preferably be spatially separated from one another and electrically insulated from one another in that the at least one free area created by the at least one undercut is arranged between the at least two electrically conductive structures. In this embodiment, the electrical line structure can comprise a plurality of individual, electrically insulated, electrically conductive structures in the form of a plurality of microstrip lines.The at least two insulated microstrip lines can be at the same electrical potential or at different electrical potentials. The microstrip lines can, for example, be arranged parallel to each other. However, other microstrip line configurations are conceivable.

[0046] In this embodiment, the electrical line structure can in particular be or comprise a slotted line, wherein the slotted line has two electrically conductive structures which are spatially separated from one another and electrically insulated from one another in all cross-sectional planes along the electrical line structure, wherein the two electrically conductive structures are at the same electrical potential.

[0047] In this embodiment, the electrical line structure (1) can be or comprise a coplanar line, wherein the coplanar line has three electrically conductive structures which are spatially separated from one another and electrically insulated from one another in all cross-sectional planes along the electrical line structure, wherein two of the electrically conductive structures are at the same electrical potential, while a third of the electrically conductive structures is at a different electrical potential.

[0048] In a further preferred embodiment, the electrical line structure can be designed in the form of an antenna. In this embodiment, the electrical line structure can preferably comprise a plurality of individual, electrically conductive structures that are electrically insulated from one another within a cross-sectional plane, which can be modified in a defined manner along the line structure and, in particular, can also be electrically connected in a defined manner within at least one further cross-sectional plane of the electrical line structure. In this embodiment, at least one free surface created by the at least one undercut can be configured, in particular, to enable a transition from a line-bound electrical signal to a free-space wave.

[0049] In a further preferred embodiment, the electrical line structure can comprise, in addition to the desired electrically conductive structures within a cross-sectional plane, at least one further electrically conductive structure as described in more detail above, in particular to enable certain functions. In this embodiment, the electrical line structure can be designed, in particular, in the form of an electrical line coupler.The electrical line coupler can have two electrically conductive structures in the form of two waveguides, which can be arranged at a distance on the support structure and can be electrically insulated from one another in all cross-sectional planes along the line structure, wherein the two waveguides carry different signals and have a mutual distance from one another, so that a desired coupling of an electrical field from one electrically conductive structure to the other electrically conductive structure can be set via at least one further electrically conductive structure.

[0050] In a further preferred embodiment, the electrical conduction structure can be designed in the form of an electrical probe tip, which is suitable for contacting electrical circuits, in particular high-frequency (HF) circuits, and which can preferably have at least one contact element for this purpose. The at least one contact element can be configured as a contact tip by appropriately shaping the carrier structure to be coated, or it can be based on suitable structural elements protruding in a direction perpendicular to the coated surface, which allow geometrically precise contacting of corresponding contact surfaces (ATFCs or probe pads) on a chip or a flat substrate.

[0051] The production of further electrical conductor structures which have special geometries or may be suitable for special purposes is conceivable using the method described here.

[0052] A particular advantage of the method described herein is that the at least one undercut can make it possible to design the support structure for the electrical conduction structure in such a way that, based on the electrically conductive material of the electrical conduction structure and the geometry of the support structure, an effective permittivity of the mode guided in the electrical conduction structure can be set and varied along the conduction structure or the propagation direction of the electromagnetic field present in the conduction structure. The effective permittivity of the mode guided in the at least one electrical conduction structure can be set along the propagation direction of the mode perpendicular to the respective plane of the drawing, preferably to 20 Ω to 100 Ω.Such a design can be particularly advantageous for reducing the influence of a high dielectric constant, for example, of a substrate, on an antenna by gradually guiding the mode guided in the electrical conduction structure away from the substrate, in particular by varying the at least one undercut along the conduction structure. This can make it possible to adapt the permittivity effectively captured by the mode to the local conditions, thus reducing conduction losses or gradually adjusting the conduction impedance.Here, the term “gradual” refers to a continuous transition of a characteristic value of a mode, in particular the impedance, preferably starting from a substrate with a high dielectric constant to a partial region of the carrier structure based on a material with a lower dielectric constant, in particular by a linear transition of the geometries at the transitions.

[0053] In a further embodiment, the method described herein can be used to provide at least one electrical conduction transition to at least one already existing electrical conduction structure, which was previously produced by means of the method described herein and / or by means of conventional manufacturing methods, on a substrate. For this purpose, the carrier structure can be aligned with the already existing electrical conduction structure in such a way that the coating of the carrier structure with the at least one electrically conductive material takes place along the projection direction, which is aligned with the at least one undercut, in such a way that the at least one electrical conduction transition is produced from the already existing electrical conduction structure to the forming electrically conductive structure of the electrical conduction structure.The carrier structure can ensure, by means of at least one undercut, that the existing electrical conductor structure remains electrically insulated in all cross-sectional planes along the conductor structure.

[0054] However, with this type of coating, a global coverage of the substrate outside the partial region of the carrier structure produced by a freeform microstructuring process can occur with the electrically conductive material, whereby the already existing electrical conduction structure as well as other components or circuits present on the substrate can be coated in an undesired manner. To prevent such undesired coating, at least one additional shading structure can be aligned at the at least one electrical conduction transition between the already existing electrical conduction structure and the electrical conduction structure newly manufactured using the method described herein in such a way that, during coating under the projection direction, the already existing electrical conduction structure can remain electrically insulated in all cross-sectional planes along the conduction structure.This also makes it possible to prevent global short circuits of the electrical conduction structure to further sloping electrically conductive structures. In a preferred embodiment, the at least one additional shading structure can cover additional areas of the substrate in such a way that these additional areas of the substrate remain protected from global coverage with the electrically conductive material. For this purpose, it is particularly conceivable to completely cover these additional areas with a protective structure, in particular in the form of a protective layer, and thus to minimize the influence of the forming electrical conduction structure on the electrical conduction structure already present on the substrate by ensuring a sufficient thickness of the protective structure, in particular of the protective layer.Alternatively, additional protective structures or shading structures, in particular a protective layer, can be selectively removed after coating, in particular by simply peeling them off using a suitable tool, preferably tweezers, or by means of a lift-off process, which makes it possible to prevent global coverage with the electrically conductive material by removing the additional electrically conductive structure formed as a by-product. For this purpose, the areas to be protected can preferably be selectively covered with a protective layer before coating. In a preferred embodiment, the selective application of the protective layer can be carried out by inkjet printing, by means of a dispenser, and / or by lithographic structuring.After the electrically conductive material has been applied, the protective layer can be removed again, along with the additional electrically conductive structure formed on the protective layer, in order to expose the already existing electrical conduction structure. It is advantageous if neither the protective materials used nor any substances used to remove them, such as solvents, damage the carrier structure, in particular the partial area produced by the freeform microstructuring process, upon prolonged exposure or otherwise negatively influence it. In a preferred embodiment, PMMA (polymethyl methacrylate) or another suitable substance can be used as a protective material for the protective layer, which can be removed again using PGMEA (propylene glycol monomethyl acetate) without attacking other areas of the carrier structure produced using two-photon lithography.Advantages of such lift-off processes include faster global coverage of the substrate, in particular by means of a deposition process, if the production of the protective structure or shading structures cannot be carried out by means of a freeform microstructuring process due to the size of the area to be covered.

[0055] In a further preferred embodiment, the electrical conductor structure can comprise at least two electrical conductor transitions and thus be designed as a connecting element between at least two conductor structures arranged on separate substrates, wherein the conductor structures were previously produced using the method described herein and / or using conventional manufacturing methods. The carrier structure can comprise at least two substrates mounted on a common base plate and the at least one partial region produced using the freeform microstructuring method, which can connect, via the electrical conductor transitions, to the existing conductor structures on the two substrates, which have the at least one undercut according to the invention with respect to the projection direction.To protect the surfaces of the two substrates, these can again be provided, at least in part, with appropriate temporary or permanent protective structures, in particular shading structures or protective layers, during the coating process in process step b).

[0056] In a further preferred embodiment, the electrical conduction structure can be embodied in the form of an interdigital capacitor. The electrical conduction structure in the form of the electrical interdigital capacitor can comprise a plurality of electrically conductive structures, wherein these can be arranged essentially alternately in two different, mutually parallel planes, and wherein these can be at different potentials. Preferably, the electrically conductive structures can lie in a common first plane defined by depressions in the support structure, while the remaining electrically conductive structures can lie in a second plane defined by webs between the depressions.To produce the electrical line arrangement, at least one undercut is introduced into the carrier structure with respect to the projection direction, which undercut can ensure electrical insulation of the electrically conductive structures applied on the two different levels by means of the at least one free surface. In a preferred embodiment, a divergence of the vapor deposition beams emanating from the vapor deposition source about the defined projection direction at the location of the carrier structure to be coated can be exploited in order to increase a width of the strip-shaped electrically conductive structures produced in the first level, so that these can overlap with the electrically conductive structures located in the second level in a projection along the projection direction. This can in particular contribute to increasing the electrical capacitance between the structures on the two levels.Electrically conductive structures located in a common plane can be electrically interconnected in a further cross-sectional plane of the electrical line structure, thus forming a common electrical supply line. Due to the configuration of the partial region of the support structure as a 3D freeform structure, this configuration can offer more degrees of freedom in the arrangement compared to prior art methods, particularly with improved resolution. In a further aspect, the present invention relates to an electrical line arrangement, in particular an electrical line arrangement produced by the method also described herein. The electrical line arrangement comprises:

[0057] - a support structure, comprising o at least one first partial region configured as a three-dimensional free-form structure and produced by means of a free-form microstructuring process, and o a second partial region comprising an electrically insulating material, wherein the support structure has at least one undercut with respect to a projection direction; and

[0058] - at least one electrical conduction structure applied to the carrier structure as a coating by means of at least one spatially directed coating process with at least one electrically conductive material along the projection direction aligned with the at least one undercut.

[0059] For further details regarding the present electrical line arrangement, reference is made to the description of the method for producing an electrical line arrangement also described herein, as well as to the exemplary embodiments.

[0060] Herein, the terms "have," "have," "comprise," or "include," or any grammatical forms thereof, are used non-exclusively. Accordingly, these terms can refer both to situations in which, besides the features introduced by these terms, no further features are present, and to situations in which one or more further features are present. For example, the expression "A has B," "A has B," "A comprises B," or "A includes B" can refer both to the situation in which, apart from B, no further element is present in A (i.e., a situation in which A consists exclusively of B), and to the situation in which, in addition to B, one or more further elements are present in A, for example, element C, elements C and D, or further elements.

[0061] It should also be noted that the terms "at least one" and "one or more," as well as grammatical forms of these terms, when used in connection with one or more elements or features and intended to express that the element or feature may be provided singly or multiple times, are generally used only once, for example, when the feature or element is first introduced. When the feature or element is subsequently mentioned again, the corresponding term "at least one" or "one or more" is generally no longer used, without limiting the possibility that the feature or element may be provided singly or multiple times.

[0062] Furthermore, the terms "preferred", "preferably", "in particular", "for example" or similar terms are used herein in connection with optional features, without limiting alternative embodiments. Thus, features introduced by these terms are optional features, and these features are not intended to limit the scope of the claims and in particular the independent claims. Thus, as those skilled in the art will recognize, the invention can also be carried out using other embodiments. Similarly, features introduced by "in an embodiment of the invention" or by "in an embodiment of the invention" are understood to be optional features, without limiting alternative embodiments or the scope of the independent claims.Furthermore, these introductory expressions are intended to leave untouched all possibilities of combining the features introduced thereby with other features, whether optional or non-optional.

[0063] Advantages of the invention

[0064] In contrast to known methods for producing electrical line arrangements, which are often based on the use of masks and are therefore essentially limited to planar support structures and the production of different heights of the electrical line arrangements, the present method does not require any masks for production, which in particular enables the production of 3D free-form line structures. By using 3D printing techniques for producing the support structures, complex three-dimensional support structures can be produced, which are particularly suitable for increasing the coupling efficiency and the bandwidth between transmission lines compared to known methods. By using free-form microstructuring methods for producing free-form support structures, no mask is required for production, and the electrical line arrangements can in particular also be produced in situ, i.e.be manufactured directly on site, for example on chips. This allows the electrical line arrangements to be aligned directly to existing circuits and to be electrically connected with, for example, a high bandwidth and low losses, wherein in particular the precise assembly steps that are usually required are omitted. This enables the implementation of a large number of components, including connecting elements between several chips or antennas that are designed as a freeform structure and spaced from the surface for more efficient radiation. The prior art cited at the outset does not disclose a first subregion of the carrier structure that is produced by means of a freeform microstructuring process. Therefore, the cited prior art also does not disclose the production of non-planar electrical line arrangements according to the present invention.In particular, the present invention solves the problem of producing a component that has electrically conductive structures that are insulated from one another within a cross-sectional plane, without the need to first remove the additional conductive structures that are unintentionally created by direct visual contact with a vapor deposition source in order to ensure electrical insulation of the desired line arrangement. In further contrast to the prior art cited at the beginning, the present invention thus also solves problems with regard to so-called packaging for the next generation of high-frequency components, which are designed in particular for millimeter waves and THz frequencies.

[0065] The present manufacturing method also allows microwave components, in particular antennas, chip-to-chip interconnects, or electrical probe tips, to be manufactured directly on existing substrates as carrier structures. Printing the subregions of the carrier structure that define the electrical conduction structures or onto a substrate contained in the carrier structure, as well as protecting the carrier structure or the substrate with shading structures, in particular protective layers, enables a wide variety of realizable structures with 3D freeform geometries and, in particular, allows the electrical conduction structures to be adapted to the conditions of existing structures.This is particularly important in high-frequency technology, since changes to electrical conduction structures on chips are typically complex and costly, whereas the function and design of the electrical conduction structures according to the invention can be flexibly varied by appropriately shaping the partial region of the carrier structure produced using a freeform microstructuring process. The possibility of three-dimensional design of the carrier structure allows, for example, electromagnetic waves to be guided away from the substrate, thus easily adapting the influence of a high dielectric constant of the substrate or the carrier structure to local requirements within a cross-sectional area as needed. Similarly, electrical probe tips with a wide variety of geometries can be flexibly implemented on standardized and thus cost-effective carrier substrates.

[0066] Short description of the characters

[0067] Further details and features of the present invention will become apparent from the following description of preferred embodiments, particularly in conjunction with the dependent claims. The respective features can be implemented individually or in combination with one another. The invention is not limited to the embodiments. The embodiments are schematically illustrated in the following figures. Like reference numerals in the figures denote like or functionally identical elements, or elements that correspond to one another in terms of their functions. In detail:

[0068] Figures 1 and 2 each show a preferred embodiment of a method according to the invention for producing an electrical line arrangement as a schematic cross-sectional representation;

[0069] Figure 3 schematically shows a geometric definition of the undercut according to the invention related to the projection direction in the support structure according to the invention;

[0070] Figures 4 to 10 each show an embodiment of the electrical line arrangement according to the invention as a schematic cross-sectional representation;

[0071] Figures 11 to 14 schematically show a process sequence for producing a further electrical line arrangement according to the invention;

[0072] Figures 15 and 16 each show a preferred embodiment of the electrical line arrangement according to the invention;

[0073] Figure 18 shows a further embodiment of the process sequence for producing a further electrical line arrangement according to the invention as microscopic images; and

[0074] Figures 19 and 20 each show a further embodiment of the electrical line arrangement according to the invention as microscopic images.

[0075] Description of the embodiments

[0076] Figures 1 and 2 show, each in the form of a schematic cross-sectional view, a preferred embodiment of a method according to the invention for producing an electrical cable arrangement. Figure 1 schematically illustrates method step a), and Figure 2 schematically illustrates method step b). The representations chosen for this purpose and the shapes used therein, in particular for the support structure 20, are to be understood as examples; a variety of other arrangements and shapes are possible according to expert considerations.

[0077] Figure 1 schematically shows method step a), which comprises the production of the carrier structure 20, wherein a first partial region 120 of the carrier structure 20 is produced by means of a freeform microstructuring process, wherein a second partial region 220 of the carrier structure 20 comprises an electrically insulating material, and wherein the carrier structure 20 has undercuts 20a, 20b, 20c, 20d with respect to a projection direction 100. In the sketched case, the partial regions 120, 220 are identical and form the carrier structure 20.

[0078] Figure 2 schematically illustrates method step b), which relates to the production of at least one electrical conductor structure 1 by coating the carrier structure 20 with at least one electrically conductive material along a projection direction 100 aligned with the undercuts 20a, 20b, 20c, 20d. Here, the coating of the carrier structure 20, including the undercuts 20a, 20b, 20c, 20d encompassed by the carrier structure 20, takes place from the projection direction 100. The regions 30a, 30b, 30c, 30d shaded by the undercuts 20a, 20b, 20c, 20d present in the carrier structure 20 result from the previously known, defined projection direction 100 and are not affected, or only insignificantly affected, by the spatially directed coating of the carrier structure 20 using the electrically conductive material.The wording “only insignificantly” in this context means that edge regions of the shaded regions 30a, 30b, 30c, 30d can be covered by the electrically conductive material, for example as a result of a non-vanishing divergence 105 of the vapor deposition beams emanating from the vapor deposition source around the defined projection direction 100, but that an open area 30a, 30b, 30c, 30d uncovered by the electrically conductive material still remains, which leads to an electrical insulation of the electrically conductive structures 10a, 10b, 10c in the sketched cross-sectional area of ​​the conductive structure 1.

[0079] As schematically shown in Figure 2, a plurality of mutually insulated electrically conductive structures 10a, 10b, 10c and further electrically conductive structures 11a, 11b are formed on the surface of the carrier structure 20 within a cross-sectional plane as a result of the coating with the electrically conductive material. In the present exemplary embodiment according to Figure 2, three electrically conductive structures 10a, 10b, 10c are located at a common height and each have a shape that is predetermined by the three-dimensional shape of the surface of the carrier structure 20. Due to the undercuts 20a, 20b, 20c, 20d encompassed by the carrier structure 20, open spaces 30a, 30b, 30c, 30d are also formed on the surface of the carrier structure 20 with respect to the projection direction 100 as a result of the coating of the surface of the carrier structure 20 with the electrically conductive material.The free surfaces 30a, 30b, 30c, 30d insulate the electrically conductive structures 10a, 10b, 10c from each other and are further configured such that the electrically conductive structures 10a, 10b, 10c remain electrically insulated within a cross-sectional plane from the further electrically conductive structures 11a, 11b, which have been forcibly formed in the recesses of the carrier structure 20 during the execution of method step b). By appropriately shaping the carrier structure 20, a configuration can be achieved in which the further electrically conductive structures 11a, 11b are so far away from the electrically conductive structures 10a, 10b, 10c that an electrical signal guided through the electrically conductive structures 10a, 10b, 10c does not interact with the further electrically conductive structures 11a, 11b, see also Figure 6 and the associated description.In this case, the three electrically conductive structures 10a, 10b, 10c form the desired electrical conduction structure 1. The electrical conduction structure 1, together with the support structure 20 and the free surfaces 30a, 30b, 30c, 30d present therein, forms the electrical conduction arrangement.

[0080] Figure 3 schematically shows the inventive definition of the projection direction p 100 as well as the inventive undercut 20a related thereto and the associated shaded region 30a in the inventive support structure 20. In the sketched case, the two partial regions 120, 220 are identical and form the support structure 20. The shaded region 30a comprises the totality of all points P 1015 on the surface of the support structure 20 for which a half-line g 1016 originating from the point P 1015 and oriented counter to the projection direction p 100 intersects the support structure 20. The totality of the sections 1030 of all such half-lines g 1016 located inside the support structure 20 defines the partial region of the support structure 20 referred to as overhang 1020.The overhang 1020 defines a shaded area 1040 - this includes the entirety of the connecting lines PP' 1031 of the points P 1015 lying outside the support structure 20 with the entry point P ' of the associated half-line g 1016 into the support structure 20, which is closest to the projection direction p 100.

[0081] Figure 4 shows an exemplary embodiment of the electrical line arrangement according to the invention in the form of a schematic cross-sectional illustration, in which the carrier structure 20 comprises a substrate 40. The first partial regions 120 of the carrier structure are produced from an electrically insulating material using a freeform microstructuring process. An electrically insulating carrier material is used as the substrate 40, which is not produced in the same manufacturing process as the first partial regions 120 of the carrier structure 20. In this exemplary embodiment, the electrically insulating second partial region 220 of the carrier structure 20 comprises both the substrate 40 and the first partial regions 120 of the carrier structure 20, which are produced using the freeform microstructuring process. The carrier structure 20 is coated with at least one electrically conductive material with respect to the projection direction 100, analogous to the illustration in Figure 2.The coating forms—also analogous to Figure 2—the mutually insulated electrically conductive structures 10a, 10b, 10c, as well as the further electrically conductive structures 11a, 11b. In contrast to the illustration according to Figure 2, however, the further electrically conductive structures 11a, 11b and the free surfaces 30a, 30b, 30c, 30d are arranged here on the surface of the substrate 40 and not (or not exclusively; not shown here) on the surface of the first partial region 120 of the carrier structure 20 produced by a freeform microstructuring process.

[0082] Figure 5 shows a further exemplary embodiment of the electrical line arrangement according to the invention in the form of a schematic cross-sectional representation, in which an isotropic coating with an inert protective material 26 is applied to the carrier structure 20, the electrically conductive structures 10a, 10b, 10c forming the electrical line structure 1, and the further electrically conductive structures 11a, 11b. The production of the line arrangement sketched as an example in Figure 5 can be carried out analogously to the process described in Figures 1 and 2. In the embodiment shown in Figure 5, the two partial regions 120, 220 are identical and form the carrier structure 20. After production, the inert protective material 26 can be applied using an isotropic process in which the structure is coated on all sides.The inert protective material 26 can, for example, be designed to prevent oxidation of the metal regions 10a, 10b, 10c, 11a, 11b.

[0083] Figure 6 schematically shows the cross-section of another electrical line arrangement according to the invention, which can be produced using the present method. In the embodiment shown in Figure 6, the two partial regions 120, 220 are identical and form the carrier structure 20. The electrical line structure 1 according to Figure 6 forms a coplanar line comprising the three electrically conductive structures 10a, 10b, 10c, which are electrically insulated from one another in all cross-sectional planes along the line structure 1, wherein the two electrically conductive structures 10a, 10c can be at the same potential, for example in the case of a so-called "ground-signal-ground" configuration.In order to prevent short circuits between the resulting electrically conductive structures 10a, 10b, 10c and the further electrically conductive structures 11a, 11b during the directed coating of the surface of the carrier structure 20 along the projection direction 100, slots introduced into the carrier structure 20 between the areas to be coated have the undercuts 20a, 20b, 20c, 20d, which are designed to provide the open areas 30a, 30b, 30c, 30d intended for insulation. In the present exemplary embodiment, the undercuts 20a, 20b, 20c, 20d in the carrier structure 20 are designed to be so deep that the signal routing in the desired electrical line structure 1, which comprises the electrically conductive structures 10a, 10b, 10c, cannot be influenced by the electrically conductive structures 11a, 11b that inevitably continue to occur on the carrier structure 20.This is indicated in Figure 6 by field lines of an electric field 80, the course of which is not affected by the additional electrically conductive structures 11a, 11b, particularly due to a sufficient distance. The additional electrically conductive structures 11a, 11b produced as a "by-product" can thus remain in place on the surface of the carrier structure 20 (or alternatively on the surface of the substrate 40; not shown here) in this exemplary embodiment and therefore do not need to be removed.

[0084] Figure 7 schematically shows the cross-section of another electrical line arrangement according to the invention, which can also be produced using the present method. In the embodiment shown in Figure 7, the two partial regions 120, 220 are identical and form the support structure 20. Here, the electrical line structure 1 is designed in the form of an electrical line coupler. The electrical line structure 1 in the form of the electrical line coupler comprises the three electrically conductive structures 10a, 10b, 10c, wherein two of the electrically conductive structures 10a, 10c are electrically insulated from one another in all cross-sectional planes along the line structure 1 and are at different electrical potentials.The distance between the two electrically conductive structures 10a, 10c is selected such that a coupling of the electric field 80 from one electrically conductive structure 10a to the other electrically conductive structure 10c (or vice versa) can be adjusted via the third electrically conductive structure 10b, which is located in a notch in the support structure 20, shown schematically in Figure 7. A width of the third electrically conductive structure 10b is determined by means of the undercuts 20b, 20c inserted into the support structure 20, which are designed as shading structures with respect to the projection direction 100, and the free areas 30b, 30c defined by these shading structures.This design is particularly advantageous in the case of strong cross-coupling, which requires small distances between the two electrically conductive structures 10a, 10c, which are more difficult to produce using planar lithography processes with limited lateral resolution. By means of the third electrically conductive structure 10b, which can be produced by coating the electrically conductive material, the strength of the cross-coupling can be increased while maintaining the same distance. An undesired influence on the electrical conduction structure 1 by the additional electrically conductive structures 11a, 11b produced as a "by-product" on the two outer sides of the carrier structure 20 can be prevented by the additional undercuts 20a, 20d inserted into the carrier structure 20.In the exemplary embodiment according to Figure 7, these two undercuts 20a, 20d are deeper than the undercuts 20b, 20c, which is why the further electrically conductive structures 11a, 11b defined by the defined free areas 30a, 30d have a greater distance from the electrically conductive structures 10a, 10c of the electrical line structure 1. Thus, cross-coupling of the electric field 80 from the electrical line structure 1 to the further electrically conductive structures 11a, 11b can be prevented.

[0085] Figure 8 schematically shows the cross-section of another electrical line arrangement according to the invention, which can also be produced using the present method. In the embodiment shown in Figure 8, the two partial regions 120, 220 are identical and form the carrier structure 20. Here, the electrical line structure 1 is designed in the form of an electrical interdigital capacitance. The electrical line structure 1 in the form of the electrical interdigital capacitance comprises, for example, the seven electrically conductive structures 10a, 10b, 10c, 10d, 10e, 10f, 10g, which are arranged essentially alternately in two different, mutually parallel planes 35, 36, and which can be at different potentials.The four electrically conductive structures 10a, 10c, 10e, 10g lie, for example, in a common first plane 35 defined by depressions in the support structure 20, while the remaining three electrically conductive structures 10b, 10d, 10f lie in a second plane 36 defined by webs between the depressions. To produce the electrical line arrangement 1, undercuts 20a, 20b, 20c, 20d, 20e, 20f are introduced into the support structure 20 with respect to the projection direction 100, which, by means of the free surfaces 30a, 30b, 30c, 30d, 30e, 30f, ensure electrical insulation of the electrically conductive structures 10a, 10b, 10c, 10d, 10e, 10f, 10g applied to the two different planes 35, 36.In the case outlined, the flow of the vapor deposition beams emanating from the vapor deposition source exhibits a divergence 105 around the defined projection direction 100 at the location of the carrier structure 20 to be coated, which is why the width of the strip-shaped electrically conductive structures 10a, 10c, 10e, 10g generated in the first plane 35 is increased, so that, in a projection along the projection direction 100, they overlap with the electrically conductive structures 10b, 10d, 10f located in the second plane 36. This can, in particular, contribute to increasing the electrical capacitance between the structures on the two planes 35, 36. The electrically conductive structures 10a, 10c, 10e, 10g and 10b, 10d, 10f lying in a common plane 35, 36 can be electrically connected to one another in a further cross-sectional plane of the electrical conductor structure 1 and thus form a common electrical supply line.

[0086] Figure 9 shows an exemplary embodiment of the electrical line arrangement according to the invention in the form of a schematic cross-sectional illustration, in which the carrier structure 20 comprises a substrate 40, which comprises an upper electrically conductive partial region 320 and a lower electrically insulating second partial region 220. The first partial regions 120 of the carrier structure 20 are produced from an electrically insulating material using a freeform microstructuring method. The electrically insulating second partial region 220 of the carrier structure 20 in this case consists of several elements and comprises both the lower second partial region 220 of the substrate 40 and all first partial regions 120 of the carrier structure 20, which are produced using the freeform microstructuring method.The carrier structure 20 is coated with the at least one electrically conductive material with respect to the projection direction 100, analogously to the illustration in Figure 4. The coating forms the mutually insulated electrically conductive structures 10a, 10b, 10c, as well as the further electrically conductive structures 11a, 11b ...This can be achieved, for example, by means of corresponding ramp structures in the first partial region 120 produced by means of the freeform microstructuring process.

[0087] Figure 10 shows an exemplary embodiment of the electrical line arrangement according to the invention in the form of a schematic cross-sectional illustration, wherein the carrier structure 20 comprises an electrically conductive or insulating substrate 40, a first partial region 120 applied thereto and produced by a freeform microstructuring process, and an insulating coating 25 substantially homogeneously surrounding the substrate 40 and the first partial region 120, wherein the insulating coating 25 forms the insulating second partial region 220 of the carrier structure 20 and is applied, for example, by an isotropic coating process. In this case, the two partial regions 120, 220 are therefore disjoint, i.e., they do not overlap.The carrier structure 20 shown can then be coated—analogously to Figure 2—with at least one electrically conductive material along the projection direction 100 to form the electrical line structure 1 consisting of the electrically conductive structure 10a. In contrast to the illustration according to Figure 2, however, the further electrically conductive structures 11a, 11b and the free surfaces 30a, 30b are arranged here on the surface of the insulating coating 25 and not on the surface of the first partial region 120 of the carrier structure 20 produced by a freeform microstructuring process.

[0088] In a particular embodiment (not shown), the electrically conductive structures 10a, 10b, 10c, etc., as well as the further electrically conductive structures 11a, 11b, etc., of the electrical line structures 1 schematically illustrated in Figures 2, 4, 5, 6, 7, 8, 9, and 10 can vary in cross-section along the propagation direction of the electromagnetic signal, which in the sketched cases runs essentially perpendicular to the respective plane of the drawing, and / or follow a non-planar trajectory. This non-planar trajectory can be predetermined by a corresponding non-planar shape of the carrier structure 20, wherein, in particular, the inventive use of a freeform microstructuring method opens up new scope for embodiments.In a further embodiment, the substrate 40 contained in the carrier structure 20 can also have a non-planar shape, which defines or significantly influences the trajectory of the line path. Furthermore, for example, a cross-section of the electrical line structure 1 can change along the propagation direction of the electromagnetic wave. This allows a line impedance to be locally adjusted according to the changing cross-section or to create line transitions 60a, 61a adapted on both sides in electrical connecting elements. Alternatively, it can be used to create specific components defined by the respective shape of the electrical line structure 1, in particular with a capacitive, resistive, or inductive effect.

[0089] Figures 11 to 14 schematically show a method sequence for producing a further electrical line arrangement according to the invention, which is designed as a non-planar electrical connection element between the two separate substrates 40, 41, according to the manufacturing method described herein using additional shading structures 70, 71.

[0090] Figure 11 schematically shows an initial situation in which the two insulating substrates 40, 41 are approximately aligned with one another. Each of the two substrates 40, 41 comprises pre-existing conductive structures 50a, 50b, 50c; 51a, 51b, 51c, sketched here as an example as a conventional coplanar line, wherein the conductive structures were previously manufactured using the method described herein and / or using conventional manufacturing methods. The coplanar lines each comprise three electrically conductive structures that are electrically insulated from one another in all cross-sectional planes along the conductive structure, wherein the two pre-existing electrically conductive structures 50a, 50c; 51a, 51c are each at the same potential.

[0091] Figure 12 schematically shows a first method step, according to which the first partial region 120 of the carrier structure 20 is manufactured from an electrically insulating material using a freeform microstructuring method. In this embodiment, the first partial region 120 of the carrier structure 20 forms a connection between the conventional coplanar lines and bridges at least one potentially existing gap between the two substrates 40, 41. The inventive use of a freeform microstructuring method makes it possible, in particular, for the structures shown in Figures 11 to 14 to adapt the geometry of the first partial region 120 of the carrier structure 20 to the positioning of the two substrates 40, 41, which is not always precisely controllable.In particular, it is possible to first assemble these substrates 40, 41 using a cost-effective method with comparatively large positioning tolerances, then to determine the exact position of the ends of the existing conductive structures 50a, 50b, 50c; 51a, 51b, 51c to be connected, and, based on this information, to design the first subregion 120 of the carrier structure 20 to be produced using the freeform microstructuring method. The first subregion 120, adapted to the position of the conductive ends to be connected, can then be realized with high precision on the substrates 40, 41, thus achieving a precisely defined, for example, broadband and / or low-loss electrical conductive transition 60a, 60b, 60c; 61a, 61b, 61c between the existing conductive structures 50a, 50b, 50c; 51a, 51b, 51c.For precisely detecting the position of the ends to be connected of the existing conductive structures 50a, 50b, 50c; 51a, 51b, 51c and for precisely aligning the first partial region 120 on the substrates 40, 41, which is adapted to the position of the conductive ends to be connected, the device used to implement the freeform microstructuring process can have additional image acquisition functions with which, for example, markers or structural elements on the substrates 40, 41 can be precisely detected. In the case of two-photon lithography processes, such functions can be based, for example, on camera-based 2D or 3D imaging processes or on scanning processes, for example, based on the principle of confocal microscopy.The precision with which structures on the substrates 40, 41 can be detected and corresponding first partial regions 120 can be placed on these substrates 40, 41 is preferably better than 100 pm, particularly preferably better than 10 pm, especially preferably better than 1 pm, 300 nm, or 100 nm.

[0092] In order to prevent short circuits from being generated between the resulting electrically conductive structures 10a, 10b, 10c; 11a, 11b, 11c, 11d, 11e, 11f during the coating of the carrier structure 20 with the electrically conductive material along the projection direction 100 as shown in Figure 13, corresponding open spaces 30a, 30b, 30c, 30d, 30e, 30f are generated between these structures with the aid of suitable undercuts 20a, 20b, 20c, 20d, 20e, 20f. The undercuts 20a, 20b, 20c, 20d, 20e, 20f are designed so deep in the cross-section of the electrical conduction structure 1 that - analogous to the representation in Figure 6 - the electrically conductive structures 10a, 10b, 10c are not influenced, only insignificantly influenced, or only locally and in a desired manner by the electrically conductive structures 11a, 11b, 11c, 11d, 11e, 11f produced as a "by-product".To further prevent the coating from short-circuiting the existing electrically conductive structures 50a, 50b, 50c; 51a, 51b, 51c, additional shading structures 70, 71 in the form of several protruding arms are used. The additional shading structures 70, 71 are aligned at the transitions between the existing electrically conductive structures 50a, 50b, 50c; 51a, 51b, 51c and the electrical conductive structure 1 in such a way that, during the coating, no connection can be created between the existing electrically conductive structures 50a, 50b, 50c; 51a, 51b, 51c in all cross-sectional planes along the conductive structure 1 under the defined projection direction 100.

[0093] The additional shading structures 70, 71 can preferably be produced using the same freeform microstructuring process as in process step a) together with the first partial region 120 of the carrier structure 20. As a result of the coating in the projection direction 100 in process step b), as shown schematically in Figures 13 and 14, first electrical conduction transitions 60a, 60b, 60c are formed between the already existing electrically conductive structures 50a, 50b, 50c on the first substrate 40 and the electrically conductive structures 10a, 10b, 10c of the electrical conduction structure 1, and further electrical conduction transitions 61a, 61b, 61c are formed between the further already existing electrically conductive structures 51a, 51b, 51c on the further substrate 41 and the electrically conductive structures 10a, 10b, 10c of the electrical conduction structure 1.The further electrically conductive structures 11a, 11b, 11c, 11d, 11e, 11f formed as a “by-product” on the substrates 40, 41 of the carrier structure 20 do not influence the electrical conduction structure 1, only insignificantly, or in a precisely known manner and thus can be taken into account during implementation.

[0094] Figure 14 schematically shows the completed electrical line arrangement after the additional shading structures 70, 71 have been removed. The additional shading structures 70, 71 can preferably be removed by simply pulling them off using tweezers or by means of a lift-off process already mentioned above. In addition to the additional shading structures 70, 71 described above, the two substrates 40, 41 can be provided, at least in some areas, with corresponding temporary or permanent protective layers 75 (not shown here), which prevent unwanted coating of the substrate surfaces or corresponding sub-areas during the coating process in process step b). These protective layers can be produced, for example, by suitable lithography, printing, or dispensing processes and removed again with suitable solvents after process step b) has been carried out.Figure 15 schematically shows a further embodiment of the electrical line arrangement according to the invention, which here is designed in the form of a non-planar dipole antenna. The electrical line arrangement comprises the insulating substrate 40, which has a conventionally manufactured coplanar line consisting of three pre-existing electrically conductive structures 50a, 50b, 50c, wherein two of the pre-existing electrically conductive structures 50a, 50c can be at the same electrical potential. In this embodiment, the electrical line structure 1 initially comprises three individual electrically conductive structures 10a, 10b, 10c that are electrically insulated from one another within a cross-sectional plane, the respective geometries of which are varied in a defined manner along the line structure 1 and, in particular, are also electrically connected within at least one further cross-sectional plane of the electrical line structure 1.

[0095] Method step a) comprises producing the first partial region 120 of the support structure 20 from an electrically insulating material according to Figure 15, which is produced by a freeform microstructuring process. In order to also be able to coat surfaces at an angle of 90° to the surface of the substrate 40, the projection direction 100 is set here to an angle of, for example, 45° to the surface of the substrate 40. Both the side walls of the slots between the structures to be coated and the outer walls of the first partial region 120 of the support structure 20 have undercuts 20a, 20b, 20c, 20d, 20e, 20f in the region of the ramp structure shown in Figure 15, which are designed to produce the free surfaces 30a, 30b, 30c, 30d, 30e, 30f along the ramp structure.The undercuts 20a, 20b, 20c, 20d, 20e, 20f are designed to be so deep that the electrical line structure 1, which comprises the electrically conductive structures 10a, 10b, 10c, - analogous to the illustration in Figure 6 - cannot be influenced by the electrically conductive structures 11a, 11b, 11c produced as a "by-product", can only be influenced insignificantly, or in a precisely known manner that must be taken into account during implementation. The further undercuts 20g, 20h introduced into the feet and wings of the first partial region 120 of the support structure 20 produced by a free-form microstructuring process are designed to produce the free surfaces 30g, 30h, which effect the electrical insulation of the electrically conductive structures 10a, 10b, 10c encompassed by the electrical line structure 1 from the substrate 40 and / or the electrically conductive structures 11c formed as a “by-product” on the substrate 40.

[0096] By coating the carrier structure 20 with the electrically conductive material along the projection direction 100, the electrical line transitions 60a, 60b, 60c are formed between the already existing electrically conductive structures 50a, 50b, 50c on the substrate 40 and the electrically conductive structures 10a, 10b, 10c of the electrical line structure 1. The electrically conductive structures 10a, 10b, 10c, which are insulated from one another within a cross-sectional plane A (section in the (x, z) plane) sketched as an example, are guided upwards via the ramp structure, wherein there, within at least one further cross-sectional plane B (section in the (x, z) plane) sketched as an example, the two outer electrically conductive structures 10a, 10c are brought together centrally with the central electrically conductive structure 10b, which is configured as a signal conductor, thereby forming a dipole antenna.If correctly implemented, this can result in an efficient adaptation of the line impedance of the electrical line structure 1 to the characteristic impedance of the free space and thus a radiation of the dipole antenna generated thereby, without a possibly increased permittivity of the substrate 40 becoming a problem.

[0097] In this exemplary embodiment, too, additional shading structures 70 (not shown) can be used analogously to the arrangements shown in Figures 12 and 13 in order to enable an electrical connection of the electrically conductive structures 10a, 10b, 10c to the already existing electrically conductive structures 50a, 50b, 50c without creating a short circuit between the electrically conductive structures 10a, 10b, 10c or the already existing electrically conductive structures 50a, 50b, 50c to the substrate 40 and / or the electrically conductive structures 11a, 11b, 11c formed as a “by-product” on the substrate 40.

[0098] Figure 16 schematically shows another embodiment of the electrical line arrangement according to the invention, which here is designed in the form of an electrical probe tip, which can be particularly suitable for contacting RF circuits. The electrical line arrangement schematically illustrated in Figure 16 can preferably be manufactured analogously to the method steps according to Figures 11 to 14 and the electrical line arrangement schematically illustrated in Figure 15. For further details, reference is therefore made to the description of Figures 11 to 15.

[0099] In Figure 16, the projection direction 100 is set at an angle of 90° to the surface of the insulating substrate 40. By coating the carrier structure 20 with the electrically conductive material along the projection direction 100, the electrical conduction transitions 60a, 60b, 60c are formed between the already existing electrically conductive structures 50a, 50b, 50c on the substrate 40 and the electrically conductive structures 10a, 10b, 10c of the electrical conduction structure 1. The electrically conductive structures 10a, 10b, 10c, which remain insulated in all cross-sectional planes along the conduction structure 1, are also guided upwards via the ramp structure schematically illustrated in Figure 16 and converge there at a predetermined distance to form three contact elements 500.The inventive production of the first partial region 120 with the aid of a free-form microstructuring process again allows a very precise alignment to structures already present on the substrate 40, see explanations of Figures 11 to 15, as well as a very dimensionally accurate production of the electrical line structures 1 with flexibly adjustable electrical parameters such as the impedance of the line arrangement and the transition to a further test substrate (not shown) defined by the contact elements 500.

[0100] The structure shown in Figure 16 further comprises contact elements 500, which were created by appropriately shaping the carrier structure 20 to be coated and which enable geometrically precise contacting of corresponding contact surfaces on a chip or a planar substrate. In the embodiment outlined in Figure 16, the contact elements 500 are based on structural elements protruding in a direction perpendicular to the coated surface, which, in the case outlined, take the form of truncated pyramids. Other geometric configurations of the contact elements 500 are conceivable.

[0101] In this exemplary embodiment, too, as shown in Figures 12 and 13, additional shading structures 70 (not shown) can be used to enable an electrical connection of the electrically conductive structures 10a, 10b, 10c to the already existing electrically conductive structures 50a, 50b, 50c in all cross-sectional planes along the line structure 1, without creating a short circuit between the electrically conductive structures 10a, 10b, 10c or the already existing electrically conductive structures 50a, 50b, 50c to the substrate 40 and / or the electrically conductive structures 11a, 11b, 11c, 11d formed as a “by-product” on the substrate 40.

[0102] The carrier structure 20 can in particular be designed such that the three contact elements 500 - as indicated in Figure 16 - protrude to the right beyond the edge of the substrate 40 and thus remain visible for contacting even when the electrical conductor structure 1 is rotated, in which the contact elements 500 point downwards and a camera image recorded from above is used for positioning. The diverse possibilities for designing the first partial region 120 of the carrier structure 20 produced by a freeform microstructuring process also allow the production of mechanical protective structures 600 with the aid of the process used in method step a) or with the aid of another freeform microstructuring process. These protective structures prevent unwanted mechanical damage to the electrical probe tip, for example due to a collision or when placed tilted on an underlying test substrate.The mechanical protective structures 600 can, as shown in Figure 16, be designed as solid protective structures 600 that prevent the electrical probe tip from unintentionally approaching an object that could damage it. Alternatively or additionally, the protective structures 600 can be designed such that an approach of the electrical probe tip or the contact elements 500 to an object that could damage it, for example, a substrate 41, leads to a detectable elastic or partially elastic deformation of the protective structure 600 or a part thereof, see Figure 17. For this purpose, dedicated monitor structures 2000 with display structures 2200 can be used, via which an approach 2300 of the electrical probe tip to the potentially damaging object, occurring essentially along a viewing direction 2100, can be converted into a deformation 2400 of the monitor structure 2000 that occurs lateral to the viewing direction 2100 and is thus visually detectable.In a preferred embodiment, the monitor structures 2000 or parts thereof can be manufactured together with the first partial region 120 of the carrier structure 20 using a freeform microstructuring process.

[0103] Figure 18 shows a further exemplary embodiment of the process sequence according to Figures 11 to 14 for producing a further electrical conductor arrangement according to the invention in the form of microscopic images. For further details, reference is made to the above description of Figures 11 to 14.

[0104] Figure 18(a) shows the further electrical conduction arrangement according to the invention, which comprises the two substrates 40, 41, each having a pre-existing electrical conduction structure comprising the pre-existing electrically conductive structures 50a, 50b, 50c; 51a, 51b, 51c, wherein two of the two pre-existing electrically conductive structures 50a, 50c; 51a, 51c are at the same potential. The substrates 40, 41 each comprise—analogous to the structure sketched in Figure 9—in a second partial region 220 an insulating carrier body made of aluminum oxide (Al2O3) with a layer thickness of 625 μm, as well as a conductive region 320, which was produced using a gold layer with a layer thickness of 3 μm on the insulating carrier body.The already existing electrically conductive structures 50a, 50b, 50c; 51a, 51b, 51c were created by structuring this gold layer, for example using a conventional lithography process or a laser ablation process.

[0105] The existing electrically conductive structures 50a, 50b, 50c; 51a, 51b, 51c are to be electrically conductively connected to their respective counterparts below. For this purpose, the first partial region 120 of the carrier structure 20, shown in Figure 18(b), is produced from an insulating material using a two-photon lithography process. In this example, the electrically insulating second partial region 220 of the carrier structure 20 comprises both the lower second partial region 220 of the substrates 40, 41 and the first partial regions 120 of the carrier structure 20, which are produced using the freeform microstructuring process. Due to limitations in the writing field size, the electrical line arrangement was divided into several sections and manufactured in several steps.

[0106] In order to avoid creating short circuits between the resulting electrically conductive structures 10a, 10b, 10c; 11a, 11b, 11c, 11d, 11e, 11f when coating the support structure using the electrically conductive material in Figure 18(c) using a PVD process along the projection direction 100 at an angle of 90° to the surface of the substrates 40, 41, the first partial region 120 of the support structure 20 has slots, in the side walls of which the undercuts 20a, 20b, 20c, 20d, 20e, 20f are introduced, which are designed to produce the free surfaces 30a, 30b, 30c, 30d, 30e, 30f.The undercuts 20a, 20b, 20c, 20d, 20e, 20f are designed to be so deep that the electrical line structure 1, which comprises the electrically conductive structures 10a, 10b, 10c - analogous to the representation in Figure 6 - is not influenced by the electrically conductive structures 11a, 11b, 11c, 11d, 11e, 11f produced as a "by-product", is only influenced insignificantly, or in a known manner which must be taken into account during implementation.

[0107] As a result of the coating in the projection direction 100, on the one hand, first electrical conduction transitions 60a, 60b, 60c are formed between the already existing electrically conductive structures 50a, 50b, 50c on the left substrate 40 shown in Figure 18(b) and the electrically conductive structures 10a, 10b, 10c of the electrical conduction structure 1 produced according to the invention, and on the other hand, further electrical conduction transitions 61a, 61b, 61c are formed between the further already existing electrically conductive structures 51a, 51b, 51c on the right substrate 41 shown in Figure 18(b) and the electrically conductive structures 10a, 10b, 10c of the electrical conduction structure 1. The coating thus produced on the carrier structure 20 has a total layer thickness of approximately 600 nm along the projection direction 100, which largely comprises a copper layer due to the high electrical conductivity.A thin titanium layer serves as an adhesion promoter between the carrier structure 20 and the copper layer; a thin gold layer is also applied as an outer layer for passivation against the environment. To prevent gold from diffusing from the gold layer into the copper layer, another thin titanium layer can be inserted between the copper layer and the gold layer.

[0108] However, in order to prevent the coating from short-circuiting the already existing electrically conductive structures 50a, 50b, 50c; 51a, 51b, 51c within themselves and with the respective adjacent substrate 40, 41, additional shading structures 70, 71 in the form of several protruding arms are used, which were preferably previously produced using the same two-photon lithography process as the first partial region 120 of the carrier structure 20.The additional shading structures 70, 71 are aligned at the electrical line transitions 60a, 60b, 60c; 61a, 61b, 61c between the already existing electrically conductive structures 50a, 50b, 50c; 51a, 51b, 51c and the electrical line structure 1 in such a way that, during coating under the defined projection direction 100, no electrically conductive connection can arise between the already existing electrically conductive structures 50a, 50b, 50c; 51a, 51b, 51c or to the substrate 40, 41. The electrically conductive structures 11a, 11b, 11c, 11d, 11e, 11f formed as a "by-product" are also electrically insulated. For this purpose, the effect of the shadow cast by the additional shading structures 70, 71 at the respective electrical line transitions 60a, 60b, 60c; 61a, 61b, 61c along the projection direction 100 is utilized.In this way, the three-dimensional electrical connection element shown in Figure 18 can be produced between the coplanar lines already present on the two substrates 40, 41, wherein the individual electrically conductive structures 10a, 10b, 10c remain electrically insulated from one another in all cross-sectional planes along the line structure 1.

[0109] In the embodiment according to Figure 18, the additional shading structures 70, 71 are configured only to protect the immediate surroundings of the electrical line transitions 60a, 60b, 60c; 61a, 61b, 61c due to the limited writing field size of the printing process. Therefore, a protective layer 75 made of PMMA (polymethyl methacrylate) covers the already existing electrically conductive structures 50a, 50b, 50c; 51a, 51b, 51c over the remaining surface of the substrates 40, 41. The protective layer 75, which in the present embodiment was applied using an inkjet printing process, can be seen in Figure 18(b) to the left of the additional shading structure 70 on the left substrate 40 and to the right of the shading structure 71 on the right substrate 41.In principle, other methods are conceivable that enable large-area coverage of the substrates 40, 41 with sufficient precision, for example, lithographic processes, dispensing processes, or simple coverage with an adhesive film. The protective layer is further covered with a metal layer during the coating process according to Figure 18(c). By dissolving the PMMA layer with PGMEA (propylene glycol monomethyl acetate), the metal layer can be removed from the areas previously covered with the PMMA layer in a lift-off process, so that—as can be seen in Figure 18(d)—the already existing electrically conductive structures 50a, 50b, 50c; 51a, 51b, 51c remain electrically insulated.

[0110] In principle, as already explained above, it may be conceivable and desirable to perform the entire coverage of the substrates 40, 41 using the same freeform microstructuring process that is also used for the production of the first partial region 120 of the carrier structure 20 and the additional shading structures 70, 71, provided that the selected freeform microstructuring process allows this. However, due to write field limitations of the two-photon lithography process used here, the complete coverage of the substrates 40, 41 would take too long in practice due to the large surface area of ​​the substrates 40, 41, which is why the printing and lift-off process described herein was used instead.The electrically conductive structures 11c, 11d, 11e, 11f formed as a "by-product" usually remain on the substrates 40, 41 without influencing the conductive structure 1, but can preferably - as can be seen from a comparison of Figures 18(c) and 18(d) - be removed by pulling them off using tweezers.

[0111] Figures 18(e) and 18(f) show the completed electrical line arrangement after the additional shading structures 70, 71 had been removed. The shadows created using the additional shading structures 70, 71 on the carrier structure 20 during coating are clearly visible in Figure 18(e) in the form of darkening at the electrical line transitions 60a, 60b, 60c; 61a, 61b, 61c.

[0112] Figure 19 shows, in the form of microscopic images, another embodiment of the inventive electrical line arrangement according to Figure 15 as a non-planar dipole antenna. For further details, please refer to the description of Figure 15.

[0113] Figure 19 shows the electrical line arrangement comprising the substrate 40, which has a conventionally manufactured coplanar line consisting of three pre-existing electrically conductive structures 50a, 50b, 50c, wherein two of the pre-existing electrically conductive structures 50a, 50c are at the same potential. Analogous to the structure sketched in Figure 9, the substrate 40 comprises, in each case in a second partial region 220, an insulating carrier body made of aluminum oxide (Al2O3) with a layer thickness of 625 μm, as well as a conductive region 320, which was produced by means of a gold layer with a layer thickness of 3 μm on the insulating carrier body. The pre-existing electrically conductive structures 50a, 50b, 50c were created by structuring this gold layer, for example, using a conventional lithography process or a laser ablation process.To produce the non-planar dipole antenna, which has a fixed distance from the substrate 40, the first partial region 120 of the carrier structure 20 was also produced using a two-photon lithography process and subsequently coated with the electrically conductive material using a PVD process. Due to limitations in the writing field size, the electrical line arrangement was divided into several sections and manufactured in several steps. Since the carrier structure 20 in this exemplary embodiment also has surfaces at an angle of 90° to the surface of the substrate 40 and in order to establish the desired distance between the non-planar dipole antenna and the substrate 40, coating at this angle is not advisable here. Therefore, the coating was carried out with respect to a projection direction 100 according to Figure 15, which has an angle of, for example, 45° to the surface of the substrate 40.The side walls of the slots introduced into the support structure 20 between the surfaces to be coated have undercuts 20a, 20b, 20c, 20d - analogous to the exemplary embodiment according to Figure 18. The undercuts 20a, 20b, 20c, 20d are also designed so deep that the electrical line structure 1, which comprises the electrically conductive structures 10a, 10b, 10c - analogous to the illustration in Figure 6 - can be influenced not at all, only insignificantly, or in a known manner that must be taken into account during implementation by the electrically conductive structures 11a, 11b. The coating on the support structure 20, which is largely implemented as a copper layer or from a suitable sequence of different materials, also has a total layer thickness of approximately 600 nm along the projection direction 100.A thin titanium layer serves as an adhesion promoter between the carrier structure 20 and the copper layer; for passivation against the environment, a thin gold layer is applied as an outer layer, whereby here too, another thin titanium layer can be inserted between the copper layer and the gold layer.

[0114] As can be seen in Figure 19(c), the further undercuts 20e, 20f, 20g, 20h introduced into the feet and wings of the support structure 20 are also designed here to produce the open spaces 30e, 30f, 30g, 30h, which effect the electrical insulation of the electrically conductive structures 10a, 10b, 10c encompassed by the electrical conduction structure 1 from the substrate 40. By coating the support structure 20 with the electrically conductive material along the projection direction 100, the electrical conduction transitions 60a, 60b, 60c are formed between the already existing electrically conductive structures 50a, 50b, 50c on the substrate 40 and the electrically conductive structures 10a, 10b, 10c of the electrical conduction structure 1.Here, too, the electrically conductive structures 10a, 10b, 10c are guided upwards via the ramp structure, whereby in all cross-sectional planes along the conductor structure 1, the electrically conductive structures 10a, 10b, 10c initially remain insulated from one another. At the apex of the ramp, after the slots have been formed, the two outer electrically conductive structures 10a, 10c are centrally joined within a cross-sectional plane with the central electrically conductive structure 10b, which is configured as a signal conductor, forming a dipole antenna. If implemented correctly, this can achieve efficient matching of the line impedance of the electrical line structure 1 to the characteristic impedance of the free space and thus efficient radiation of the dipole antennas created thereby.

[0115] In this exemplary embodiment, additional shading structures 70, 71 are also used to enable an electrical connection of the electrically conductive structures 10a, 10b, 10c of the electrical line structure 1 to the already existing electrically conductive structures 50a, 50b, 50c, without creating a short circuit between the electrically conductive structures 10a, 10b, 10c or the already existing electrically conductive structures 50a, 50b, 50c to the substrate 40 and / or the electrically conductive structure 11a, 11b, 11c formed as a “by-product” on the substrate 40.

[0116] Figure 19(c) shows the substrate 40 with three dipole antennas after the additional shading structures 70, 71 have been removed. To protect the already existing electrically conductive structures 50a, 50b, 50c over the entire surface of the substrate 40 from short circuits, a protective layer 75 made of PMMA is used here as well—as in the exemplary embodiment of Figure 18—which is removed again in a lift-off process using PGMEA.

[0117] Figure 20 shows, in the form of microscopic images, another embodiment of the electrical conductor arrangement according to the invention according to Figure 16 as an electrical probe tip, particularly for contacting RF circuits. For further details, please refer to the description of Figure 16.

[0118] Figure 20 shows the electrical line arrangement comprising the substrate 40, which has a conventionally manufactured coplanar line consisting of three pre-existing electrically conductive structures 50a, 50b, 50c, wherein two of the pre-existing electrically conductive structures 50a, 50c can be at the same potential. Analogous to the structure outlined in Figure 9, the substrate 40 comprises, in each case in a second partial region 220, an insulating carrier body made of aluminum oxide (Al2O3) with a layer thickness of 625 μm, as well as a conductive region 320, which was produced by means of a gold layer with a layer thickness of 3 μm on the insulating carrier body. The pre-existing electrically conductive structures 50a, 50b, 50c were created by structuring this gold layer, for example, using a conventional lithography process or a laser ablation process.To produce the electrical probe tip, the first partial region 120 of the support structure 20 was also structured using a two-photon lithography process. Subsequently, the support structure 20 was coated with the electrically conductive material using a PVD process along the projection direction 100 according to Figure 16 at an angle of 90° to the surface of the substrate 40. The side walls of the slots introduced into the support structure 20 between the surfaces to be coated have undercuts 20a, 20b, 20c, 20d, 20e, 20f—analogous to the embodiments according to Figures 18 and 19.Here, too, the undercuts 20a, 20b, 20c, 20d, 20e, 20f are designed to be deep enough that the electrical conduction structure 1, which comprises the electrically conductive structures 10a, 10b, 10c, is not influenced, only insignificantly influenced, or influenced in a known manner that must be taken into account during implementation by the electrically conductive structures 11a, 11b, 11c, 11d produced as a "by-product" - analogous to the illustration in Figure 6. The coating on the carrier structure 20, which is largely implemented as a copper layer, also has a total layer thickness of approximately 600 nm along the projection direction 100. A thin titanium layer serves as an adhesion promoter between the carrier structure 20 and the copper layer; for passivation against the environment, a thin gold layer is applied as an outer layer, whereby here, too, another thin titanium layer can be inserted between the copper layer and the gold layer.

[0119] By coating the carrier structure 20 with the electrically conductive material along the projection direction 100, the electrical conduction transitions 60a, 60b, 60c are formed between the already existing electrically conductive structures 50a, 50b, 50c on the substrate 40 and the electrically conductive structures 10a, 10b, 10c of the electrical conduction structure 1. The electrically conductive structures 10a, 10b, 10c, which remain insulated in all cross-sectional planes along the conduction structure 1, are also guided upwards via the ramp structure and converge there at a predetermined distance to form contact elements 500. The contact elements 500 are designed in the form of truncated pyramid-like structures in this case.

[0120] In this exemplary embodiment, additional shading structures 70 are also used to enable an electrical connection of the electrically conductive structures 10a, 10b, 10c of the electrical line structure 1 to the already existing electrically conductive structures 50a, 50b, 50c, without creating a short circuit between the electrically conductive structures 10a, 10b, 10c or the already existing electrically conductive structures 50a, 50b, 50c to the substrate 40 and / or the electrically conductive structure 11a, 11b, 11c, 11d formed as a “by-product” on the substrate 40. In order to protect the already existing electrically conductive structures 50a, 50b, 50c over the entire surface of the substrate 40 from a short circuit, a protective layer 75 made of PMMA is used here as well - as in the exemplary embodiments of Figures 18 and 19 - which is removed in a lift-off process with PGMEA.In addition to the illustrated embodiments, further designs are possible. The use of a lithography process with significantly larger writing fields and, at the same time, sufficiently high lateral resolution in the micrometer range, such as projection microstereolithography (PpSL), enables complete coverage of the substrate surface 40 as protection during coating and eliminates the need for the previously used, complex lift-off process using PMMA and PGMEA. The production of large-area protective structures directly together with the carrier structure 20 and the additional shading structures 70 - according to Figure 12 - in the same lithography step results in a significant time saving and a considerable simplification of the process and, by eliminating the use of.

[0121] Chemicals on the substrate 40 and the carrier structure 20, in particular the first partial area 120, provide extensive protection of sensitive components and thus significantly greater freedom in the choice of material for the carrier structure 20.

[0122] List of reference symbols

Claims

Patent claims 1. A method for producing an electrical line arrangement, comprising the following steps: a) producing a carrier structure (20), wherein at least a first partial region (120) of the carrier structure (20) is produced by means of a freeform microstructuring process, wherein at least a second partial region (220) of the carrier structure (20) comprises an electrically insulating material, and wherein the carrier structure (20) has at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h) with respect to a projection direction (100); and b) producing at least one electrical conductor structure (1) by coating the carrier structure (20) with at least one electrically conductive material, wherein the coating comprises at least one spatially directed coating process which is oriented along the projection direction (100) aligned with the at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h).

2. Method according to the preceding claim, wherein the coating of the carrier structure (20) comprises at least one spatially directed coating process using at least two mutually different electrically conductive materials.

3. Method according to one of the preceding claims, wherein a thickness of the at least one electrical line structure (1) comprising the electrically conductive structures (10a, 10b, 10c, 10d, 10e, 10f, 10g) is increased by galvanic growth.

4. Method according to one of the preceding claims, wherein the production of the at least one electrical conduction structure (1) is carried out in such a way that at least one electrically conductive structure (10a, 10b, 10c, 10d, 10e, 10f, 10g) is formed, which by means of at least one free area (30a, 30b, 30c, 30d, 30e, 30f, 30g, 30h) generated by the at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h) is arranged opposite a further electrically conductive structure (10a, 10b, 10c, 10d, 10e, 10f, 10g) adjacent to the at least one electrically conductive structure (10a, 10b, 10c, 10d, 10e, 10f, 10g) within a cross-sectional plane of the at least one electrical line structure (1) is electrically insulated.

5. Method according to one of the preceding claims, wherein the carrier structure (20) comprises a substrate (40, 41).

6. Method according to one of the preceding claims, wherein the production of the at least one electrical line structure (1) is selected from the production - a microstrip line, comprising producing a single structure (10a) which is electrically conductive in all cross-sectional planes along the at least one electrical line structure (1); - a slotted line, comprising the production of two electrically conductive structures (10a, 10b) which are electrically insulated from one another in all cross-sectional planes along the at least one electrical line structure (1); - a coplanar line, comprising the production of three electrically conductive structures (10a, 10b, 10c) which are electrically insulated from one another in all cross-sectional planes along the at least one electrical line structure (1); - an antenna, comprising the production of at least one electrically conductive structure (10a) which, in cooperation with the at least one free surface (30a, 30b, 30c, 30d, 30e, 30f, 30g, 30h) generated by the at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h), is designed to provide a transition of an electrical signal bound to the at least one electrically conductive structure (10a) to a free-wave space; - an electrical line coupler, comprising the production of three electrically conductive structures (10a, 10b, 10c) which are electrically insulated from one another in all cross-sectional planes along the at least one electrical line structure (1), wherein two of the electrically conductive structures (10a, 10c) are placed at different electrical potentials from one another, wherein a distance between the two electrically conductive structures (10a, 10c) is selected such that a coupling of an electrical field (80) from the one electrically conductive structure (10a) to the other electrically conductive structure (10c) is set via the third electrically conductive structure (10b); - an electrical probe tip having at least one contact element (500) suitable for contacting corresponding contact surfaces; - an electrical connection element between at least two at least one electrical conductor structure (50a-50c, 51a-51c) arranged on separate substrates (40, 41), wherein the carrier structure (20) comprises the at least two substrates (40, 41) and the first partial region (120); - an interdigital capacitor comprising a plurality of electrically conductive structures (10a, 10b, 10c, 10d, 10e, 10f, 10g), which are arranged alternately in two different planes (35, 36) running parallel to one another.

7. Method according to the preceding claim, wherein in method step a) additional mechanical protective structures (600) or monitor structures (2000) are produced which are designed to prevent unwanted mechanical damage to the electrical probe tip.

8. Method according to one of the preceding claims, wherein the introduction of the at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h) into the carrier structure (20) is carried out in such a way that an effective permittivity of a mode (80) guided in the at least one electrical line structure (1) is thereby set along a propagation direction of the mode (80).

9. Method according to the preceding claim, wherein the effective permittivity of the mode (80) guided in the at least one electrical conduction structure (1) is set to 20 £2 to 100 £2 along the propagation direction of the mode (80) perpendicular to the respective plane of the drawing.

10. The method according to any one of the preceding claims, wherein the freeform microstructuring method comprises producing the first partial region (120) of the support structure (20) from a plurality of individual layers, wherein the first partial region (120) of the support structure (20) is constructed from more than 10 layers.

11. Method according to one of the preceding claims, wherein the production of the carrier structure (20) is carried out by means of a multiphoton polymerization method or a stereolithography method.

12. Method according to one of the preceding claims, wherein a cross section of the at least one electrical line structure (1) varies along the propagation direction of the electromagnetic signal or follows a non-planar trajectory which is predetermined by a non-planar shape of the carrier structure (20).

13. Method according to one of the preceding claims, wherein the first partial region (120) of the support structure (20) and the second partial region (220) of the support structure (20) - encompass each other in whole or in part; or - are disjoint or non-overlapping; or - overlap at least in part; or - are identical.

14. Method according to one of the preceding claims, wherein an electrical line transition (60a-60c, 61a-61c) is formed between at least one already existing electrical line structure (50a-50c, 51a-51c, 51) and the at least one electrical line structure (1).

15. Method according to the preceding claim, wherein the production of at least one additional shading structure (70, 71) on the at least one electrical line transition (60a-60c, 61a-61c) is carried out in such a way that during the coating of the carrier structure (20) by means of the electrically conductive material along the projection direction (100) - at least one further electrically conductive connection is formed between the at least two already existing electrical line structures (50a-50c, 51a-51c, 51) and the at least one electrical line structure (1); or - the at least two existing electrical conductor structures (50a-50c, 51a-51c) remain electrically insulated from each other.

16. Method according to the preceding claim, wherein the at least one additional shading structure (70, 71) or a protective layer (75) is applied to further parts of the substrate (40, 41) in such a way that the further parts of the substrate (40, 41) are protected from being covered with the conductive material.

17. Method according to one of the two preceding claims, wherein the production of the at least one additional shading structure (70, 71) or the protective layer (75) is carried out by means of the freeform microstructuring method, in particular selected from a multiphoton polymerization method or a projection lithography method.

18. Method according to one of the three preceding claims, wherein the at least one additional shading structure (70, 71) or the protective layer (75) is removed after coating the carrier structure (20), in particular by means of a lift-off process or by peeling off the at least one additional shading structure (70, 71).

19. Electrical wiring arrangement comprising: - a carrier structure (20), comprising o at least one first partial region (120) designed as a three-dimensional free-form structure and produced by means of a free-form microstructuring method, and o a second partial region (220) comprising an electrically insulating material, wherein the carrier structure (20) has at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h) with respect to a projection direction (100); and - at least one layer, which is applied to the carrier structure (20) as a coating by means of at least one spatially directed coating process with at least one at least one electrical conduction structure (1) applied from electrically conductive material along the projection direction (100) aligned with the at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h).

20. Electrical cable arrangement according to the preceding claim, wherein the coating of the support structure (20) comprises at least two different electrically conductive materials.

21. Electrical line arrangement according to one of the preceding claims relating to the electrical line arrangement, wherein the thickness of the at least one electrical line structure (1) comprising the electrically conductive structures (10a, 10b, 10c, 10d, 10e, 10f, 10g) is increased by galvanic growth.

22. Electrical line arrangement according to one of the preceding claims relating to the electrical line arrangement, wherein the freeform microstructuring method comprises producing the first partial region (120) of the carrier structure (20) from a plurality of individual layers, wherein the first partial region (120) of the carrier structure (20) is constructed from more than 10 layers.

23. Electrical line arrangement according to one of the preceding claims relating to the electrical line arrangement, wherein the at least one electrical line structure (1) comprises at least one electrically conductive structure (10a, 10b, 10c, 10d, 10e, 10f, 10g) which, by means of at least one free surface (30a, 30b, 30c, 30d, 30e, 30f, 30g, 30h) generated by the at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h), is arranged opposite a further electrically conductive structure (10a, 10b, 10c, 10d, 10e, 10f, 10g) adjacent to the at least one electrically conductive structure (10a, 10b, 10c, 10d, 10e, 10f, 10g). 10g) is electrically insulated within a cross-sectional area of ​​the at least one electrical conductor structure (1).

24. Electrical line arrangement according to one of the preceding claims relating to the electrical line arrangement, wherein the carrier structure (20) comprises a substrate (40, 41).

25. Electrical line arrangement according to one of the preceding claims relating to the electrical line arrangement, wherein the at least one electrical line structure (1) is selected from: — a microstrip line comprising a single structure (10a) which is electrically conductive in all cross-sectional planes along the at least one electrical line structure (1); - a slotted line comprising two electrically conductive structures (10a, 10b) which are electrically insulated from one another in all cross-sectional planes along the at least one electrical line structure (1); - a coplanar line comprising three electrically conductive structures (10a, 10b, 10c) which are electrically insulated from one another in all cross-sectional planes along the at least one electrical line structure (1); - an antenna, comprising the production of at least one electrically conductive structure (10a) which, in cooperation with the at least one free surface (30a, 30b, 30c, 30d, 30e, 30f, 30g, 30h) generated by the at least one undercut (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h), is designed to provide a transition of an electrical signal bound to the at least one electrically conductive structure (10a) to a free-wave space; - an electrical line coupler comprising three electrically conductive structures (10a, 10b, 10c) which are insulated from one another in all cross-sectional planes along the at least one electrical line structure (1), wherein two of the electrically conductive structures (10a, 10c) are at different electrical potentials from one another, wherein a distance between the two electrically conductive structures (10a, 10c) is selected such that a coupling of an electrical field (80) from the one electrically conductive structure (10a) to the other electrically conductive structure (10c) is set via the third electrically conductive structure (10b); - an electrical probe tip having at least one contact element (500) suitable for contacting corresponding contact surfaces; - an electrical connection element between at least two electrical conductor structures (50a-50c, 51a-51c) arranged on separate substrates (40, 41), wherein the carrier structure (20) comprises the at least two substrates (40, 41) and the first partial region (120); or - an interdigital capacitor comprising a plurality of electrically conductive structures (10a, 10b, 10c, 10d, 10e, 10f, 10g), wherein these are arranged substantially alternately in two different planes (35, 36) running parallel to one another, and wherein these can be at different potentials.

26. Electrical line arrangement according to the preceding claim, comprising additional mechanical protection structures (600) or monitor structures (2000) which are designed to prevent unwanted mechanical damage to the probe tip.

27. Electrical line arrangement according to one of the preceding claims relating to the electrical line arrangement, wherein the undercuts (20a, 20b, 20c, 20d, 20e, 20f, 20g, 20h) in the carrier structure (20) are designed such that an effective permittivity of a mode (80) guided in the at least one electrical line structure (1) is thereby set along a propagation direction of the mode (80).

28. Electrical line arrangement according to the preceding claim, wherein the effective permittivity of the mode (80) guided in the at least one electrical line structure (1) is set to 20 Q to 100 Q along the propagation direction of the mode (80) perpendicular to the respective plane of the drawing.

29. Electrical line arrangement according to one of the preceding claims relating to the electrical line arrangement, wherein a cross section of the at least one electrical line structure (1) varies along the propagation direction of the electromagnetic signal or follows a non-planar trajectory which is predetermined by a non-planar shape of the carrier structure (20).

30. Electrical line arrangement according to one of the preceding claims relating to the electrical line arrangement, wherein the first partial region (120) of the support structure (20) and the second partial region (220) of the support structure (20) - encompass each other in whole or in part; or - are disjoint or non-overlapping; or - overlap at least in part; or - are identical.

31. Electrical line arrangement according to one of the preceding claims relating to the electrical line arrangement, comprising at least one additional shading structure (70, 71) or a protective layer (75) which are applied to further parts of the substrate (40, 41) in such a way that the further parts of the substrate (40, 41) are protected from being covered with the conductive material.

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