Printed circuit board

Abstract

To provide a printed circuit board and a method for manufacturing the printed circuit board that can provide a space for mounting components in an outermost insulating layer and can reduce thickness.SOLUTION: A printed circuit board 100 according to an embodiment includes a first insulating layer 110, a second insulating layer 120 disposed on the first insulating layer 110, and a cavity C formed in the first and second insulating layers. The cavity C includes a first portion C1 formed in the second insulating layer 120 and a second portion C2 formed in the first insulating layer 110. The first portion C1 has a first cross-sectional shape, and the second portion C2 has a second cross-sectional shape different from the first cross-sectional shape.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The embodiments relate to printed circuit boards, and more particularly to printed circuit boards that include cavities for mounting components. [Background technology]

[0002] Unlike conventional printed circuit boards, in which passive and active elements share the same surface, embedded printed circuit boards have elements such as resistors and capacitors built into the board, which allows for more space to be secured on the surface of the printed circuit board, thereby enabling a higher wiring density compared to conventional printed circuit boards and the development of more compact electronic devices.

[0003] In addition, such embedded printed circuit boards have the effect of significantly reducing the length of wiring by connecting elements vertically, thereby reducing problems such as the generation of impedance and signal delay due to parasitic effects in electronic devices that use high-frequency signals.

[0004] The core technologies of such an embedded printed circuit board are a technology for embedding elements inside the board and a technology for precisely connecting the embedded elements to wiring circuits. Generally, an embedded printed circuit board is manufactured by forming an insulating layer and then performing a cavity forming process to remove a device mounting area, and then mounting a device in the formed cavity and laminating additional insulating layers on the upper and lower sides of the insulating layer on which the device is mounted.

[0005] However, various problems arise in the cavity forming process, which may affect the reliability of the product.

[0006] Therefore, SIP (System In Package) has been developed recently, which performs multiple functions by mounting ICs and passive elements on the outermost layer of a printed circuit board.

[0007] However, while conventional SIPs can achieve package miniaturization by integrating multiple ICs and passive elements into a single module within the package, they have problems with thickness limitations and the long manufacturing time for the package substrate due to the multiple layers, which increases production costs. Summary of the Invention [Problem to be solved by the invention]

[0008] In the embodiments, a printed circuit board with a new structure and a method for manufacturing the same are provided. In the embodiment, a printed circuit board and a manufacturing method thereof are provided that can reduce the thickness by providing a space in which elements can be mounted on the outermost insulating layer.

[0009] In addition, in the embodiment, the outermost insulating layer is made of a photosensitive insulating resin (PID: Photoimageable dielectrics), which makes it possible to easily form a cavity for mounting an element, and also to provide a printed circuit board and a manufacturing method thereof that can solve reliability problems that may occur during cavity formation.

[0010] In addition, the present invention provides a printed circuit board and a manufacturing method thereof that can improve the adhesion between the outermost insulating layer and the inner insulating layer by disposing an additional insulating layer of a different material between the outermost insulating layer and the inner insulating layer, which are made of different materials.

[0011] In addition, the present invention provides a printed circuit board and a package substrate including the same, which can solve the problem of peeling between the inner insulating layer and the outermost insulating layer that occurs after the cavity is formed by arranging a pad on the boundary region of the cavity on the inner insulating layer.

[0012] The technical problems to be achieved by the proposed embodiments are not limited to the technical problems mentioned above, and other technical problems not mentioned above will be clearly understood by those skilled in the art to which the embodiments pertain from the following description. [Means for solving the problem]

[0013] A printed circuit board according to an embodiment includes a first insulating layer, a second insulating layer disposed on the first insulating layer, and a cavity formed in the first and second insulating layers, the cavity including a first portion formed in the second insulating layer and a second portion formed in the first insulating layer, the first portion having a first cross-sectional shape, and the second portion having a second cross-sectional shape different from the first cross-sectional shape.

[0014] The second insulating layer includes a photosensitive insulating resin. The first insulating layer includes a non-photosensitive insulating resin. Additionally, the first portion has a first depth and the second portion has a second depth that is greater than the first depth.

[0015] The semiconductor device also includes a first circuit pattern embedded in the upper portion of the first insulating layer, the first depth corresponding to a thickness of the second insulating layer, and the second depth corresponding to a thickness of the first circuit pattern.

[0016] The first cross-sectional shape includes a trapezoidal shape, and the second cross-sectional shape includes a quadrangular shape. It also includes a first via that penetrates the first insulating layer and a second via that penetrates the second insulating layer, the first cross-sectional shape corresponding to the cross-sectional shape of the first via, and the second cross-sectional shape corresponding to the cross-sectional shape of the first circuit pattern.

[0017] On the other hand, a printed circuit board according to an embodiment includes a first insulating layer, a second insulating layer disposed on the first insulating layer, and a first circuit pattern embedded in the lower part of the first insulating layer and having a lower surface disposed on the same plane as the lower surface of the first insulating layer, wherein a cavity is formed at a first depth on the lower surface of the first insulating layer, the first depth corresponding to the thickness of the first circuit pattern, and the cross-sectional shape of the cavity corresponding to the cross-sectional shape of the first circuit pattern. On the other hand, a printed circuit board according to an embodiment includes a first insulating layer, a first circuit pattern disposed on an upper surface of the first insulating layer, and a second insulating layer disposed on the upper surface of the first insulating layer to cover the first circuit pattern and having a cavity formed therein, the second insulating layer including a first insulating part disposed on the upper surface of the first insulating layer and a second insulating part disposed on the upper surface of the first insulating part and having the cavity formed therein, the second insulating part including a photosensitive insulating resin, and the cavity disposed through the second insulating part.

[0018] It also includes a via arranged through the second insulating layer, the via including a first via part that penetrates the first insulating part and a second via part that penetrates the second insulating part and is in direct contact with the first via part.

[0019] The cross-sectional shape of the cavity corresponds to the cross-sectional shape of the second bead part. Additionally, at least a portion of the first circuit pattern overlaps with the cavity in the vertical direction.

[0020] Meanwhile, a method for manufacturing a printed circuit board according to an embodiment includes preparing a first insulating layer, forming a first circuit pattern embedded on top of the first insulating layer, forming a second insulating layer on the top surface of the first insulating layer to cover the first circuit pattern, forming a first portion of a cavity penetrating the second insulating layer, and removing a cavity pattern exposed through the first portion of the first circuit pattern embedded on top of the first insulating layer to form a second portion of the cavity, wherein the first portion has a first cross-sectional shape and the second portion has a second cross-sectional shape different from the first cross-sectional shape.

[0021] The second insulating layer includes a photosensitive insulating resin, and the first insulating layer includes a non-photosensitive insulating resin. Additionally, the first portion has a first depth corresponding to a thickness of the second insulating layer, and the second portion has a second depth greater than the first depth and corresponding to the first circuit pattern.

[0022] The first cross-sectional shape includes a trapezoidal shape, and the second cross-sectional shape includes a quadrangular shape. Also, when forming the cavity, a step of forming a via hole penetrating the second insulating layer together with the cavity is included, wherein the first cross-sectional shape corresponds to the cross-sectional shape of the via hole and the second cross-sectional shape corresponds to the cross-sectional shape of the first circuit pattern.

[0023] A printed circuit board according to an embodiment includes a first insulating portion, a second insulating portion disposed on an upper surface of the first insulating portion and including a first opening, and a third insulating portion disposed below a lower surface of the first insulating portion and including a second opening, wherein the second insulating portion is an insulating layer disposed at the top of a plurality of insulating layers, and the third insulating portion is an insulating layer disposed at the bottom of the plurality of insulating layers, and the second and third insulating portions include a photosensitive insulating resin.

[0024] The first insulating portion includes a prepreg. It also includes a first circuit pattern portion arranged on the upper and lower surfaces of the first insulating portion and including lead portions exposed through the first and second openings, and a first via portion arranged within the first insulating portion, wherein the first opening exposes the lead portions arranged on the upper surface of the first insulating portion, and the second opening exposes the lead portions arranged on the lower surface of the first insulating portion.

[0025] It also includes a second circuit pattern portion arranged on the upper surface of the second insulating portion, a second via portion arranged within the second insulating portion, a third circuit pattern portion arranged on the lower surface of the third insulating portion, and a third via portion arranged within the third insulating portion, and at least one of the second and third via portions has a width smaller than the width of the first via portion.

[0026] At least one of the second and third circuit pattern portions has a line width smaller than that of the first circuit pattern portion. At least one of the second and third via portions has a width in the range of 5 um to 50 um.

[0027] At least one of the first and second openings has a width in the range of 500 to 8000 μm. The insulating layer further includes a first adhesive insulating layer disposed between the first insulating portion and the second insulating portion, and a second adhesive insulating layer disposed between the first insulating portion and the third insulating portion, and the first and second adhesive insulating layers include an insulating material different from that of the second and third insulating portions.

[0028] At least one of the first and second adhesive insulating layers contains a thermosetting resin. Further, the first via portion is arranged to penetrate at least one of the first and second adhesive insulating layers, the second circuit pattern portion is arranged on the upper surface of the first adhesive insulating layer, and the third circuit pattern portion is arranged below the lower surface of the second adhesive insulating layer.

[0029] In addition, the first circuit pattern portion arranged on the upper surface of the first insulating portion includes a first pad arranged around the area exposed through the first opening, and the first circuit pattern portion arranged on the lower surface of the first insulating portion includes a second pad arranged around the area exposed through the second opening.

[0030] Each of the first and second pads includes a first portion covered by one of the second and third insulating portions and a second portion exposed by one of the first and second openings.

[0031] Furthermore, the first pad is arranged to surround the periphery of the lead portion arranged on the upper surface of the first insulating portion, and the second pad is arranged to surround the periphery of the lead portion arranged on the lower surface of the first insulating portion.

[0032] On the other hand, a package substrate according to an embodiment includes a first insulating portion, a second insulating portion disposed on an upper surface of the first insulating portion and including a first opening, a third insulating portion disposed below a lower surface of the first insulating portion and including a second opening, a first circuit pattern portion disposed on the upper and lower surfaces of the first insulating portion and including lead portions exposed through the first and second openings, a first via portion disposed so as to penetrate at least one insulating layer constituting the first insulating portion, a second circuit pattern portion disposed on the upper surface of the second insulating portion, a second via portion disposed so as to penetrate the second insulating portion, a third circuit pattern portion disposed on a lower surface of the third insulating portion, and a lead portion disposed so as to penetrate the third insulating portion. a third via portion formed on the upper surface of the first insulating portion; a first connection portion disposed on top of the lead portion disposed on the upper surface of the first insulating portion; a second connection portion disposed below the lead portion disposed on the lower surface of the first insulating portion; a first element disposed on the first connection portion and exposed through the first opening; and a second element disposed below the second connection portion and exposed through the second opening, wherein the second insulating portion is an insulating layer disposed at the top of a plurality of insulating layers constituting the printed circuit board, the third insulating portion is an insulating layer disposed at the bottom of the plurality of insulating layers, the first insulating portion includes prepreg, and the second and third insulating portions each include a photosensitive insulating resin.

[0033] The insulating layer further includes a first adhesive insulating layer disposed between the first insulating portion and the second insulating portion and containing an insulating material different from that of the second and third insulating portions, and a second adhesive insulating layer disposed between the first insulating portion and the third insulating portion and containing an insulating material different from that of the second and third insulating portions, and at least one of the first and second adhesive insulating layers contains a thermosetting resin.

[0034] In addition, the first circuit pattern portion arranged on the upper surface of the first insulating portion includes a first pad arranged around the area exposed through the first opening, and the first circuit pattern portion arranged on the lower surface of the first insulating portion includes a second pad arranged around the area exposed through the second opening, and each of the first and second pads includes a first portion covered by one of the second and third insulating portions and a second portion exposed by one of the first and second openings. [Effects of the Invention]

[0035] According to the embodiment, the outermost insulating layer of the printed circuit board is made of a photoimageable dielectric (PID) resin, and a cavity in which a device can be mounted is formed in the outermost insulating layer, so that the device can be mounted in the formed cavity. In this case, since at least a portion of the device is disposed within the outermost insulating layer of the printed circuit board, the overall thickness of the package substrate can be reduced by the depth of the cavity. Also, according to the embodiment, the insulating layer in which the cavity is formed is made of a photoimageable dielectric (PID), so that the cavity for mounting the device can be easily formed through exposure and development, thereby resolving reliability issues that may occur during cavity formation.

[0036] In addition, according to the embodiment, when a circuit pattern to be embedded in an insulating layer is formed, a cavity pattern is formed together with the circuit pattern. The formed cavity pattern is then removed to form a cavity in the insulating layer. This solves the problem of glass fibers contained in the insulating layer being exposed through the cavity due to the material forming the insulating layer, thereby improving the reliability of the cavity.

[0037] In addition, according to the embodiment, the depth of the entire cavity can be easily adjusted by combining the first part of the cavity formed on the photosensitive insulating resin and the second part of the cavity formed on the non-photosensitive insulating resin.

[0038] Furthermore, according to the embodiment, processes such as a laser process and sandblasting, which are essential for forming a cavity, can be eliminated, thereby simplifying the manufacturing process and significantly reducing manufacturing costs.

[0039] According to an embodiment of the present invention, an additional insulating layer made of a different material is disposed between the outermost insulating layer and the inner insulating layer. The additional insulating layer may be made of a thermosetting insulating resin. Here, if a prepreg (PPG) constituting the inner insulating layer and a PID (photosensitive insulating resin) constituting the outermost insulating layer come into direct contact with each other, the adhesive strength between the prepreg and the photosensitive insulating resin may be reduced due to differences in physical properties between the prepreg and the photosensitive insulating resin. Therefore, in this embodiment, a thermosetting insulating resin is additionally disposed between the photosensitive insulating resin and the prepreg to increase the adhesive strength between the photosensitive insulating resin and the prepreg, thereby improving product reliability.

[0040] According to another embodiment of the present invention, a pad is disposed on the inner insulating layer in a boundary region of the cavity, the pad being disposed so as to surround the periphery of the region in which the cavity is formed. In this case, if the pad is not present, an undercut occurs in the lower region of the photosensitive insulating resin on the boundary region of the cavity, which may cause a problem of delamination between the inner insulating layer and the outermost insulating layer. Therefore, in the embodiment, by disposing the pad on the boundary region of the cavity, the undercut problem that weakens reliability can be solved, thereby improving the reliability of the product. [Brief explanation of the drawings]

[0041] [Figure 1] FIG. 1 is a diagram showing a package substrate according to a comparative example. [Figure 2] FIG. 2 is a diagram showing a printed circuit board according to a first embodiment. [Figure 3-9] 3 to 9 are cross-sectional views illustrating the steps of a method for manufacturing the printed circuit board according to the first embodiment shown in FIG. 2 in order of steps. [Figure 10] FIG. 10 is a diagram showing a printed circuit board according to a second embodiment. [Figure 11-17] 11 to 17 are cross-sectional views showing the manufacturing method of the printed circuit board according to the second embodiment shown in FIG. 10 in the order of steps. [Figure 18] FIG. 18 is a diagram showing a printed circuit board according to a third embodiment. [Figure 19-23] 19 to 23 are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 18 in the order of steps. [Figure 24] FIG. 24 is a diagram showing a printed circuit board according to a fourth embodiment. [Figure 25] FIG. 25 is a diagram showing a package substrate according to an embodiment. [Figure 26-30] 26 to 30 are diagrams for explaining the manufacturing process of the printed circuit board shown in FIG. 24 in order. [Figure 31] FIG. 31 is a diagram showing a printed circuit board according to a fifth embodiment. [Figure 32]FIG. 32 is a diagram showing a printed circuit board according to a sixth embodiment. [Figure 33] FIG. 33 is a plan view of the pad of FIG. [Figure 34] FIG. 34 is a diagram showing a modified example of the pad according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0042] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The technical concept of the present invention is not limited to the described embodiments, but can be embodied in various forms, and components between the embodiments can be selectively combined or substituted within the scope of the technical concept of the present invention.

[0043] Furthermore, unless otherwise clearly and specifically stated, terms (including technical and scientific terms) used in the embodiments of the present invention are to be interpreted as meanings that are commonly understood by a person of ordinary skill in the art to which the present invention belongs, and commonly used terms such as dictionary-defined terms may be interpreted in light of the contextual meaning of the relevant art. Furthermore, the terms used in the embodiments of the present invention are intended to explain the embodiments and are not intended to limit the present invention.

[0044] In this specification, the singular can include the plural unless otherwise specified, and when it is stated that "A and at least one (or one or more) of B and C" it can include one or more of all possible combinations of A, B and C. Furthermore, in describing components of the embodiments of the present invention, terms such as first, second, A, B, (a), (b) etc. can be used.

[0045] Such terms are used to distinguish a component from other components, and do not limit the nature or order of the components. When a component is described as being "coupled," "bonded," or "connected" to another component, this includes both cases where the component is directly coupled or connected to the other component, and cases where other components are further "coupled," "coupled," or "connected" between the components.

[0046] Furthermore, when it is stated that something is formed or disposed "above or below" a component, "above or below" does not only mean that the two components are in direct contact with each other, but also means that one or more other components are formed or disposed between the two components. Furthermore, when it is expressed as "above or below," it can mean not only the upper direction but also the lower direction based on one component.

[0047] FIG. 1 is a diagram showing a package substrate according to a comparative example. Hereinafter, a printed circuit board and a package substrate including the same according to a comparative example will be described with reference to FIG.

[0048] At least one element is mounted on the package substrate 1. The element mounted on the package substrate 1 includes at least one of a passive element and an active element. The package substrate 1 includes a printed circuit board including an insulating layer 1 having a multi-layer structure, a circuit pattern 20 disposed on the surface of the insulating layer 1, vias 30 disposed through the insulating layer 1 and electrically connecting the circuit patterns of different layers, and a protective layer 40 disposed on the outermost insulating layer of the insulating layer 1.

[0049] At this time, the circuit pattern 20 includes pads arranged in the area on the surface of the outermost insulating layer where the elements 60 and 80 are mounted. Then, elements 60 and 80 are mounted on the pads.

[0050] At this time, the connecting portions 50, 70 are disposed on the pads, and the elements 60, 80 are fixed onto the pads by the connecting portions 50, 70. Here, the elements 60 and 80 include inductors, power supply elements, and the like.

[0051] On the other hand, the package substrate 1 in the comparative example described above has a structure in which the elements 60 and 80 are mounted on the pads arranged on the outermost sides of the printed circuit board. As a result, the package substrate 1 in the comparative example has the elements 60 and 80 mounted on the pads arranged on the outermost sides, which increases the overall thickness of the package substrate.

[0052] That is, the thickness of the package substrate 1 in the comparative example is determined by the sum of the thickness of the printed circuit board, the thickness of the connection parts 50 and 70, and the thickness of the elements 60 and 80. That is, the thickness of the package substrate 1 in the comparative example is affected not only by the thickness of the printed circuit board but also by the thickness of the elements 60 and 80. Therefore, the overall thickness of the package substrate in the comparative example increases.

[0053] Furthermore, in the package substrate 1 of the comparative example, it was possible to form a cavity on the printed circuit board and mount an element on the formed cavity. However, the printed circuit board of the comparative example uses a laser drill to form the cavity, which poses a problem of reducing the reliability of the printed circuit board during the cavity formation process.

[0054] Although some of the components 60 and 80 are embedded in the substrate, others must be mounted on the outermost surface of the substrate due to various reliability issues. In this case, the outermost components, as in the comparative example, are simply mounted on pads located on the outermost surface of the printed circuit board. This increases the overall thickness of the package substrate in the comparative example.

[0055] That is, the package substrate 1 in the comparative example uses a method of forming a cavity using a CO2 laser drill and then mounting a device in the cavity. However, the package substrate 1 in the comparative example has difficulty in accurate alignment during cavity formation.

[0056] In addition, in the package substrate 1 according to the comparative example, the glass fibers of the PPG are not completely processed during the cavity formation process, which can cause damage to the device when it is mounted. That is, in the package substrate 1 according to the comparative example, the cavity is formed using a laser drill, which causes unevenness in the cavity area due to wall roughness after the cavity formation process, which can cause damage when the device is mounted.

[0057] Furthermore, the package substrate 1 according to the comparative example has a problem in that the process cost increases due to the number of laser drills used to form the cavities. Furthermore, the package substrate 1 according to the comparative example requires the placement of a laser stopper for the laser drilling process, and it is difficult to completely remove the stopper after the cavity formation is completed. That is, the package substrate 1 according to the comparative example has plating deviations in the copper plating, making it difficult to uniformly etch the stopper, and as a result, when etching the stopper, the circuit pattern connected to the device is also etched.

[0058] Furthermore, the package substrate 1 according to the comparative example necessarily requires a process using a laser or sandblasting when forming a cavity, which complicates the manufacturing process and increases manufacturing costs.

[0059] In order to solve such problems, the present embodiment aims to provide a printed circuit board with a new structure that allows a plurality of elements to be mounted on a single printed circuit board, and a method for manufacturing the same. FIG. 2 is a diagram showing a printed circuit board according to a first embodiment.

[0060] Referring to FIG. 2, a printed circuit board 100 may include multiple insulating layers 110, 120. Here, although the printed circuit board 100 in the embodiment has been illustrated as having a two-layer structure based on an insulating layer, the present invention is not limited to this.

[0061] That is, the first insulating layer 110 of the printed circuit board 100 may have a multi-layer structure. For example, the first insulating layer 110 may have a layer structure of two or more layers. Vias are disposed in each first insulating layer 110 having a layer structure of two or more layers, and a circuit pattern is disposed on the surface of each first insulating layer 110.

[0062] The printed circuit board 100 expresses the electrical wiring that connects circuit components as wiring diagrams based on the circuit design, thereby reproducing electrical conductors on the multiple insulating layers 110 and 120. The printed circuit board 100 can also mount elements that are the same as the electrical components and form wiring that connects them in a circuit, and can also mechanically fix components other than those that have an electrical connection function.

[0063] The multiple insulating layers 110, 120 have a mutually laminated structure. Preferably, the plurality of insulating layers 110 , 120 may include a first insulating layer 110 and a second insulating layer 120 .

[0064] The printed circuit board 100 in the embodiment may have a three-layer structure based on the circuit pattern layer, but is not limited thereto. For example, the printed circuit board 100 in the embodiment may have an increased number of insulating layers, and therefore, the number of circuit pattern layers may also be increased.

[0065] The first insulating layer 110 and the second insulating layer 120 can be made of different insulating resins. For example, the first insulating layer 110 can be made of a non-photosensitive insulating resin. Specifically, the first insulating layer 110 may include glass or plastic. More specifically, the first insulating layer 110 may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass, or may include reinforced or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), or sapphire.

[0066] That is, the first insulating layer 110 may be made of, but is not limited to, a material such as LCP (Liquid Crystal Polymer), PPG (FR1, 2, 3, 4), Teflon (registered trademark), ABF (Ajinomoto build-up film), RCC (Resin Coated Copper), etc. For example, the first insulating layer 110 may be made of any one of prepreg (PPG), ABF (Ajinomoto build-up film), RCC (Resin Coated Copper), Liquid Crystal Polymer (LCP), and Teflon (registered trademark).

[0067] The first insulating layer 110 may also contain glass therein to ensure rigidity. The second insulating layer 120 is disposed on the first insulating layer 110. Unlike the first insulating layer 110, the second insulating layer 120 may be made of a photosensitive insulating resin.

[0068] For example, the second insulating layer 120 may be formed by laminating a photosensitive resin film or by applying a photosensitive resin paste or liquid phase. Here, as an example, the photosensitive resin material may include at least one selected from the group consisting of photosensitive polyhydroxystyrene (PHS), photosensitive polybenzoxazole (PBO), photosensitive polyimide (PI), photosensitive benzocyclobutene (BCB), photosensitive polysiloxane, photosensitive epoxy, and novolac resin.

[0069] Also, the second insulating layer 120 may be made of a photosensitive insulating resin including an epoxy resin, a photoinitiator, a silicon filler, and a hardener. Meanwhile, the printed circuit board 100 in the embodiment includes a cavity C. In this case, the cavity C may include a first portion C1 formed in the second insulating layer 120 and a second portion C2 formed in the first insulating layer 110.

[0070] In the embodiment, the cavity C may be formed by a combination of the second portion C2 formed in the first insulating layer 110 and the first portion C1 formed in the second insulating layer 120. That is, the first portion C1 formed in the second insulating layer 120 and the second portion C2 formed in the first insulating layer 110 may be connected to form one cavity C.

[0071] At this time, the first portion C1 formed in the second insulating layer 120 may be formed by processes such as exposure and development. That is, in the comparative example, a laser drilling process or a sandblasting process was performed to form a cavity on the insulating layer. As a result, in the comparative example, surface damage to the circuit pattern or the insulating layer may occur during the laser drilling or sandblasting process, which complicates the manufacturing process and increases manufacturing costs.

[0072] On the other hand, in the embodiment, the second insulating layer 120 is made of a photosensitive insulating resin. Accordingly, a first portion C1, which is a part of a cavity C for mounting an electronic component (not shown), can be formed in the second insulating layer 120 through an exposure and development process. In this case, the first portion C1 may be formed to penetrate the upper and lower surfaces of the second insulating layer 120. That is, the first portion C1 may be a through-hole that penetrates the second insulating layer 120.

[0073] As described above, in the embodiment, the second insulating layer 120 is made of a photosensitive insulating resin, and a cavity for mounting a device is formed in the photosensitive insulating resin by performing exposure and development, etc., thereby solving various reliability problems that arise during the cavity formation process, and by allowing a device to be mounted in the cavity, the overall thickness of the package substrate can be reduced by the depth of the cavity.

[0074] Meanwhile, the first portion C1 may have a first cross-sectional shape. For example, the first portion C1 may have a shape in which an inner wall has a constant slope. For example, the first portion C1 may have a trapezoidal shape.

[0075] The surface of the first insulating layer 110 is formed with a second portion C2 of the cavity C that is recessed inward. The second portion C2 of the cavity C may be connected to the first portion C1.

[0076] The second portion C2 may be a recess disposed in the upper surface of the first insulating layer 110. The second portion C2 may have a second cross-sectional shape. For example, the second portion C2 may have an inner wall perpendicular to the main surface. For example, the second portion C2 may have a quadrangular shape.

[0077] Meanwhile, the first portion C1 of the cavity C may have a first depth, and the second portion C2 of the cavity C may have a second depth. The first portion C1 may be formed to penetrate the second insulating layer 120. Thus, a first depth of the first portion C1 may correspond to the thickness of the second insulating layer 120.

[0078] The second portion C2 may be a recess disposed at a second depth in the upper portion of the first insulating layer 110. In this case, the second depth of the second portion C2 may correspond to the thickness of the first circuit pattern 130 embedded in the upper portion of the first insulating layer 110. Preferably, the second portion C2 may be formed by removing a cavity pattern (described below) formed together with the first circuit pattern 130 when the first circuit pattern 130 is formed. Therefore, the depth of the second portion C2 may correspond to the thickness of the first circuit pattern 130.

[0079] For example, a first depth of the first portion C1 of the cavity C may be equal to the thickness of the second insulating layer 120. For example, a second depth of the second portion C2 of the cavity C may be equal to the thickness of the first circuit pattern 130.

[0080] In the embodiment, when forming the first circuit pattern 130 embedded in the first insulating layer 110 as described above, a cavity pattern is formed together with the first circuit pattern 130. Then, the formed cavity pattern is removed to form the second portion C2 of the cavity in the first insulating layer 110. At this time, when the surface of the first insulating layer 110 is removed using a laser or sandblasting to form the cavity, glass present in the first insulating layer 110 is exposed to the outside, and the exposed glass affects the reliability of the cavity C.

[0081] On the other hand, in the embodiment, the first insulating layer 110 is not removed, but the cavity pattern disposed in the first insulating layer 110 is removed to form a part of the cavity C. Therefore, in the embodiment, the problem of the glass fiber contained in the insulating layer being exposed through the cavity can be solved, and the reliability of the cavity can be improved.

[0082] In addition, according to the embodiment, the depth of the entire cavity can be easily adjusted by combining the first part of the cavity formed on the photosensitive insulating resin and the second part of the cavity formed on the non-photosensitive insulating resin.

[0083] Furthermore, according to the embodiment, processes such as a laser process and sandblasting, which are essential for forming a cavity, can be eliminated, thereby simplifying the manufacturing process and significantly reducing manufacturing costs.

[0084] Meanwhile, a circuit pattern layer is disposed on the surface of the first insulating layer 110 and the second insulating layer 120 . The circuit pattern layer may include a first circuit pattern 130 embedded in the upper part of the first insulating layer 110, a second circuit pattern 140 disposed under the lower surface of the first insulating layer 110, and a third circuit pattern 150 disposed on the upper surface of the second insulating layer 120.

[0085] The first circuit pattern 130 is disposed to be embedded in the first insulating layer 110. That is, the top surface of the first circuit pattern 130 may be located on the same plane as the top surface of the first insulating layer 110.

[0086] Therefore, the lower surface of the second insulating layer 120 may include a region in contact with the upper surface of the first insulating layer 110 and a region in contact with the upper surface of the first circuit pattern 130 . The second circuit pattern 140 may have a structure that protrudes below the lower surface of the first insulating layer 110. Also, the third circuit pattern 150 may have a structure that protrudes above the upper surface of the second insulating layer 120.

[0087] As described above, the first to third circuit patterns 130, 140, and 150 disposed on the surfaces of the respective insulating layers may be made of a metal material having high electrical conductivity. To this end, the first to third circuit patterns 130, 140, and 150 may be made of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Furthermore, the first to third circuit patterns 130, 140, and 150 may be made of a paste or solder paste containing at least one metal material having excellent bonding strength selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the first to third circuit patterns 130, 140, and 150 may be made of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0088] The first to third circuit patterns 130, 140, and 150 can be formed using conventional printed circuit board manufacturing processes such as additive process, subtractive process, MSAP (Modified Semi-Additive Process), and SAP (Semi-Additive Process), and detailed description thereof will be omitted here.

[0089] Meanwhile, vias 160 and 170 are disposed in each insulating layer to electrically connect circuit patterns disposed on different layers. The vias 160 and 170 are disposed through each insulating layer, thereby electrically connecting circuit patterns disposed on the surfaces of different insulating layers.

[0090] To this end, the vias 160 , 170 may include a first via 160 and a second via 170 . The first via 160 is disposed through the first insulating layer 110. The first via 170 may electrically connect the first circuit pattern 130 disposed on the upper surface of the first insulating layer 110 and the second circuit pattern 140 disposed on the lower surface of the first insulating layer 110.

[0091] The second via 170 is disposed through the second insulating layer 120. The second via 170 may electrically connect the first circuit pattern 130 to a third circuit pattern 150 disposed on the upper surface of the second insulating layer 120.

[0092] As described above, the first insulating layer 110 may be made of a non-photosensitive insulating resin. For example, the first insulating layer 110 may be made of a prepreg containing glass therein. Thus, the first via 160 may have a first width.

[0093] The first via 160 may be formed by drilling an electrically isolated layer as a path for electrical connection between layers of a printed circuit board to form a via hole, and then filling or plating the formed via hole with a conductive material.

[0094] The metal material for forming the first via 160 may be any one selected from Cu, Ag, Sn, Au, Ni, and Pd, and any one or a combination of methods selected from filling of the metal material, electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet method, and dispensing may be used.

[0095] At this time, the via hole can be formed by any one of mechanical, laser, and chemical processing methods. When the via hole is formed by mechanical processing, methods such as milling, drilling, and routing can be used; when it is formed by laser processing, UV or CO2 laser methods can be used; when it is formed by chemical processing, the first insulating layer 110 can be opened using chemicals including aminosilane, ketones, etc.

[0096] On the other hand, laser processing is a cutting method that focuses optical energy on the surface to melt and vaporize part of the material, resulting in the desired shape. It can easily process complex shapes created by computer programs, and can also process composite materials that are difficult to cut using other methods. The laser processing drill is preferably a YAG (Yttrium Aluminum Garnet) laser, a CO2 laser, or an ultraviolet (UV) laser. The YAG laser is a laser that can process both the copper foil layer and the insulating layer, while the CO2 laser is a laser that can process only the insulating layer.

[0097] As described above, the first via 160 is formed by filling a via hole formed by laser processing with a metal material, and therefore there is a limit to the minimum width of the via hole that can be formed by laser processing. Therefore, the first via 160 may have a width of 50 μm to 200 μm. For example, the first via 160 may have a width in the range of 70 μm to 100 μm.

[0098] Meanwhile, the second via 170 is disposed in the second insulating layer 120 made of a photosensitive insulating resin. The second via 170 can be formed by opening the photosensitive insulating resin constituting the second insulating layer 120 through exposure and development to form a via hole, and then filling the formed via hole with a metal material. The second via 170 can have a second width smaller than the first width. For example, the second via 170 can have a width satisfying a range of 15 μm to 50 μm. For example, the second via 170 can have a width satisfying a range of 20 μm to 35 μm.

[0099] Meanwhile, a first protective layer 180 is disposed on the lower surface of the first insulating layer 110, and a second protective layer 190 is disposed on the upper surface of the second insulating layer 120. The first protective layer 180 is disposed on the lower surface of the first insulating layer 110 to protect the lower surface of the first insulating layer 110. In addition, the first protective layer 180 is disposed to cover at least a portion of the lower surface of the second circuit pattern 140 disposed on the lower surface of the first insulating layer 110.

[0100] In addition, a second protective layer 190 is disposed on the upper surface of the second insulating layer 120, but is not limited thereto. That is, the second protective layer 190 is also made of the same photosensitive insulating resin as the second insulating layer 120. Therefore, the second protective layer 190 may be selectively omitted. However, the second protective layer 190 is selectively disposed on the second insulating layer 120 to protect the surface of the third circuit pattern 150 disposed on the upper surface of the second insulating layer 120.

[0101] The first and second protective layers 180 and 190 may include an insulating material. The first and second protective layers 180 and 190 may include various materials that can be applied and then heated to harden to protect the surface of the circuit pattern. The first and second protective layers 180 and 190 may be resist layers. For example, the first and second protective layers 180 and 190 may be solder resist layers including an organic polymer material. For example, the first and second protective layers 180 and 190 may include an epoxy acrylate resin. More specifically, the first and second protective layers 180 and 190 may include a resin, a hardener, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. However, embodiments are not limited thereto, and the first and second protective layers 180 and 190 may be any one of a photo solder resist layer, a coverlay, and a polymer material.

[0102] The first and second protective layers 180 and 190 may have a thickness of 1 μm to 20 μm. The first and second protective layers 180 and 190 may have a thickness of 1 μm to 15 μm. For example, the first and second protective layers 180 and 190 may have a thickness of 5 μm to 20 μm. If the thickness of the first and second protective layers 180 and 190 exceeds 20 μm, the thickness of the printed circuit board increases. If the thickness of the first and second protective layers 180 and 190 is less than 1 μm, the reliability of the circuit pattern decreases.

[0103] According to the embodiment, the outermost insulating layer of the printed circuit board is made of a photoimageable dielectric (PID) resin, and a cavity in which a device can be mounted is formed in the outermost insulating layer, so that the device can be mounted in the formed cavity.

[0104] In this case, since at least a portion of the device is disposed within the outermost insulating layer of the printed circuit board, the overall thickness of the package substrate can be reduced by the depth of the cavity. Also, according to the embodiment, the insulating layer in which the cavity is formed is made of a photoimageable dielectric (PID), so that the cavity for mounting the device can be easily formed through exposure and development, thereby resolving reliability issues that may occur during cavity formation.

[0105] In addition, according to the embodiment, when a circuit pattern to be embedded in an insulating layer is formed, a cavity pattern is formed together with the circuit pattern. The formed cavity pattern is then removed to form a cavity in the insulating layer. This solves the problem of glass fibers contained in the insulating layer being exposed through the cavity due to the material forming the insulating layer, thereby improving the reliability of the cavity.

[0106] In addition, according to the embodiment, the depth of the entire cavity can be easily adjusted by combining the first part of the cavity formed on the photosensitive insulating resin and the second part of the cavity formed on the non-photosensitive insulating resin.

[0107] Furthermore, according to the embodiment, processes such as a laser process and sandblasting, which are essential for forming a cavity, can be eliminated, thereby simplifying the manufacturing process and significantly reducing manufacturing costs.

[0108] Hereinafter, the method for manufacturing the printed circuit board according to the first embodiment shown in FIG. 2 will be described in detail. 3 to 9 are cross-sectional views illustrating the steps of a method for manufacturing the printed circuit board according to the first embodiment shown in FIG. 2 in order of steps.

[0109] First, a method for manufacturing a printed circuit board may include a process for simultaneously manufacturing multiple printed circuit boards on both sides of a carrier board CB by placing a member such as a carrier board CB between the two printed circuit boards. Referring to FIG. 3, the method for manufacturing a printed circuit board may include a process for preparing a carrier board CB and forming a first circuit pattern 130 on each of the upper and lower surfaces of the carrier board CB. At this time, a cavity pattern 130A is formed on the upper and lower surfaces of the carrier board CB together with the first circuit pattern 130. At this time, the cavity pattern 130A is formed together with the first circuit pattern 130. Preferably, the cavity pattern 130A may be made of the same metal material as the first circuit pattern 130.

[0110] 4, after the cavity pattern 130A and the first circuit pattern 130 are formed, a first insulating layer 110 may be formed on each of the upper and lower surfaces of the carrier board CB. At this time, the first insulating layer 110 may be made of a non-photosensitive material as described above. For example, the first insulating layer 110 may be made of prepreg.

[0111] After the first insulating layer 110 is formed, the via holes VH can be formed by processing the first insulating layer 110. At this time, the first insulating layer 110 is formed from a prepreg, and therefore, the via holes VH can be formed by a laser process.

[0112] 5, after the via hole VH is formed, the inside of the formed via hole VH may be filled with a metal material to form a first via 160 penetrating the first insulating layer 110. Furthermore, at the same time as forming the first via 160, a second circuit pattern 140 may be formed on the surface of the first insulating layer 110. Thus, the first via 160 may electrically connect the first circuit pattern 130 and the second circuit pattern 140.

[0113] 6, the upper and lower substrates can be separated based on the carrier board CB. That is, in the first embodiment, the processes of forming the first circuit pattern 130, the cavity pattern 130A, the second circuit pattern 140, the first via 160, and the first insulating layer 110 are performed by simultaneously manufacturing a plurality of substrates on both sides of the carrier board CB while the carrier board CB is in place.

[0114] Next, referring to FIG. 7, when the carrier board CB is separated, a second insulating layer 120 is formed on the top surface of the first insulating layer 110 to cover the top surface of the first circuit pattern 130 embedded on the top of the first insulating layer 110.

[0115] In this case, the second insulating layer 120 may be made of a photosensitive insulating resin. After the second insulating layer 120 is formed, a via hole VH and a first portion C1 of a cavity C may be formed on the second insulating layer 120.

[0116] At this time, the via hole VH and the first portion C1 of the cavity C are simultaneously formed on the second insulating layer 120 by performing an exposure and development process. In addition, the first portion C1 of the cavity C may overlap the cavity pattern 130A embedded in the upper portion of the first insulating layer 110 in the vertical direction.

[0117] In this case, the depth of the first portion C1 of the cavity C may be the same as the thickness of the second insulating layer 120. That is, the first portion C1 of the cavity C may be formed through the second insulating layer 120. Therefore, the top surface of the cavity pattern 130A buried in the upper portion of the first insulating layer 110 may be exposed through the first portion C1 of the cavity C.

[0118] At this time, the first portion C1 of the cavity C may have a first cross-sectional shape formed by exposing and developing the second insulating layer 120 made of the photosensitive insulating resin as described above. For example, the first portion C1 of the cavity C may have a trapezoidal cross-sectional shape in which the inner wall is inclined with respect to the main surface.

[0119] Next, referring to FIG. 8, a metal material may be filled into the via hole VH formed in the second insulating layer 120 to form a second via 170. Additionally, a process of forming a third circuit pattern 150 on the upper surface of the second insulating layer 120 may be performed simultaneously with the formation of the second via 170 .

[0120] 9, a process may be performed to remove the cavity pattern 130A exposed through the first portion C1 of the cavity C. The process may be performed using an etchant that etches the metal material constituting the cavity pattern 130A. At this time, a mask (not shown) for protecting the third circuit pattern 150 may be disposed on the upper surface of the second insulating layer 120, and the process of removing the cavity pattern 130A may be performed with the mask in place.

[0121] By removing the cavity pattern 130A, the area where the cavity pattern 130A is disposed forms a second portion C2 connected to the first portion C1 of the cavity C, thereby forming one cavity C by connecting the first portion C1 and the second portion C2.

[0122] In this case, the second portion C2 of the cavity C may have a second cross-sectional shape. That is, the second portion C2 may have a second cross-sectional shape that is different from the first cross-sectional shape of the first portion C1. The second cross-sectional shape may be the same as the cross-sectional shape of the first circuit pattern 130. For example, the second cross-sectional shape of the second portion C2 may be a quadrangle.

[0123] After the second portion C2 of the cavity C is formed, a first protective layer 180 and a second protective layer 190 may be formed on the lower surface of the first insulating layer 110 and the upper surface of the second insulating layer 120, respectively.

[0124] According to the embodiment, the outermost insulating layer of the printed circuit board is made of a photoimageable dielectric (PID) resin, and a cavity in which a device can be mounted is formed in the outermost insulating layer, so that the device can be mounted in the formed cavity.

[0125] In this case, since at least a portion of the device is disposed within the outermost insulating layer of the printed circuit board, the overall thickness of the package substrate can be reduced by the depth of the cavity. Also, according to the embodiment, the insulating layer in which the cavity is formed is made of a photoimageable dielectric (PID), so that the cavity for mounting the device can be easily formed through exposure and development, thereby resolving reliability issues that may occur during cavity formation.

[0126] In addition, according to the embodiment, when a circuit pattern to be embedded in an insulating layer is formed, a cavity pattern is formed together with the circuit pattern. The formed cavity pattern is then removed to form a cavity in the insulating layer. This solves the problem of glass fibers contained in the insulating layer being exposed through the cavity due to the material forming the insulating layer, thereby improving the reliability of the cavity.

[0127] In addition, according to the embodiment, the depth of the entire cavity can be easily adjusted by combining the first part of the cavity formed on the photosensitive insulating resin and the second part of the cavity formed on the non-photosensitive insulating resin.

[0128] Furthermore, according to the embodiment, processes such as a laser process and sandblasting, which are essential for forming a cavity, can be eliminated, thereby simplifying the manufacturing process and significantly reducing manufacturing costs.

[0129] Meanwhile, the printed circuit board according to the first embodiment may constitute an upper substrate in a package substrate including a lower substrate and an upper substrate. For example, electronic components may be mounted on the upper part of the lower substrate, and the upper substrate corresponding to the printed circuit board according to the first embodiment may be attached onto the lower substrate, so that at least a portion of the electronic components is disposed within a cavity C formed in the upper substrate.

[0130] In addition, the printed circuit board 100 according to the first embodiment includes a cavity C including a first portion C1 and a second portion C2 formed in the second insulating layer 120 made of a photosensitive insulating resin and the first insulating layer 110 made of a non-photosensitive insulating resin, respectively.

[0131] Alternatively, the cavity C of the printed circuit board may include only one of the first portion C1 and the second portion C2. Hereinafter, a printed circuit board including a cavity C including only the second portion C2 (second embodiment) and a printed circuit board including a cavity C including only the first portion C1 (third embodiment) will be described. *196 *

[0132] FIG. 10 is a diagram showing a printed circuit board according to a second embodiment. *Referring to FIG. 10, a printed circuit board 200 may include multiple insulating layers 210, 220. The multiple insulating layers 210, 220 have a mutually laminated structure.

[0133] Preferably, the plurality of insulating layers 210 , 220 may include a first insulating layer 210 and a second insulating layer 220 . The first insulating layer 210 and the second insulating layer 220 may be made of different insulating resins or may be made of the same insulating resin.

[0134] For example, the first insulating layer 210 can be made of a non-photosensitive insulating resin. Specifically, the first insulating layer 210 may include glass or plastic. More specifically, the first insulating layer 210 may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass, or may include reinforced or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), or sapphire.

[0135] That is, the first insulating layer 210 may be made of, but is not limited to, a material such as LCP (Liquid Crystal Polymer), PPG (FR1, 2, 3, 4), Teflon (registered trademark), ABF (Ajinomoto build-up film), RCC (Resin Coated Copper), etc. As an example, the first insulating layer 210 may be made of any one of prepreg (PPG), ABF (Ajinomoto build-up film), RCC (Resin Coated Copper), Liquid Crystal Polymer (LCP), and Teflon (registered trademark).

[0136] The first insulating layer 210 may also contain glass therein to ensure rigidity. The second insulating layer 220 is disposed on the first insulating layer 210. The second insulating layer 220 may be made of a non-photosensitive insulating resin, similar to the first insulating layer 210. However, unlike the first insulating layer 210, the second insulating layer 220 may be made of a photosensitive insulating resin.

[0137] Meanwhile, the printed circuit board 200 in this embodiment includes a cavity C. At this time, the cavity C may be formed in the first insulating layer 210. The cavity C may be a recess recessed from the bottom to the top of the first insulating layer 210 .

[0138] The cavity C may have the same cross-sectional shape as the first circuit pattern 230 . For example, the inner wall of the cavity C may be perpendicular to the main surface. For example, the cross-sectional shape of the cavity C may be rectangular.

[0139] Meanwhile, the depth of the cavity C may correspond to the thickness of the first circuit pattern 230 embedded under the first insulating layer 210. Preferably, the cavity C may be formed by removing a cavity pattern (described below) formed together with the first circuit pattern 230 when forming the first circuit pattern 230. Therefore, the depth of the cavity C may correspond to the thickness of the first circuit pattern 230. For example, the depth of the cavity C may be the same as the thickness of the first circuit pattern 230 .

[0140] In the embodiment, when forming the first circuit pattern 230 buried in the lower part of the first insulating layer 210 as described above, a cavity pattern is formed together with the first circuit pattern 230. Then, the formed cavity pattern is removed to form a cavity C in the first insulating layer 210. At this time, when the surface of the first insulating layer 210 is removed using a laser or sandblasting to form a cavity, glass present in the first insulating layer 210 is exposed to the outside, and the exposed glass affects the reliability of the cavity C.

[0141] On the other hand, in the embodiment, the first insulating layer 210 is not removed, but the cavity pattern disposed in the first insulating layer 210 is removed to form the cavity C. Therefore, in the embodiment, the problem of the glass fiber contained in the insulating layer being exposed through the cavity can be solved, and thus the reliability of the cavity can be improved.

[0142] Furthermore, according to the embodiment, processes such as a laser process and sandblasting, which are essential for forming a cavity, can be eliminated, thereby simplifying the manufacturing process and significantly reducing manufacturing costs.

[0143] Meanwhile, a circuit pattern layer is disposed on the surface of the first insulating layer 210 and the second insulating layer 220. The circuit pattern layer may include a first circuit pattern 230 embedded in the lower portion of the first insulating layer 210, a second circuit pattern 240 disposed on the upper surface of the first insulating layer 210, and a third circuit pattern 250 disposed on the upper surface of the second insulating layer 220.

[0144] The first circuit pattern 230 is disposed to be embedded in the lower portion of the first insulating layer 210. That is, the lower surface of the first circuit pattern 230 may be located on the same plane as the lower surface of the first insulating layer 210.

[0145] The second circuit pattern 240 may have a structure that protrudes above the top surface of the first insulating layer 210. Also, the third circuit pattern 250 may have a structure that protrudes above the top surface of the second insulating layer 220.

[0146] As described above, the first to third circuit patterns 230, 240, and 250 disposed on the surfaces of the respective insulating layers may be made of a metal material having high electrical conductivity. To this end, the first to third circuit patterns 230, 240, and 250 may be made of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Furthermore, the first to third circuit patterns 230, 240, and 250 may be made of a paste or solder paste containing at least one metal material having excellent bonding strength selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the first to third circuit patterns 230, 240, and 250 may be made of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0147] The first to third circuit patterns 230, 240, and 250 can be formed using conventional printed circuit board manufacturing processes such as additive process, subtractive process, MSAP (Modified Semi-Additive Process), and SAP (Semi-Additive Process), and detailed description thereof will be omitted here.

[0148] Meanwhile, vias 260 and 270 are disposed in each insulating layer to electrically connect circuit patterns disposed on different layers. The vias 260 and 270 are disposed through each insulating layer, thereby electrically connecting circuit patterns disposed on the surfaces of different insulating layers.

[0149] Meanwhile, a first protective layer 280 is disposed on the lower surface of the first insulating layer 210, and a second protective layer 290 is disposed on the upper surface of the second insulating layer 220. The first protective layer 280 is disposed on the lower surface of the first insulating layer 210 to protect the lower surface of the first insulating layer 210. In addition, the first protective layer 280 is disposed to cover at least a portion of the lower surface of the first circuit pattern 230 disposed on the lower surface of the first insulating layer 210.

[0150] In addition, a second protective layer 290 is disposed on the upper surface of the second insulating layer 220, but is not limited thereto. That is, the second protective layer 290 is also made of the same photosensitive insulating resin as the second insulating layer 220. Therefore, the second protective layer 290 may be selectively omitted. However, the second protective layer 290 is selectively disposed on the second insulating layer 220 to protect the surface of the third circuit pattern 250 disposed on the upper surface of the second insulating layer 220.

[0151] The first and second protective layers 280 and 290 may include an insulating material. The first and second protective layers 280 and 290 may include various materials that can be applied and then hardened by heating to protect the surface of the circuit pattern. The first and second protective layers 280 and 290 may be resist layers. For example, the first and second protective layers 280 and 290 may be solder resist layers including an organic polymer material. For example, the first and second protective layers 280 and 290 may include an epoxy acrylate resin. More specifically, the first and second protective layers 280 and 290 may include a resin, a hardener, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. However, embodiments are not limited thereto, and the first and second protective layers 280 and 290 may be any one of a photo solder resist layer, a coverlay, and a polymer material.

[0152] The first and second protective layers 280 and 290 may have a thickness of 1 μm to 20 μm. The first and second protective layers 280 and 290 may have a thickness of 1 μm to 15 μm. For example, the first and second protective layers 280 and 290 may have a thickness of 5 μm to 20 μm. If the thickness of the first and second protective layers 280 and 290 exceeds 20 μm, the thickness of the printed circuit board increases. If the thickness of the first and second protective layers 280 and 290 is less than 1 μm, the reliability of the circuit pattern decreases.

[0153] 11 to 17 are cross-sectional views showing the manufacturing method of the printed circuit board according to the second embodiment shown in FIG. 10 in the order of steps. First, the method for manufacturing a printed circuit board may involve a process of simultaneously manufacturing a plurality of printed circuit boards on both sides of a carrier board CB by placing a member such as a carrier board CB between the two sides.

[0154] 11, the method for manufacturing a printed circuit board may include the steps of preparing a carrier board CB and forming a first circuit pattern 230 on each of the upper and lower surfaces of the carrier board CB. At this time, a cavity pattern 230A is formed on the upper and lower surfaces of the carrier board CB together with the first circuit pattern 230. At this time, the cavity pattern 230A is formed together with the first circuit pattern 230. Preferably, the cavity pattern 230A may be made of the same metal material as the first circuit pattern 230.

[0155] 12, after the cavity pattern 230A and the first circuit pattern 230 are formed, a first insulating layer 210 may be formed on each of the upper and lower surfaces of the carrier board CB. At this time, the first insulating layer 210 may be made of a non-photosensitive material as described above. For example, the first insulating layer 210 may be made of prepreg.

[0156] After the first insulating layer 210 is formed, the via holes VH can be formed by processing the first insulating layer 210. At this time, the first insulating layer 210 is formed from a prepreg, and therefore, the via holes VH can be formed by a laser process.

[0157] 13, after the via hole VH is formed, the inside of the formed via hole VH may be filled with a metal material to form a first via 260 penetrating the first insulating layer 210. Furthermore, at the same time as forming the first via 260, a second circuit pattern 240 may be formed on the surface of the first insulating layer 210. Thus, the first via 260 may electrically connect the first circuit pattern 230 and the second circuit pattern 240.

[0158] 14, the upper and lower substrates can be separated based on the carrier board CB. That is, in the second embodiment, the processes of forming the first circuit pattern 230, the cavity pattern 230A, the second circuit pattern 240, the first via 260, and the first insulating layer 210 are performed by simultaneously manufacturing a plurality of substrates on both sides of the carrier board CB while the carrier board CB is in place.

[0159] Next, referring to FIG. 15, when the carrier board CB is separated, a second insulating layer 220 is formed on the upper surface of the first insulating layer 210 to cover the upper surface of the second circuit pattern 240 disposed on the upper surface of the first insulating layer 210.

[0160] At this time, the second insulating layer 220 may be formed of a photosensitive insulating resin or a non-photosensitive insulating resin. After the second insulating layer 220 is formed, a via hole VH may be formed on the second insulating layer 220 .

[0161] Next, referring to FIG. 16, a metal material may be filled into the via hole VH formed in the second insulating layer 220 to form a second via 270. Additionally, a process of forming a third circuit pattern 250 on the upper surface of the second insulating layer 220 may be performed simultaneously with the formation of the second via 270 .

[0162] 17, a process for removing the cavity pattern 230A buried under the first insulating layer 210 may be performed. The process for removing the cavity pattern 230A may be performed using an etchant that etches the metal material constituting the cavity pattern 230A. At this time, a mask (not shown) for protecting the first circuit pattern 230 may be placed on the lower surface of the first insulating layer 210, and the process for removing the cavity pattern 230A may be performed with the mask in place.

[0163] By removing the cavity pattern 230A, the area where the cavity pattern 230A was disposed is opened, and the cavity C can be formed. At this time, the cross-sectional shape of the cavity C may have the same cross-sectional shape as the first circuit pattern 230, for example, a rectangular shape.

[0164] After the cavity C is formed, a first protective layer 280 and a second protective layer 290 may be formed on the lower surface of the first insulating layer 210 and the upper surface of the second insulating layer 220, respectively. FIG. 18 is a diagram showing a printed circuit board according to a third embodiment. Hereinafter, the description of the same parts as those of the printed circuit boards of the first and second embodiments described with reference to FIGS. 2 and 10 will be omitted.

[0165] Referring to FIG. 18, a printed circuit board 300 includes a first insulating layer 310 and a second insulating layer 320 . The second insulating layer 320 is disposed on the first insulating layer 310 .

[0166] In this case, in the printed circuit board of the first embodiment, it was not possible to arrange a circuit pattern on the upper surface of the first insulating layer 110 because the second portion C2 of the cavity C was formed there, which reduced the density of the circuit in the area where the second portion C2 of the cavity C was formed.

[0167] In contrast to this, in the third embodiment, a circuit pattern can be formed on the top surface of the first insulating layer 310 as well, thereby improving the density of the circuit. To this end, the second insulating layer 320 includes a first insulating part 321 disposed on the upper surface of the first insulating layer 310 and a second insulating part 322 disposed on the upper surface of the first insulating part 321 .

[0168] A second circuit pattern 340 is disposed on the upper surface of the first insulating layer 310. The second circuit pattern 340 may include a circuit pattern 340A disposed in an area vertically overlapping the cavity C.

[0169] In this case, the first insulating part 321 is disposed on the top surface of the first insulating layer 310 with a certain thickness, thereby covering the second circuit patterns 340 and 340A. That is, the thickness of the first insulating part 321 may be greater than the thickness of the second circuit patterns 340 and 340A, and therefore the top surface of the first insulating part 321 may be higher than the top surfaces of the second circuit patterns 340 and 340A.

[0170] The second insulating part 322 is disposed on the upper surface of the first insulating part 321 . A cavity C in the printed circuit board 300 is formed in the second insulating part 322 .

[0171] In this case, the second insulating part 322 may be made of a photosensitive insulating resin, and the cavity C may be formed by exposing and developing the second insulating part 322. As a result, the vertical cross section of the cavity C may have a trapezoidal shape.

[0172] Meanwhile, the first insulating part 321 may be formed of a photosensitive insulating resin or a non-photosensitive insulating resin. At this time, if the first insulating part 321 is formed of a non-photosensitive insulating resin, the first insulating part 321 is not removed when forming the cavity C, and therefore, the cavity C can be formed by removing only the second insulating part 322.

[0173] However, if the first insulating part 321 is made of a photosensitive insulating resin, the first insulating part 321 is removed when the cavity C is formed. Accordingly, if the first insulating part 321 is made of a photosensitive insulating resin, the second insulating part 322 is laminated after the first insulating part 321 is completely cured. Furthermore, when the cavity C is formed by exposing and developing the second insulating part 322, the first insulating part 321 is not removed because it is in a completely cured state. Therefore, the cavity C can be formed by removing only the second insulating part 322.

[0174] Meanwhile, a first via 360 is disposed in the first insulating layer 310, and a second via 370 is disposed in the second insulating layer 320. In this case, the second via 370 may include a first via part 371 penetrating the first insulating part 321 of the second insulating layer 320 and a second via part 372 penetrating the second insulating part 322 of the second insulating layer 320.

[0175] A first protective layer 380 is disposed on the lower surface of the first insulating layer 310, and a second protective layer 390 is disposed on the upper surface of the second insulating layer 320. 19 to 23 are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 18 in the order of steps.

[0176] Referring to FIG. 19, a first insulating layer 310 is prepared, and a first circuit pattern 330 embedded in the lower part of the first insulating layer 310, a second circuit pattern 340 disposed on the upper surface of the first insulating layer 310, and a first via 360 penetrating the first insulating layer 310 are formed.

[0177] Next, referring to FIG. 20, the first insulating part 321 of the second insulating layer 320 is formed on the upper surface of the first insulating layer 310 . At this time, the first insulating part 321 may be formed of a photosensitive insulating resin or a non-photosensitive insulating resin.

[0178] Thereafter, a first via hole VH1 is formed in the first insulating part 321. Here, if the first insulating part 321 is formed of a photosensitive insulating resin, the first via hole VH1 may be formed by a photolithography process such as an exposure and development process. Alternatively, if the first insulating part 321 is formed of a non-photosensitive insulating resin, the first via hole VH1 may be formed by a laser process.

[0179] 21, a second insulating part 322 is formed on the first insulating part 321. At this time, the second insulating part 322 may be made of a photosensitive insulating resin.

[0180] Then, the second insulating part 322 is subjected to processes such as exposure and development to form a second via hole VH1 that overlaps the first via hole VH1 in the vertical direction in the second insulating part 322. In addition, when the second via hole VH1 is formed, a cavity C that penetrates the second insulating part 322 can be formed at the same time.

[0181] 22, the first and second via holes VH1 and VH2 may be filled with a metal material to form a second via 370. Furthermore, when forming the second via 370, a third circuit pattern 350 may be formed on the top surface of the second insulating layer 320. In this case, the second via 370 may include a first via part 371 disposed to penetrate the first insulating part 321 and a second via part 372 directly connected to the first via part 371 and disposed to penetrate the second insulating part 322.

[0182] Furthermore, the cavity C is disposed in a region that vertically overlaps the second circuit pattern 340 disposed on the first insulating layer 310. However, a first insulating part 321 is disposed on the first insulating layer 310, and the cavity C is formed in a second insulating part 322 disposed on the first insulating part 321. Therefore, the second circuit pattern 340 is protected by the first insulating part 321, and reliability problems that may occur when the cavity C is formed can be resolved.

[0183] Next, referring to FIG. 23, a first protective layer 380 is formed under the lower surface of the first insulating layer 310, and a second protective layer 390 is formed on the upper surface of the second insulating layer 320. According to the embodiment, the outermost insulating layer of the printed circuit board is made of a photoimageable dielectric (PID) resin, and a cavity in which a device can be mounted is formed in the outermost insulating layer, so that the device can be mounted in the formed cavity.

[0184] In this case, since at least a portion of the device is disposed within the outermost insulating layer of the printed circuit board, the overall thickness of the package substrate can be reduced by the depth of the cavity. Also, according to the embodiment, the insulating layer in which the cavity is formed is made of a photoimageable dielectric (PID), so that the cavity for mounting the device can be easily formed through exposure and development, thereby resolving reliability issues that may occur during cavity formation.

[0185] In addition, according to the embodiment, when a circuit pattern to be embedded in an insulating layer is formed, a cavity pattern is formed together with the circuit pattern. The formed cavity pattern is then removed to form a cavity in the insulating layer. This solves the problem of glass fibers contained in the insulating layer being exposed through the cavity due to the material forming the insulating layer, thereby improving the reliability of the cavity.

[0186] In addition, according to the embodiment, the depth of the entire cavity can be easily adjusted by combining the first part of the cavity formed on the photosensitive insulating resin and the second part of the cavity formed on the non-photosensitive insulating resin.

[0187] Furthermore, according to the embodiment, processes such as a laser process and sandblasting, which are essential for forming a cavity, can be eliminated, thereby simplifying the manufacturing process and significantly reducing manufacturing costs.

[0188] FIG. 24 is a diagram showing a printed circuit board according to a fourth embodiment. Referring to FIG. 24, the printed circuit board may include multiple insulating layers 411, 412, 413, 414, 415, 416, 421, 422.

[0189] In this case, some of the insulating layers 411, 412, 413, 414, 415, 416, 421, 422, namely, insulating layers 411, 412, 413, 414, 415, 416, can be referred to as first insulating parts, inner insulating layers, middle insulating layers, or inner layers, and the remaining insulating layers 421, 422 can be referred to as second insulating parts / third insulating parts, outer insulating layers, outer edge insulating layers, upper insulating layers / lower insulating layers, or outer layers.

[0190] In the following description, the multiple insulating layers 411, 412, 413, 414, 415, 416, 421, and 422 will be classified as first to eighth insulating layers. However, as described above, the insulating layers 411, 412, 413, 414, 415, 416, 421, and 422 that are arranged internally are the first insulating portion, the seventh insulating layer 421 arranged on the first insulating portion can be referred to as the second insulating portion, and the eighth insulating layer 422 arranged below the first insulating portion can be referred to as the third insulating portion.

[0191] Furthermore, circuit patterns and vias are arranged on the surfaces and inside of the plurality of insulating layers 411, 412, 413, 414, 415, 416, 421, and 422, respectively.

[0192] Hereinafter, the circuit patterns arranged on the multiple insulating layers 411, 412, 413, 414, 415, 416, 421, and 422 will be divided into first to ninth circuit patterns based on their positions. Of the multiple circuit patterns, the circuit pattern arranged on the surface of the first insulating portion can be referred to as the first circuit pattern portion, the circuit pattern arranged on the surface of the second insulating portion can be referred to as the second circuit pattern portion, and the circuit pattern arranged on the surface of the third insulating portion can be referred to as the third circuit pattern portion. Similarly, of the multiple vias, the vias arranged in the first insulating portion can be referred to as the first via portion, the vias arranged in the second insulating portion can be referred to as the second via portion, and the vias arranged in the third insulating portion can be referred to as the third via portion.

[0193] Printed circuit board 400 can represent electrical wiring connecting circuit components as wiring diagrams based on circuit design, and can reproduce electrical conductors on insulating layers 411, 412, 413, 414, 415, 416, 421, and 422. Furthermore, printed circuit board 400 can mount elements that are the same as electrical components, form wiring that connects these in a circuit, and can also mechanically fix components other than those that have an electrical connection function.

[0194] The insulating layers 411, 412, 413, 414, 415, 416, 421, and 422 have a mutually laminated structure. Preferably, the insulating layers 411, 412, 413, 414, 415, 416, 421, 422 may include a first insulating layer 411, a second insulating layer 412, a third insulating layer 413, a fourth insulating layer 414, a fifth insulating layer 415, a sixth insulating layer 416, a seventh insulating layer 421 and an eighth insulating layer 422.

[0195] That is, the printed circuit board 400 in this embodiment has a nine-layer structure based on the circuit pattern layer, and therefore may include eight insulating layers 411, 412, 413, 414, 415, 416, 421, and 422 on which the circuit patterns are disposed.

[0196] In this case, among the insulating layers 411, 412, 413, 414, 415, 416, 421, and 422, the first insulating layer 411, the second insulating layer 412, the third insulating layer 413, the fourth insulating layer 414, the fifth insulating layer 415, and the sixth insulating layer 416 can be referred to as inner insulating layers. Also, the seventh insulating layer 421 and the eighth insulating layer 422 can be referred to as outer insulating layers or the outermost insulating layers.

[0197] That is, the seventh insulating layer 421 is disposed on the sixth insulating layer 416, which is disposed at the top of the inner insulating layers. The eighth insulating layer 422 is disposed below the fifth insulating layer 415, which is disposed at the bottom of the inner insulating layers.

[0198] The first insulating layer 411, the second insulating layer 412, the third insulating layer 413, the fourth insulating layer 414, the fifth insulating layer 415, and the sixth insulating layer 416 may include prepreg. The seventh insulating layer 421 may be the insulating layer arranged at the top of the multiple insulating layers that make up the printed circuit board 400. The eighth insulating layer 422 may be the insulating layer arranged at the bottom of the multiple insulating layers that make up the printed circuit board 400.

[0199] In this case, the seventh insulating layer 421 and the eighth insulating layer 422 may include a photosensitive insulating resin. When the seventh insulating layer 421 and the eighth insulating layer 422 contain a photosensitive insulating resin, a protective layer such as a solder resist that is generally disposed on the outermost side of a printed circuit board can be selectively removed.

[0200] The seventh insulating layer 421 and the eighth insulating layer 422 include a first opening OR1 and a second opening OR2, respectively. The seventh insulating layer 421 includes a first opening OR1. The first opening OR1 may be formed by opening the seventh insulating layer 421 in a region where a first element (described later) is to be disposed. Preferably, the first opening OR1 may expose a first lead portion 437a of a circuit pattern 437 disposed on the sixth insulating layer 416, the first lead portion 437a being disposed in a region where the first element is to be mounted.

[0201] The eighth insulating layer 422 includes a second opening OR2. The second opening OR2 may be formed by opening the eighth insulating layer 422 in a region where a second element (described later) is to be disposed. Preferably, the second opening OR2 may expose a second lead portion 436a of the circuit pattern 436 disposed under the fifth insulating layer 415, the second lead portion 436a being disposed in a region where the second element is to be mounted.

[0202] In this case, the first opening OR1 and the second opening OR2 can be formed by exposing and developing the seventh insulating layer 421 and the eighth insulating layer 422. That is, in the comparative example, a laser drilling process was generally performed to form cavities on the insulating layer. As a result, in the comparative example, the laser drilling could damage the insulating layer or the circuit pattern layer, and accurate positioning was difficult.

[0203] On the other hand, in this embodiment, the seventh insulating layer 421 and the eighth insulating layer 422, which are arranged on the outermost sides, are made of a photosensitive insulating resin, so that the first opening OR1 and the second opening OR2 can be formed in the seventh insulating layer 421 and the eighth insulating layer 422 by an exposure and development process. The first opening OR1 and the second opening OR2 may then be cavities for mounting the first element and the second element on the first lead portion 437a and the second lead portion 436a.

[0204] As described above, in the embodiment, the outermost insulating layer is made of a photosensitive insulating resin, and a cavity for mounting a device is formed in the photosensitive insulating resin by performing exposure and development, etc., thereby solving various reliability problems that arise during the cavity formation process, and by allowing a device to be mounted in the cavity, the overall thickness of the package substrate can be reduced by the depth of the cavity.

[0205] In the embodiment, circuit patterns 431, 432, 433, 434, 435, 436, 437, 438, and 439 are disposed on the surfaces of the insulating layers. Preferably, a first circuit pattern 431 is disposed on the upper surface of the first insulating layer 411. And, a second circuit pattern 432 is disposed on the lower surface of the first insulating layer 411.

[0206] Furthermore, a third circuit pattern 433 is disposed on the upper surface of the second insulating layer 412. A fourth circuit pattern 434 is disposed on the lower surface of the third insulating layer 413. A fifth circuit pattern 434 is disposed on the upper surface of the fourth insulating layer 414. A sixth circuit pattern 436 is disposed on the lower surface of the fifth insulating layer 415. A seventh circuit pattern 437 is disposed on the upper surface of the sixth insulating layer 416. An eighth circuit pattern 438 is disposed on the upper surface of the seventh insulating layer 421. And a ninth circuit pattern 439 is disposed on the lower surface of the eighth insulating layer 422.

[0207] As described above, the circuit patterns 431, 432, 433, 434, 435, 436, 437, 438, and 439 disposed on the surface of each insulating layer may be made of a metal material having high electrical conductivity, and thus, the circuit patterns 431, 432, 433, 434, 435, 436, 437, 438, and 439 may be made of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). In addition, the circuit patterns 431, 432, 433, 434, 435, 436, 437, 438, and 439 may be made of a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which have excellent bonding strength. Preferably, the circuit patterns 431, 432, 433, 434, 435, 436, 437, 438, and 439 may be made of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0208] The circuit patterns 431, 432, 433, 434, 435, 436, 437, 438, and 439 can be formed using conventional printed circuit board manufacturing processes such as additive process, subtractive process, MSAP (Modified Semi-Additive Process), and SAP (Semi-Additive Process), and detailed description thereof will be omitted here.

[0209] Meanwhile, vias 441, 442, 443, 444, 445, 446, 446, 448, and 449 are arranged in each insulating layer to electrically connect circuit patterns arranged on different layers. The vias 441, 442, 443, 444, 445, 446, 446, 448, and 449 are arranged through each insulating layer, thereby electrically connecting circuit patterns arranged on the surfaces of different insulating layers.

[0210] For this reason, the vias 441, 442, 443, 444, 445, 446, 446, 448, and 449 may include the first to ninth vias. The first via 441 is disposed through the first insulating layer 411. The first via 441 can electrically connect the first circuit pattern 431 disposed on the upper surface of the first insulating layer 411 and the second circuit pattern 432 disposed on the lower surface of the first insulating layer 411.

[0211] The second via 442 is disposed through the second insulating layer 412. The second via 442 may electrically connect the first circuit pattern 431 to a third circuit pattern 433 disposed on the upper surface of the second insulating layer 412.

[0212] The third via 443 is disposed through the third insulating layer 413. The third via 443 may electrically connect the second circuit pattern 432 disposed on the lower surface of the first insulating layer 411 to the fourth circuit pattern 434 disposed on the lower surface of the third insulating layer 413.

[0213] The fourth via 444 is disposed through the fourth insulating layer 414. The fourth via 444 can electrically connect the third circuit pattern 433 disposed on the upper surface of the second insulating layer 412 to the fifth circuit pattern 435 disposed on the upper surface of the fourth insulating layer 414.

[0214] The fifth via 445 is disposed through the third insulating layer 415. The fifth via 445 may electrically connect the fourth circuit pattern 434 disposed on the lower surface of the third insulating layer 413 to the sixth circuit pattern 436 disposed on the lower surface of the fifth insulating layer 415.

[0215] The sixth via 446 is disposed through the sixth insulating layer 416. The sixth via 446 may electrically connect the fifth circuit pattern 435 disposed on the upper surface of the fourth insulating layer 414 to the seventh circuit pattern 437 disposed on the upper surface of the sixth insulating layer 416.

[0216] The seventh via 447 is disposed to penetrate the seventh insulating layer 421. The seventh via 447 may electrically connect the seventh circuit pattern 437 disposed on the upper surface of the sixth insulating layer 416 to the eighth circuit pattern 438 disposed on the upper surface of the seventh insulating layer 421.

[0217] The eighth via 448 is disposed through the eighth insulating layer 422. The eighth via 448 may electrically connect the sixth circuit pattern 436 disposed on the lower surface of the fifth insulating layer 415 to the ninth circuit pattern 439 disposed on the lower surface of the eighth insulating layer 422.

[0218] At this time, as described above, the first insulating layer 411, the second insulating layer 412, the third insulating layer 413, the fourth insulating layer 414, the fifth insulating layer 415 and the sixth insulating layer 416 may be made of prepreg.

[0219] As a result, the first to sixth vias 441, 442, 443, 444, 445, and 446 can have a third width W3. The first to sixth vias 441, 442, 443, 444, 445, and 446 may be formed by drilling electrically isolated layers as paths for electrical connection between layers of a printed circuit board to form via holes, and then filling or plating the formed via holes with a conductive material.

[0220] The metal material for forming the first to sixth vias 441, 442, 443, 444, 445, and 446 may be any one selected from Cu, Ag, Sn, Au, Ni, and Pd, and the filling of the metal material may be performed using any one or a combination of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet, and dispensing.

[0221] At this time, the via hole can be formed by any one of mechanical, laser, and chemical processing methods. *326 When the via holes are formed by mechanical processing, methods such as milling, drilling, and routing can be used; when they are formed by laser processing, UV or CO2 laser methods can be used; when they are formed by chemical processing, the first to sixth insulating layers 411, 412, 413, 414, 415, and 416 can be opened using chemicals including aminosilane, ketones, etc.

[0222] On the other hand, laser processing is a cutting method that focuses optical energy on the surface to melt and vaporize part of the material, resulting in the desired shape. It can easily process complex shapes created by computer programs, and can also process composite materials that are difficult to cut using other methods.

[0223] The laser processing drill is preferably a YAG (Yttrium Aluminum Garnet) laser, a CO2 laser, or an ultraviolet (UV) laser. The YAG laser is a laser that can process both the copper foil layer and the insulating layer, while the CO2 laser is a laser that can process only the insulating layer.

[0224] As described above, the first to sixth vias 441, 442, 443, 444, 445, and 446 are formed by filling via holes formed by laser processing with a metal material, which limits the minimum width of via holes that can be formed by laser processing. Therefore, the first to sixth vias 441, 442, 443, 444, 445, and 446 may have widths ranging from 50 μm to 400 μm. For example, the first to sixth vias 441, 442, 443, 444, 445, and 446 may have widths ranging from 70 μm to 500 μm.

[0225] Meanwhile, the seventh and eighth vias 447 and 448 are disposed in the seventh and eighth insulating layers 421 and 422, which are made of a photosensitive insulating resin. The seventh and eighth insulating layers 421 and 422 may be formed by exposing and developing the photosensitive insulating resin to form via holes, and then filling the formed via holes with a metal material. The seventh and eighth vias 447 and 448 may have a second width W2. Preferably, the seventh and eighth vias 447 and 448 may have a second width W2 that is smaller than the third width W3. Preferably, the via holes formed in the first to sixth insulating layers may be larger than the via holes formed in the seventh and eighth insulating layers. Preferably, the seventh and eighth vias 447 and 448 may have a width ranging from 15 μm to 50 μm. For example, the seventh and eighth vias 447 and 448 may have a width ranging from 20 μm to 35 μm.

[0226] In addition, an eighth circuit pattern 438 disposed on the upper surface of the seventh insulating layer 421 and a ninth circuit pattern 439 disposed on the lower surface of the eighth insulating layer 422 may have a first line width. The first to seventh circuit patterns 431, 432, 433, 434, 435, 436, and 437 disposed on the surfaces of the first to sixth insulating layers 411, 412, 413, 414, 415, and 416 may have a second line width greater than the first line width.

[0227] That is, on the surfaces of the seventh and eighth insulating layers 421 and 422 made of photosensitive insulating resin, it is possible to form finer circuit patterns than the circuit patterns formed on the surfaces of the first to sixth insulating layers 411, 412, 413, 414, 415 and 416.

[0228] On the other hand, the seventh insulating layer 421 and the eighth insulating layer 422 have a first opening OR1 and a second opening OR2 formed therein. The first opening OR1 and the second opening OR2 may be formed simultaneously with via holes formed in the seventh insulating layer 421 and the eighth insulating layer 422 to form the seventh and eighth vias 447 and 448.

[0229] The area exposed through the first opening OR1 and the second opening OR2 may have a width in the range of 500 μm to 8000 μm, that is, the first opening OR1 and the second opening OR2 may have a width smaller than the width of the cavity formed by the laser in the comparative example.

[0230] Meanwhile, a protective layer 450 is disposed on the upper surface of the seventh insulating layer 421 and / or the lower surface of the eighth insulating layer 422. The protective layer 450 can protect the surface of the seventh insulating layer 421 and / or the surface of the eighth insulating layer 422 and the surface of the eighth circuit pattern 438 and / or the surface of the ninth circuit pattern 439.

[0231] In this case, although the protective layer PL is illustrated as being disposed only on the lower surface of the eighth insulating layer 422 in the drawings, the present invention is not limited to this. The protective layer PL may also be disposed on the upper surface of the seventh insulating layer 421, or alternatively, may be omitted without being disposed on the eighth insulating layer 422 either.

[0232] The protective layer PL may include an insulating material. The protective layer PL may include various materials that can be applied to protect the surface of the circuit pattern and then cured by heating. The protective layer PL may be a resist layer. For example, the protective layer PL may be a solder resist layer including an organic polymer material. For example, the protective layer PL may include an epoxy acrylate resin. More specifically, the protective layer PL may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. However, embodiments are not limited thereto, and the protective layer PL may be any one of a photo solder resist layer, a coverlay, and a polymer material.

[0233] The protective layer PL may have a thickness of 1 μm to 20 μm. The protective layer PL may have a thickness of 1 μm to 15 μm. For example, the protective layer PL may have a thickness of 5 μm to 20 μm. If the thickness of the protective layer PL exceeds 20 μm, the thickness of the printed circuit board increases. If the thickness of the protective layer PL is less than 1 μm, the reliability of the circuit pattern decreases.

[0234] According to an embodiment of the present invention, the outermost insulating layer of a printed circuit board is made of a photoimageable dielectric (PID). A cavity, such as an opening, in which a device can be mounted is formed in the outermost insulating layer, and a package substrate is provided in which the device is mounted in the formed cavity. By embedding the device in the outermost insulating layer of the printed circuit board, the overall thickness of the package substrate can be reduced. In addition, according to the embodiment, the insulating layer in which the cavity is formed is made of a photoimageable dielectric (PID) resin, so that the cavity for mounting the element can be easily formed through exposure and development, thereby solving the reliability problem that may occur during the cavity formation.

[0235] FIG. 25 is a diagram showing a package substrate according to an embodiment. 25, a package substrate 500 has a structure in which a first element 510 and a second element 520 are disposed in a first opening OR1 and a second opening OR2 included in the printed circuit board 500 of FIG.

[0236] That is, the first lead portion 437a is exposed on the sixth insulating layer 416 through the first opening OR1. Furthermore, the second lead portion 436a is exposed on the fifth insulating layer 415 through the second opening OR2.

[0237] A first connection portion 450 is disposed on the exposed first lead portion 437a. In addition, a second connection portion 460 is disposed on the exposed second lead portion 436a.

[0238] The first connecting portion 450 and the second connecting portion 460 may have different shapes. For example, the first connecting portion 450 may have a hexahedral shape. Specifically, the cross section of the first connecting portion 450 may have a quadrilateral shape. More specifically, the cross section of the first connecting portion 450 may have a rectangular or square shape. For example, the second connecting portion 460 may have a spherical shape. The cross section of the second connecting portion 460 may have a circular shape. Alternatively, the second connecting portion 460 may have a partially or entirely rounded shape. For example, the cross section of the second connecting portion 460 may have a flat surface on one side and a curved surface on the opposite side.

[0239] The first connecting portion 450 and the second connecting portion 460 may have different sizes. The first connecting portion 450 may be smaller than the second connecting portion 460. The first connecting portion 450 and the second connecting portion 460 may have different widths.

[0240] For example, the width between the two side surfaces of one first connecting portion 450 may be smaller than the width between the two side surfaces of one second connecting portion 460 . The first element 510 is disposed on the first connection portion 450. The first connection portion 450 may include a conductive material, thereby electrically connecting the first element 510 disposed on the upper surface of the first connection portion 450 and the first lead portion 437a.

[0241] The second element 520 is disposed on the second connection part 460. The second connection part 460 may include a conductive material, thereby electrically connecting the second element 520 disposed on the upper surface of the second connection part 460 and the second lead part 436a disposed on the lower surface of the second connection part 460.

[0242] The first element 510 and the second element 520 may be electronic components such as chips, which can be classified as active elements or passive elements. The active element is an element that actively utilizes nonlinear characteristics, while the passive element is an element that does not utilize nonlinear characteristics even if it has both linear and nonlinear characteristics. The passive element may include a transistor, an IC semiconductor chip, etc., and may include a capacitor, a resistor, an inductor, etc. The passive element is typically mounted on a printed circuit board to increase the signal processing speed of the semiconductor chip, which is an active element, or to perform filtering functions.

[0243] For example, the first element 510 may be an inductor or a low noise amplifier (LNA) for filtering, and the second element 520 may be a power amplifier (PA).

[0244] As described above, in the embodiment, at least a portion of the first element 510 and the second element 520 are disposed within the first opening OR1 and the second opening OR2 of the seventh insulating layer 421 and the eighth insulating layer 422 made of the photosensitive insulating resin, thereby reducing the overall thickness of the package substrate.

[0245] Meanwhile, an outer lead (not shown), which is a part of the ninth circuit pattern, may be exposed through an opening in the protective layer PL on the lower surface of the eighth insulating layer 422. The third connection part 170 is disposed on the outer lead. The third connection part 170 may be, for example, a solder ball, but is not limited thereto. The third connection part 450 may electrically connect the package substrate 500 to another external substrate.

[0246] Hereinafter, the manufacturing process of the printed circuit board shown in FIG. 24 will be described in detail. 26 to 30 are diagrams for explaining the manufacturing process of the printed circuit board shown in FIG. 24 in order.

[0247] 26, the inner layer of the printed circuit board is formed. Here, the inner layer refers to the board in a state before the seventh insulating layer 421 and the eighth insulating layer 422, which constitute the outermost layer of the printed circuit board 400, are laminated.

[0248] To this end, a first insulating layer 411 may be prepared first, and then a first circuit pattern 431 and a second circuit pattern 432 may be formed on the surface of the first insulating layer 411 . In addition, a first via 441 may be formed in the first insulating layer 411 to penetrate the first insulating layer 411 and electrically connect the first circuit pattern 431 and the second circuit pattern 432 .

[0249] Thereafter, a second insulating layer 412 may be formed on the first insulating layer 411. A third circuit pattern 433 may be formed on the second insulating layer 412. Also, a second via 442 may be formed through the second insulating layer 412 to electrically connect the third circuit pattern 433 and the first circuit pattern 431.

[0250] Thereafter, a fourth insulating layer 414 may be formed on the second insulating layer 412, and a third insulating layer 413 may be formed under the first insulating layer 411. After the fourth insulating layer 414 and the third insulating layer 413 are formed, the processes of forming the fifth circuit pattern 435, the fourth circuit pattern 434, the fourth via 443, and the third via 443 may be performed as before.

[0251] Thereafter, a sixth insulating layer 416 may be formed on the fourth insulating layer 414, and a fifth insulating layer 415 may be formed under the third insulating layer 413. After the sixth insulating layer 416 and the fifth insulating layer 415 are formed, the processes of forming the seventh circuit pattern 437, the sixth circuit pattern 436, the sixth via 446, and the fifth via 445 may be performed as before.

[0252] Thereafter, as shown in FIG. 27, a seventh insulating layer 421 and an eighth insulating layer 422 are formed on the sixth insulating layer 416 and under the fifth insulating layer 415, respectively. The seventh insulating layer 421 may be the insulating layer disposed at the top of the multiple insulating layers that make up the printed circuit board 400.

[0253] The eighth insulating layer 422 may be the insulating layer disposed at the bottom of the multiple insulating layers that make up the printed circuit board 400. In this case, the seventh insulating layer 421 and the eighth insulating layer 422 may include a photosensitive insulating resin.

[0254] When the seventh insulating layer 421 and the eighth insulating layer 422 contain a photosensitive insulating resin, a protective layer such as a solder resist that is generally disposed on the outermost side of a printed circuit board can be selectively removed.

[0255] In this case, the seventh insulating layer 421 and the eighth insulating layer 422 may be attached on the fifth insulating layer 415 and the sixth insulating layer 416 in the form of a film. 28, via holes, a first opening OR1, and a second opening OR2 may be formed in the seventh insulating layer 421 and the eighth insulating layer 422 through an exposure and development process.

[0256] As a result, the seventh insulating layer 421 and the eighth insulating layer 422 include the first opening OR1 and the second opening OR2, respectively. The seventh insulating layer 421 includes a first opening OR1. The first opening OR1 may be formed by opening the seventh insulating layer 421 in a region where a first element (described later) is to be disposed. Preferably, the first opening OR1 may expose a first lead portion 437a of a circuit pattern 437 disposed on the sixth insulating layer 416, the first lead portion 437a being disposed in a region where the first element is to be mounted.

[0257] The eighth insulating layer 422 includes a second opening OR2. The second opening OR2 may be formed by opening the eighth insulating layer 422 in a region where a second element (described later) is to be disposed. Preferably, the second opening OR2 may expose a second lead portion 436a of the circuit pattern 436 disposed under the fifth insulating layer 415, the second lead portion 436a being disposed in a region where the second element is to be mounted.

[0258] In this case, the first opening OR1 and the second opening OR2 can be formed by exposing and developing the seventh insulating layer 421 and the eighth insulating layer 422. That is, in the comparative example, a laser drilling process was generally performed to form cavities on the insulating layer. As a result, in the comparative example, the laser drilling could damage the insulating layer or the circuit pattern layer, and accurate positioning was difficult.

[0259] On the other hand, in this embodiment, the seventh insulating layer 421 and the eighth insulating layer 422, which are arranged on the outermost sides, are made of a photosensitive insulating resin, so that the first opening OR1 and the second opening OR2 can be formed in the seventh insulating layer 421 and the eighth insulating layer 422 by an exposure and development process. The first opening OR1 and the second opening OR2 may then be cavities for mounting the first element and the second element on the first lead portion 437a and the second lead portion 436a.

[0260] As described above, in the embodiment, the outermost insulating layer is made of a photosensitive insulating resin, and a cavity for mounting a device is formed in the photosensitive insulating resin by performing exposure and development, etc., thereby solving various reliability problems that arise during the cavity formation process, and by allowing a device to be mounted in the cavity, the overall thickness of the package substrate can be reduced by the depth of the cavity.

[0261] Next, as shown in FIG. 29, seventh vias 447 and eighth vias 448 are formed to fill the insides of the via holes, and eighth circuit patterns 438 and ninth circuit patterns 439 are formed on the surfaces of the seventh insulating layer 421 and the eighth insulating layer 422, respectively.

[0262] Meanwhile, as described above, the first to sixth vias 441, 442, 443, 444, 445, and 446 are formed by filling the interior of via holes formed by laser processing with a metal material, and therefore there is a limit to the minimum width that can be formed by laser processing. Therefore, the first to sixth vias 441, 442, 443, 444, 445, and 446 may have a width of 50 μm to 500 μm. For example, the first to sixth vias 441, 442, 443, 444, 445, and 446 may have a width in the range of 70 μm to 400 μm.

[0263] Meanwhile, the seventh and eighth vias 447 and 448 are disposed in the seventh and eighth insulating layers 421 and 422, which are made of a photosensitive insulating resin. The seventh and eighth insulating layers 421 and 422 may be formed by exposing and developing the photosensitive insulating resin to form via holes, and then filling the formed via holes with a metal material. The seventh and eighth vias 447 and 448 may have a second width W2. Preferably, the seventh and eighth vias 447 and 448 may have a second width W2 that is smaller than the third width W3. Preferably, the via holes formed in the first to sixth insulating layers may be larger than the via holes formed in the seventh and eighth insulating layers. Preferably, the seventh and eighth vias 447 and 448 may have a width ranging from 15 μm to 50 μm. For example, the seventh and eighth vias 447 and 448 may have a width ranging from 20 μm to 35 μm.

[0264] In addition, an eighth circuit pattern 438 disposed on the upper surface of the seventh insulating layer 421 and a ninth circuit pattern 439 disposed on the lower surface of the eighth insulating layer 422 may have a first line width. The first to seventh circuit patterns 431, 432, 433, 434, 435, 436, and 437 disposed on the surfaces of the first to sixth insulating layers 411, 412, 413, 414, 415, and 416 may have a second line width greater than the first line width.

[0265] That is, on the surfaces of the seventh and eighth insulating layers 421 and 422 made of photosensitive insulating resin, it is possible to form finer circuit patterns than the circuit patterns formed on the surfaces of the first to sixth insulating layers 411, 412, 413, 414, 415 and 416.

[0266] In addition, the area exposed through the first opening OR1 and the second opening OR2 may have a width in the range of 500 μm to 8000 μm, that is, the first opening OR1 and the second opening OR2 may have a width smaller than the width of the cavity formed by the laser in the comparative example.

[0267] Meanwhile, a protective layer 450 is disposed on the upper surface of the seventh insulating layer 421 and / or the lower surface of the eighth insulating layer 422. The protective layer 450 can protect the surface of the seventh insulating layer 421 and / or the surface of the eighth insulating layer 422 and the surface of the eighth circuit pattern 438 and / or the surface of the ninth circuit pattern 439.

[0268] In this case, although the protective layer PL is illustrated as being disposed only on the lower surface of the eighth insulating layer 422 in the drawings, the present invention is not limited to this. The protective layer PL may also be disposed on the upper surface of the seventh insulating layer 421, or alternatively, may be omitted without being disposed on the eighth insulating layer 422 either.

[0269] The protective layer PL may include an insulating material. The protective layer PL may include various materials that can be applied to protect the surface of the circuit pattern and then cured by heating. The protective layer PL may be a resist layer. For example, the protective layer PL may be a solder resist layer including an organic polymer material. For example, the protective layer PL may include an epoxy acrylate resin. More specifically, the protective layer PL may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. However, embodiments are not limited thereto, and the protective layer PL may be any one of a photo solder resist layer, a coverlay, and a polymer material.

[0270] The protective layer PL may have a thickness of 1 μm to 20 μm. The protective layer PL may have a thickness of 1 μm to 15 μm. For example, the protective layer PL may have a thickness of 5 μm to 20 μm. If the thickness of the protective layer PL exceeds 20 μm, the thickness of the printed circuit board increases. If the thickness of the protective layer PL is less than 1 μm, the reliability of the circuit pattern decreases.

[0271] Next, as shown in FIG. 30, a first connecting portion 450 and a second connecting portion 460 may be formed on the first lead portion 437a and the second lead portion 436a, respectively. The first element 510 can be mounted on the first lead portion 437a using the first connection portion 450.

[0272] In addition, the second element 510 can be mounted on the second lead portion 436a using the second connection portion 460. On the other hand, the outer leads are exposed through the protective layer PL, and the third connection parts 170 are disposed on the outer leads.

[0273] FIG. 31 is a diagram showing a printed circuit board according to a fifth embodiment. Before describing FIG. 31, the same reference numerals as in FIG. 24 indicate the same components, and descriptions that overlap with the fourth embodiment will be omitted.

[0274] The printed circuit board shown in FIG. 31 further includes adhesive insulating layers 481 and 482 compared to the printed circuit board shown in FIG. Preferably, a first adhesive insulating layer 481 is disposed between the sixth insulating layer 416 and the seventh insulating layer 421.

[0275] In addition, a second adhesive insulating layer 482 is disposed between the fifth insulating layer 415 and the eighth insulating layer 422. Preferably, the first adhesive insulating layer 481 and the second adhesive insulating layer 482 are disposed between the prepreg and the photosensitive insulating resin, thereby solving the adhesive strength problem caused by the difference in physical properties between the photosensitive insulating resin and the prepreg.

[0276] For this purpose, the first adhesive insulating layer 481 and the second adhesive insulating layer 482 are made of a thermosetting resin, which can increase the adhesive strength between the prepreg and the photosensitive insulating resin.

[0277] In this case, the thermosetting resin constituting the first adhesive insulating layer 481 and the second adhesive insulating layer 482 can be any known substance without any restrictions as long as it is a resin that hardens when heated, and examples that can be used include urea resin, melamine resin, bismaleimide resin, polyurethane resin, resin having a benzoxazine ring, cyanate ester resin, bisphenol S type epoxy resin, bisphenol F type epoxy resin, and copolymer epoxy resin of bisphenol S and bisphenol F.

[0278] As a result, in Figure 24, the sixth via 446 is arranged to penetrate only the sixth insulating layer 416, but according to Figure 31, the sixth via 446 is arranged to penetrate the sixth insulating layer 416 and the first adhesive insulating layer 481.

[0279] Also, in Figure 24, the fifth via 445 is arranged to penetrate only the fifth insulating layer 415, but according to Figure 31, the fifth via 445 is arranged to penetrate the fifth insulating layer 415 and the second adhesive insulating layer 482.

[0280] That is, each of the fifth insulating layer 415 and the sixth insulating layer 416 in FIG. 31 can have a two-layer structure including a first adhesive insulating layer 481 and a second adhesive insulating layer 482, rather than a single-layer structure.

[0281] According to this embodiment, an additional insulating layer of a different material is disposed between the outermost insulating layer and the inner insulating layer, and the additional insulating layer may be made of a thermosetting insulating resin. When the prepreg (PPG) constituting the inner insulating layer and the PID (photosensitive insulating resin) constituting the outermost insulating layer come into direct contact with each other, the adhesive strength between the prepreg and the photosensitive insulating resin may be reduced due to the difference in physical properties between them. Therefore, in the embodiment, a thermosetting insulating resin is additionally disposed between the photosensitive insulating resin and the prepreg to increase the adhesive strength between the photosensitive insulating resin and the prepreg, thereby improving the reliability of the product.

[0282] Meanwhile, although not shown in the drawing, in order to maximize adhesive strength and improve reliability, the adhesive insulating layer and the first and second pads shown in Fig. 30 may be formed simultaneously. In this case, the first pad is disposed on the first adhesive insulating layer, and the second pad is disposed on the second adhesive insulating layer.

[0283] FIG. 32 is a diagram showing a printed circuit board according to a sixth embodiment. Before describing FIG. 32, the same reference numerals as in FIG. 24 indicate the same components, and descriptions that overlap with the fourth embodiment will be omitted.

[0284] 32, a first pad 491 is disposed on the upper surface of the sixth insulating layer 416 in a region where the first opening OR1 is formed. That is, the first pad 491 is formed in a region outside the first opening OR1. Preferably, the first pad 491 is disposed surrounding the periphery of the region where the first opening OR1 is formed. That is, the first pad 491 is disposed on a boundary region of a cavity in which the first element 510 is mounted. For example, the first pad 491 is disposed on a boundary region between the region where the first opening OR1 is formed and the other region.

[0285] As a result, the first pad 491 is disposed outside the first lead portion 437a exposed by the first opening OR1. For example, the first pad 491 is disposed surrounding the periphery of the first lead portion 437a exposed by the first opening OR1.

[0286] Furthermore, a second pad 492 is disposed on the lower surface of the fifth insulating layer 415 in a region where the second opening OR2 is formed. That is, the second pad 492 is formed in a region outside the second opening OR2. Preferably, the second pad 492 is disposed surrounding the periphery of the region where the second opening OR2 is formed. That is, the second pad 492 is disposed on a boundary region of a cavity in which the second element 520 is mounted. Here, the boundary region of the cavity may be a region where the inner wall of the cavity is located. For example, the second pad 492 is disposed on a boundary region between the region where the second opening OR2 is formed and the other region.

[0287] As a result, the second pad 492 is disposed outside the second lead portion 436a exposed by the second opening OR2. For example, the second pad 492 is disposed surrounding the periphery of the second lead portion 436a exposed by the second opening OR2.

[0288] The first pad 491 and the second pad 492 may be made of a metal material. Preferably, the first pad 491 and the second pad 492 may be made of the same metal material as the circuit pattern. More preferably, the first pad 491 and the second pad 492 are formed together with the seventh circuit pattern 437. Therefore, the first pad 491 and the second pad 492 may be made of a metal material having high electrical conductivity. To this end, the first pad 491 and the second pad 492 may be made of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the first pad 491 and the second pad 492 may be made of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0289] FIG. 33 is a plan view of the pad of FIG. FIG. 33 shows the structure above the sixth insulating layer 416 in a state where the seventh insulating layer 421 has been removed from FIG.

[0290] 33, a region where a first opening OR1 is to be formed exists on the sixth insulating layer 416. The region where the first opening OR1 is to be formed may refer to a region of the upper surface of the sixth insulating layer 416 that vertically overlaps with the first opening OR1 formed on the seventh insulating layer 421.

[0291] A first pad 491 is disposed on the upper surface of the sixth insulating layer 416 in a region that vertically overlaps the inner wall of the first opening OR1. Although not shown in FIG. 33, a second pad 492 is arranged in a region of the lower surface of the fifth insulating layer 415 that vertically overlaps the inner wall of the second opening OR2, similar to the first pad 491.

[0292] At this time, at least a portion of the first pad 491 may overlap the first opening OR1. Accordingly, the first pad 491 may include a first portion 491a disposed on the upper surface of the sixth insulating layer 416 and covered by the seventh insulating layer 421. The first pad 491 may also include a second portion 491b exposed through a first opening OR1 of the seventh insulating layer 421. That is, the first portion 491a of the first pad 491 may be covered by the seventh insulating layer 421, and the remaining second portion 491b excluding the first portion 491a may be exposed through the first opening OR1.

[0293] Similarly, although not shown in the drawing, the second pad 492 may include a first portion disposed on the lower surface of the fifth insulating layer 415 and covered by the eighth insulating layer 422, and a second portion exposed through the second opening OR2 of the eighth insulating layer 422.

[0294] According to the above-described embodiment of the present invention, a pad is disposed on the boundary region of a cavity on an inner insulating layer. The pad is disposed surrounding the periphery of the region where the cavity is formed. In this case, if the pad is not present, an undercut may occur in the lower region of the photosensitive insulating resin on the boundary region of the cavity, which may result in delamination between the inner insulating layer and the outermost insulating layer. Therefore, in this embodiment, by disposing the pad on the boundary region of the cavity, the undercut problem, which is a cause of reliability, can be resolved, thereby improving product reliability.

[0295] 33, the first pad 491 and the second pad 492 may have a closed loop shape surrounding the periphery of the open area opened by the first opening and the second opening. In this case, the first pad 491 and the second pad 492 may have a rectangular shape, but are not limited thereto.

[0296] FIG. 34 is a diagram showing a modified example of the pad according to the embodiment. As shown in FIG. 34(a), the first pad 491 and the second pad 492 may have a circular shape instead of a square shape.

[0297] Also, as shown in FIG. 34(b), the first pad 491 and the second pad 492 may have a polygonal shape, for example, a hexagonal shape. In addition to the shape shown in FIG. 34, the first pad 491 and the second pad 492 can be modified into various shapes such as a triangular shape, a sector shape, a trapezoid shape, and the like.

[0298] According to an embodiment of the present invention, an outermost insulating layer of a printed circuit board is made of a photoimageable dielectric (PID). A cavity in which a device can be mounted is formed in the outermost insulating layer, and a package substrate is provided in which the device is mounted in the formed cavity. Since the device is embedded in the outermost insulating layer of the printed circuit board, the overall thickness of the package substrate can be reduced. Furthermore, according to an embodiment, by forming the insulating layer in which the cavity is formed using a photoimageable dielectric (PID), the cavity for mounting the device can be easily formed through exposure and development, thereby resolving reliability issues that may arise during cavity formation.

[0299] According to an embodiment of the present invention, an additional insulating layer made of a different material is disposed between the outermost insulating layer and the inner insulating layer. The additional insulating layer may be made of a thermosetting insulating resin. Here, if a prepreg (PPG) constituting the inner insulating layer and a PID (photosensitive insulating resin) constituting the outermost insulating layer come into direct contact with each other, the adhesive strength between the prepreg and the photosensitive insulating resin may be reduced due to differences in physical properties between the prepreg and the photosensitive insulating resin. Therefore, in this embodiment, a thermosetting insulating resin is additionally disposed between the photosensitive insulating resin and the prepreg to increase the adhesive strength between the photosensitive insulating resin and the prepreg, thereby improving product reliability.

[0300] According to another embodiment of the present invention, a pad is disposed on the inner insulating layer in a boundary region of the cavity, the pad being disposed so as to surround the periphery of the region in which the cavity is formed. In this case, if the pad is not present, an undercut occurs in the lower region of the photosensitive insulating resin on the boundary region of the cavity, which may cause a problem of delamination between the inner insulating layer and the outermost insulating layer. Therefore, in the embodiment, by disposing the pad on the boundary region of the cavity, the undercut problem that weakens reliability can be solved, thereby improving the reliability of the product.

Claims

1. a first insulating layer; a second insulating layer disposed on the first insulating layer; a cavity formed in the first and second insulating layers; the cavity includes a first portion formed in the second insulating layer and a second portion formed in the first insulating layer; the first portion has a first cross-sectional shape; The second portion has a second cross-sectional shape different from the first cross-sectional shape.

2. the second insulating layer includes a photosensitive insulating resin; The printed circuit board according to claim 1 , wherein the first insulating layer comprises a non-photosensitive insulating resin.

3. the first portion has a first depth; The printed circuit board of claim 1 , wherein the second portion has a second depth that is greater than the first depth.

4. a first circuit pattern embedded in the first insulating layer; the first depth corresponds to a thickness of the second insulating layer; The printed circuit board of claim 3 , wherein the second depth corresponds to a thickness of the first circuit pattern.

5. the first cross-sectional shape includes a trapezoidal shape, The printed circuit board of claim 1 , wherein the second cross-sectional shape comprises a square shape.

6. a first via penetrating the first insulating layer; a second via that penetrates the second insulating layer; the first cross-sectional shape corresponds to a cross-sectional shape of the first via; The printed circuit board of claim 4 , wherein the second cross-sectional shape corresponds to a cross-sectional shape of the first circuit pattern.

7. an adhesive insulating layer disposed between the first insulating layer and the second insulating layer; The printed circuit board of claim 2 , wherein the adhesive insulating layer comprises a different insulating material than the first insulating layer and the second insulating layer.

8. The printed circuit board of claim 7 , wherein the adhesive insulating layer comprises a thermosetting resin.

9. a first insulating layer; a second insulating layer disposed on the first insulating layer; a first circuit pattern embedded in a lower portion of the first insulating layer, the lower surface of the first circuit pattern being flush with the lower surface of the first insulating layer; a cavity formed at a first depth in a lower surface of the first insulating layer; the first depth corresponds to a thickness of the first circuit pattern; A printed circuit board, wherein the cross-sectional shape of the cavity corresponds to the cross-sectional shape of the first circuit pattern.

10. a first insulating layer; a first circuit pattern disposed on an upper surface of the first insulating layer; a second insulating layer disposed on the upper surface of the first insulating layer to cover the first circuit pattern, the second insulating layer having a cavity formed therein; the second insulating layer includes a first insulating part disposed on an upper surface of the first insulating layer, and a second insulating part disposed on an upper surface of the first insulating part and having the cavity formed therein; the second insulating part includes a photosensitive insulating resin, The cavity is disposed through the second insulating part of the printed circuit board.

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