Pixel driving circuit and driving method therefor, display apparatus, and signal processing method

Abstract

A pixel driving circuit and a driving method therefor, a display apparatus, and a signal processing method. The pixel driving circuit comprises: a third control sub-circuit. The third control sub-circuit is configured to, under the control of signals of at least one reset signal line (Reset) and at least one signal line among a dynamic signal line (Var) and an auxiliary signal line (Vx), adjust signals of a third node (N3) and a fourth node (N4). In at least one display frame, the start time of at least one time period in which a first control unit provides an effective level signal to a second light-emitting signal line (EM2) is earlier than or equal to the start time of a second control unit providing an invalid level signal to at least one reset signal line (Reset).

Description

[0001] The present application claims priority to PCT International Application No. PCT / CN2023 / 113514 filed on August 17, 2023 and entitled "Pixel Driving Circuit and Driving Method Therefor, and Display Apparatus" and PCT International Application No. PCT / CN2024 / 097840 filed on June 6, 2024 and entitled "Pixel Driving Circuit and Driving Method Therefor, Display Apparatus, and Signal Processing Method", the contents of which should be construed as being incorporated herein by reference.Technical Field

[0002] The present disclosure relates to, but is not limited to, the field of display technologies, and particularly relates to a pixel driving circuit and a driving method therefor, a display apparatus, and a signal processing method.Background

[0003] An organic light emitting diode (OLED) and a quantum dot light emitting diode (QLED) are active light emitting display devices and have advantages of self-illumination, a wide viewing angle, a high contrast ratio, low power consumption, an extremely high reaction speed, lightness and thinness, flexibility, and a low cost, etc. With constant development of display technologies, a flexible display apparatus (Flexible Display) in which the OLED or QLED is used as the light emitting device and signal control is performed through a thin film transistor (TFT) has become a mainstream product in the field of display at present.Summary

[0004] The following is a summary of subject matter described in detail in the present application. This summary is not intended to limit the protection scope of claims.

[0005] In a first aspect, the present disclosure provides a pixel driving circuit provided in a display apparatus, including: a driving sub-circuit, a storage sub-circuit, a first control sub-circuit, a second control sub-circuit, and a third control sub-circuit.

[0006] The driving sub-circuit is electrically connected to a first node, a second node, and a third node respectively, and configured to provide a driving current to the third node under control of signals of the first node and the second node.

[0007] The storage sub-circuit is electrically connected to the first node and the third node, respectively, and configured to store a voltage difference between signals of the first node and the third node.

[0008] The first control sub-circuit is electrically connected to a first scan signal line, a second scan signal line, a data signal line, a reference signal line and the first node, respectively, and configured to provide a signal of the data signal line or the reference signal line to the first node under control of signals of the first scan signal line and the second scan signal line.

[0009] The second control sub-circuit is electrically connected to a first light emitting signal line, a second light emitting signal line, a first power supply line, the second node, the third node and a fourth node, respectively, and configured to provide a signal of the first power supply line to the second node and provide a signal of the third node to the fourth node under control of signals of the first light emitting signal line and the second light emitting signal line.

[0010] The third control sub-circuit is electrically connected to the third node, the fourth node, at least one reset signal line, and at least one signal line of a dynamic signal line and an auxiliary signal line, respectively, and configured to adjust signals of the third node and the fourth node under control of signals of the at least one reset signal line and the at least one signal line of the dynamic signal line and the auxiliary signal line.

[0011] The display apparatus includes: a first control unit, a second control unit, and a data unit, wherein the first control unit is electrically connected to the second light emitting signal line and configured to provide a signal to the second light emitting signal line, the second control unit is electrically connected to the at least one reset signal line and configured to provide a signal to the at least one reset signal line, and the data unit is electrically connected to the dynamic signal line and configured to provide a signal to the dynamic signal line.

[0012] Content displayed by the display apparatus includes at least one display frame in which a start time of at least one time period in which the first control unit provides an effective level signal to the second light emitting signal line is earlier than or equal to a start time at which the second control unit provides an ineffective level signal to the at least one reset signal line.

[0013] In an exemplary embodiment, a voltage value of a signal of the dynamic signal line includes a plurality of voltage values, and a voltage value of a dynamic signal provided by the data unit to the dynamic signal line is positively correlated with a temperature of the display apparatus at at least some moments of the at least one display frame.

[0014] In an exemplary embodiment, the at least one reset signal line includes: a third reset signal line; the third control sub-circuit is electrically connected with the third node, the fourth node, the third reset signal line and the dynamic signal line, respectively.

[0015] In an exemplary embodiment, the third control sub-circuit includes a second capacitor and an eighth transistor.

[0016] A first terminal of the second capacitor is electrically connected to the third node, and a second terminal of the second capacitor is electrically connected to the fourth node.

[0017] A control electrode of the eighth transistor is electrically connected to the third reset signal line, a first electrode of the eighth transistor is electrically connected to the dynamic signal line, and a second electrode of the eighth transistor is electrically connected to the fourth node.

[0018] In an exemplary embodiment, the display apparatus further includes: a third control unit electrically connected to the first light emitting signal line and configured to provide a signal to the first light emitting signal line.

[0019] In the at least one display frame, the start time of the at least one time period in which the first control unit provides the effective level signal to the second light emitting signal line is earlier than a start time at which the second control unit provides an ineffective level signal to the third reset signal line, and a start time of at least one time period in which the third control unit provides an effective level signal to the first light emitting signal line is later than the start time at which the second control unit provides the ineffective level signal to the third reset signal line.

[0020] In an exemplary embodiment, the at least one reset signal line includes: a first reset signal line and a third reset signal line.

[0021] The third control sub-circuit is electrically connected to the third node, the fourth node, the first reset signal line, the third reset signal line and the dynamic signal line, respectively.

[0022] In an exemplary embodiment, the third control sub-circuit includes: a second capacitor, a sixth transistor, and an eighth transistor.

[0023] A first terminal of the second capacitor is electrically connected to the third node, and a second terminal of the second capacitor is electrically connected to a fifth node.

[0024] A control electrode of the sixth transistor is electrically connected to the first reset signal line, a first electrode of the sixth transistor is electrically connected to the fifth node, and a second electrode of the sixth transistor is electrically connected to the fourth node.

[0025] A control electrode of the eighth transistor is electrically connected to the third reset signal line, a first electrode of the eighth transistor is electrically connected to the dynamic signal line, and a second electrode of the eighth transistor is electrically connected to the fourth node.

[0026] In an exemplary embodiment, the third control sub-circuit includes: a second capacitor, a third capacitor, a sixth transistor, and an eighth transistor.

[0027] A first terminal of the second capacitor is electrically connected to the third node, and a second terminal of the second capacitor is electrically connected to a fifth node.

[0028] A first terminal of the third capacitor is electrically connected to the fifth node, and a second terminal of the third capacitor is electrically connected to the fourth node.

[0029] A control electrode of the sixth transistor is electrically connected to the first reset signal line, a first electrode of the sixth transistor is electrically connected to the fifth node; a second electrode of the sixth transistor is electrically connected to the fourth node.

[0030] A control electrode of the eighth transistor is electrically connected to the third reset signal line, a first electrode of the eighth transistor is electrically connected to the dynamic signal line, and a second electrode of the eighth transistor is electrically connected to the fourth node.

[0031] In an exemplary embodiment, the at least one reset signal line includes: a first reset signal line and a third reset signal line.

[0032] The third control sub-circuit is electrically connected to the third node, the fourth node, the first reset signal line, the third reset signal line, the dynamic signal line and the auxiliary signal line, respectively.

[0033] In an exemplary embodiment, the third control sub-circuit includes: a second capacitor, a third capacitor, a sixth transistor, and an eighth transistor.

[0034] A first terminal of the second capacitor is electrically connected to the third node, and a second terminal of the second capacitor is electrically connected to a fifth node.

[0035] A first terminal of the third capacitor is electrically connected to the fifth node, and a second terminal of the third capacitor is electrically connected to the auxiliary signal line.

[0036] A control electrode of the sixth transistor is electrically connected to the first reset signal line, a first electrode of the sixth transistor is electrically connected to the fifth node, and a second electrode of the sixth transistor is electrically connected to the fourth node.

[0037] A control electrode of the eighth transistor is electrically connected to the third reset signal line, a first electrode of the eighth transistor is electrically connected to the dynamic signal line, and a second electrode of the eighth transistor is electrically connected to the fourth node.

[0038] In an exemplary embodiment, the at least one reset signal line includes: a first reset signal line and a third reset signal line.

[0039] The third control sub-circuit is electrically connected to the third node, the fourth node, the first reset signal line, the third reset signal line and the auxiliary signal line, respectively.

[0040] In an exemplary embodiment, the third control sub-circuit includes: a second capacitor, a third capacitor, a sixth transistor, and a ninth transistor.

[0041] A first terminal of the second capacitor is electrically connected to the third node, and a second terminal of the second capacitor is electrically connected to a fifth node.

[0042] A first terminal of the third capacitor is electrically connected to the fifth node, and a second terminal of the third capacitor is electrically connected to the fourth node.

[0043] A control electrode of the sixth transistor is electrically connected to the first reset signal line, a first electrode of the sixth transistor is electrically connected to the fifth node, and a second electrode of the sixth transistor is electrically connected to the fourth node.

[0044] A control electrode of the ninth transistor is electrically connected to the third reset signal line, a first electrode of the ninth transistor is electrically connected to the auxiliary signal line, and a second electrode of the ninth transistor is electrically connected to the fifth node.

[0045] In an exemplary embodiment, the display apparatus further includes: a third control unit electrically connected to the first light emitting signal line and configured to provide a signal to the first light emitting signal line, the second control unit includes: a first sub-control unit electrically connected to the first reset signal line and configured to provide a signal to the first reset signal line, and a second sub-control unit electrically connected to the third reset signal line and configured to provide a signal to the third reset signal line.

[0046] In the at least one display frame, at least one of a start time at which the first sub-control unit provides an ineffective level signal to the first reset signal line and a start time at which the second sub-control unit provides an ineffective level signal to the third reset signal line is later than the start time of the at least one time period in which the first control unit provides the effective level signal to the second light emitting signal line and is earlier than a start time of at least one time period in which the third control unit provides an effective level signal to the first light emitting signal line, and the start time at which the first sub-control unit provides the ineffective level signal to the first reset signal line is earlier than the start time at which the second sub-control unit provides the ineffective level signal to the third reset signal line.

[0047] In an exemplary embodiment, the at least one reset signal line includes: a first reset signal line, a third reset signal line, and a fourth reset signal line.

[0048] The third control sub-circuit is electrically connected to the third node, the fourth node, the first reset signal line, the third reset signal line, the fourth reset signal line, the dynamic signal line and the auxiliary signal line, respectively.

[0049] In an exemplary embodiment, the third control sub-circuit includes: a second capacitor, a third capacitor, a sixth transistor, an eighth transistor, and a ninth transistor.

[0050] A first terminal of the second capacitor is electrically connected to the third node, and a second terminal of the second capacitor is electrically connected to a fifth node.

[0051] A first terminal of the third capacitor is electrically connected to the fifth node, and a second terminal of the third capacitor is electrically connected to the fourth node.

[0052] A control electrode of the sixth transistor is electrically connected to the first reset signal line, a first electrode of the sixth transistor is electrically connected to the fifth node, and a second electrode of the sixth transistor is electrically connected to the fourth node.

[0053] A control electrode of the eighth transistor is electrically connected to the third reset signal line, a first electrode of the eighth transistor is electrically connected to the dynamic signal line, and a second electrode of the eighth transistor is electrically connected to the fourth node.

[0054] A control electrode of the ninth transistor is electrically connected to the fourth reset signal line, a first electrode of the ninth transistor is electrically connected to the auxiliary signal line, and a second electrode of the ninth transistor is electrically connected to the fifth node.

[0055] In an exemplary embodiment, the display apparatus further includes: a third control unit electrically connected to the first light emitting signal line and configured to provide a signal to the first light emitting signal line, the second control unit includes a first sub-control unit, a second sub-control unit and a third sub-control unit, wherein the first sub-control unit is electrically connected to the first reset signal line and is configured to provide a signal to the first reset signal line, the second sub-control unit is electrically connected to the third reset signal line and is configured to provide a signal to the third reset signal line, the third sub-control unit is electrically connected to the fourth reset signal line and is configured to provide a signal to the fourth reset signal line.

[0056] In the at least one display frame, at least one of a start time at which the first sub-control unit provides an ineffective level signal to the first reset signal line, a start time at which the second sub-control unit provides an ineffective level signal to the third reset signal line, and a start time at which the third sub-control unit provides an ineffective level signal to the fourth reset signal line is later than the start time of the at least one time period in which the first control unit provides the effective level signal to the second light emitting signal line and earlier than a start time of at least one time period in which the third control unit provides an effective level signal to the first light emitting signal line, and the start time at which the first sub-control unit provides the ineffective level signal to the first reset signal line is earlier than at least one of the start time at which the second sub-control unit provides the ineffective level signal to the third reset signal line and the start time at which the third sub-control unit provides the ineffective level signal to the fourth reset signal line.

[0057] In an exemplary embodiment, the driving sub-circuit includes: a third transistor, the first control sub-circuit includes: a first transistor and a second transistor, the second control sub-circuit includes: a fourth transistor and a fifth transistor, and the storage sub-circuit includes: a first capacitor.

[0058] A control electrode of the first transistor is electrically connected to the first scan signal line, a first electrode of the first transistor is electrically connected to the data signal line, and a second electrode of the first transistor is electrically connected to the first node.

[0059] A control electrode of the second transistor is electrically connected to the second scan signal line, a first electrode of the second transistor is electrically connected to the reference signal line, and a second electrode of the second transistor is electrically connected to the first node.

[0060] A control electrode of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the second node, and a second electrode of the third transistor is electrically connected to the third node.

[0061] A control electrode of the fourth transistor is electrically connected to the first light emitting signal line, a first electrode of the fourth transistor is electrically connected to the first power supply line, and a second electrode of the fourth transistor is electrically connected to the second node.

[0062] A control electrode of the fifth transistor is electrically connected to the second light emitting signal line, a first electrode of the fifth transistor is electrically connected to the third node, and a second electrode of the fifth transistor is electrically connected to the fourth node.

[0063] A first terminal of the first capacitor is electrically connected to the first power supply line, and a second terminal of the first capacitor is electrically connected to the first node.

[0064] The display apparatus further includes: a fourth control unit electrically connected to the first scan signal line and configured to provide a signal to the first scan signal line, and a fifth control unit electrically connected to the second scan signal line and configured to provide a signal to the second scan signal line.

[0065] In the at least one display frame, an end time at which the fifth control unit provides an effective level signal to the second scan signal line is earlier than a start time at which the fourth control unit provides an effective level signal to the first scan signal line, and the start time at which the fourth control unit provides the effective level signal to the first scan signal line is earlier than the start time of the at least one time period in which the first control unit provides the effective level signal to the second light emitting signal line.

[0066] In an exemplary embodiment, the dynamic signal line is an initial signal line.

[0067] A signal of the auxiliary signal line is a signal of at least one signal line of the first power supply line, the reference signal line, and the initial signal line.

[0068] A signal of the auxiliary signal line is a signal of at least one signal line of the first power supply line and the reference signal line.

[0069] In a second aspect, the present disclosure further provides display apparatus including: sub-pixels arranged in an array, and at least one of the sub-pixels includes: a pixel driving circuit described above.

[0070] In an exemplary embodiment, the display apparatus further includes: a temperature sensor, a control chip, and a signal transmission component, wherein the signal transmission component includes a data unit, wherein a sub-pixel is electrically connected to the dynamic signal line.

[0071] The temperature sensor is configured to detect a first temperature signal of the display apparatus.

[0072] The control chip is electrically connected to the temperature sensor and the signal transmission component, respectively, and is configured to acquire the first temperature signal detected by the temperature sensor, obtain a voltage offset corresponding to the at least one sub-pixel according to the first temperature signal, obtain an adjusted dynamic signal corresponding to the at least one sub-pixel according to the voltage offset corresponding to the at least one sub-pixel, and transmit the adjusted dynamic signal to the signal transmission component, and is further configured to transmit a control signal to the signal transmission component.

[0073] The signal transmission component is electrically connected to the dynamic signal line and configured to provide the adjusted dynamic signal corresponding to the sub-pixel to the dynamic signal line to which the sub-pixel is connected under control of the control signal.

[0074] In an exemplary embodiment, the control chip is further configured to acquire the first temperature signal detected by the temperature sensor within a preset time interval.

[0075] In an exemplary embodiment, a correspondence table between temperatures and voltage offsets is stored in the control chip, and the control chip is further configured to obtain a second temperature signal according to the first temperature signal, and obtain the voltage offset corresponding to the at least one sub-pixel by looking up the correspondence table according to the second temperature signal, wherein the first temperature signal is an analog signal and the second temperature signal is a digital signal.

[0076] In an exemplary embodiment, the control chip is further configured to acquire a current dynamic signal of the at least one sub-pixel, and obtain the adjusted dynamic signal corresponding to the at least one sub-pixel according to the current dynamic signal of the at least one sub-pixel and the voltage offset corresponding to the at least one sub-pixel.

[0077] In an exemplary embodiment, voltage values of dynamic signals at a same temperature of at least two among a plurality of sub-pixels are same.

[0078] In an exemplary embodiment, the signal transmission component is further configured to provide the adjusted dynamic signal corresponding to the at least one sub-pixel to a dynamic signal line, to which the at least one sub-pixel is connected, in the at least one display frame under control of the control signal.

[0079] In a third aspect, the present disclosure further provides a method for driving a pixel driving circuit, used to drive a pixel driving circuit, wherein the method includes: providing, by the driving sub-circuit, a driving current to the third node under control of signals of the first node and the second node; storing, by the storage sub-circuit, the voltage difference between the signals of the first node and the third node; providing, by the first control sub-circuit, the signal of the data signal line or the reference signal line to the first node under control of signals of the first scan signal line and the second scan signal line; providing, by the second control sub-circuit, the signal of the first power supply line to the second node and the signal of the third node to the fourth node under control of signals of the first light emitting signal line and the second light emitting signal line; and adjusting, by the third control sub-circuit, signals of the third node and the fourth node under control of signals of the at least one reset signal line and at least one of the dynamic signal line and the auxiliary signal line; wherein in the at least one display frame, a start time of at least one time period in which the first control unit provides an effective level signal to the second light emitting signal line is earlier than or equal to a start time at which the second control unit provides an ineffective level signal to the at least one reset signal line.

[0080] In a fourth aspect, the present disclosure further provides a signal processing method for applied to in the above-described display apparatus. The method includes: acquiring a first temperature signal detected by a temperature sensor; obtaining a voltage offset corresponding to at least one sub-pixel according to the first temperature signal; obtaining an adjusted dynamic signal corresponding to the at least one sub-pixel according to the voltage offset corresponding to the at least one sub-pixel, and transmitting the adjusted dynamic signal to a signal transmission component, to enable the signal transmission component to provide the adjusted dynamic signal corresponding to the sub-pixel to a dynamic signal line connected to the sub-pixel under control of a control signal.

[0081] The acquiring the first temperature signal detected by the temperature sensor includes: acquiring the first temperature signal detected by the temperature sensor within a preset time interval.

[0082] The obtaining the voltage offset corresponding to the at least one sub-pixel according to the first temperature signal includes: obtaining a second temperature signal according to the first temperature signal, obtaining the voltage offset corresponding to the at least one sub-pixel by looking up a correspondence table according to the second temperature signal, wherein the first temperature signal is an analog signal and the second temperature signal is a digital signal.

[0083] The obtaining the adjusted dynamic signal corresponding to the at least one sub-pixel according to the voltage offset corresponding to the at least one sub-pixel includes acquiring a current dynamic signal of the at least one sub-pixel, and obtaining the adjusted dynamic signal corresponding to the at least one sub-pixel according to the current dynamic signal of the at least one sub-pixel and the voltage offset corresponding to the at least one sub-pixel.

[0084] Other aspects of the present disclosure may be comprehended after the drawings and the detailed descriptions are read and understood.Brief Description of Drawings

[0085] Accompanying drawings are intended to provide an understanding of technical solutions of the present application and form a part of the specification, and are used to explain the technical solutions of the present application together with embodiments of the present application, and do not constitute a limitation on the technical solutions of the present application. FIG. 1 is a schematic diagram of a structure of a pixel driving circuit according to an embodiment of the present disclosure. FIG. 2 is a first equivalent circuit diagram of a third control sub-circuit. FIG. 3 is a second equivalent circuit diagram of a third control sub-circuit. FIG. 4 is a third equivalent circuit diagram of a third control sub-circuit. FIG. 5 is a fourth equivalent circuit diagram of a third control sub-circuit. FIG. 6 is a fifth equivalent circuit diagram of a third control sub-circuit. FIG. 7 is a sixth equivalent circuit diagram of a third control sub-circuit. FIG. 8 is a partial equivalent circuit diagram of a pixel driving circuit. FIG. 9 is a first equivalent circuit diagram of the pixel driving circuit. FIG. 10 is a second equivalent circuit diagram of the pixel driving circuit. FIG. 11 is a third equivalent circuit diagram of the pixel driving circuit. FIG. 12 is a fourth equivalent circuit diagram of the pixel driving circuit. FIG. 13 is a fifth equivalent circuit diagram of the pixel driving circuit. FIG. 14 is a sixth equivalent circuit diagram of the pixel driving circuit. FIG. 15 is an operating timing diagram of the pixel driving circuits provided in FIGS. 9 and 10. FIG. 16 is a working timing diagram of the pixel driving circuit provided in FIG. 11. FIG. 17 is a working timing diagram of the pixel driving circuit provided in FIG. 12. FIG. 18 is an operating timing diagram of the pixel driving circuits provided in FIGS. 13 and 14. FIG. 19 is a schematic diagram of a structure of another pixel driving circuit according to an embodiment of the present disclosure. FIG. 20 is a schematic diagram of a structure of a display apparatus. FIG. 21 is a first schematic diagram of a structure of the pixel driving circuit provided in FIG. 19. FIG. 22A is a first equivalent circuit diagram of the pixel driving circuit provided in FIG. 21. FIG. 22B is a second equivalent circuit diagram of the pixel driving circuit provided in FIG. 21. FIG. 23 is a schematic diagram of a structure of a display apparatus in which the pixel driving circuit provided in FIG. 22 is located. FIG. 24 is a second schematic diagram of a structure of the pixel driving circuit provided in FIG. 19. FIG. 25A is a first equivalent circuit diagram of the pixel driving circuit provided in FIG. 24. FIG. 25B is a second equivalent circuit diagram of the pixel driving circuit provided in FIG. 21. FIG. 26A is a third equivalent circuit diagram of the pixel driving circuit provided in FIG. 24. FIG. 26B is a fourth equivalent circuit diagram of the pixel driving circuit provided in FIG. 24. FIG. 27 is a third schematic diagram of a structure of the pixel driving circuit provided in FIG. 19. FIG. 28A is a first equivalent circuit diagram of the pixel driving circuit provided in FIG. 27. FIG. 28B is a second equivalent circuit diagram of the pixel driving circuit provided in FIG. 27. FIG. 29 is a fourth schematic diagram of a structure of the pixel driving circuit provided in FIG. 19. FIG. 30A is a first equivalent circuit diagram of the pixel driving circuit provided in FIG. 29. FIG. 30B is a second equivalent circuit diagram of the pixel driving circuit provided in FIG. 29. FIG. 31 is a schematic diagram of a structure of a display apparatus in which the pixel driving circuits provided in FIGS. 25, 26, 28, and 30 are located. FIG. 32 is a fifth schematic diagram of a structure of the pixel driving circuit provided in FIG. 19. FIG. 33A is a first equivalent circuit diagram of the pixel driving circuit provided in FIG. 32. FIG. 33B is a second equivalent circuit diagram of the pixel driving circuit provided in FIG. 32. FIG. 34 is a schematic diagram of a structure of a display apparatus in which the pixel driving circuit provided in FIG. 33 is located. FIG. 35A is a first working timing diagram of the pixel driving circuit provided in FIG. 22A. FIG. 35B is a second working timing diagram of the pixel driving circuit provided in FIG. 22A. FIG. 36A is a first working timing diagram of the pixel driving circuit provided in FIG. 22B. FIG. 36B is a second working timing diagram of the pixel driving circuit provided in FIG. 22B. FIG. 37A is a first working timing diagram of the pixel driving circuits provided in FIGS. 25A, 26A, 28A, and 30A. FIG. 37B is a second working timing diagram of the pixel driving circuits provided in FIGS. 25A, 26A, 28A, and 30A. FIG. 38A is a first working timing diagram of the pixel driving circuits provided in FIGS. 25B, 26B, 28B, and 30B. FIG. 38B is a second working timing diagram of the pixel driving circuits provided in FIGS. 25B, 26B, 28B, and 30B. FIG. 39A is a first working timing diagram of the pixel driving circuit provided in FIG. 33A. FIG. 39B is a second working timing diagram of the pixel driving circuit provided in FIG. 33A. FIG. 40A is a first working timing diagram of the pixel driving circuit provided in FIG. 33B. FIG. 40B is a second working timing diagram of the pixel driving circuit provided in FIG. 33B. FIG. 41 is a schematic diagram of a structure of a display apparatus according to an embodiment of the present disclosure. FIG. 42 is a first schematic diagram of voltage values of dynamic signals of different sub-pixels at different temperatures. FIG. 43 is a second schematic diagram of voltage values of dynamic signals of different sub-pixels at different temperatures. FIG. 44 is a schematic diagram of variation of brightness of a light emitting device with a gray scale in at least one embodiment of the present disclosure. Detailed Description

[0086] To make objectives, technical solutions, and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It is to be noted that implementations may be implemented in multiple different forms. Those of ordinary skills in the art may easily understand such a fact that implementations and contents may be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be explained as being limited to the contents recorded in the following implementations only. The embodiments and features in the embodiments of the present disclosure may be randomly combined with each other if there is no conflict. In order to keep following description of the embodiments of the present disclosure clear and concise, detailed description of part of known functions and known components are omitted in the present disclosure. The drawings of the embodiments of the present disclosure only involve structures involved in the embodiments of the present disclosure, and for other structures, reference may be made to conventional designs.

[0087] Scales of the drawings in the present disclosure may be used as a reference in actual processes, but are not limited thereto. For example, a width-length ratio of a channel, a thickness and spacing of each film layer, and a width and spacing of each signal line may be adjusted according to actual needs. A quantity of pixels in a display substrate and a quantity of sub-pixels in each pixel are not limited to numbers shown in the drawings. The drawings described in the present disclosure are schematic structural diagrams only, and one implementation of the present disclosure is not limited to shapes, numerical values, or the like shown in the drawings.

[0088] Ordinal numerals "first", "second", "third", etc., in the specification are set not to form limits in numbers but only to avoid confusion between constituent elements.

[0089] In the specification, for convenience, expressions "central", "above", "below", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., for indicating directional or positional relationships are used to illustrate positional relationships between the constituent elements with reference to the accompanying drawings, not to indicate or imply that involved devices or elements are required to have specific orientations or are structured and operated in the specific orientations but only to easily describe the present specification and simplify the description, and thus should not be understood as limitations on the present disclosure. The positional relationships between the constituent elements may be changed as appropriate based on a direction according to which each constituent element is described. Therefore, appropriate replacements based on situations are allowed, which is not limited to the expressions in the specification.

[0090] In the specification, unless otherwise explicitly specified and defined, terms "mounting", "coupling", and "connection" should be understood in a broad sense. For example, a connection may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be a direct connection, or an indirect connection through a middleware, or an internal communication between two elements. Those of ordinary skills in the art may understand specific meanings of the above terms in the present disclosure according to specific situations.

[0091] In the specification, a transistor refers to an element that at least includes three terminals, i.e., a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and a current can flow through the drain electrode, the channel region, and the source electrode. It is to be noted that in the specification, the channel region refers to a region through which a current mainly flows.

[0092] In the specification, an "electrical connection" includes a case that constituent elements are connected together through an element with a certain electrical action. The "element with a certain electrical effect" is not particularly limited as long as electrical signals between the connected constituent elements may be sent and received. Examples of the "element with a certain electrical action" not only include an electrode and a wiring, but also include a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements with various functions, etc.

[0093] In the specification, "disposed in a same layer" adopted refers to a structure formed by patterning two (or more than two) structures through a same patterning process, and their materials may be the same or different. For example, materials of precursors for forming multiple structures disposed in a same layer are the same, and materials finally formed may be the same or different.

[0094] With development of OLED display technologies, oxide process is often applied in OLED display products because of its high uniformity. The coupling effect of some capacitors in the pixel driving circuits made with the oxide process will introduce noise in the display stage, which makes the driving current output by the pixel driving circuit unstable and affects the reliability of the pixel driving circuit.

[0095] FIG. 1 is a schematic diagram of a structure of a pixel driving circuit according to an embodiment of the present disclosure. As shown in FIG. 1, the pixel driving circuit according to an embodiment of the present disclosure may include a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a storage sub-circuit.

[0096] As shown in FIG. 1, the driving sub-circuit is electrically connected to the first node N1, the second node N2, and the third node N3, respectively, and configured to provide a driving current to the third node N3 under control of signals of the first node N1 and the second node N2. The first control sub-circuit is electrically connected to the first scan signal line G1, the second scan signal line G2, the data signal line Data, the reference signal line REF, and the first node N1, respectively, and configured to provide a signal of the data signal line Data or the reference signal line REF to the first node N1 under control of signals of the first scan signal line G1 and the second scan signal line G2. The second control sub-circuit is electrically connected to the first light emitting signal line EM1, the second light emitting signal line EM2, the first power supply line VDD, the second node N2, the third node N3, and the fourth node N4, respectively, and configured to provide a signal of the first power supply line VDD to the second node N2 and a signal of the third node N3 to the fourth node N4 under control of signals of the first light emitting signal line EM1 and the second light emitting signal line EM2. The third control sub-circuit is electrically connected to the first reset signal line Reset1, the auxiliary signal line VX, and the third node N3, respectively, and configured to control a signal of the third node N3 under control of a signal of the first reset signal line Reset1 and under drive of a signal of the auxiliary signal line VX. The storage sub-circuit is electrically connected to the first node N1 and the third node N3, respectively, and configured to store a voltage difference between signals of the first node N1 and the third node N3.

[0097] In an exemplary embodiment, as shown in FIG. 1, the pixel driving circuit is electrically connected to the light emitting device L through the fourth node N4.

[0098] In an exemplary implementation, the light emitting device L may include a first electrode (anode), an organic emitting layer, and a second electrode (cathode) that are stacked. Exemplarily, the anode of the light emitting device L is electrically connected to the fourth node N4, and the cathode of the light emitting device L is electrically connected to the second power supply line VSS.

[0099] In an exemplary implementation, the light emitting device L, which may include a current-driven device, may use a current-type light emitting diode, such as a micro light emitting diode (Micro LED), or a mini light emitting Diode (Mini LED), or an Organic light emitting diode (OLED), or a quantum light emitting diode (QLED). A typical size (e.g., length) of a Micro LED may be less than 100 µm, e.g., 10 µm to 50 µm. A typical size (e.g., length) of a Mini LED may be about 100 µm to 300 µm, e.g., 120 µm to 260 µm.

[0100] In an exemplary embodiment, the organic emitting layer may include a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Block Layer (EBL), an Emitting Layer (EML), a Hole Block Layer (HBL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL) that are stacked. In an exemplary implementation, hole injection layers of all sub-pixels may be connected together to be a common layer, electron injection layers of all the sub-pixels may be connected together to be a common layer, hole transport layers of all the sub-pixels may be connected together to be a common layer, electron transport layers of all the sub-pixels may be connected together to be a common layer, hole block layers of all the sub-pixels may be connected together to be a common layer, emitting layers of adjacent sub-pixels may be overlapped slightly or may be isolated, and electron block layers of adjacent sub-pixels may be overlapped slightly or may be isolated.

[0101] In an exemplary embodiment, the first power supply line VDD continuously provides a high-level signal, and a signal of the first power supply line VDD is a Direct Current (DC) signal.

[0102] In an exemplary embodiment, the second power supply line VSS continuously provides a low-level signal, and a signal of the second power supply line VSS is a DC signal.

[0103] In an exemplary embodiment, the reference signal line REF continuously provides a low-level signal, a signal of the reference signal line REF is a DC signal, and exemplarily, a voltage of the signal of the reference signal line REF may be 0V.

[0104] In an exemplary embodiment, the pixel driving circuit is located in a display substrate, and the content displayed by the display substrate includes a plurality of display frames. In any display frame, a signal of the first scan signal line G1 is a pulse signal, a signal of the second scan signal line G2 is a pulse signal, and a time period in which the second scan signal line G2 is an effective level signal occurs before a time period in which the first scan signal line G1 is an effective level signal.

[0105] An embodiment of the present disclosure provides a pixel driving circuit, including: a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a storage sub-circuit. The driving sub-circuit is electrically connected to a first node, a second node, and a third node, respectively, and configured to provide a driving current to the third node under control of signals of the first node and the second node. The first control sub-circuit is electrically connected to a first scan signal line, a second scan signal line, a data signal line, a reference signal line, and the first node, respectively, and configured to provide a signal of the data signal line or the reference signal line to the first node under control of signals of the first scan signal line and the second scan signal line. The second control sub-circuit is electrically connected to a first light emitting signal line, a second light emitting signal line, a first power supply line, the second node, the third node, and a fourth node, respectively, and configured to provide a signal of the first power supply line to the second node and a signal of the third node to the fourth node under control of signals of the first light emitting signal line and the second light emitting signal line. The third control sub-circuit is electrically connected to a first reset signal line, an auxiliary signal line, and the third node, respectively, and configured to control a signal of the third node under control of a signal of the first reset signal line and under drive of a signal of the auxiliary signal line. The storage sub-circuit is electrically connected to the first node and the third node, respectively, and configured to store a voltage difference between signals of the first node and the third node. The present disclosure can control the signal of the third node through signals of the first reset signal line and the auxiliary signal line by providing the third control sub-circuit, so as to avoid the introduction of noise in the display stage, keep the stability of the driving current output by the pixel driving circuit, and improve the reliability of the pixel driving circuit.

[0106] In an exemplary embodiment, a working process of the pixel driving circuit includes a display stage including a writing stage and a light emitting stage, wherein the light emitting stage occurs after the writing stage, and a signal of the first scan signal line G1 is an effective level signal in the writing stage. Signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are both effective level signals in the light emitting stage, and the time at which the writing stage occurs is a writing time period.

[0107] FIG. 2 is a first equivalent circuit diagram of a third control sub-circuit. As shown in FIG. 2, in an exemplary embodiment, the third control sub-circuit may be electrically connected to the third reset signal line Reset3 and the initial signal line INIT, respectively, and configured to provide a signal of the initial signal line to the fourth node N4 under control of a signal of the third reset signal line Reset3. Exemplarily, the third control sub-circuit may include a sixth transistor T6, an eighth transistor T8 and a second capacitor C2. A control electrode of the sixth transistor T6 is electrically connected to the first reset signal line Reset1, a first electrode of the sixth transistor T6 is electrically connected to the auxiliary signal line VX, and a second electrode of the sixth transistor T6 is electrically connected to the fifth node N5; a first terminal of the second capacitor C2 is electrically connected to the fifth node N5, and a second terminal of the second capacitor C2 is electrically connected to the third node N3; a first electrode of the eighth transistor T8 is electrically connected to the initial signal line INIT, and a second electrode of the eighth transistor T8 is electrically connected to the fourth node N4.

[0108] In an exemplary embodiment, as shown in FIG. 2, a signal of the auxiliary signal line VX is a non-DC signal and is electrically connected to the fourth node N4.

[0109] In an exemplary embodiment, as shown in FIG. 2, the present disclosure, by enabling a signal of the second light emitting signal line EM2 to be an effective level signal during part of a time period in which a signal of the third reset signal line Reset3 is an effective level signal, can reset the third node N3 and the fourth node N4 prior to the writing time period, and can ensure the display uniformity of the pixel driving circuit. The present disclosure, by enabling signals of the first reset signal line Reset1 and the second light emitting signal line EM2 to be effective level signals during at least part of a time period after the writing time period, can make voltage values of signals at two ends of the second capacitor C2 in the light emitting stage the same, avoid the influence of the second capacitor C2 on the third node N3 in the light emitting stage, avoid the introduction of noise in the third node N3, which can keep the stability of the driving current output by the pixel driving circuit, and improve the reliability of the pixel driving circuit.

[0110] FIG. 3 is a second equivalent circuit diagram of a third control sub-circuit. As shown in FIG. 3, in an exemplary embodiment, the third control sub-circuit may be electrically connected to the second reset signal line Reset2, and is configured to provide a signal of the fifth node N5 to the third node N3 under control of a signal of the second reset signal line Reset2. Exemplarily, the third control sub-circuit may include a sixth transistor T6, a seventh transistor T7 and a second capacitor C2. A first electrode of the sixth transistor T6 is electrically connected to the auxiliary signal line VX, and a second electrode of the sixth transistor T6 is electrically connected to the fifth node N5; a control electrode of the seventh transistor T7 is electrically connected to a second reset signal line Reset3, a first electrode of the seventh transistor T7 is electrically connected to the fifth node N5, and a second electrode of the seventh transistor T7 is electrically connected to the third node N3; a first terminal of the second capacitor C2 is electrically connected to the fifth node N5, and a second terminal of the second capacitor C2 is electrically connected to the third node N3.

[0111] In an exemplary embodiment, as shown in FIG. 3, a signal of the auxiliary signal line VX may be a DC signal and is the same as a signal of any one of the initial signal line INIT, the reference signal line REF, and the first power supply line VDD.

[0112] In an exemplary embodiment, as shown in FIG. 3, the present disclosure, by enabling signals of the second reset signal line Reset2 and the second light emitting signal line EM2 to be effective level signals during part of a time period in which a signal of the first reset signal line Reset1 is the effective level signal, can reset the third node N3 and the fourth node N4 prior to the writing time period, and can ensure the display uniformity of the pixel driving circuit. The present disclosure, by enabling the second reset signal line Reset2 to be an effective level signal during at least part of a time period after the writing time period, can make voltage values of signals at two ends of the second capacitor C2 in the light emitting stage the same, avoid the influence of the second capacitor C2 on the third node N3 in the light emitting stage, avoid the introduction of noise in the display stage, keep the stability of the driving current output by the pixel driving circuit, and improve the reliability of the pixel driving circuit.

[0113] FIG. 4 is a third equivalent circuit diagram of a third control sub-circuit, and FIG. 5 is a fourth equivalent circuit diagram of a third control sub-circuit. In an exemplary embodiment, as shown in FIGS. 4 and 5, the third control sub-circuit may be electrically connected to the third reset signal line Reset3 and the initial signal line INIT, respectively, and configured to provide a signal of the initial signal line to the fourth node N4 under control of a signal of the third reset signal line Reset3. Exemplarily, the third control sub-circuit may further include an eighth transistor T8, a control electrode of the eighth transistor T8 is electrically connected to the third reset signal line Reset3, a first electrode of the eighth transistor T8 is electrically connected to the initial signal line, and a second electrode of the eighth transistor T8 is electrically connected to the fourth node N4.

[0114] In an exemplary embodiment, a signal of the auxiliary signal line VX is a DC signal, and the signal of the auxiliary signal line VX is the same as a signal of any one of the initial signal line INIT, the reference signal line REF, and the first power supply line VDD; alternatively, a signal of the auxiliary signal line VX is a non-DC signal, and the signal of the auxiliary signal line VX is electrically connected to the fourth node N4. FIG. 4 is illustrated by taking a case in which the signal of the auxiliary signal line VX is a DC signal as an example, and FIG. 5 is illustrated by taking a case in which the signal of the auxiliary signal line VX is a non-DC signal as an example.

[0115] In an exemplary embodiment, as shown in FIGS. 4 and 5, when a signal of the first reset signal line Reset1 is an effective level signal, a signal of the third reset signal line is an effective level signal, and a signal of the second reset signal line is an ineffective level signal; when the signal of the second reset signal line is an effective level signal, the signal of the first reset signal line is an ineffective level signal, the present disclosure, by enabling a signal of the second light emitting signal line EM2 to be an effective level signal during part of a time period in which a signal of the third reset signal line Reset3 is an effective level signal, can reset the third node N3 and the fourth node N4 prior to the writing time period, and can ensure the display uniformity of the pixel driving circuit. The present disclosure, by enabling the second reset signal line Reset2 to be an effective level signal during at least part of a time period after the writing time period, can make voltage values of signals at two ends of the second capacitor C2 in the light emitting stage the same, avoid the influence of the second capacitor C2 on the third node N3 in the light emitting stage, avoid the introduction of noise in the display stage, keep the stability of the driving current output by the pixel driving circuit, and improve the reliability of the pixel driving circuit.

[0116] FIG. 6 is a fifth equivalent circuit diagram of a third control sub-circuit, and FIG. 7 is a sixth equivalent circuit diagram of a third control sub-circuit. In an exemplary embodiment, as shown in FIGS. 6 and 7, the third control sub-circuit may be electrically connected to the third reset signal line Reset3 and the initial signal line INIT, respectively, and configured to provide a signal of the initial signal line to the fourth node N4 under control of a signal of the third reset signal line Reset3. Exemplarily, the third control sub-circuit may include a sixth transistor T6, an eighth transistor T8 and a second capacitor C2. A control electrode of the sixth transistor T6 is electrically connected to the first reset signal line Reset1, a first electrode of the sixth transistor T6 is electrically connected to the fifth node N5, and a second electrode of the sixth transistor T6 is electrically connected to the third node N3; a control electrode of the eighth transistor T8 is electrically connected to the third reset signal line Reset3, a first electrode of the eighth transistor T8 is electrically connected to the initial signal line INIT, and a second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; a first terminal of the second capacitor C2 is electrically connected to the auxiliary signal line VX, and a second terminal of the second capacitor C2 is electrically connected to the fifth node N5.

[0117] In an exemplary embodiment, a signal of the auxiliary signal line VX is a DC signal, and the signal of the auxiliary signal line VX is the same as a signal of any one of the initial signal line, the reference signal line REF, and the first power supply line VDD; alternatively, a signal of the auxiliary signal line VX is a non-DC signal, and the signal of the auxiliary signal line VX is electrically connected to the fourth node N4. FIG. 6 is illustrated by taking a case in which a signal of the auxiliary signal line VX is a DC signal as an example, and FIG. 7 is illustrated by taking a case in which a signal of the auxiliary signal line VX is a non-DC signal as an example.

[0118] In an exemplary embodiment, as shown in FIGS. 6 and 7, the present disclosure, by enabling a signal of the second light emitting signal line EM2 to be an effective level signal during part of a time period in which a signal of the third reset signal line Reset3 is an effective level signal, can reset the third node N3 and the fourth node N4 prior to the writing time period, and can ensure the display uniformity of the pixel driving circuit. The present disclosure, by enabling the first reset signal line Reset1 to be an ineffective level signal during a time period after the writing time period, can prevent the second capacitor C2 from affecting the third node N3, avoid the introduction of noise in the display stage, keep the stability of the driving current output by the pixel driving circuit, and improve the reliability of the pixel driving circuit.

[0119] In an exemplary embodiment, the initial signal line INIT continuously provides a low-level signal and a signal of the initial signal line INIT is a DC signal.

[0120] In an exemplary embodiment, a voltage value of a signal of the initial signal line INIT may be smaller than a voltage value of a signal of the second power supply line VSS, which may avoid light emission error of the light emitting device L and may enhance the reliability of the pixel driving circuit.

[0121] Only six exemplary structures of the third control sub-circuit are shown in FIGS. 2 to 7, and those skills in that art can easily understand that the implementation of the third control sub-circuit is not limit to these.

[0122] FIG. 8 is a partial equivalent circuit diagram of a pixel driving circuit. As shown in FIG. 8, in an exemplary embodiment, the first control sub-circuit may include a first transistor T1 and a second transistor T2, the driving sub-circuit may include a third transistor T3, the second control sub-circuit may include a fourth transistor T4 and a fifth transistor T5, and the storage sub-circuit may include a first capacitor C1. Herein, a control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, a first electrode of the first transistor T1 is electrically connected to the data signal line Data, and a second electrode of the first transistor T1 is electrically connected to the first node N1. A control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, a first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and a second electrode of the second transistor T2 is electrically connected to the first node N1. A control electrode of the third transistor T3 is electrically connected to the first node N1, a first electrode of the third transistor T3 is electrically connected to the second node N2, and a second electrode of the third transistor T3 is electrically connected to the third node N3. A control electrode of the fourth transistor T4 is electrically connected to the first light emitting signal line EM1, a first electrode of the fourth transistor T4 is electrically connected to the first power supply line VDD, and a second electrode of the fourth transistor T4 is electrically connected to the second node N2. A control electrode of the fifth transistor T5 is electrically connected to the second light emitting signal line EM2, a first electrode of the fifth transistor T5 is electrically connected to the third node N3, and a second electrode of the fifth transistor T5 is electrically connected to the fourth node N4. A first terminal of the first capacitor C1 is electrically connected to the first node N1, and a second terminal of the first capacitor C1 is electrically connected to the third node N3.

[0123] Only one exemplary structure of the driving sub-circuit, the first control sub-circuit, the second control sub-circuit, and the storage sub-circuit is shown in FIG. 8, and those skills in that art can easily understand that the implementations of the driving sub-circuit, the first control sub-circuit, the second control sub-circuit, and the storage sub-circuit are not limited this.

[0124] In an exemplary embodiment, FIG. 9 is a first equivalent circuit diagram of a pixel driving circuit, FIG. 10 is a second equivalent circuit diagram of a pixel driving circuit, FIG. 11 is a third equivalent circuit diagram of a pixel driving circuit, and FIG. 12 is a fourth equivalent circuit diagram of a pixel driving circuit. As shown in FIGS. 9 to 12, in an exemplary embodiment, in the pixel driving circuit, the first control sub-circuit includes a first transistor T1 and a second transistor T2, the driving sub-circuit includes a third transistor T3, the second control sub-circuit includes a fourth transistor T4 and a fifth transistor T5, the storage sub-circuit includes a first capacitor C1, the third control sub-circuit includes a second capacitor C2 and a sixth transistor T6, and the third control sub-circuit further includes at least one of a seventh transistor T7 and an eighth transistor T8. Herein, a control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, a first electrode of the first transistor T1 is electrically connected to the data signal line Data, and a second electrode of the first transistor T1 is electrically connected to the first node N1. A control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, a first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and a second electrode of the second transistor T2 is electrically connected to the first node N1. A control electrode of the third transistor T3 is electrically connected to the first node N1, a first electrode of the third transistor T3 is electrically connected to the second node N2, and a second electrode of the third transistor T3 is electrically connected to the third node N3. A control electrode of the fourth transistor T4 is electrically connected to the first light emitting signal line EM1, a first electrode of the fourth transistor T4 is electrically connected to the first power supply line VDD, and a second electrode of the fourth transistor T4 is electrically connected to the second node N2. A control electrode of the fifth transistor T5 is electrically connected to the second light emitting signal line EM2, a first electrode of the fifth transistor T5 is electrically connected to the third node N3, and a second electrode of the fifth transistor T5 is electrically connected to the fourth node N4. A control electrode of the sixth transistor T6 is electrically connected to the first reset signal line Reset1, a first electrode of the sixth transistor T6 is electrically connected to the auxiliary signal line VX, and a second electrode of the sixth transistor T6 is electrically connected to the fifth node N5. A control electrode of the seventh transistor T7 is electrically connected to the second reset signal line Reset2, a first electrode of the seventh transistor T7 is electrically connected to the fifth node N5, and a second electrode of the seventh transistor T7 is electrically connected to the third node N3. A control electrode of the eighth transistor T8 is electrically connected to the third reset signal line Reset3, a first electrode of the eighth transistor T8 is electrically connected to the initial signal line INIT, and a second electrode of the eighth transistor T8 is electrically connected to the fourth node N4. A first terminal of the first capacitor C1 is electrically connected to the first node N1, and a second terminal of the first capacitor C1 is electrically connected to the third node N3. A first terminal of the second capacitor C2 is electrically connected to the fifth node N5, and a second terminal of the second capacitor C2 is electrically connected to the third node N3. FIGS. 9 and 10 are illustrated by taking a case in which the third control sub-circuit further include a seventh transistor T7 and an eighth transistor T8 as an example, FIG. 11 is illustrated by taking a case in which the third control sub-circuit further includes a seventh transistor T7 as an example, and FIG. 12 is illustrated by taking a case in which the third control sub-circuit further includes an eighth transistor T8 as an example.

[0125] In an exemplary embodiment, as shown in FIGS. 9 and 10, the third control sub-circuit further includes that a signal of the auxiliary signal line VX in the pixel driving circuit of the seventh transistor T7 and the eighth transistor T8 may be a DC signal or may be a non-DC signal, FIG. 9 is illustrated by taking a case in which that a signal of the auxiliary signal line VX in the pixel driving circuit is a DC signal and is the same as a signal of any one of the initial signal line INIT, the reference signal line REF and the first power supply line VDD as an example, and FIG. 10 is illustrated by taking a case in which a signal of the auxiliary signal line VX in the pixel driving circuit is a non-DC signal and is electrically connected to the fourth node N4 as an example.

[0126] In an exemplary embodiment, as shown in FIG. 11, the third control sub-circuit further includes that a signal of the auxiliary signal line VX in the pixel driving circuit of the seventh transistor T7 is a DC signal and is the same as a signal of any one of the initial signal line, the reference signal line and the first power supply line.

[0127] In an exemplary embodiment, as shown in FIG. 12, the third control sub-circuit further includes that a signal of the auxiliary signal line VX in the pixel driving circuit of the eighth transistor T8 is a non-DC signal and is electrically connected to the fourth node N4.

[0128] Transistors may be classified as N-type transistors and P-type transistors according to characteristics of the transistors. When a transistor is a P-type transistor, its turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or another suitable voltage), and its turn-off voltage is a high-level voltage (e.g., 5V, 10V, or another suitable voltage). When a transistor is an N-type transistor, its turn-on voltage is a high-level voltage (e.g., 5V, 10V, or another suitable voltage), and its turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or another suitable voltage).

[0129] In an exemplary embodiment, any of the first transistor T1 to the eighth transistor T8 may be made of an oxide thin film transistor. An active layer of the oxide thin film transistor is made of an oxide semiconductor. The oxide thin film transistor has advantages such as a low drain current.

[0130] In an exemplary embodiment, any of the first transistor T1 to the eighth transistor T8 is an N-type transistor.

[0131] In an exemplary embodiment, FIG. 13 is a fifth equivalent circuit diagram of a pixel driving circuit and FIG. 14 is a sixth equivalent circuit diagram of a pixel driving circuit. As shown in FIGS. 13 and 14, in the pixel driving circuit, the first control sub-circuit may include a first transistor T1 and a second transistor T2, the driving sub-circuit may include a third transistor T3, the second control sub-circuit may include a fourth transistor T4 and a fifth transistor T5, and the storage sub-circuit may include a first capacitor C1, the third control sub-circuit may include a second capacitor C2, a sixth transistor T6 and an eighth transistor T8. Herein, a control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, a first electrode of the first transistor T1 is electrically connected to the data signal line Data, and a second electrode of the first transistor T1 is electrically connected to the first node N1. A control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, a first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and a second electrode of the second transistor T2 is electrically connected to the first node N1. A control electrode of the third transistor T3 is electrically connected to the first node N1, a first electrode of the third transistor T3 is electrically connected to the second node N2, and a second electrode of the third transistor T3 is electrically connected to the third node N3. A control electrode of the fourth transistor T4 is electrically connected to the first light emitting signal line EM1, a first electrode of the fourth transistor T4 is electrically connected to the first power supply line VDD, and a second electrode of the fourth transistor T4 is electrically connected to the second node N2. A control electrode of the fifth transistor T5 is electrically connected to the second light emitting signal line EM2, a first electrode of the fifth transistor T5 is electrically connected to the third node N3, and a second electrode of the fifth transistor T5 is electrically connected to the fourth node N4. A control electrode of the sixth transistor T6 is electrically connected to the first reset signal line Reset1, a first electrode of the sixth transistor T6 is electrically connected to the fifth node N5, and a second electrode of the sixth transistor T6 is electrically connected to the third node N3. A control electrode of the eighth transistor T8 is electrically connected to the third reset signal line Reset3, a first electrode of the eighth transistor T8 is electrically connected to the initial signal line INIT, and a second electrode of the eighth transistor T8 is electrically connected to the fourth node N4. A first terminal of the first capacitor C1 is electrically connected to the first node N1, and a second terminal of the first capacitor C1 is electrically connected to the third node N3. A first terminal of the second capacitor C2 is electrically connected to the auxiliary signal line VX, and a second terminal of the second capacitor C2 is electrically connected to the fifth node N5.

[0132] In an exemplary embodiment, as shown in FIGS. 13 and 14, the third control sub-circuit includes the sixth transistor T6, the eighth transistor T8 and the second capacitor C2, a signal of the auxiliary signal line VX in the pixel driving circuit of the sixth transistor T6, the eighth transistor T8 and the second capacitor C2 may be a DC signal or a non-DC signal. FIG. 13 is illustrated by taking a case in which a signal of the auxiliary signal line VX in the pixel driving circuit is a DC signal and is the same as a signal of any one of the initial signal line INIT, the reference signal line REF and the first power supply line VDD as an example, and FIG. 14 is illustrated by taking a case in which a signal of the auxiliary signal line VX in the pixel driving circuit is a non-DC signal and is electrically connected to the fourth node N4 as an example.

[0133] In an exemplary embodiment, any of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 may be made of an oxide thin film transistor. An active layer of the oxide thin film transistor is made of an oxide semiconductor. The oxide thin film transistor has advantages such as a low drain current.

[0134] In an exemplary embodiment, any of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 is an N-type transistor.

[0135] In an exemplary embodiment, in the pixel driving circuits as provided in FIGS. 9 to 14, a quantity of each of the first transistor T1, the second transistor T2 and the fourth transistor T4 may be at least one.

[0136] In an exemplary embodiment, when a quantity of the first transistors T1 may be at least two, control electrodes of all the first transistors are electrically connected to the first scan signal line, at least two first transistors are provided in series, a first electrode of a first first transistor is electrically connected to the data signal line, and a second electrode of a last first transistor is electrically connected to the first node N1.

[0137] In an exemplary embodiment, when a quantity of second transistors T2 may be at least two, control electrodes of all second transistors T2 are electrically connected to the second scan signal line, at least two second transistors are provided in series, a first electrode of a first second transistor is electrically connected to the reference signal line, and a second electrode of a last second transistor is electrically connected to the second node N2.

[0138] FIG. 15 is an operating timing diagram of the pixel driving circuits provided in FIGS. 9 and 10. Exemplary embodiments of the present disclosure will be described below with reference to a working process of the pixel driving circuit illustrated in FIGS. 9 and 10. The pixel driving circuit in FIGS. 9 and 10 includes eight transistors (a first transistor T1 to an eighth transistor T8) and two capacitors (a first capacitor C1 and a second capacitor C2), and the eight transistors are all N-type transistors.

[0139] In an exemplary embodiment, the working process of the pixel driving circuits provided in FIGS. 9 and 10 may include following stages.

[0140] In a first stage P1 referred to as a first reset stage, signals of the second scan signal line G2, the second light emitting signal line EM2, the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, and signals of the first scan signal line G1, the first light emitting signal line EM1 and the second reset signal line Reset2 are low-level signals. When a signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is written into the first node N1, to initialize (reset) a signal of the first node N1 and clear original charges in the first node N1. A signal of the first reset signal line Reset1 is a high-level signal, the sixth transistor T6 is turned on, a signal of the auxiliary signal line VX is written into the fifth node N5, to initialize (reset) a signal of the fifth node N5 and clear original charges in the fifth node N5. Signals of the second light emitting signal line EM2 and the third reset signal line Reset3 are high-level signals, the fifth transistor T5 and the eighth transistor T8 are turned on, and a signal of the initial signal line INIT is written into the third node N3 and the fourth node N4, respectively. Because a voltage value of a signal of the first node N1 and a voltage value of a signal of the third node N3 are greater than a threshold voltage of the third transistor T3, at this time, the third transistor T3 is turned on, and a signal of the initial signal line INIT is written into the second node N2, to initialize (reset) signals of the second node N2, the third node N3 and the fourth node N4 and clear original charges in the second node N2, the third node N3 and the fourth node N4. Signals of the first scan signal line G1, the first light emitting signal line EM1, and the second reset signal line Reset2 are low-level signals, and the first transistor T1, the fourth transistor T4, and the seventh transistor T7 are turned off. The light emitting device L does not emit light in this stage.

[0141] In a second stage P2, that is, a threshold compensation stage, signals of the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2 and the first light emitting signal line EM1 are high-level signals, and signals of the second reset signal line Reset2, the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals. A signal of the first reset signal line Reset1 is a high-level signal, the sixth transistor T6 is turned on, a signal of the auxiliary signal line VX is continuously written to the fifth node N5, to continuously initialize (reset) a signal of the fifth node N5. A signal of the third reset signal line Reset3 is a high-level signal, the eighth transistor T8 is turned on, a signal of the initial signal line INIT is continuously written to the fourth node N4, to continuously initialize (reset) a signal of the fourth node N4. A signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is continuously provided to the first node N1, a signal of the first light emitting signal line EM1 is a high-level signal, the fourth transistor T4 is turned on, and a signal of the first power supply line VDD is written to the third node N3 through the turned-on fourth transistor T4, the second node N2 and the turned-on third transistor T3 until a voltage V3 of a signal of the third node N3 meets V3=Vref-Vth, wherein Vref is a voltage value of the signal of the initial signal line REF, and Vth is the threshold voltage of the third transistor T3, at this time, the first capacitor C1 stores a voltage difference Vth between signals of the first node N1 and the third node N3. Signals of the second reset signal line Reset2, the first scan signal line G1, and the second light emitting signal line EM2 are low-level signals, and the first transistor T1, the fifth transistor T5, and the seventh transistor are turned off. The light emitting device L does not emit light in this stage.

[0142] In a third stage P3, that is, a data writing stage, signals of the first reset signal line Reset1, the third reset signal line Reset3 and the first scan signal line G1 are high-level signals, signals of the second reset signal line Reset2, the second scan signal line G2, the first light emitting signal line EM1 and the second light emitting signal line EM2 are low-level signals, and the data signal line Data outputs a data voltage. A signal of the first reset signal line Reset1 is a high-level signal, the sixth transistor T6 is turned on, a signal of the auxiliary signal line VX is continuously written to the fifth node N5, to continuously initialize (reset) a signal of the fifth node N5. A signal of the third reset signal line Reset3 is a high-level signal, the eighth transistor T8 is turned on, a signal of the initial signal line INIT is continuously written to the fourth node N4, to continuously initialize (reset) a signal of the fourth node N4. A signal of the first scan signal line G1 is a high-level signal, the first transistor T1 is turned on, and a data voltage of the data signal line Data is written to the first node N1. at this time, the voltage value V1 of the first node N1 meets V1=Vdata, wherein Vdata is the data voltage of the data signal line. The voltage value of the signal of the first node N1 in the present stage undergoes a jump compared to the voltage value in the previous stage. Therefore, a signal of the third node N3 also undergoes a jump under an action of the first capacitor C1 and the second capacitor C2. At this time, the voltage value V3 of the signal of the third node N3 meets V3=Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 ), where C 1 is the capacitance value of the first capacitor, C 2 is the capacitance value of the second capacitor. Signals of the second reset signal line Reset2, the second scan signal line G2, the first light emitting signal line EM1 and the second light emitting signal line EM2 are low-level signals, and the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the seventh transistor T7 are turned off. The light emitting device L does not emit light in this stage.

[0143] In a fourth stage P4 referred to as a second reset stage, signals of the second reset signal line Reset2, the third reset signal line Reset3 and the second light emitting signal line EM2 are high-level signals, and signals of the first reset signal line Reset1, the first light emitting signal line EM1, the first scan signal line G1 and the second scan signal line G2 are low-level signals. A signal of the third reset signal line Reset3 is a high-level signal, the eighth transistor T8 is turned on, a signal of the initial signal line INIT is continuously written to the fourth node N4, to continuously initialize (reset) a signal of the fourth node N4. A signal of the second light emitting signal line EM2 is a high-level signal, the fifth transistor T5 is turned on, a voltage V3 of a signal of the third node N3 meets V3=Vinit, and Vinit is a voltage value of a signal of the initial signal line, at this time, the first node N1 is pulled down under the action of the first capacitor C1, so that a voltage V1 of a signal of the first node N1 meets V1= Vdata- [Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 )]+ Vinit, a signal of the second reset signal line Reset2 is a high-level signal, the seventh transistor T7 is turned on, and voltages of signals of the third node N3 and the fifth node N5 are consistent. Signals of the first reset signal line Reset1, the first light emitting signal line EM1, the first scan signal line G1 and the second scan signal line G2 are low-level signals, and the first transistor T1, the second transistor T2, the fourth transistor T4 and the sixth transistor T6 are turned off. The light emitting device L does not emit light in this stage.

[0144] In a fifth stage P5, that is, a light emitting stage, signals of the second reset signal line Reset2, the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, and signals of the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals. Signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, a power supply voltage output by the first power supply line VDD provides a driving voltage to a first electrode of the light emitting device L through the fourth transistor T4, the third transistor T3 and the fifth transistor T5 which are turned on, to drive the light emitting device L to emit light, a signal of the second reset signal line Reset2 is high-level signal, the seventh transistor T7 is turned on, and the voltages of signals of the third node N3 and the fifth node N5 keep to be consistent. Signals of the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals, and the first transistor T1, the second transistor T2, the sixth transistor T6 and the eighth transistor T8 are turned off. In this stage, the light emitting device L emits light.

[0145] In a drive process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by a voltage difference between the control electrode (also the first node N1) and the second electrode (also the third node N3) of the third transistor T3. Because the voltage value V1 of the signal of the first node meets V1= Vdata-[Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 )]+ Vinit and the voltage value of the signal of the third node N3 is V3=Vinit, the driving current of the third transistor T3 is as follows. I = K * Vgs − Vth 2 = K * Vdata − Vref − Vth + Vdata − Vref * C 1 / C 1 + C 2 − Vth 2 = K * C 2 / C 1 + C 2 * Vdata − Vref 2

[0146] Herein, I is a driving current flowing through the third transistor T3, that is, a driving current driving the light emitting device L, K is a constant, and Vgs is a voltage difference between the control electrode and the second electrode of the third transistor T3.

[0147] It may be seen from a derivation result of the above current formula that in the light emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3. Therefore, an influence of the threshold voltage of the third transistor T3 on the driving current is eliminated, which may ensure uniformity of display brightness of a display product, and improve an overall display effect of the display product.

[0148] FIG. 16 is a working timing diagram of the pixel driving circuit provided in FIG. 11. An exemplary embodiment of the present disclosure will be described below through a working process of the pixel driving circuit exemplified in FIG. 11. The pixel driving circuit in FIG. 11 includes seven transistors (a first transistor T1 to a seventh transistor T7) and two capacitors (a first capacitor C1 and a second capacitor C2), and the seven transistors are all N-type transistors.

[0149] In an exemplary embodiment, a working process of the pixel driving circuit provided in FIG. 11 may include the following stages.

[0150] In a first stage P1 referred to as a first reset stage, signals of the second scan signal line G2, the second light emitting signal line EM2, the first reset signal line Reset1 and the second reset signal line Reset2 are high-level signals, and signals of the first scan signal line G1 and the first light emitting signal line EM1 are low-level signals. When a signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is written into the first node N1, to initialize (reset) a signal of the first node N1 and clear original charges in the first node N1. Signals of the first reset signal line Reset1, the second reset signal line Reset2 and the second light emitting signal line EM2 are high-level signals, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned on, a signal of the auxiliary signal line VX is written into the fifth node N5, the third node N3 and the fourth node N4 sequentially, to initialize (reset) signals of the third node N3, the fourth node N4 and the fifth node N5, and clear original charges in the third node N3, the fourth node N4 and the fifth node N5. Signals of the first scan signal line G1 and the first light emitting signal line EM1 are low-level signals, and the first transistor T1 and the fourth transistor T4 are turned off. The light emitting device L does not emit light in this stage.

[0151] In a second stage P2, that is, a threshold compensation stage, signals of the first reset signal line Reset1, the second scan signal line G2 and the first light emitting signal line EM1 are high-level signals, and signals of the second reset signal line Reset2, the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals. A signal of the first reset signal line Reset1 is a high-level signal, the sixth transistor T6 is turned on, a signal of the auxiliary signal line VX is continuously written to the fifth node N5, to continuously initialize (reset) a signal of the fifth node N5. A signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is continuously provided to the first node N1, a signal of the first light emitting signal line EM1 is a high-level signal, the fourth transistor T4 is turned on, and a signal of the first power supply line VDD is written to the third node N3 through the turned-on fourth transistor T4, the second node N2 and the turned-on third transistor T3 until a voltage V3 of a signal of the third node N3 meets V3=Vref-Vth, wherein Vref is a voltage value of the signal of the initial signal line REF, and Vth is the threshold voltage of the third transistor T3, at this time, the first capacitor C1 stores a voltage difference Vth between signals of the first node N1 and the third node N3. Signals of the second reset signal line Reset2, the first scan signal line G1, and the second light emitting signal line EM2 are low-level signals, and the first transistor T1, the fifth transistor T5, and the seventh transistor are turned off. The light emitting device L does not emit light in this stage.

[0152] In a third stage P3, that is, a data writing stage, signals of the first reset signal line Reset1 and the first scan signal line G1 are high-level signals, signals of the second reset signal line Reset2, the second scan signal line G2, the first light emitting signal line EM1 and the second light emitting signal line EM2 are low-level signals, and the data signal line Data outputs a data voltage. A signal of the first reset signal line Reset1 is a high-level signal, the sixth transistor T6 is turned on, a signal of the auxiliary signal line VX is continuously written to the fifth node N5, to continuously initialize (reset) a signal of the fifth node N5. A signal of the first scan signal line G1 is a high-level signal, the first transistor T1 is turned on, and the data voltage of the data signal line Data is written to the first node N1, at this time, the voltage value V1 of the first node N1 meets V1=Vdata, wherein Vdata is the data voltage of the data signal line. The voltage value of the signal of the first node N1 in the present stage undergoes a jump compared to the voltage value in the previous stage. Therefore, a signal of the third node N3 also undergoes a jump under an action of the first capacitor C1 and the second capacitor C2. At this time, the voltage value V3 of the signal of the third node N3 meets V3=Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 ), where C 1 is the capacitance value of the first capacitor, C 2 is the capacitance value of the second capacitor. Signals of the second reset signal line Reset2, the second scan signal line G2, the first light emitting signal line EM1 and the second light emitting signal line EM2 are low-level signals, and the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the seventh transistor T7 are turned off. The light emitting device L does not emit light in this stage.

[0153] In a fourth stage P4 referred to as a second reset stage, signals of the second reset signal line Reset2 and the second light emitting signal line EM2 are high-level signals, and signals of the first reset signal line Reset1, the first light emitting signal line EM1, the first scan signal line G1 and the second scan signal line G2 are low-level signals. A signal of the second light emitting signal line EM2 is a high-level signal, the fifth transistor T5 is turned on, a voltage V3 of a signal of the third node N3 meets V3=Vinit, and Vinit is a voltage value of a signal of the initial signal line. At this time, the first node N1 is pulled down under the action of the first capacitor C1, so that a voltage V1 of a signal of the first node N1 meets V1= Vdata- [Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 )]+ Vinit, a signal of the second reset signal line Reset2 is a high-level signal, the seventh transistor T7 is turned on, and voltages of signals of the third node N3 and the fifth node N5 keeps to be consistent. Signals of the first reset signal line Reset1, the first light emitting signal line EM1, the first scan signal line G1 and the second scan signal line G2 are low-level signals, and the first transistor T1, the second transistor T2, the fourth transistor T4 and the sixth transistor T6 are turned off. The light emitting device L does not emit light in this stage.

[0154] In a fifth stage P5, that is, a light emitting stage, signals of the second reset signal line Reset2, the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, and signals of the first reset signal line Reset1, the first scan signal line G1 and the second scan signal line G2 are low-level signals. Signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, a power supply voltage output by the first power supply line VDD provides a driving voltage to a first electrode of the light emitting device L through the fourth transistor T4, the third transistor T3 and the fifth transistor T5 which are turned on, to drive the light emitting device L to emit light, a signal of the second reset signal line Reset2 is a high-level signal, the seventh transistor T7 is turned on, and the voltages of signals of the third node N3 and the fifth node N5 keep to be consistent. Signals of the first reset signal line Reset1, the first scan signal line G1, and the second scan signal line G2 are low-level signals, the first transistor T1, the second transistor T2, and the sixth transistor T6 are turned off, and the light emitting device L emits light in this stage.

[0155] In a drive process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by a voltage difference between the control electrode (also the first node N1) and the second electrode (also the third node N3) of the third transistor T3. Because the voltage value V1 of the signal of the first node meets V1= Vdata-[Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 )]+ Vinit and the voltage value V3 of the signal of the third node N3 meets V3=Vinit, the driving current of the third transistor T3 is as follows. I = K * Vgs − Vth 2 = K * Vdata − Vref − Vth + Vdata − Vref * C 1 / C 1 + C 2 − Vth 2 = K * C 2 / C 1 + C 2 * Vdata − Vref 2

[0156] Herein, I is a driving current flowing through the third transistor T3, that is, a driving current driving the light emitting device L, K is a constant, and Vgs is a voltage difference between the control electrode and the second electrode of the third transistor T3.

[0157] It may be seen from a derivation result of the above current formula that in the light emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3. Therefore, an influence of the threshold voltage of the third transistor T3 on the driving current is eliminated, which may ensure uniformity of display brightness of a display product, and improve an overall display effect of the display product.

[0158] FIG. 17 is a working timing diagram of the pixel driving circuit provided in FIG. 12. An exemplary embodiment of the present disclosure will be described below through a working process of the pixel driving circuit exemplified in FIG. 12. The pixel driving circuit in FIG. 12 includes seven transistors (a first transistor T1 to a sixth transistor T6, an eighth transistor T8) and two capacitors (a first capacitor C1 and a second capacitor C2), and the seven transistors are all N-type transistors.

[0159] In an exemplary embodiment, a working process of the pixel driving circuit provided in FIG. 12 may include the following stages.

[0160] In a first stage P1 referred to as a first reset stage, signals of the second scan signal line G2, the second light emitting signal line EM2, the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, and signals of the first scan signal line G1 and the first light emitting signal line EM1 are low-level signals. When the signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is written into the first node N1, to initialize (reset) a signal of the first node N1 and clear original charges in the first node N1. A signal of the first reset signal line Reset1 is a high-level signal, the sixth transistor T6 is turned on, a signal of the auxiliary signal line VX is written into the fifth node N5, to initialize (reset) a signal of the fifth node N5 and clear original charges in the fifth node N5. Signals of the second light emitting signal line EM2 and the third reset signal line Reset3 are high-level signals, the fifth transistor T5 and the eighth transistor T8 are turned on, and a signal of the initial signal line INIT is written into the third node N3 and the fourth node N4, respectively. Because a voltage value of a signal of the first node N1 and a voltage value of a signal of the third node N3 are greater than a threshold voltage of the third transistor T3, at this time, the third transistor T3 is turned on, and the signal of the initial signal line INIT is written into the second node N2, to initialize (reset) signals of the second node N2, the third node N3 and the fourth node N4 and clear original charges in the second node N2, the third node N3 and the fourth node N4. Signals of the first scan signal line G1 and the first light emitting signal line EM1 are low-level signals, and the first transistor T1 and the fourth transistor T4 are turned off. The light emitting device L does not emit light in this stage.

[0161] In a second stage P2, that is, a threshold compensation stage, signals of the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2 and the first light emitting signal line EM1 are high-level signals, and signals of the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals. A signal of the first reset signal line Reset1 is a high-level signal, the sixth transistor T6 is turned on, a signal of the auxiliary signal line VX is continuously written to the fifth node N5, to continuously initialize (reset) a signal of the fifth node N5. A signal of the third reset signal line Reset3 is a high-level signal, the eighth transistor T8 is turned on, a signal of the initial signal line INIT is continuously written to the fourth node N4, to continuously initialize (reset) a signal of the fourth node N4. A signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is continuously provided to the first node N1, a signal of the first light emitting signal line EM1 is a high-level signal, the fourth transistor T4 is turned on, and a signal of the first power supply line VDD is written to the third node N3 through the turned-on fourth transistor T4, the second node N2 and the turned-on third transistor T3 until a voltage V3 of a signal of the third node N3 meets V3=Vref-Vth, wherein Vref is a voltage value of a signal of the initial signal line REF, and Vth is the threshold voltage of the third transistor T3, at this time, the first capacitor C1 stores a voltage difference Vth between signals of the first node N1 and the third node N3. Signals of the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals, and the first transistor T1 and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0162] In a third stage P3, that is, a data writing stage, signals of the first reset signal line Reset1, the third reset signal line Reset3 and the first scan signal line G1 are high-level signals, signals of the second scan signal line G2, the first light emitting signal line EM1 and the second light emitting signal line EM2 are low-level signals, and the data signal line Data outputs a data voltage. A signal of the first reset signal line Reset1 is a high-level signal, the sixth transistor T6 is turned on, a signal of the auxiliary signal line VX is continuously written to the fifth node N5, to continuously initialize (reset) a signal of the fifth node N5. A signal of the third reset signal line Reset3 is a high-level signal, the eighth transistor T8 is turned on, a signal of the initial signal line INIT is continuously written to the fourth node N4, to continuously initialize (reset) a signal of the fourth node N4. A signal of the first scan signal line G1 is a high-level signal, the first transistor T1 is turned on, and the data voltage of the data signal line Data is written to the first node N1. At this time, the voltage value V1 of the first node N1 meets V1=Vdata, where Vdata is the data voltage of the data signal line. The voltage value of the signal of the first node N1 in the present stage undergoes a jump compared to the voltage value in the previous stage. Therefore, a signal of the third node N3 also undergoes a jump under an action of the first capacitor C1 and the second capacitor C2. At this time, the voltage value V3 of the signal of the third node N3 meets V3=Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 ), where C 1 is the capacitance value of the first capacitor, C 2 is the capacitance value of the second capacitor. Signals of the second scan signal line G2, the first light emitting signal line EM1, and the second light emitting signal line EM2 are low-level signals, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0163] In a fourth stage P4 referred to as a second reset stage, signals of the first reset signal line Reset1, the third reset signal line Reset3 and the second light emitting signal line EM2 are high-level signals, and signals of the first light emitting signal line EM1, the first scan signal line G1 and the second scan signal line G2 are low-level signals. A signal of the third reset signal line Reset3 is a high-level signal, the eighth transistor T8 is turned on, a signal of the initial signal line INIT is continuously written to the fourth node N4, to continuously initialize (reset) a signal of the fourth node N4. A signal of the second light emitting signal line EM2 is a high-level signal, the fifth transistor T5 is turned on, a voltage V3 of a signal of the third node N3 meets V3=Vinit, where Vinit is a voltage value of a signal of the initial signal line. At this time, the first node N1 is pulled down under the action of the first capacitor C1, so that a voltage V1 of a signal of the first node N1 meets V1= Vdata- [Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 )]+ Vinit, a signal of the first reset signal line Reset1 is a high-level signal, the sixth transistor T6 is turned on, and voltages of signals of the third node N3 and the fifth node N5 keep to be consistent. Signals of the first reset signal line Reset1, the first light emitting signal line EM1, the first scan signal line G1, and the second scan signal line G2 are low-level signals, and the first transistor T1, the second transistor T2, and the fourth transistor T4 are turned off. The light emitting device L does not emit light in this stage.

[0164] In a fifth stage P5, that is, a light emitting stage, signals of the first reset signal line Reset1, the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, and signals of the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals. Signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, a power supply voltage output by the first power supply line VDD provides a driving voltage to a first electrode of the light emitting device L through the fourth transistor T4, the third transistor T3 and the fifth transistor T5 which are turned on, to drive the light emitting device L to emit light, a signal of the first reset signal line Reset1 is a high-level signal, the sixth transistor T6 is turned on, and voltages of signals of the third node N3 and the fifth node N5 keep to be consistent. Signals of the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals, the first transistor T1, the second transistor T2, and the eighth transistor T8 are turned off, and the light emitting device L emits light in this stage.

[0165] In a drive process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by a voltage difference between the control electrode (also the first node N1) and the second electrode (also the third node N3) of the third transistor T3. Because the voltage value V1 of the signal of the first node meets V1= Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]+ Vinit and the voltage value V3 of the signal of the third node N3 meets V3=Vinit, the driving current of the third transistor T3 is as follows. I = K * Vgs − Vth 2 = K * Vdata − Vref − Vth + Vdata − Vref * C 1 / C 1 + C 2 − Vth 2 = K * C 2 / C 1 + C 2 * Vdata − Vref 2

[0166] Herein, I is a driving current flowing through the third transistor T3, that is, a driving current driving the light emitting device L, K is a constant, and Vgs is a voltage difference between the control electrode and the second electrode of the third transistor T3.

[0167] It may be seen from a derivation result of the above current formula that in the light emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3. Therefore, an influence of the threshold voltage of the third transistor T3 on the driving current is eliminated, which may ensure uniformity of display brightness of a display product, and improve an overall display effect of the display product.

[0168] In a fourth stage and the fifth stage, for the pixel driving circuits provided in FIGS. 9 to 12, signals of the third node N3 and the fifth node N5 at two ends of the second capacitor C2 are consistent, so that the third node of the pixel driving circuit is not affected by the coupling of the second capacitor C2 in the fifth stage, which can improve the stability of the driving current of the pixel driving circuit and improve the reliability of the pixel driving circuit.

[0169] FIG. 18 is an operating timing diagram of the pixel driving circuits provided in FIGS. 13 and 14. An exemplary embodiment of the present disclosure will be described below through a working process of the pixel driving circuits exemplified in FIGS. 13 and 14. The pixel driving circuits in FIGS. 13 and 14 includes seven transistors (a first transistor T1 to a sixth transistor T6, an eighth transistor T8) and two capacitors (a first capacitor C1 and a second capacitor C2), and the seven transistors are all N-type transistors.

[0170] In an exemplary embodiment, a working process of the pixel driving circuits provided in FIGS. 13 and 14 may include the following stages.

[0171] In a first stage P1 referred to as a first reset stage, signals of the second scan signal line G2, the second light emitting signal line EM2, the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, and signals of the first scan signal line G1 and the first light emitting signal line EM1 are low-level signals. When a signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is written into the first node N1, to initialize (reset) a signal of the first node N1 and clear original charges in the first node N1. A signal of the first reset signal line Reset1 is a high-level signal, the sixth transistor T6 is turned on, a signal of the auxiliary signal line VX is written into the fifth node N5 to initialize (reset) a signal of the fifth node N5 and clear original charges in the fifth node N5. Signals of the second light emitting signal line EM2 and the third reset signal line Reset3 are high-level signals, the fifth transistor T5 and the eighth transistor T8 are turned on, and a signal of the initial signal line INIT is written into the third node N3 and the fourth node N4, respectively. Because a voltage value of a signal of the first node N1 and a voltage value of a signal of the third node N3 are greater than a threshold voltage of the third transistor T3, at this time, the third transistor T3 is turned on, and a signal of the initial signal line INIT is written into the second node N2, to initialize (reset) signals of the second node N2, the third node N3 and the fourth node N4 and clear original charges in the second node N2, the third node N3 and the fourth node N4. Signals of the first scan signal line G1 and the first light emitting signal line EM1 are low-level signals, and the first transistor T1 and the fourth transistor T4 are turned off. The light emitting device L does not emit light in this stage.

[0172] In a second stage P2, that is, a threshold compensation stage, signals of the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2 and the first light emitting signal line EM1 are high-level signals, and signals of the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals. A signal of the first reset signal line Reset1 is a high-level signal, the sixth transistor T6 is turned on, a signal of the auxiliary signal line VX is continuously written to the fifth node N5, to continuously initialize (reset) a signal of the fifth node N5. A signal of the third reset signal line Reset3 is a high-level signal, the eighth transistor T8 is turned on, a signal of the initial signal line INIT is continuously written to the fourth node N4, to continuously initialize (reset) a signal of the fourth node N4. A signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is continuously provided to the first node N1, a signal of the first light emitting signal line EM1 is a high-level signal, the fourth transistor T4 is turned on, and a signal of the first power supply line VDD is written to the third node N3 through the turned-on fourth transistor T4, the second node N2 and the turned-on third transistor T3 until a voltage V3 of a signal of the third node N3 meets V3=Vref-Vth, wherein Vref is a voltage value of the signal of the initial signal line REF, and Vth is the threshold voltage of the third transistor T3, at this time, the first capacitor C1 stores a voltage difference Vth between signals of the first node N1 and the third node N3. Signals of the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals, and the first transistor T1 and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0173] In a third stage P3, that is, a data writing stage, signals of the first reset signal line Reset1, the third reset signal line Reset3 and the first scan signal line G1 are high-level signals, signals of the second scan signal line G2, the first light emitting signal line EM1 and the second light emitting signal line EM2 are low-level signals, and the data signal line Data outputs a data voltage. A signal of the first reset signal line Reset1 is a high-level signal, the sixth transistor T6 is turned on, a signal of the auxiliary signal line VX is continuously written to the fifth node N5, to continuously initialize (reset) a signal of the fifth node N5. A signal of the third reset signal line Reset3 is a high-level signal, the eighth transistor T8 is turned on, a signal of the initial signal line INIT is continuously written to the fourth node N4, to continuously initialize (reset) a signal of the fourth node N4. A signal of the first scan signal line G1 is a high-level signal, the first transistor T1 is turned on, and the data voltage of the data signal line Data is written to the first node N1. At this time, the voltage value V1 of the first node N1 meets V1=Vdata, wherein Vdata is the data voltage of the data signal line. The voltage value of the signal of the first node N1 in the present stage undergoes a jump compared to the voltage value in the previous stage. Therefore, a signal of the third node N3 also undergoes a jump under an action of the first capacitor C1 and the second capacitor C2. At this time, the voltage value V3 of the signal of the third node N3 meets V3=Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 ), where C 1 is the capacitance value of the first capacitor, C 2 is the capacitance value of the second capacitor. Signals of the second scan signal line G2, the first light emitting signal line EM1, and the second light emitting signal line EM2 are low-level signals, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0174] In a fourth stage P4 referred to as a second reset stage, signals of the third reset signal line Reset3 and the second light emitting signal line EM2 are high-level signals, and signals of the first reset signal line Reset1, the first light emitting signal line EM1, the first scan signal line G1 and the second scan signal line G2 are low-level signals. A signal of the third reset signal line Reset3 is a high-level signal, the eighth transistor T8 is turned on, a signal of the initial signal line INIT is continuously written to the fourth node N4, to continuously initialize (reset) a signal of the fourth node N4. A signal of the second light emitting signal line EM2 is a high-level signal, the fifth transistor T5 is turned on, a voltage V3 of a signal of the third node N3 meets V3=Vinit, wherein Vinit is a voltage value of a signal of the initial signal line. At this time, the first node N1 is pulled down under the action of the first capacitor C1, so that a voltage V1 of a signal of the first node N1 meets V1= Vdata- [Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 )]+ Vinit. Signals of the first reset signal line Reset1, the first light emitting signal line EM1, the first scan signal line G1 and the second scan signal line G2 are low-level signals, and the first transistor T1, the second transistor T2, the fourth transistor T4 and the sixth transistor T6 are turned off. The light emitting device L does not emit light in this stage.

[0175] In a fifth stage P5, that is, a light emitting stage, signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, and signals of the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals. Signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, a power supply voltage output by the first power supply line VDD provides a driving voltage to a first electrode of the light emitting device L through the fourth transistor T4, the third transistor T3 and the fifth transistor T5 which are turned on, to drive the light emitting device L to emit light, a signal of the first reset signal line Reset1 is a high-level signal, the sixth transistor T6 is turned on, and voltages of signals of the third node N3 and the fifth node N5 keep to be consistent. Signals of the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals, the first transistor T1, the second transistor T2, the sixth transistor T6 and the eighth transistor T8 are turned off, and the light emitting device L emits light in this stage.

[0176] In a drive process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by a voltage difference between the control electrode (also the first node N1) and the second electrode (also the third node N3) of the third transistor T3. Because the voltage value V1 of the signal of the first node meets V1= Vdata-[Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 )]+ Vinit and the voltage value V3 of the signal of the third node N3 meets V3=Vinit, the driving current of the third transistor T3 is as follows. I = K * Vgs − Vth 2 = K * Vdata − Vref − Vth + Vdata − Vref * C 1 / C 1 + C 2 − Vth 2 = K * C 2 / C 1 + C 2 * Vdata − Vref 2

[0177] Herein, I is a driving current flowing through the third transistor T3, that is, a driving current driving the light emitting device L, K is a constant, and Vgs is a voltage difference between the control electrode and the second electrode of the third transistor T3.

[0178] It may be seen from a derivation result of the above current formula that in the light emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3. Therefore, an influence of the threshold voltage of the third transistor T3 on the driving current is eliminated, which may ensure uniformity of display brightness of a display product, and improve an overall display effect of the display product.

[0179] In a fourth stage and the fifth stage, for the pixel driving circuits provided in FIGS. 13 and 14, the second capacitor C2 is disconnected from the sixth transistor T6 which is disconnected from the third node N3, so that the third node of the pixel driving circuit is not affected by the coupling of the second capacitor C2 in the fifth stage, which can improve the stability of the driving current of the pixel driving circuit and improve the reliability of the pixel driving circuit.

[0180] FIG. 19 is a schematic diagram of a structure of another pixel driving circuit according to an embodiment of the present disclosure. As illustrated in FIG. 19, the pixel driving circuit according to an embodiment of the present disclosure is provided in a display apparatus and includes a driving sub-circuit, a storage sub-circuit, a first control sub-circuit, a second control sub-circuit, and a third control sub-circuit.

[0181] As shown in FIG. 19, the driving sub-circuit is electrically connected to the first node N1, the second node N2, and the third node N3, respectively, and configured to provide a driving current to the third node N3 under control of signals of the first node N1 and the second node N2. The storage sub-circuit is electrically connected to the first node N1 and the third node N3, respectively, and configured to store a voltage difference between signals of the first node N1 and the third node N3. The first control sub-circuit is electrically connected to the first scan signal line G1, the second scan signal line G2, the data signal line Data, the reference signal line REF, and the first node N1, respectively, and configured to provide a signal of the data signal line Data or the reference signal line REF to the first node N1 under control of signals of the first scan signal line G1 and the second scan signal line G2. The second control sub-circuit is electrically connected to the first light emitting signal line EM1, the second light emitting signal line EM2, the first power supply line VDD, the second node N2, the third node N3, and the fourth node N4, respectively, and configured to provide a signal of the first power supply line VDD to the second node N2 and a signal of the third node N3 to the fourth node N4 under control of signals of the first light emitting signal line EM1 and the second light emitting signal line EM2. The third control sub-circuit is electrically connected to the third node N3, the fourth node N4, the at least one reset signal line Reset, and at least one signal line of the dynamic signal line Var and the auxiliary signal line VX, respectively, and configured to adjust signals of the third node N3 and the fourth node N4 under control of signals of the at least one reset signal line Reset and the at least one signal line of the dynamic signal line Var and the auxiliary signal line VX.

[0182] FIG. 20 is a schematic diagram of a structure of a display apparatus. As shown in FIG. 20, the display apparatus includes a first control unit, a second control unit and a data unit. The first control unit is electrically connected to the second light emitting signal line EM2 and configured to provide a signal to the second light emitting signal line EM2, the second control unit is electrically connected to at least one reset signal line Reset and configured to provide a signal to the at least one reset signal line Reset, and the data unit is electrically connected to the dynamic signal line Var and configured to provide a signal to the dynamic signal line Var.

[0183] In an exemplary embodiment, content displayed by the display apparatus includes at least one display frame, and in the at least one display frame, a start time of at least one time period in which the first control unit provides an effective level signal to the second light emitting signal line EM2 is earlier than or equal to a start time at which the second control unit provides an ineffective level signal to the at least one reset signal line.

[0184] In an exemplary embodiment, as shown in FIG. 19, the pixel driving circuit is electrically connected to the light emitting device L through the fourth node N4. The light emitting device L is also electrically connected to the second power supply line VSS.

[0185] In an exemplary embodiment, the first power supply line VDD continuously provides a high-level signal, and a signal of the first power supply line VDD is a Direct Current (DC) signal.

[0186] In an exemplary embodiment, the second power supply line VSS continuously provides a low-level signal, and a signal of the second power supply line VSS is a DC signal.

[0187] In an exemplary embodiment, the reference signal line REF continuously provides a low-level signal, a signal of the reference signal line REF is a DC signal, and exemplarily, a voltage of the signal of the reference signal line REF may be 0V.

[0188] The mobility of the oxide thin film transistor in the pixel driving circuit varies with the temperature of the display apparatus, and with the increase of the temperature of the display apparatus, the change in the mobility of the oxide thin film transistor and the change in the voltage across the OLED will cause the increase of the brightness of the display substrate which will lead to the uneven brightness of the display substrate at different temperatures, and affect the display effect of the display apparatus. In the present disclosure, signals of the third node and the fourth node are adjusted by the third control sub-circuit under control of signals of at least one reset signal line and at least one signal line of the dynamic signal line and the auxiliary signal line. By adjusting the signal of the dynamic signal line, the temperature of the display apparatus is reduced, thereby reducing the influence of the temperature change of the display apparatus on the display brightness, improving the brightness uniformity of the display apparatus at different temperatures, and ensuring the display effect of the display apparatus.

[0189] In an exemplary embodiment, the voltage value of the signal of the dynamic signal line Var includes a plurality of voltage values, and the voltage value of the dynamic signal provided by the data unit to the dynamic signal line Var is positively correlated with the temperature of the display apparatus at at least some moments of the at least one display frame.

[0190] In an exemplary embodiment, the dynamic signal line Var may be the initial signal line.

[0191] FIG. 21 is a first schematic diagram of a structure of the pixel driving circuit provided in FIG. 19. As illustrated in FIG. 21, the at least one reset signal line may include a third reset signal line Reset3. The third control sub-circuit may be electrically connected to the third node N3, the fourth node N4, the third reset signal line Reset3, and the dynamic signal line Var, respectively.

[0192] FIG. 22A is an equivalent circuit diagram of the pixel driving circuit provided in FIG. 21, and FIG. 22B is a second equivalent circuit diagram of the pixel driving circuit provided in FIG. 21. As shown in FIGS. 22A and 22B, the driving sub-circuit includes a third transistor T3, the first control sub-circuit includes a first transistor T1 and a second transistor T2, the second control sub-circuit includes a fourth transistor T4 and a fifth transistor T5, and the storage sub-circuit includes a first capacitor C1; the third control sub-circuit includes a second capacitor C2 and an eighth transistor T8. Herein, a control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, a first electrode of the first transistor T1 is electrically connected to the data signal line Data, and a second electrode of the first transistor T1 is electrically connected to the first node N1. A control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, a first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and a second electrode of the second transistor T2 is electrically connected to the first node N1. A control electrode of the third transistor T3 is electrically connected to the first node N1, a first electrode of the third transistor T3 is electrically connected to the second node N2, and a second electrode of the third transistor T3 is electrically connected to the third node N3. A control electrode of the fourth transistor T4 is electrically connected to the first light emitting signal line EM1, a first electrode of the fourth transistor T4 is electrically connected to the first power supply line VDD, and a second electrode of the fourth transistor T4 is electrically connected to the second node N2. A control electrode of the fifth transistor T5 is electrically connected to the second light emitting signal line EM2, a first electrode of the fifth transistor T5 is electrically connected to the third node N3, and a second electrode of the fifth transistor T5 is electrically connected to the fourth node N4. A control electrode of the eighth transistor T8 is electrically connected to the third reset signal line Reset3, a first electrode of the eighth transistor T8 is electrically connected to the dynamic signal line Var, and a second electrode of the eighth transistor T8 is electrically connected to the fourth node N4. A first terminal of the first capacitor C1 is electrically connected to the first power supply line VDD, and a second terminal of the first capacitor C1 is electrically connected to the first node N1. A first terminal of the second capacitor C2 is electrically connected to the third node N3, and a second terminal of the second capacitor C2 is electrically connected to the fourth node N4.

[0193] In an exemplary embodiment, any of the first transistor T1 to the fifth transistor T5 and the eighth transistor T8 in FIGS. 22A and 22B may be an N-type transistor or a P-type transistor. The first transistor T1 to the fifth transistor T5 and the eighth transistor T8 may all be N-type transistors, or the first transistor T1 to the fifth transistor T5 and the eighth transistor T8 may all be P-type transistors. Use of a same type of transistors in a pixel driving circuit may simplify a process flow, reduce process difficulties of a display panel, and improve a yield of products. In some possible implementations, the first transistor T1 to the fifth transistor T5 and the eighth transistor T8 may include P-type transistors and N-type transistors.

[0194] FIG. 22A is illustrated by taking a case in which any of the first transistor T1 to the fifth transistor T5, and the eighth transistor T8 is an N-type transistor as an example, and FIG. 22B is illustrated by taking a case in which the first transistor T1, the second transistor T2, the third transistor T3, and the eighth transistor T8 are N-type transistors, and the fourth transistor T4 and the fifth transistor T5 are P-type transistors as an example.

[0195] In an exemplary embodiment, one of the fourth transistor T4 and the fifth transistor T5 may be a P-type transistor according to actual needs, for example, the fourth transistor T4 may be a P-type transistor, or the fifth transistor T5 may be a P-type transistor.

[0196] In an exemplary embodiment, the P-type transistor may be a Low Temperature Poly-Silicon (LTPS) thin film transistor, and the N-type transistor may be an oxide thin film transistor.

[0197] The pixel driving circuit provided in FIG. 22B has a fourth transistor T4 and a fifth transistor T5 of a different transistor type from the pixel driving circuit provided in FIG. 22A. The fourth transistor T4 and the fifth transistor T5 in the pixel driving circuit provided in FIG. 22B are P-type transistors, which can reduce a width-to-length ratio of a channel region of at least one transistor of the fourth transistor T4 and the fifth transistor T5, improve the mobility of at least one transistor of the fourth transistor T4 and the fifth transistor T5, and further reduce the switching power consumption of at least one of the fourth transistor T4 and the fifth transistor T5, thereby reducing the power consumption of the display apparatus where the pixel driving circuit is located.

[0198] FIG. 23 is a schematic diagram of a structure of a display apparatus in which the pixel driving circuit provided in FIG. 22 is located. As illustrated in FIG. 23, in an exemplary embodiment, the display apparatus further includes a third control unit electrically connected to the first light emitting signal line EM1 and configured to provide a signal to the first light emitting signal line EM1, wherein, in at least one display frame, a start time of at least one time period in which the first control unit provides an effective level signal to the second light emitting signal line EM2 is earlier than a start time at which the second control unit provides an ineffective level signal to the third reset signal line Reset3, and a start time of at least one time period in which the third control unit provides an effective level signal to the first light emitting signal line EM1 is later than a start time at which the second control unit provides an ineffective level signal to the third reset signal line Reset3.

[0199] FIG. 24 is a second schematic diagram of a structure of the pixel driving circuit provided in FIG. 19. As shown in FIG. 24, the at least one reset signal line includes a first reset signal line Reset1 and a third reset signal line Reset3. The third control sub-circuit is electrically connected to the third node N3, the fourth node N4, the first reset signal line Reset1, the third reset signal line Reset3, and the dynamic signal line Var, respectively.

[0200] FIG. 25A is a first equivalent circuit diagram of the pixel driving circuit provided in FIG. 24, and FIG. 25B is a second equivalent circuit diagram of the pixel driving circuit provided in FIG. 24. As shown in FIGS. 25A and 25B, the driving sub-circuit includes a third transistor T3, the first control sub-circuit includes a first transistor T1 and a second transistor T2, the second control sub-circuit includes a fourth transistor T4 and a fifth transistor T5, the storage sub-circuit includes a first capacitor C1, and the third control sub-circuit includes a second capacitor C2, a sixth transistor T6, and an eighth transistor T8. Herein, a control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, a first electrode of the first transistor T1 is electrically connected to the data signal line Data, and a second electrode of the first transistor T1 is electrically connected to the first node N1; a control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, a first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and a second electrode of the second transistor T2 is electrically connected to the first node N1; a control electrode of the third transistor T3 is electrically connected to the first node N1, a first electrode of the third transistor T3 is electrically connected to the second node N2, and a second electrode of the third transistor T3 is electrically connected to the third node N3; a control electrode of the fourth transistor T4 is electrically connected to the first light emitting signal line EM1, a first electrode of the fourth transistor T4 is electrically connected to the first power supply line VDD, and a second electrode of the fourth transistor T4 is electrically connected to the second node N2; a control electrode of the fifth transistor T5 is electrically connected to the second light emitting signal line EM2, a first electrode of the fifth transistor T5 is electrically connected to the third node N3, and a second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; a control electrode of the sixth transistor T6 is electrically connected to the first reset signal line Reset1, a first electrode of the sixth transistor T6 is electrically connected to the fifth node N5, and a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4; a control electrode of the eighth transistor T8 is electrically connected to the third reset signal line Reset3, a first electrode of the eighth transistor T8 is electrically connected to the dynamic signal line Var, a second electrode of the eighth transistor T8 is electrically connected to the fourth node N4, a first terminal of the first capacitor C1 is electrically connected to the first power supply line VDD, and a second terminal of the first capacitor C1 is electrically connected to the first node N1; a first terminal of the second capacitor C2 is electrically connected to the third node N3, and a second terminal of the second capacitor C2 is electrically connected to the fifth node N5.

[0201] FIG. 26A is a third equivalent circuit diagram of the pixel driving circuit provided in FIG. 24, and FIG. 26B is a fourth equivalent circuit diagram of the pixel driving circuit provided in FIG. 24. As shown in FIGS. 26A and 26B, the driving sub-circuit includes a third transistor T3, the first control sub-circuit includes a first transistor T1 and a second transistor T2, the second control sub-circuit includes a fourth transistor T4 and a fifth transistor T5, the storage sub-circuit includes a first capacitor C1, and the third control sub-circuit includes a second capacitor C2, a third capacitor C3, a sixth transistor T6, and an eighth transistor T8. Herein, a control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, a first electrode of the first transistor T1 is electrically connected to the data signal line Data, and a second electrode of the first transistor T1 is electrically connected to the first node N1; a control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, a first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and a second electrode of the second transistor T2 is electrically connected to the first node N1; a control electrode of the third transistor T3 is electrically connected to the first node N1, a first electrode of the third transistor T3 is electrically connected to the second node N2, and a second electrode of the third transistor T3 is electrically connected to the third node N3; a control electrode of the fourth transistor T4 is electrically connected to the first light emitting signal line EM1, a first electrode of the fourth transistor T4 is electrically connected to the first power supply line VDD, and a second electrode of the fourth transistor T4 is electrically connected to the second node N2; a control electrode of the fifth transistor T5 is electrically connected to the second light emitting signal line EM2, a first electrode of the fifth transistor T5 is electrically connected to the third node N3, and a second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; a control electrode of the sixth transistor T6 is electrically connected to the first reset signal line Reset1, and a first electrode of the sixth transistor T6 is electrically connected to the fifth node N5; a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4; a control electrode of the eighth transistor T8 is electrically connected to the third reset signal line Reset3, a first electrode of the eighth transistor T8 is electrically connected to the dynamic signal line Var, and a second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; a first terminal of the first capacitor C1 is electrically connected to the first power supply line VDD, and a second terminal of the first capacitor C1 is electrically connected to the first node N1; a first terminal of the second capacitor C2 is electrically connected to the third node N3, and a second terminal of the second capacitor C2 is electrically connected to the fifth node N5; and a first terminal of the third capacitor C3 is electrically connected to the fifth node N5, and a second terminal of the third capacitor C3 is electrically connected to the fourth node N4.

[0202] In an exemplary embodiment, any of the first transistor T1 to the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 in FIGS. 25A, 25B, 26A, and 26B may be an N-type transistor or a P-type transistor. The first transistor T1 to the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 may all be N-type transistors, or the first transistor T1 to the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 may all be P-type transistors. Use of a same type of transistors in a pixel driving circuit may simplify a process flow, reduce process difficulties of a display panel, and improve a yield of products. In some possible implementations, the first transistor T1 to the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 may include P-type transistor(s) and N-type transistor(s).

[0203] FIGS. 25A and 26A are illustrated by taking a case in which any of the first transistor T1 to the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 is an N-type transistor as an example, and FIGS. 25B and 26B are illustrated by taking a case in which the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, and the eighth transistor T8 are N-type transistors, and the fourth transistor T4 and the fifth transistor T5 are P-type transistors as an example.

[0204] In an exemplary embodiment, one of the fourth transistor T4 and the fifth transistor T5 may be a P-type transistor according to actual needs, for example, the fourth transistor T4 may be a P-type transistor, or the fifth transistor T5 may be a P-type transistor.

[0205] In an exemplary embodiment, the P-type transistor may be a Low Temperature Poly-Silicon (LTPS) thin film transistor, and the N-type transistor may be an oxide thin film transistor.

[0206] The pixel driving circuit provided in FIG. 25B has a fourth transistor T4 and a fifth transistor T5 of a different transistor type from the pixel driving circuit provided in FIG. 25A. The fourth transistor T4 and the fifth transistor T5 in the pixel driving circuit provided in FIG. 25B are P-type transistors, which can reduce a width-to-length ratio of a channel region of at least one transistor of the fourth transistor T4 and the fifth transistor T5, improve the mobility of at least one transistor of the fourth transistor T4 and the fifth transistor T5, and further reduce the switching power consumption of at least one of the fourth transistor T4 and the fifth transistor T5, thereby reducing the power consumption of the display apparatus where the pixel driving circuit is located.

[0207] The pixel driving circuit provided in FIG. 26B has a fourth transistor T4 and a fifth transistor T5 of a different transistor type from the pixel driving circuit provided in FIG. 26A. The fourth transistor T4 and the fifth transistor T5 in the pixel driving circuit provided in FIG. 26B are P-type transistors, which can reduce a width-to-length ratio of a channel region of at least one transistor of the fourth transistor T4 and the fifth transistor T5, improve the mobility of at least one transistor of the fourth transistor T4 and the fifth transistor T5, and further reduce the switching power consumption of at least one of the fourth transistor T4 and the fifth transistor T5, thereby reducing the power consumption of the display apparatus where the pixel driving circuit is located.

[0208] FIG. 27 is a third schematic diagram of a structure of the pixel driving circuit provided in FIG. 19. As shown in FIG. 27, the at least one reset signal line includes a first reset signal line Reset1 and a third reset signal line Reset3. The third control sub-circuit is electrically connected to the third node N3, the fourth node N4, the first reset signal line Reset1, the third reset signal line Reset3, the dynamic signal line Var, and the auxiliary signal line VX, respectively.

[0209] FIG. 28A is a first equivalent circuit diagram of the pixel driving circuit provided in FIG. 27, and FIG. 28B is a second equivalent circuit diagram of the pixel driving circuit provided in FIG. 27. As shown in FIGS. 28A and 28B, the driving sub-circuit includes a third transistor T3, the first control sub-circuit includes a first transistor T1 and a second transistor T2, the second control sub-circuit includes a fourth transistor T4 and a fifth transistor T5, and the storage sub-circuit includes a first capacitor C1; the third control sub-circuit includes a second capacitor C2, a third capacitor C3, a sixth transistor T6, and an eighth transistor T8. Herein, a control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, a first electrode of the first transistor T1 is electrically connected to the data signal line Data, and a second electrode of the first transistor T1 is electrically connected to the first node N1; a control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, a first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and a second electrode of the second transistor T2 is electrically connected to the first node N1; a control electrode of the third transistor T3 is electrically connected to the first node N1, a first electrode of the third transistor T3 is electrically connected to the second node N2, and a second electrode of the third transistor T3 is electrically connected to the third node N3; a control electrode of the fourth transistor T4 is electrically connected to the first light emitting signal line EM1, a first electrode of the fourth transistor T4 is electrically connected to the first power supply line VDD, and a second electrode of the fourth transistor T4 is electrically connected to the second node N2; a control electrode of the fifth transistor T5 is electrically connected to the second light emitting signal line EM2, a first electrode of the fifth transistor T5 is electrically connected to the third node N3, and a second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; a control electrode of the sixth transistor T6 is electrically connected to the first reset signal line Reset1, a first electrode of the sixth transistor T6 is electrically connected to the fifth node N5, and a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4; a control electrode of the eighth transistor T8 is electrically connected to the third reset signal line Reset3, a first electrode of the eighth transistor T8 is electrically connected to the dynamic signal line Var, and a second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; a first terminal of the first capacitor C1 is electrically connected to the first power supply line VDD, and a second terminal of the first capacitor C1 is electrically connected to the first node N1; a first terminal of the second capacitor C2 is electrically connected to the third node N3, and a second terminal of the second capacitor C2 is electrically connected to the fifth node N5; a first terminal of the third capacitor C3 is electrically connected to the fifth node N5, and a second terminal of the third capacitor C3 is electrically connected to the auxiliary signal line VX.

[0210] In an exemplary embodiment, any of the first transistor T1 to the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 in FIGS. 28A and 28B may be an N-type transistor or a P-type transistor. The first transistor T1 to the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 may all be N-type transistors, or the first transistor T1 to the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 may all be P-type transistors. Use of a same type of transistors in a pixel driving circuit may simplify a process flow, reduce process difficulties of a display panel, and improve a yield of products. In some possible implementations, the first transistor T1 to the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 may include P-type transistor(s) and N-type transistor(s).

[0211] FIG. 28A is illustrated by taking a case in which any of the first transistor T1 to the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 is an N-type transistor as an example, and FIG. 28B is illustrated by taking a case in which the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, and the eighth transistor T8 are N-type transistors, and the fourth transistor T4, and the fifth transistor T5 are P-type transistors as an example.

[0212] In an exemplary embodiment, one of the fourth transistor T4 and the fifth transistor T5 may be a P-type transistor according to actual needs, for example, the fourth transistor T4 may be a P-type transistor, or the fifth transistor T5 may be a P-type transistor.

[0213] In an exemplary embodiment, the P-type transistor may be a Low Temperature Poly-Silicon (LTPS) thin film transistor, and the N-type transistor may be an oxide thin film transistor.

[0214] The pixel driving circuit provided in FIG. 28B has a fourth transistor T4 and a fifth transistor T5 of a different transistor type from the pixel driving circuit provided in FIG. 28A. The fourth transistor T4 and the fifth transistor T5 in the pixel driving circuit provided in FIG. 28B are P-type transistors, which can reduce a width-to-length ratio of a channel region of at least one transistor of the fourth transistor T4 and the fifth transistor T5, improve the mobility of at least one transistor of the fourth transistor T4 and the fifth transistor T5, and further reduce the switching power consumption of at least one of the fourth transistor T4 and the fifth transistor T5, thereby reducing the power consumption of the display apparatus where the pixel driving circuit is located.

[0215] FIG. 29 is a fourth schematic diagram of a structure of the pixel driving circuit provided in FIG. 19. As shown in FIG. 29, the at least one reset signal line includes a first reset signal line Reset1 and a third reset signal line Reset3. The third control sub-circuit is electrically connected to the third node N3, the fourth node N4, the first reset signal line Reset1, the third reset signal line Reset3, and the auxiliary signal line VX, respectively.

[0216] FIG. 30A is a first equivalent circuit diagram of the pixel driving circuit provided in FIG. 29, and FIG. 30B is a second equivalent circuit diagram of the pixel driving circuit provided in FIG. 29. As shown in FIGS. 30A and 30B, the driving sub-circuit includes a third transistor T3, the first control sub-circuit includes a first transistor T1 and a second transistor T2, the second control sub-circuit includes a fourth transistor T4 and a fifth transistor T5, and the storage sub-circuit includes a first capacitor C1; the third control sub-circuit includes a second capacitor C2, a third capacitor C3, a sixth transistor T6, and a ninth transistor T9. Herein, a control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, a first electrode of the first transistor T1 is electrically connected to the data signal line Data, and a second electrode of the first transistor T1 is electrically connected to the first node N1; a control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, a first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and a second electrode of the second transistor T2 is electrically connected to the first node N1; a control electrode of the third transistor T3 is electrically connected to the first node N1, a first electrode of the third transistor T3 is electrically connected to the second node N2, and a second electrode of the third transistor T3 is electrically connected to the third node N3; a control electrode of the fourth transistor T4 is electrically connected to the first light emitting signal line EM1, a first electrode of the fourth transistor T4 is electrically connected to the first power supply line VDD, and a second electrode of the fourth transistor T4 is electrically connected to the second node N2; a control electrode of the fifth transistor T5 is electrically connected to the second light emitting signal line EM2, a first electrode of the fifth transistor T5 is electrically connected to the third node N3, and a second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; a control electrode of the sixth transistor T6 is electrically connected to the first reset signal line Reset1, a first electrode of the sixth transistor T6 is electrically connected to the fifth node N5, and a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4; a control electrode of the ninth transistor T9 is electrically connected to the third reset signal line Reset3, a first electrode of the ninth transistor T9 is electrically connected to the auxiliary signal line VX, and a second electrode of the ninth transistor T9 is electrically connected to the fifth node N5; a first terminal of the first capacitor C1 is electrically connected to the first power supply line VDD, and a second terminal of the first capacitor C1 is electrically connected to the first node N1; a first terminal of the second capacitor C2 is electrically connected to the third node N3, and a second terminal of the second capacitor C2 is electrically connected to the fifth node N5; a first terminal of the third capacitor C3 is electrically connected to the fifth node N5, and a second terminal of the third capacitor C3 is electrically connected to the fourth node N4.

[0217] In an exemplary embodiment, any of the first transistor T1 to the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 in FIGS. 30A and 30B may be an N-type transistor or a P-type transistor. The first transistor T1 to the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 may all be N-type transistors, or the first transistor T1 to the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 may all be P-type transistors. Use of a same type of transistors in a pixel driving circuit may simplify a process flow, reduce process difficulties of a display panel, and improve a yield of products. In some possible implementations, the first transistor T1 to the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 may include a P-type transistor and an N-type transistor.

[0218] FIG. 30A is illustrated by taking a case in which any of the first transistor T1 to the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 is an N-type transistor as an example, and FIG. 30B is illustrated by taking a case in which the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, and the ninth transistor T9 are N-type transistors, and the fourth transistor T4, and the fifth transistor T5 are P-type transistors as an example.

[0219] In an exemplary embodiment, one of the fourth transistor T4 and the fifth transistor T5 may be a P-type transistor according to actual needs, for example, the fourth transistor T4 may be a P-type transistor, or the fifth transistor T5 may be a P-type transistor.

[0220] In an exemplary embodiment, the P-type transistor may be a Low Temperature Poly-Silicon (LTPS) thin film transistor, and the N-type transistor may be an oxide thin film transistor. The pixel driving circuit provided in FIG. 30B has a fourth transistor T4 and a fifth transistor T5 of a different transistor type from the pixel driving circuit provided in FIG. 30A. The fourth transistor T4 and the fifth transistor T5 in the pixel driving circuit provided in FIG. 30B are P-type transistors, which can reduce a width-to-length ratio of a channel region of at least one transistor of the fourth transistor T4 and the fifth transistor T5, improve the mobility of at least one transistor of the fourth transistor T4 and the fifth transistor T5, and further reduce the switching power consumption of at least one of the fourth transistor T4 and the fifth transistor T5, thereby reducing the power consumption of the display apparatus where the pixel driving circuit is located.

[0221] FIG. 31 is a schematic diagram of a structure of a display apparatus in which the pixel driving circuits provided in FIGS. 25, 26, 28, and 30 is located. As shown in FIG. 31, the display apparatus may further include a third control unit electrically connected to the first light emitting signal line EM1 and configured to provide a signal to the first light emitting signal line EM1, the second control unit includes a first sub-control unit and a second sub-control unit, the first sub-control unit is electrically connected to the first reset signal line Reset1 and configured to provide a signal to the first reset signal line Reset1, the second sub-control unit is electrically connected to the first reset signal line Reset3 and configured to provide a signal to the first reset signal line Reset3, wherein, in at least one display frame, at least one of the start time at which the first sub-control unit provides an ineffective level signal to the first reset signal line Reset1 and the start time at which the second sub-control unit provides an ineffective level signal to the third reset signal line Reset3 is later than the start time of at least one time period in which the first control unit provides an effective level signal to the second light emitting signal line EM2, and is earlier than the start time of at least one time period in which the third control unit provides the effective level signal to the first light emitting signal line EM1, and the start time in which the first sub-control unit provides the ineffective level signal to the first reset signal line Reset1 is earlier than the start time in which the second sub-control unit provides the ineffective level signal to the third reset signal line Reset3.

[0222] FIG. 32 is a fifth schematic diagram of a structure of the pixel driving circuit provided in FIG. 19. As shown in FIG. 32, the at least one reset signal line includes a first reset signal line Reset1, a third reset signal line Reset3, and a fourth reset signal line Reset4. The third control sub-circuit is electrically connected to the third node N3, the fourth node N4, the first reset signal line Reset1, the third reset signal line Reset3, the fourth reset signal line Reset4, the dynamic signal line Var, and the auxiliary signal line VX, respectively.

[0223] FIG. 33A is a first equivalent circuit diagram of the pixel driving circuit provided in FIG. 32, and FIG. 33B is a second equivalent circuit diagram of the pixel driving circuit provided in FIG. 32. As shown in FIGS. 33A and 33B, the driving sub-circuit includes a third transistor T3, the first control sub-circuit includes a first transistor T1 and a second transistor T2, the second control sub-circuit includes a fourth transistor T4 and a fifth transistor T5, the storage sub-circuit includes a first capacitor C1, and the third control sub-circuit includes a second capacitor C2, a third capacitor C3, a sixth transistor T6, an eighth transistor T8, and a ninth transistor T9. Herein, a control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, a first electrode of the first transistor T1 is electrically connected to the data signal line Data, and a second electrode of the first transistor T1 is electrically connected to the first node N1; a control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, a first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and a second electrode of the second transistor T2 is electrically connected to the first node N1; a control electrode of the third transistor T3 is electrically connected to the first node N1, a first electrode of the third transistor T3 is electrically connected to the second node N2, and a second electrode of the third transistor T3 is electrically connected to the third node N3; a control electrode of the fourth transistor T4 is electrically connected to the first light emitting signal line EM1, a first electrode of the fourth transistor T4 is electrically connected to the first power supply line VDD, and a second electrode of the fourth transistor T4 is electrically connected to the second node N2; a control electrode of the fifth transistor T5 is electrically connected to the second light emitting signal line EM2, a first electrode of the fifth transistor T5 is electrically connected to the third node N3, and a second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; a control electrode of the sixth transistor T6 is electrically connected to the first reset signal line Reset1, a first electrode of the sixth transistor T6 is electrically connected to the fifth node N5, and a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4; a control electrode of the eighth transistor T8 is electrically connected to the third reset signal line Reset3, a first electrode of the eighth transistor T8 is electrically connected to the dynamic signal line Var, and a second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; a control electrode of the ninth transistor T9 is electrically connected to the fourth reset signal line Reset4, a first electrode of the ninth transistor T9 is electrically connected to the auxiliary signal line VX, and a second electrode of the ninth transistor T9 is electrically connected to the fifth node N5; a first terminal of the first capacitor C1 is electrically connected to the first power supply line VDD, and a second terminal of the first capacitor C1 is electrically connected to the first node N1; a first terminal of the second capacitor C2 is electrically connected to the third node N3, and a second terminal of the second capacitor C2 is electrically connected to the fifth node N5; a first terminal of the third capacitor C3 is electrically connected to the fifth node N5, and a second terminal of the third capacitor C3 is electrically connected to the fourth node N4.

[0224] In an exemplary embodiment, any of the first transistor T1 to the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 in FIGS. 33A and 33B may be an N-type transistor or a P-type transistor. The first transistor T1 to the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 may all be N-type transistors, or the first transistor T1 to the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 may all be P-type transistors. Use of a same type of transistors in a pixel drive circuit may simplify a process flow, reduce process difficulties of a display panel, and improve a yield of products. In some possible implementations, the first transistor T1 to the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 may include a P-type transistor and an N-type transistor.

[0225] FIG. 33A is illustrated by taking a case in which any of the first transistor T1 to the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 is an N-type transistor as an example, and FIG. 33B is illustrated by taking a case in which the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are N-type transistors, and the fourth transistor T4 and the fifth transistor T5 are P-type transistors as an example.

[0226] In an exemplary embodiment, one of the fourth transistor T4 and the fifth transistor T5 may be a P-type transistor according to actual needs, for example, the fourth transistor T4 may be a P-type transistor, or the fifth transistor T5 may be a P-type transistor.

[0227] In an exemplary embodiment, the P-type transistor may be a Low Temperature Poly-Silicon (LTPS) thin film transistor, and the N-type transistor may be an oxide thin film transistor. The pixel driving circuit provided in FIG. 33B has a fourth transistor T4 and a fifth transistor T5 of a different transistor type from the pixel driving circuit provided in FIG. 33A. The fourth transistor T4 and the fifth transistor T5 in the pixel driving circuit provided in FIG. 33B are P-type transistors, which can reduce a width-to-length ratio of a channel region of at least one transistor of the fourth transistor T4 and the fifth transistor T5, improve the mobility of at least one transistor of the fourth transistor T4 and the fifth transistor T5, and further reduce the switching power consumption of at least one of the fourth transistor T4 and the fifth transistor T5, thereby reducing the power consumption of the display apparatus where the pixel driving circuit is located.

[0228] FIG. 34 is a schematic diagram of a structure of a display apparatus in which the pixel driving circuit provided in FIG. 33 is located. As shown in FIG. 34, the display apparatus may further include: a third control unit electrically connected to the first light emitting signal line EM1 and configured to provide a signal to the first light emitting signal line EM1, and the second control unit includes a first sub-control unit, a second sub-control unit and a third sub-control unit, wherein the first sub-control unit is electrically connected with the first reset signal line Reset1 and is configured to provide a signal to the first reset signal line Reset1, the second sub-control unit is electrically connected with the third reset signal line Reset3 and is configured to provide a signal to the third reset signal line Reset3, the third sub-control unit is electrically connected with the fourth reset signal line Reset4 and is configured to provide a signal to the fourth reset signal line Reset4; in at least one display frame, at least one of the start time at which the first sub-control unit provides an ineffective level signal to the first reset signal line Reset1, the start time at which the second sub-control unit provides an ineffective level signal to the third reset signal line Reset3, and the start time at which the third sub-control unit provides an ineffective level signal to the fourth reset signal line Reset4 is later than the start time of at least one time period in which the first control unit provides an effective level signal to the second light emitting signal line EM2, and is earlier than the start time of at least one time period in which the third control unit provides the effective level signal to the first light emitting signal line EM1, the start time at which the first sub-control unit provides an ineffective level signal to the first reset signal line Reset1 is earlier than at least one of the start time at which the second sub-control unit provides an ineffective level signal to the third reset signal line Reset3 and the start time at which the third sub-control unit provides an ineffective level signal to the fourth reset signal line Reset4.

[0229] In an exemplary embodiment, as illustrated in FIGS. 23, 31, and 34, the display apparatus may further include a fourth control unit and a fifth control unit, wherein the fourth control unit is electrically connected to the first scan signal line G1 and configured to provide a signal to the first scan signal line G1, and the fifth control unit is electrically connected to the second scan signal line G2 and configured to provide a signal to the second scan signal line G2. In at least one display frame, the end time at which the fifth control unit provides an effective level signal to the second scan signal line G2 is earlier than the start time at which the fourth control unit provides an effective level signal to the first scan signal line G1, and the start time at which the fourth control unit provides the effective level signal to the first scan signal line G1 is earlier than the start time of at least one time period in which the first control unit provides an effective level signal to the second light emitting signal line EM2.

[0230] In an exemplary embodiment, a signal of the auxiliary signal line VX is a DC signal, and may be a constant voltage signal.

[0231] In an exemplary embodiment, a signal of the auxiliary signal line VX may be a signal of at least one signal line of the first power supply line VDD, the reference signal line REF, and the initial signal line INIT.

[0232] In an exemplary embodiment, a signal of the initial signal line is a DC signal, and may be a constant voltage signal.

[0233] In an exemplary embodiment, the change of the voltage value of the dynamic signal provided by the dynamic signal line Var affects the voltage of the third node N3, thereby affecting the voltage difference between the control electrode (that is, the first node N1) and the second electrode (that is, the third node N3) of the third transistor T3 (that is, the driving transistor), and finally affecting the magnitude of the light emitting current. When the temperature of the display apparatus rises, the voltage value of the dynamic signal provided by the dynamic signal line Var is adjusted to reduce the light emitting current, so that the temperature of the display apparatus is reduced, and thus the brightness uniformity of the display apparatus is ensured.

[0234] FIG. 35A is a first working timing diagram of the pixel driving circuit provided in FIG. 22A, which further illustrates the pixel driving circuit according to the present disclosure in conjunction with FIGS. 22A and 35A.

[0235] In a first stage P11 referred to as a reset stage, signals of the second scan signal line G2, the second light emitting signal line EM2, and the third reset signal line Reset3 are high-level signals, and signals of the first scan signal line G1 and the first light emitting signal line EM1 are low-level signals. When the signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is written into the first node N1, to initialize (reset) a signal of the first node N1 and clear original charges in the first node N1. Signals of the second light emitting signal line EM2 and the third reset signal line Reset3 are high-level signals, the fifth transistor T5 and the eighth transistor T8 are turned on, and a signal of the dynamic signal line Var is written into the third node N3 and the fourth node N4, respectively. Because a voltage value of a signal of the first node N1 and a voltage value of a signal of the third node N3 are greater than a threshold voltage of the third transistor T3, at this time, the third transistor T3 is turned on, and a signal of the dynamic signal line Var is written into the second node N2, to initialize (reset) signals of the second node N2, the third node N3 and the fourth node N4 and clear original charges in the second node N2, the third node N3 and the fourth node N4. Signals of the first scan signal line G1 and the first light emitting signal line EM1 are low-level signals, and the first transistor T1 and the fourth transistor T4 are turned off. The light emitting device L does not emit light in this stage.

[0236] In a second stage P12, that is, a threshold compensation stage, signals of the third reset signal line Reset3, the second scan signal line G2 and the first light emitting signal line EM1 are high-level signals, and signals of the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals. A signal of the third reset signal line Reset3 is a high-level signal, the eighth transistor T8 is turned on, a signal of the dynamic signal line Var is continuously written to the fourth node N4, to continuously initialize (reset) a signal of the fourth node N4. A signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is continuously provided to the first node N1, a signal of the first light emitting signal line EM1 is a high-level signal, the fourth transistor T4 is turned on, and a signal of the first power supply line VDD is written to the third node N3 through the turned-on fourth transistor T4, the second node N2 and the turned-on third transistor T3 until a voltage V3 of a signal of the third node N3 meets V3=Vref-Vth, wherein Vref is a voltage value of a signal of the reference signal line REF, and Vth is the threshold voltage of the third transistor T3, at this time, the first capacitor C1 stores a voltage difference Vth between signals of the first node N1 and the third node N3. Signals of the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals, and the first transistor T1 and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0237] In a third stage P13, that is, a data writing stage, a signal of the third reset signal line Reset is a high-level signal, signals of the second scan signal line G2, the first light emitting signal line EM1, and the second light emitting signal line EM2 are low-level signals, the signal of the first scan signal line G1 is a high-level signal for part of a time period, and the data signal line Data outputs a data voltage. A signal of the third reset signal line Reset3 is a high-level signal, the eighth transistor T8 is turned on, a signal of the dynamic signal line Var is continuously written to the fourth node N4, to continuously initialize (reset) a signal of the fourth node N4. A signal of the first scan signal line G1 is a high-level signal, the first transistor T1 is turned on, and the data voltage of the data signal line Data is written to the first node N1. At this time, the voltage value V1 of the first node N1 meets V1=Vdata, and Vdata is the data voltage of the data signal line. The voltage value of the signal of the first node N1 in the present stage undergoes a jump compared to the voltage value in the previous stage. Therefore, a signal of the third node N3 also undergoes a jump under an action of the first capacitor C1 and the second capacitor C2. At this time, the voltage value V3 of the signal of the third node N3 meets V3=Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 ), where C 1 is the capacitance value of the first capacitor, C 2 is the capacitance value of the second capacitor. Signals of the second scan signal line G2, the first light emitting signal line EM1, and the second light emitting signal line EM2 are low-level signals, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0238] In a fourth stage P14, that is, a light emitting stage, signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, and signals of the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals. Signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, a power supply voltage output from the first power supply line VDD provides a driving voltage to a first electrode of the light emitting device L through the turned-on fourth transistor T4, third transistor T3 and fifth transistor T5 to drive the light emitting device L to emit light, signals of the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals, and the first transistor T1, the second transistor T2 and the eighth transistor T8 are turned off, and the light emitting device L emits light in this stage.

[0239] In a drive process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by a voltage difference between the control electrode (also the first node N1) and the second electrode (also the third node N3) of the third transistor T3. Because the voltage value V1 of the signal of the first node meets V1= Vdata-[Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 )]+ Vinit and the voltage value V3 of the signal of the third node N3 meets V3=Vinit, the driving current of the third transistor T3 is as follows. I = K * Vgs − Vth 2 = K * Vdata − Vref − Vth + Vdata − Vref * C 1 / C 1 + C 2 − Vth 2 = K * C 2 / C 1 + C 2 * Vdata − Vref 2

[0240] Herein, I is a driving current flowing through the third transistor T3, that is, a driving current driving the light emitting device L, K is a constant, and Vgs is a voltage difference between the control electrode and the second electrode of the third transistor T3.

[0241] It may be seen from a derivation result of the above current formula that in the light emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3. Therefore, an influence of the threshold voltage of the third transistor T3 on the driving current is eliminated, which may ensure uniformity of display brightness of a display product, and improve an overall display effect of the display product.

[0242] FIG. 35B is a second working timing diagram of the pixel driving circuit provided in FIG. 22A, and the pixel driving circuit according to the present disclosure is further described in conjunction with FIGS. 22A and 35B.

[0243] In a first stage P21 referred to as a reset stage, signals of the second scan signal line G2, the second light emitting signal line EM2 and the third reset signal line Reset3 are high-level signals, and signals of the first scan signal line G1 and the first light emitting signal line EM1 are low-level signals. When the signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is written into the first node N1, to initialize (reset) a signal of the first node N1 and clear original charges in the first node N1. Signals of the second light emitting signal line EM2 and the third reset signal line Reset3 are high-level signals, the fifth transistor T5 and the eighth transistor T8 are turned on, and a signal of the dynamic signal line Var is written into the third node N3 and the fourth node N4, respectively. Because a voltage value of a signal of the first node N1 and a voltage value of a signal of the third node N3 are greater than a threshold voltage of the third transistor T3, at this time, the third transistor T3 is turned on, and a signal of the dynamic signal line Var is written into the second node N2, to initialize (reset) signals of the second node N2, the third node N3 and the fourth node N4 and clear original charges in the second node N2, the third node N3 and the fourth node N4. Signals of the first scan signal line G1 and the first light emitting signal line EM1 are low-level signals, and the first transistor T1 and the fourth transistor T4 are turned off. The light emitting device L does not emit light in this stage.

[0244] In a second stage P22, that is, a threshold compensation stage, signals of the third reset signal line Reset3, the second scan signal line G2 and the first light emitting signal line EM1 are high-level signals, and signals of the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals. A signal of the third reset signal line Reset3 is a high-level signal, the eighth transistor T8 is turned on, a signal of the dynamic signal line Var is continuously written to the fourth node N4, to continuously initialize (reset) a signal of the fourth node N4. A signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is continuously provided to the first node N1, a signal of the first light emitting signal line EM1 is a high-level signal, the fourth transistor T4 is turned on, and a signal of the first power supply line VDD is written to the third node N3 through the turned-on fourth transistor T4, the second node N2 and the turned-on third transistor T3 until a voltage V3 of a signal of the third node N3 meets V3=Vref-Vth, wherein Vref is a voltage value of a signal of the reference signal line REF, and Vth is the threshold voltage of the third transistor T3, at this time, the first capacitor C1 stores a voltage difference Vth between signals of the first node N1 and the third node N3. Signals of the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals, and the first transistor T1 and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0245] In a third stage P23, that is, a data writing stage, a signal of the third reset signal line Reset is a high-level signal, signals of the second scan signal line G2, the first light emitting signal line EM1, and the second light emitting signal line EM2 are low-level signals, the signal of the first scan signal line G1 is a high-level signal for part of a time period, and the data signal line Data outputs a data voltage. A signal of the third reset signal line Reset3 is a high-level signal, the eighth transistor T8 is turned on, a signal of the dynamic signal line Var is continuously written to the fourth node N4, to continuously initialize (reset) a signal of the fourth node N4. A signal of the first scan signal line G1 is a high-level signal, the first transistor T1 is turned on, and a data voltage of the data signal line Data is written to the first node N1. At this time, the voltage value V1 of the first node N1 meets V1=Vdata, where Vdata is the data voltage of the data signal line. The voltage value of the signal of the first node N1 in the present stage undergoes a jump compared to the voltage value in the previous stage. Therefore, a signal of the third node N3 also undergoes a jump under an action of the first capacitor C1 and the second capacitor C2. At this time, the voltage value V3 of the signal of the third node N3 meets V3=Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 ), where C 1 is the capacitance value of the first capacitor, C 2 is the capacitance value of the second capacitor. Signals of the second scan signal line G2, the first light emitting signal line EM1, and the second light emitting signal line EM2 are low-level signals, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0246] In a fourth stage P24, a second reset stage, a signal of the second light emitting signal line EM2 is a high-level signal, signals of the first scan signal line G1, the second scan signal line G2, and the first light emitting signal line EM1 are low-level signals, a signal of the third reset signal line Reset3 is a high-level signal for part of a time period and a low-level signal for part of a time period, and a time duration in which the signal of the third reset signal line Reset3 is the high-level signal occurs before a time duration in which the signal is the low-level signal. A signal of the second light emitting signal line EM2 is a high-level signal, the fifth transistor T5 is turned on, and then the eighth transistor T8 is turned off. Although a signal of the third node N3 becomes a signal of the dynamic signal line Var, the voltage difference between signals of the first node N1 and the third node N3 remains unchanged. Signals of the first scan signal line G1, the second scan signal line G2, and the first light emitting signal line EM1 are low-level signals, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0247] In a fifth stage P25, that is, a light emitting stage, signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, and signals of the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals. Signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, a power supply voltage output from the first power supply line VDD provides a driving voltage to a first electrode of the light emitting device L through the turned-on fourth transistor T4, third transistor T3 and fifth transistor T5. to drive the light emitting device L to emit light, signals of the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals, and the first transistor T1, the second transistor T2 and the eighth transistor T8 are turned off, and the light emitting device L emits light in this stage.

[0248] In a drive process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by a voltage difference between the control electrode (also the first node N1) and the second electrode (also the third node N3) of the third transistor T3. Because the voltage value V1 of the signal of the first node meets V1= Vdata-[Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 )]+ Vinit and the voltage value V3 of the signal of the third node N3 meets V3=Vinit, the driving current of the third transistor T3 is as follows. I = K * Vgs − Vth 2 = K * Vdata − Vref − Vth + Vdata − Vref * C 1 / C 1 + C 2 − Vth 2 = K * C 2 / C 1 + C 2 * Vdata − Vref 2

[0249] Herein, I is a driving current flowing through the third transistor T3, that is, a driving current driving the light emitting device L, K is a constant, and Vgs is a voltage difference between the control electrode and the second electrode of the third transistor T3.

[0250] It may be seen from a derivation result of the above current formula that in the light emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3. Therefore, an influence of the threshold voltage of the third transistor T3 on the driving current is eliminated, which may ensure uniformity of display brightness of a display product, and improve an overall display effect of the display product.

[0251] FIG. 36A is a first working timing diagram of the pixel driving circuit provided in FIG. 22B, and the pixel driving circuit according to the present disclosure is further described in conjunction with FIGS. 22B and 36A.

[0252] In a first stage P11 referred to as a reset stage, signals of the second scan signal line G2, the first light emitting signal line EM1 and the third reset signal line Reset3 are high-level signals, and signals of the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals. When the signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is written into the first node N1, to initialize (reset) a signal of the first node N1 and clear original charges in the first node N1. A signal of the second light emitting signal line EM2 is a low-level signal, and a signal of the third reset signal line Reset3 is a high-level signal, the fifth transistor T5 and the eighth transistor T8 are turned on, and a signal of the dynamic signal line Var is written into the third node N3 and the fourth node N4, respectively. Because a voltage value of a signal of the first node N1 and a voltage value of a signal of the third node N3 are greater than a threshold voltage of the third transistor T3, at this time, the third transistor T3 is turned on, and a signal of the dynamic signal line Var is written into the second node N2, to initialize (reset) signals of the second node N2, the third node N3 and the fourth node N4 and clear original charges in the second node N2, the third node N3 and the fourth node N4. A signal of the first scan signal line G1 is a low-level signal, a signal of the first light emitting signal line EM1 is a high-level signal, and the first transistor T1 and the fourth transistor T4 are turned off. The light emitting device L does not emit light in this stage.

[0253] In a second stage P12, that is, a threshold compensation stage, signals of the third reset signal line Reset3, the second scan signal line G2 and the second light emitting signal line EM2 are high-level signals, and signals of the first scan signal line G1 and the first light emitting signal line EM1 are low-level signals. A signal of the third reset signal line Reset3 is a high-level signal, the eighth transistor T8 is turned on, a signal of the dynamic signal line Var is continuously written to the fourth node N4, to continuously initialize (reset) a signal of the fourth node N4. A signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is continuously provided to the first node N1, a signal of the first light emitting signal line EM1 is a low-level signal, the fourth transistor T4 is turned on, and a signal of the first power supply line VDD is written to the third node N3 through the turned-on fourth transistor T4, the second node N2 and the turned-on third transistor T3 until a voltage V3 of a signal of the third node N3 meets V3=Vref-Vth, wherein Vref is a voltage value of a signal of the reference signal line REF, and Vth is the threshold voltage of the third transistor T3, at this time, the first capacitor C1 stores a voltage difference Vth between signals of the first node N1 and the third node N3. A signal of the first scan signal line G1 is a low-level signal, a signal of the second light emitting signal line EM2 is a high-level signal, and the first transistor T1 and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0254] In a third stage P13, that is, a data writing stage, signals of the first light emitting signal line EM1, the second light emitting signal line EM2, and the third reset signal line Reset are high-level signals, a signal of the second scan signal line G2 is a low-level signal, the first scan signal line G1 is a high-level signal for part of a time period, and the data signal line Data outputs a data voltage. A signal of the third reset signal line Reset3 is a high-level signal, the eighth transistor T8 is turned on, a signal of the dynamic signal line Var is continuously written to the fourth node N4, to continuously initialize (reset) a signal of the fourth node N4. A signal of the first scan signal line G1 is a high-level signal, the first transistor T1 is turned on, and a data voltage of the data signal line Data is written to the first node N1. At this time, the voltage value V1 of the first node N1 meets V1=Vdata, wherein Vdata is the data voltage of the data signal line. The voltage value of the signal of the first node N1 in the present stage undergoes a jump compared to the voltage value in the previous stage. Therefore, a signal of the third node N3 also undergoes a jump under an action of the first capacitor C1 and the second capacitor C2. At this time, the voltage value V3 of the signal of the third node N3 meets V3=Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 ), where C 1 is the capacitance value of the first capacitor, C 2 is the capacitance value of the second capacitor. A signal of the second scan signal line G2 is a low-level signal, signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0255] In a fourth stage P14, that is, a light emitting stage, signals of the first light emitting signal line EM1, the second light emitting signal line EM2, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals. Signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are low-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, a power supply voltage output from the first power supply line VDD provides a driving voltage to a first electrode of the light emitting device L through the turned-on fourth transistor T4, third transistor T3 and fifth transistor T5, to drive the light emitting device L to emit light, signals of the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals, and the first transistor T1, the second transistor T2 and the eighth transistor T8 are turned off, and the light emitting device L emits light in this stage.

[0256] In a drive process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by a voltage difference between the control electrode (also the first node N1) and the second electrode (also the third node N3) of the third transistor T3. Because the voltage value V1 of the signal of the first node meets V1= Vdata-[Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 )]+ Vinit and the voltage value V3 of the signal of the third node N3 meets V3=Vinit, the driving current of the third transistor T3 is as follows. I = K * Vgs − Vth 2 = K * Vdata − Vref − Vth + Vdata − Vref * C 1 / C 1 + C 2 − Vth 2 = K * C 2 / C 1 + C 2 * Vdata − Vref 2

[0257] Herein, I is a driving current flowing through the third transistor T3, that is, a driving current driving the light emitting device L, K is a constant, and Vgs is a voltage difference between the control electrode and the second electrode of the third transistor T3.

[0258] It may be seen from a derivation result of the above current formula that in the light emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3. Therefore, an influence of the threshold voltage of the third transistor T3 on the driving current is eliminated, which may ensure uniformity of display brightness of a display product, and improve an overall display effect of the display product.

[0259] FIG. 36B is a second working timing diagram of the pixel driving circuit provided in FIG. 22B, and the pixel driving circuit according to the present disclosure is further described in conjunction with FIGS. 22B and 36B.

[0260] In a first stage P21 referred to as a reset stage, signals of the second scan signal line G2, the first light emitting signal line EM1 and the third reset signal line Reset3 are high-level signals, and signals of the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals. When the signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is written into the first node N1, to initialize (reset) a signal of the first node N1 and clear original charges in the first node N1. A signal of the second light emitting signal line EM2 is a low-level signal and a signal of the third reset signal line Reset3 is a high-level signal, the fifth transistor T5 and the eighth transistor T8 are turned on, and a signal of the dynamic signal line Var is written into the third node N3 and the fourth node N4, respectively. Because a voltage value of a signal of the first node N1 and a voltage value of a signal of the third node N3 are greater than a threshold voltage of the third transistor T3, at this time, the third transistor T3 is turned on, and a signal of the dynamic signal line Var is written into the second node N2, to initialize (reset) signals of the second node N2, the third node N3 and the fourth node N4 and clear original charges in the second node N2, the third node N3 and the fourth node N4. A signal of the first scan signal line G1 is a low-level signal, a signal of the first light emitting signal line EM1 is a high-level signal, and the first transistor T1 and the fourth transistor T4 are turned off. The light emitting device L does not emit light in this stage.

[0261] In a second stage P22, that is, a threshold compensation stage, signals of the third reset signal line Reset3, the second scan signal line G2 and the second light emitting signal line EM2 are high-level signals, and signals of the first scan signal line G1 and the first light emitting signal line EM1 are low-level signals. A signal of the third reset signal line Reset3 is a high-level signal, the eighth transistor T8 is turned on, a signal of the dynamic signal line Var is continuously written to the fourth node N4, to continuously initialize (reset) a signal of the fourth node N4. A signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is continuously provided to the first node N1, a signal of the first light emitting signal line EM1 is a low-level signal, the fourth transistor T4 is turned on, and a signal of the first power supply line VDD is written to the third node N3 through the turned-on fourth transistor T4, the second node N2 and the turned-on third transistor T3 until a voltage V3 of a signal of the third node N3 meets V3=Vref-Vth, wherein Vref is a voltage value of a signal of the reference signal line REF, and Vth is the threshold voltage of the third transistor T3, at this time, the first capacitor C1 stores a voltage difference Vth between signals of the first node N1 and the third node N3. A signal of the first scan signal line G1 is a low-level signal, a signal of the second light emitting signal line EM2 is a high-level signal, and the first transistor T1 and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0262] In a third stage P23, that is, a data writing stage, signals of the third reset signal line Reset, the first light emitting signal line EM1, and the second light emitting signal line EM2 are high-level signals, a signal of the second scan signal line G2 is a low-level signal, the first scan signal line G1 is a high-level signal for part of a time period, and the data signal line Data outputs a data voltage. A signal of the third reset signal line Reset3 is a high-level signal, the eighth transistor T8 is turned on, a signal of the dynamic signal line Var is continuously written to the fourth node N4, to continuously initialize (reset) a signal of the fourth node N4. A signal of the first scan signal line G1 is a high-level signal, the first transistor T1 is turned on, and a data voltage of the data signal line Data is written to the first node N1. At this time, the voltage value V1 of the first node N1 meets V1=Vdata, wherein Vdata is the data voltage of the data signal line. The voltage value of the signal of the first node N1 in the present stage undergoes a jump compared to the voltage value in the previous stage. Therefore, a signal of the third node N3 also undergoes a jump under an action of the first capacitor C1 and the second capacitor C2. At this time, the voltage value V3 of the signal of the third node N3 meets V3=Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 ), where C 1 is the capacitance value of the first capacitor, C 2 is the capacitance value of the second capacitor. A signal of the second scan signal line G2 is a low-level signal, signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0263] In a fourth stage P24, that is, a second reset stage, a signal of the first light emitting signal line EM1 is a high-level signal, signals of the first scan signal line G1, the second scan signal line G2, and the second light emitting signal line EM2 are low-level signals, a signal of the third reset signal line Reset3 is a high-level signal for part of a time period and a low-level signal for part of a time period, and a time duration in which the signal of the third reset signal line Reset3 is the high-level signal occurs before a time duration in which the signal is a low-level signal. A signal of the second light emitting signal line EM2 is a low-level signal, the fifth transistor T5 is turned on, and then the eighth transistor T8 is turned off. Although a signal of the third node N3 becomes a signal of the dynamic signal line Var, the voltage difference between signals of the first node N1 and the third node N3 remains unchanged. Signals of the first scan signal line G1 and the second scan signal line G2 are low-level signals, and a signal of the first light emitting signal line EM1 is a high-level signal, so that the second transistor T2, the fourth first transistor T4 and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0264] In a fifth stage P25, that is, a light emitting stage, signals of the first light emitting signal line EM1, the second light emitting signal line EM2, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals. Signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are low-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, a power supply voltage output from the first power supply line VDD provides a driving voltage to a first electrode of the light emitting device L through the turned-on fourth transistor T4, third transistor T3 and fifth transistor T5 to drive the light emitting device L to emit light, signals of the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals, and the first transistor T1, the second transistor T2 and the eighth transistor T8 are turned off, and the light emitting device L emits light in this stage.

[0265] In a drive process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by a voltage difference between the control electrode (also the first node N1) and the second electrode (also the third node N3) of the third transistor T3. Because the voltage value V1 of the signal of the first node meets V1= Vdata-[Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 )]+ Vinit and the voltage value V3 of the signal of the third node N3 meets V3=Vinit, the driving current of the third transistor T3 is as follows. I = K * Vgs − Vth 2 = K * Vdata − Vref − Vth + Vdata − Vref * C 1 / C 1 + C 2 − Vth 2 = K * C 2 / C 1 + C 2 * Vdata − Vref 2

[0266] Herein, I is a driving current flowing through the third transistor T3, that is, a driving current driving the light emitting device L, K is a constant, and Vgs is a voltage difference between the control electrode and the second electrode of the third transistor T3.

[0267] It may be seen from a derivation result of the above current formula that in the light emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3. Therefore, an influence of the threshold voltage of the third transistor T3 on the driving current is eliminated, which may ensure uniformity of display brightness of a display product, and improve an overall display effect of the display product.

[0268] FIG. 37A is a first working timing diagram of the pixel driving circuits provided in FIGS. 25A, 26A, 28A, and 30A, and the pixel driving circuit according to the present disclosure is further described in conjunction with FIGS. 25A and 37A.

[0269] In a first stage P31 referred to as a reset stage, signals of the second scan signal line G2, the second light emitting signal line EM2, the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, and signals of the first scan signal line G1 and the first light emitting signal line EM1 are low-level signals. When the signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is written into the first node N1, to initialize (reset) a signal of the first node N1 and clear original charges in the first node N1. Signals of the second light emitting signal line EM2, the first reset signal line Reset1, and the third reset signal line Reset3 are high-level signals, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are turned on, and a signal of the dynamic signal line Var is written into the third node N3, the fourth node N4, and the fifth node N5, respectively. Because a voltage value of a signal of the first node N1 and a voltage value of a signal of the third node N3 are greater than a threshold voltage of the third transistor T3, at this time, the third transistor T3 is turned on, and a signal of the dynamic signal line Var is written into the second node N2, to initialize (reset) signals of the second node N2, the third node N3, the fourth node N4, and the fifth node N5 and clear original charges in the second node N2, the third node N3, the fourth node N4, and the fifth node N5. Signals of the first scan signal line G1 and the first light emitting signal line EM1 are low-level signals, and the first transistor T1 and the fourth transistor T4 are turned off. The light emitting device L does not emit light in this stage.

[0270] In a second stage P32, that is, a threshold compensation stage, signals of the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2 and the first light emitting signal line EM1 are high-level signals, and signals of the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals. Signals of the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the sixth transistor T6 and the eighth transistor T8 are turned on, a signal of the dynamic signal line Var is continuously written to the fourth node N4 and the fifth node N5, to continuously initialize (reset) signals of the fourth node N4 and the fifth node N5. A signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is continuously provided to the first node N1, a signal of the first light emitting signal line EM1 is a high-level signal, the fourth transistor T4 is turned on, and a signal of the first power supply line VDD is written to the third node N3 through the turned-on fourth transistor T4, the second node N2 and the turned-on third transistor T3 until a voltage V3 of a signal of the third node N3 meets V3=Vref-Vth, wherein Vref is a voltage value of a signal of the reference signal line REF, and Vth is the threshold voltage of the third transistor T3, at this time, the first capacitor C1 stores a voltage difference Vth between signals of the first node N1 and the third node N3. Signals of the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals, and the first transistor T1 and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0271] In a third stage P33, that is, a data writing stage, signals of the first reset signal line Reset1 and the third reset signal line Reset are high-level signals, signals of the second scan signal line G2, the first light emitting signal line EM1 and the second light emitting signal line EM2 are low-level signals, the first scan signal line G1 is a high-level signal for part of a time period, and the data signal line Data outputs a data voltage. Signals of the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the sixth transistor T6 and the eighth transistor T8 are turned on, a signal of the dynamic signal line Var is continuously written to the fourth node N4 and the fifth node N5, to continuously initialize (reset) signals of the fourth node N4 and the fifth node N5. A signal of the first scan signal line G1 is a high-level signal, the first transistor T1 is turned on, and a data voltage of the data signal line Data is written to the first node N1. At this time, the voltage value V1 of the first node N1 meets V1=Vdata, wherein Vdata is the data voltage of the data signal line. The voltage value of the signal of the first node N1 in the present stage undergoes a jump compared to the voltage value in the previous stage. Therefore, a signal of the third node N3 also undergoes a jump under an action of the first capacitor C1 and the second capacitor C2. At this time, the voltage value V3 of the signal of the third node N3 meets V3=Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 ), where C 1 is the capacitance value of the first capacitor, C 2 is the capacitance value of the second capacitor. Signals of the second scan signal line G2, the first light emitting signal line EM1, and the second light emitting signal line EM2 are low-level signals, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0272] In a fourth stage P34, that is, a light emitting stage, signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, and signals of the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals. Signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, a power supply voltage output from the first power supply line VDD provides a driving voltage to a first electrode of the light emitting device L through the turned-on fourth transistor T4, third transistor T3 and fifth transistor T5 to drive the light emitting device L to emit light, signals of the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals, the first transistor T1, the second transistor T2, the sixth transistor T6 and the eighth transistor T8 are turned off, and the light emitting device L emits light in this stage.

[0273] In a drive process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by a voltage difference between the control electrode (also the first node N1) and the second electrode (also the third node N3) of the third transistor T3. Because the voltage value V1 of the signal of the first node meets V1= Vdata-[Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 )]+ Vinit and the voltage value V3 of the signal of the third node N3 meets V3=Vinit, the driving current of the third transistor T3 is as follows. I = K * Vgs − Vth 2 = K * Vdata − Vref − Vth + Vdata − Vref * C 1 / C 1 + C 2 − Vth 2 = K * C 2 / C 1 + C 2 * Vdata − Vref 2

[0274] Herein, I is a driving current flowing through the third transistor T3, that is, a driving current driving the light emitting device L, K is a constant, and Vgs is a voltage difference between the control electrode and the second electrode of the third transistor T3.

[0275] It may be seen from a derivation result of the above current formula that in the light emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3. Therefore, an influence of the threshold voltage of the third transistor T3 on the driving current is eliminated, which may ensure uniformity of display brightness of a display product, and improve an overall display effect of the display product.

[0276] FIG. 37B is a second working timing diagram of the pixel driving circuits provided in FIGS. 25A, 26A, 28A, and 30A, and the pixel driving circuit according to the present disclosure is further described in conjunction with FIGS. 25A and 37B.

[0277] In a first stage P41 referred to as a reset stage, signals of the first reset line Reset1, the second scan signal line G2, the second light emitting signal line EM2 and the third reset signal line Reset3 are high-level signals, and signals of the first scan signal line G1 and the first light emitting signal line EM1 are low-level signals. When the signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is written into the first node N1, to initialize (reset) a signal of the first node N1 and clear original charges in the first node N1. Signals of the first reset signal line Reset1, the second light emitting signal line EM2 and the third reset signal line Reset3 are high-level signals, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are turned on, and a signal of the dynamic signal line Var is written into the third node N3, the fourth node N4, and the fifth node N5, respectively. Because a voltage value of a signal of the first node N1 and a voltage value of a signal of the third node N3 are greater than a threshold voltage of the third transistor T3, at this time, the third transistor T3 is turned on, and a signal of the dynamic signal line Var is written into the second node N2, to initialize (reset) signals of the second node N2, the third node N3, the fourth node N4, and the fifth node N5 and clear original charges in the second node N2, the third node N3, the fourth node N4, and the fifth node N5. Signals of the first scan signal line G1 and the first light emitting signal line EM1 are low-level signals, and the first transistor T1 and the fourth transistor T4 are turned off. The light emitting device L does not emit light in this stage.

[0278] In a second stage P42, that is, a threshold compensation stage, signals of the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2 and the first light emitting signal line EM1 are high-level signals, and signals of the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals. Signals of the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the sixth transistor T6 and the eighth transistor T8 are turned on, a signal of the dynamic signal line Var is continuously written to the fourth node N4 and the fifth node N5, to continuously initialize (reset) signals of the fourth node N4 and the fifth node N5. A signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is continuously provided to the first node N1, a signal of the first light emitting signal line EM1 is a high-level signal, the fourth transistor T4 is turned on, and a signal of the first power supply line VDD is written to the third node N3 through the turned-on fourth transistor T4, the second node N2 and the turned-on third transistor T3 until a voltage V3 of a signal of the third node N3 meets V3=Vref-Vth, wherein Vref is a voltage value of a signal of the reference signal line REF, and Vth is the threshold voltage of the third transistor T3, at this time, the first capacitor C1 stores a voltage difference Vth between signals of the first node N1 and the third node N3. Signals of the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals, and the first transistor T1 and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0279] In a third stage P43, that is, a data writing stage, signals of the first reset signal line Reset1 and the third reset signal line Reset are high-level signals, signals of the second scan signal line G2, the first light emitting signal line EM1 and the second light emitting signal line EM2 are low-level signals, the first scan signal line G1 is a high-level signal for part of a time period, and the data signal line Data outputs a data voltage. Signals of the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the eighth transistor T8 is turned on, a signal of the dynamic signal line Var is continuously written to the fourth node N4 and the fifth node N5, to continuously initialize (reset) signals of the fourth node N4 and the fifth node N5. A signal of the first scan signal line G1 is a high-level signal, the first transistor T1 is turned on, and the data voltage of the data signal line Data is written to the first node N1. At this time, the voltage value V1 of the first node N1 meets V1=Vdata, wherein Vdata is the data voltage of the data signal line. The voltage value of the signal of the first node N1 in the present stage undergoes a jump compared to the voltage value in the previous stage. Therefore, a signal of the third node N3 also undergoes a jump under an action of the first capacitor C1 and the second capacitor C2. At this time, the voltage value V3 of the signal of the third node N3 meets V3=Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 ), where C 1 is the capacitance value of the first capacitor, C 2 is the capacitance value of the second capacitor. Signals of the second scan signal line G2, the first light emitting signal line EM1, and the second light emitting signal line EM2 are low-level signals, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0280] In a fourth stage P44, that is, a second reset stage, a signal of the second light emitting signal line EM2 is a high-level signal, signals of the first scan signal line G1, the second scan signal line G2 and the first light emitting signal line EM1 are low-level signals, signals of the third reset signal line Reset3 and the first reset signal line Reset1 are high-level signals for part of a time period and low-level signals for part of a time period, and a time duration in which a signal of any of the third reset signal line Reset3 and the first reset signal line Reset1 is a high-level signal is earlier than a time duration in which the signal is a low-level signal, a signal of the second light emitting signal line EM2 is a high-level signal, the fifth transistor T5 is turned on, and then the sixth transistor T6 and the eighth transistor T8 are turned off sequentially. Although a signal of the third node N3 becomes a signal of the dynamic signal line Var, the voltage difference between signals of the first node N1 and the third node N3 remains unchanged. Signals of the first scan signal line G1, the second scan signal line G2, and the first light emitting signal line EM1 are low-level signals, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0281] In a fifth stage P45, that is, a light emitting stage, signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, and signals of the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals. Signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, a power supply voltage output from the first power supply line VDD provides a driving voltage to a first electrode of the light emitting device L through the turned-on fourth transistor T4, third transistor T3 and fifth transistor T5 to drive the light emitting device L to emit light, signals of the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals, the first transistor T1, the second transistor T2, the sixth transistor T6 and the eighth transistor T8 are turned off, and the light emitting device L emits light in this stage.

[0282] In a drive process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by a voltage difference between the control electrode (also the first node N1) and the second electrode (also the third node N3) of the third transistor T3. Because the voltage value V1 of the signal of the first node meets V1= Vdata-[Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 )]+ Vinit and the voltage value V3 of the signal of the third node N3 meets V3=Vinit, the driving current of the third transistor T3 is as follows. I = K * Vgs − Vth 2 = K * Vdata − Vref − Vth + Vdata − Vref * C 1 / C 1 + C 2 − Vth 2 = K * C 2 / C 1 + C 2 * Vdata − Vref 2

[0283] Herein, I is a driving current flowing through the third transistor T3, that is, a driving current driving the light emitting device L, K is a constant, and Vgs is a voltage difference between the control electrode and the second electrode of the third transistor T3.

[0284] It may be seen from a derivation result of the above current formula that in the light emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3. Therefore, an influence of the threshold voltage of the third transistor T3 on the driving current is eliminated, which may ensure uniformity of display brightness of a display product, and improve an overall display effect of the display product.

[0285] The transistors included in FIGS. 25A, 26A, and 28A are the same, and FIGS. 25A, 26A, and 28A differ only in the connection relationship and the number of capacitors, and the capacitors do not affect timing. Therefore, the working process of the pixel driving circuits provided in FIGS. 26A and 28A is completely the same as that of FIG. 25, and the present disclosure is not limited thereto.

[0286] The pixel driving circuit according to the present disclosure is further described in conjunction with FIGS. 30A and 37A.

[0287] In a first stage P31 referred to as a reset stage, signals of the second scan signal line G2, the second light emitting signal line EM2, the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, and signals of the first scan signal line G1 and the first light emitting signal line EM1 are low-level signals. When the signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is written into the first node N1, to initialize (reset) a signal of the first node N1 and clear original charges in the first node N1. Signals of the second light emitting signal line EM2, the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the fifth transistor T5, the sixth transistor T6 and the ninth transistor T9 are turned on, and a signal of the auxiliary signal line VX is written into the third node N3, the fourth node N4, and the fourth node N5, respectively. Because a voltage value of a signal of the first node N1 and a voltage value of a signal of the third node N3 are greater than a threshold voltage of the third transistor T3, at this time, the third transistor T3 is turned on, and a signal of the auxiliary signal line VX is written into the second node N2, to initialize (reset) signals of the second node N2, the third node N3, the fourth Node N4 and the fourth node N5 and clear original charges in the second node N2, the third node N3, the fourth Node N4 and the fourth node N5. Signals of the first scan signal line G1 and the first light emitting signal line EM1 are low-level signals, and the first transistor T1 and the fourth transistor T4 are turned off. The light emitting device L does not emit light in this stage.

[0288] In a second stage P32, that is, a threshold compensation stage, signals of the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2 and the first light emitting signal line EM1 are high-level signals, and signals of the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals. Signals of the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the sixth transistor T6 and the ninth transistor T9 are turned on, a signal of the auxiliary signal line VX is continuously written to the fourth node N4 and the fifth node N5, to continuously initialize (reset) signals of the fourth node N4 and the fifth node N5. A signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is continuously provided to the first node N1, a signal of the first light emitting signal line EM1 is a high-level signal, the fourth transistor T4 is turned on, and a signal of the first power supply line VDD is written to the third node N3 through the turned-on fourth transistor T4, the second node N2 and the turned-on third transistor T3 until a voltage V3 of a signal of the third node N3 meets V3=Vref-Vth, wherein Vref is a voltage value of a signal of the reference signal line REF, and Vth is the threshold voltage of the third transistor T3, at this time, the first capacitor C1 stores a voltage difference Vth between signals of the first node N1 and the third node N3. Signals of the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals, and the first transistor T1 and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0289] In a third stage P33, that is, a data writing stage, signals of the first reset signal line Reset1 and the third reset signal line Reset are high-level signals, signals of the second scan signal line G2, the first light emitting signal line EM1 and the second light emitting signal line EM2 are low-level signals, the signal of the first scan signal line G1 is a high-level signal for part of a time period, and the data signal line Data outputs a data voltage. Signals of the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the sixth transistor T6 and the ninth transistor T9 are turned on, a signal of the auxiliary signal line VX is continuously written to the fourth node N4 and the fifth node N5, to continuously initialize (reset) signals of the fourth node N4 and the fifth node N5. A signal of the first scan signal line G1 is a high-level signal, the first transistor T1 is turned on, and the data voltage of the data signal line Data is written to the first node N1. At this time, the voltage value V1 of the first node N1 meets V1=Vdata, wherein Vdata is the data voltage of the data signal line. The voltage value of the signal of the first node N1 in the present stage undergoes a jump compared to the voltage value in the previous stage. Therefore, a signal of the third node N3 also undergoes a jump under an action of the first capacitor C1 and the second capacitor C2. At this time, the voltage value V3 of the signal of the third node N3 meets V3=Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 ), where C 1 is the capacitance value of the first capacitor, C 2 is the capacitance value of the second capacitor. Signals of the second scan signal line G2, the first light emitting signal line EM1, and the second light emitting signal line EM2 are low-level signals, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0290] In a fourth stage P34, that is, a light emitting stage, signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, and signals of the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals. Signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, a power supply voltage output from the first power supply line VDD provides a driving voltage to a first electrode of the light emitting device L through the turned-on fourth transistor T4, third transistor T3 and fifth transistor T5 to drive the light emitting device L to emit light, signals of the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals, the first transistor T1, the second transistor T2, the sixth transistor T6 and the ninth transistor T9 are turned off, and the light emitting device L emits light in this stage.

[0291] In a drive process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by a voltage difference between the control electrode (also the first node N1) and the second electrode (also the third node N3) of the third transistor T3. Because the voltage value V1 of the signal of the first node meets V1= Vdata-[Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 )]+ Vinit and the voltage value V3 of the signal of the third node N3 meets V3=Vinit, the driving current of the third transistor T3 is as follows. I = K * Vgs − Vth 2 = K * Vdata − Vref − Vth + Vdata − Vref * C 1 / C 1 + C 2 − Vth 2 = K * C 2 / C 1 + C 2 * Vdata − Vref 2

[0292] Herein, I is a driving current flowing through the third transistor T3, that is, a driving current driving the light emitting device L, K is a constant, and Vgs is a voltage difference between the control electrode and the second electrode of the third transistor T3.

[0293] It may be seen from a derivation result of the above current formula that in the light emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3. Therefore, an influence of the threshold voltage of the third transistor T3 on the driving current is eliminated, which may ensure uniformity of display brightness of a display product, and improve an overall display effect of the display product.

[0294] The pixel driving circuit according to the present disclosure is further described in conjunction with FIGS. 30A and 37B.

[0295] In a first stage P41 referred to as a reset stage, signals of the first reset signal line Reset1, the second scan signal line G2, the light emitting signal line EM2 and the third reset signal line Reset3 are high-level signals, and signals of the first scan signal line G1 and the first light emitting signal line EM1 are low-level signals. When the signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is written into the first node N1, to initialize (reset) a signal of the first node N1 and clear original charges in the first node N1. Signals of the first reset signal line Reset1, the second light emitting signal line EM2 and the third reset signal line Reset3 are high-level signals, the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are turned on, and a signal of the auxiliary signal line VX is written into the third node N3, the fourth node N4, and the fifth node N5, respectively. Because a voltage value of a signal of the first node N1 and a voltage value of a signal of the third node N3 are greater than a threshold voltage of the third transistor T3, at this time, the third transistor T3 is turned on, and a signal of the auxiliary signal line VX is written into the second node N2, to initialize (reset) signals of the second node N2, the third node N3, the fourth node N4, and the fifth node N5 and clear original charges in the second node N2, the third node N3, the fourth node N4, and the fifth node N5. Signals of the first scan signal line G1 and the first light emitting signal line EM1 are low-level signals, and the first transistor T1 and the fourth transistor T4 are turned off. The light emitting device L does not emit light in this stage.

[0296] In a second stage P42, that is, a threshold compensation stage, signals of the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2 and the first light emitting signal line EM1 are high-level signals, and signals of the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals. Signals of the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the sixth transistor T6 and the ninth transistor T9 are turned on, a signal of the auxiliary signal line VX is continuously written to the fourth node N4 and the fifth node N5, to continuously initialize (reset) signals of the fourth node N4 and the fifth node N5. A signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is continuously provided to the first node N1, a signal of the first light emitting signal line EM1 is a high-level signal, the fourth transistor T4 is turned on, and a signal of the first power supply line VDD is written to the third node N3 through the turned-on fourth transistor T4, the second node N2 and the turned-on third transistor T3 until a voltage V3 of a signal of the third node N3 meets V3=Vref-Vth, wherein Vref is a voltage value of a signal of the reference signal line REF, and Vth is the threshold voltage of the third transistor T3, at this time, the first capacitor C1 stores a voltage difference Vth between signals of the first node N1 and the third node N3. Signals of the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals, and the first transistor T1 and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0297] In a third stage P43, that is, a data writing stage, signals of the first reset signal line Reset1 and the third reset signal line Reset are high-level signals, signals of the second scan signal line G2, the first light emitting signal line EM1 and the second light emitting signal line EM2 are low-level signals, the first scan signal line G1 is a high-level signal for part of a time period, and the data signal line Data outputs a data voltage. Signals of the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the ninth transistor T9 is turned on, a signal of the auxiliary signal line VX is continuously written to the fourth node N4 and the fifth node N5, to continuously initialize (reset) signals of the fourth node N4 and the fifth node N5. A signal of the first scan signal line G1 is a high-level signal, the first transistor T1 is turned on, and the data voltage of the data signal line Data is written to the first node N1. At this time, the voltage value V1 of the first node N1 meets V1=Vdata, wherein Vdata is the data voltage of the data signal line. The voltage value of the signal of the first node N1 in the present stage undergoes a jump compared to the voltage value in the previous stage. Therefore, a signal of the third node N3 also undergoes a jump under an action of the first capacitor C1 and the second capacitor C2. At this time, the voltage value V3 of the signal of the third node N3 meets V3=Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 ), where C 1 is the capacitance value of the first capacitor, C 2 is the capacitance value of the second capacitor. Signals of the second scan signal line G2, the first light emitting signal line EM1, and the second light emitting signal line EM2 are low-level signals, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0298] In a fourth stage P44, that is, a second reset stage, a signal of the second light emitting signal line EM2 is a high-level signal, signals of the first scan signal line G1, the second scan signal line G2 and the first light emitting signal line EM1 are low-level signals, signals of the third reset signal line Reset3 and the first reset signal line Reset1 are high-level signals for part of a time period and low-level signals for part of a time period, and a time duration in which a signal of any of the third reset signal line Reset3 and the first reset signal line Reset1 is the high-level signal is earlier than a time duration in which the signal is the low-level signal, a signal of the second light emitting signal line EM2 is a high-level signal, the fifth transistor T5 is turned on, and then the sixth transistor T6 and the ninth transistor T9 are turned off sequentially. Although a signal of the third node N3 becomes a signal of the dynamic signal line Var, the voltage difference between signals of the first node N1 and the third node N3 remains unchanged. Signals of the first scan signal line G1, the second scan signal line G2, and the first light emitting signal line EM1 are low-level signals, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0299] In a fifth stage P45, that is, a light emitting stage, signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, and signals of the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals. Signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, a power supply voltage output from the first power supply line VDD provides a driving voltage to a first electrode of the light emitting device L through the turned-on fourth transistor T4, third transistor T3 and fifth transistor T5 to drive the light emitting device L to emit light, signals of the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals, the first transistor T1, the second transistor T2, the sixth transistor T6 and the ninth transistor T9 are turned off, and the light emitting device L emits light in this stage.

[0300] In a drive process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by a voltage difference between the control electrode (also the first node N1) and the second electrode (also the third node N3) of the third transistor T3. Because the voltage value V1 of the signal of the first node meets V1= Vdata-[Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 )]+ Vinit and the voltage value V3 of the signal of the third node N3 meets V3=Vinit, the driving current of the third transistor T3 is as follows. I = K * Vgs − Vth 2 = K * Vdata − Vref − Vth + Vdata − Vref * C 1 / C 1 + C 2 − Vth 2 = K * C 2 / C 1 + C 2 * Vdata − Vref 2

[0301] Herein, I is a driving current flowing through the third transistor T3, that is, a driving current driving the light emitting device L, K is a constant, and Vgs is a voltage difference between the control electrode and the second electrode of the third transistor T3.

[0302] It may be seen from a derivation result of the above current formula that in the light emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3. Therefore, an influence of the threshold voltage of the third transistor T3 on the driving current is eliminated, which may ensure uniformity of display brightness of a display product, and improve an overall display effect of the display product.

[0303] FIG. 38A is a first working timing diagram of the pixel driving circuits provided in FIGS. 25B, 26B, 28B, and 30B, and the pixel driving circuit according to the present disclosure is further described in conjunction with FIGS. 25B and 38A.

[0304] In a first stage P31 referred to as a reset stage, signals of the second scan signal line G2, the first light emitting signal line EM1, the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, and signals of the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals. When the signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is written into the first node N1, to initialize (reset) a signal of the first node N1 and clear original charges in the first node N1. A signal of the second light emitting signal line EM2 is a low-level signal, signals of the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are turned on, and a signal of the dynamic signal line Var is written into the third node N3, the fourth node N4, and the fifth node N5, respectively. Because a voltage value of a signal of the first node N1 and a voltage value of a signal of the third node N3 are greater than a threshold voltage of the third transistor T3, at this time, the third transistor T3 is turned on, and a signal of the dynamic signal line Var is written into the second node N2, to initialize (reset) signals of the second node N2, the third node N3, the fourth node N4, and the fifth node N5 and clear original charges in the second node N2, the third node N3, the fourth node N4, and the fifth node N5. A signal of the first scan signal line G1 is a low-level signal, a signal of the first light emitting signal line EM1 is a high-level signal, and the first transistor T1 and the fourth transistor T4 are turned off. The light emitting device L does not emit light in this stage.

[0305] In a second stage P32, that is, a threshold compensation stage, signals of the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2 and the second light emitting signal line EM2 are high-level signals, and signals of the first scan signal line G1 and the first light emitting signal line EM1 are low-level signals. Signals of the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the sixth transistor T6 and the eighth transistor T8 are turned on, a signal of the dynamic signal line Var is continuously written to the fourth node N4 and the fifth node N5, to continuously initialize (reset) signals of the fourth node N4 and the fifth node N5. A signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is continuously provided to the first node N1, a signal of the first light emitting signal line EM1 is a low-level signal, the fourth transistor T4 is turned on, and a signal of the first power supply line VDD is written to the third node N3 through the turned-on fourth transistor T4, the second node N2 and the turned-on third transistor T3 until a voltage V3 of a signal of the third node N3 meets V3=Vref-Vth, wherein Vref is a voltage value of a signal of the reference signal line REF, and Vth is the threshold voltage of the third transistor T3, at this time, the first capacitor C1 stores a voltage difference Vth between signals of the first node N1 and the third node N3. A signal of the first scan signal line G1 is a low-level signal, a signal of the second light emitting signal line EM2 is a high-level signal, and the first transistor T1 and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0306] In a third stage P33, that is, a data writing stage, the signals of the first reset signal line Reset1, the third reset signal line Reset, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, the signal of the second scan signal line G2 is a low-level signal, the first scan signal line G1 is a high-level signal for part of a time period, and the data signal line Data outputs a data voltage. Signals of the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the sixth transistor T6 and the eighth transistor T8 are turned on, a signal of the dynamic signal line Var is continuously written to the fourth node N4 and the fifth node N5, to continuously initialize (reset) signals of the fourth node N4 and the fifth node N5. A signal of the first scan signal line G1 is a high-level signal, the first transistor T1 is turned on, and the data voltage of the data signal line Data is written to the first node N1. At this time, the voltage value V1 of the first node N1 meets V1=Vdata, wherein Vdata is the data voltage of the data signal line. The voltage value of the signal of the first node N1 in the present stage undergoes a jump compared to the voltage value in the previous stage. Therefore, a signal of the third node N3 also undergoes a jump under an action of the first capacitor C1 and the second capacitor C2. At this time, the voltage value V3 of the signal of the third node N3 meets V3=Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 ), where C 1 is the capacitance value of the first capacitor, C 2 is the capacitance value of the second capacitor. A signal of the second scan signal line G2 is a low-level signal, signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0307] In a fourth stage P34, that is, a light emitting stage, signals of the first light emitting signal line EM1, the second light emitting signal line EM2, the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals. Signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are low-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, a power supply voltage output from the first power supply line VDD provides a driving voltage to a first electrode of the light emitting device L through the turned-on fourth transistor T4, third transistor T3 and fifth transistor T5 to drive the light emitting device L to emit light, signals of the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals, the first transistor T1, the second transistor T2, the sixth transistor T6 and the eighth transistor T8 are turned off, and the light emitting device L emits light in this stage.

[0308] In a drive process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by a voltage difference between the control electrode (also the first node N1) and the second electrode (also the third node N3) of the third transistor T3. Because the voltage value V1 of the signal of the first node meets V1= Vdata-[Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 )]+ Vinit and the voltage value V3 of the signal of the third node N3 meets V3=Vinit, the driving current of the third transistor T3 is as follows. I = K * Vgs − Vth 2 = K * Vdata − Vref − Vth + Vdata − Vref * C 1 / C 1 + C 2 − Vth 2 = K * C 2 / C 1 + C 2 * Vdata − Vref 2

[0309] Herein, I is a driving current flowing through the third transistor T3, that is, a driving current driving the light emitting device L, K is a constant, and Vgs is a voltage difference between the control electrode and the second electrode of the third transistor T3.

[0310] It may be seen from a derivation result of the above current formula that in the light emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3. Therefore, an influence of the threshold voltage of the third transistor T3 on the driving current is eliminated, which may ensure uniformity of display brightness of a display product, and improve an overall display effect of the display product.

[0311] FIG. 38B is a second working timing diagram of the pixel driving circuits provided in FIGS. 25B, 26B, 28B, and 30B, and the pixel driving circuit according to the present disclosure is further described in conjunction with FIGS. 25B and 38B.

[0312] In a first stage P41 referred to as a reset stage, signals of the first reset signal line Reset1, the second scan signal line G2, the first light emitting signal line EM1 and the third reset signal line Reset3 are high-level signals, and signals of the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals. When the signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is written into the first node N1, to initialize (reset) a signal of the first node N1 and clear original charges in the first node N1. Signals of the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, a signal of the second light emitting signal line EM2 is a low-level signal, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are turned on, and a signal of the dynamic signal line Var is written into the third node N3, the fourth node N4, and the fifth node N5, respectively. Because a voltage value of a signal of the first node N1 and a voltage value of a signal of the third node N3 are greater than a threshold voltage of the third transistor T3, at this time, the third transistor T3 is turned on, and a signal of the dynamic signal line Var is written into the second node N2, to initialize (reset) signals of the second node N2, the third node N3, the fourth node N4, and the fifth node N5 and clear original charges in the second node N2, the third node N3, the fourth node N4, and the fifth node N5. A signal of the first scan signal line G1 is a low-level signal, a signal of the first light emitting signal line EM1 is a high-level signal, and the first transistor T1 and the fourth transistor T4 are turned off. The light emitting device L does not emit light in this stage.

[0313] In a second stage P42, that is, a threshold compensation stage, signals of the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2 and the second light emitting signal line EM2 are high-level signals, and signals of the first scan signal line G1 and the first light emitting signal line EM1 are low-level signals. Signals of the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the sixth transistor T6 and the eighth transistor T8 are turned on, a signal of the dynamic signal line Var is continuously written to the fourth node N4 and the fifth node N5, to continuously initialize (reset) signals of the fourth node N4 and the fifth node N5. A signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is continuously provided to the first node N1, a signal of the first light emitting signal line EM1 is a low-level signal, the fourth transistor T4 is turned on, and a signal of the first power supply line VDD is written to the third node N3 through the turned-on fourth transistor T4, the second node N2 and the turned-on third transistor T3 until a voltage V3 of a signal of the third node N3 meets V3=Vref-Vth, wherein Vref is a voltage value of a signal of the reference signal line REF, and Vth is the threshold voltage of the third transistor T3, at this time, the first capacitor C1 stores a voltage difference Vth between signals of the first node N1 and the third node N3. A signal of the first scan signal line G1 is a low-level signal, a signal of the second light emitting signal line EM2 is a high-level signal, and the first transistor T1 and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0314] In a third stage P43, that is, a data writing stage, the signals of the first reset signal line Reset1, the third reset signal line Reset, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, the signal of the second scan signal line G2 is a low-level signal, the first scan signal line G1 is a high-level signal for part of a time period, and the data signal line Data outputs a data voltage. Signals of the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the eighth transistor T8 is turned on, a signal of the dynamic signal line Var is continuously written to the fourth node N4 and the fifth node N5, to continuously initialize (reset) signals of the fourth node N4 and the fifth node N5. A signal of the first scan signal line G1 is a high-level signal, the first transistor T1 is turned on, and the data voltage of the data signal line Data is written to the first node N1. At this time, the voltage value V1 of the first node N1 meets V1=Vdata, wherein Vdata is the data voltage of the data signal line. The voltage value of the signal of the first node N1 in the present stage undergoes a jump compared to the voltage value in the previous stage. Therefore, a signal of the third node N3 also undergoes a jump under an action of the first capacitor C1 and the second capacitor C2. At this time, the voltage value V3 of the signal of the third node N3 meets V3=Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 ), where C 1 is the capacitance value of the first capacitor, C 2 is the capacitance value of the second capacitor. A signal of the second scan signal line G2 is a low-level signal, signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0315] In a fourth stage P44, that is, a second reset stage, a signal of the first light emitting signal line EM1 is a high-level signal, signals of the first scan signal line G1, the second scan signal line G2, and the second light emitting signal line EM2 are low-level signals, signals of the third reset signal line Reset3 and the first reset signal line Reset1 are high-level signals for part of a time period and are low-level signals for part of a time period, a time duration in which a signal of any of the third reset signal line Reset3 and the first reset signal line Reset1 is the high-level signal is earlier than a time duration in which the signal is the low-level signal, a signal of the second light emitting signal line EM2 is a low-level signal, the fifth transistor T5 is turned on, and then the sixth transistor T6 and the eighth transistor T8 are turned off sequentially. Although a signal of the third node N3 becomes a signal of the dynamic signal line Var, the voltage difference between signals of the first node N1 and the third node N3 remains unchanged. Signals of the first scan signal line G1 and the second scan signal line G2 are low-level signals, and a signal of the first light emitting signal line EM1 is a high-level signal, so that the second transistor T2, the fourth transistor T4 and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0316] In a fifth stage P45, that is, a light emitting stage, signals of the first light emitting signal line EM1, the second light emitting signal line EM2, the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals. Signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are low-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, a power supply voltage output from the first power supply line VDD provides a driving voltage to a first electrode of the light emitting device L through the turned-on fourth transistor T4, third transistor T3 and fifth transistor T5 to drive the light emitting device L to emit light, signals of the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals, the first transistor T1, the second transistor T2, the sixth transistor T6 and the eighth transistor T8 are turned off, and the light emitting device L emits light in this stage.

[0317] In a drive process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by a voltage difference between the control electrode (also the first node N1) and the second electrode (also the third node N3) of the third transistor T3. Because the voltage value V1 of the signal of the first node meets V1= Vdata-[Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 )]+ Vinit and the voltage value V3 of the signal of the third node N3 meets V3=Vinit, the driving current of the third transistor T3 is as follows. I = K * Vgs − Vth 2 = K * Vdata − Vref − Vth + Vdata − Vref * C 1 / C 1 + C 2 − Vth 2 = K * C 2 / C 1 + C 2 * Vdata − Vref 2

[0318] Herein, I is a driving current flowing through the third transistor T3, that is, a driving current driving the light emitting device L, K is a constant, and Vgs is a voltage difference between the control electrode and the second electrode of the third transistor T3.

[0319] It may be seen from a derivation result of the above current formula that in the light emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3. Therefore, an influence of the threshold voltage of the third transistor T3 on the driving current is eliminated, which may ensure uniformity of display brightness of a display product, and improve an overall display effect of the display product.

[0320] The transistors included in FIGS. 25B, 26B, and 28B are the same, but FIGS. 25B, 26B, and 28B differ only in the connection relationship and the number of capacitors, and the capacitors do not affect timing. Therefore, the working process of the pixel driving circuits provided in FIGS. 26B and 28B is completely the same as that of FIG. 25, and the present disclosure is not limited thereto.

[0321] The pixel driving circuit according to the present disclosure is further described in conjunction with FIGS. 30B and 38A.

[0322] In a first stage P31 referred to as a reset stage, signals of the second scan signal line G2, the first light emitting signal line EM1, the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, and signals of the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals. When the signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is written into the first node N1, to initialize (reset) a signal of the first node N1 and clear original charges in the first node N1. A signal of the second light emitting signal line EM2 is a low-level signal, signals of the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the fifth transistor T5, the sixth transistor T6 and the ninth transistor T9 are turned on, and a signal of the auxiliary signal line VX is written into the third node N3, the fourth node N4, and the fourth node N5, respectively. Because a voltage value of a signal of the first node N1 and a voltage value of a signal of the third node N3 are greater than a threshold voltage of the third transistor T3, at this time, the third transistor T3 is turned on, and a signal of the auxiliary signal line VX is written into the second node N2, to initialize (reset) signals of the second node N2, the third node N3, the fourth Node N4 and the fourth node N5 and clear original charges in the second node N2, the third node N3, the fourth Node N4 and the fourth node N5. A signal of the first scan signal line G1 is a low-level signal, a signal of the first light emitting signal line EM1 is a high-level signal, and the first transistor T1 and the fourth transistor T4 are turned off. The light emitting device L does not emit light in this stage.

[0323] In a second stage P32, that is, a threshold compensation stage, signals of the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2 and the second light emitting signal line EM2 are high-level signals, and signals of the first scan signal line G1 and the first light emitting signal line EM1 are low-level signals. Signals of the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the sixth transistor T6 and the ninth transistor T9 are turned on, a signal of the auxiliary signal line VX is continuously written to the fourth node N4 and the fifth node N5, to continuously initialize (reset) signals of the fourth node N4 and the fifth node N5. A signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is continuously provided to the first node N1, a signal of the first light emitting signal line EM1 is a low-level signal, the fourth transistor T4 is turned on, and a signal of the first power supply line VDD is written to the third node N3 through the turned-on fourth transistor T4, the second node N2 and the turned-on third transistor T3 until a voltage V3 of a signal of the third node N3 meets V3=Vref-Vth, wherein Vref is a voltage value of a signal of the reference signal line REF, and Vth is the threshold voltage of the third transistor T3, at this time, the first capacitor C1 stores a voltage difference Vth between signals of the first node N1 and the third node N3. A signal of the first scan signal line G1 is a low-level signal, a signal of the second light emitting signal line EM2 is a high-level signal, and the first transistor T1 and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0324] In a third stage P33, that is, a data writing stage, signals of the first reset signal line Reset1, the third reset signal line Reset2, the first light emitting signal line EM1, and the second light emitting signal line EM2 are high-level signals, a signal of the second scan signal line G is a low-level signal, the first scan signal line G1 is a high-level signal for part of a time period, and the data signal line Data outputs a data voltage. Signals of the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the sixth transistor T6 and the ninth transistor T9 are turned on, a signal of the auxiliary signal line VX is continuously written to the fourth node N4 and the fifth node N5, to continuously initialize (reset) signals of the fourth node N4 and the fifth node N5. A signal of the first scan signal line G1 is a high-level signal, the first transistor T1 is turned on, and the data voltage of the data signal line Data is written to the first node N1. At this time, the voltage value V1 of the first node N1 meets V1=Vdata, wherein Vdata is the data voltage of the data signal line. The voltage value of the signal of the first node N1 in the present stage undergoes a jump from compared to the voltage value in the previous stage. Therefore, a signal of the third node N3 also undergoes a jump under an action of the first capacitor C1 and the second capacitor C2. At this time, the voltage value V3 of the signal of the third node N3 meets v3=Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 ), where C 1 is the capacitance value of the first capacitor, C 2 is the capacitance value of the second capacitor. A signal of the second scan signal line G2 is a low-level signal, signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0325] In a fourth stage P34, that is, a light emitting stage, signals of the first light emitting signal line EM1, the second light emitting signal line EM2, the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals. Signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are low-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, a power supply voltage output from the first power supply line VDD provides a driving voltage to a first electrode of the light emitting device L through the turned-on fourth transistor T4, third transistor T3 and fifth transistor T5, to drive the light emitting device L to emit light, signals of the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals, the first transistor T1, the second transistor T2, the sixth transistor T6 and the ninth transistor T9 are turned off, and the light emitting device L emits light in this stage.

[0326] In a drive process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by a voltage difference between the control electrode (also the first node N1) and the second electrode (also the third node N3) of the third transistor T3. Because the voltage value V1 of the signal of the first node meets V1= Vdata-[Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 )]+ Vinit and the voltage value V3 of the signal of the third node N3 meets V3=Vinit, the driving current of the third transistor T3 is as follows. I = K * Vgs − Vth 2 = K * Vdata − Vref − Vth + Vdata − Vref * C 1 / C 1 + C 2 − Vth 2 = K * C 2 / C 1 + C 2 * Vdata − Vref 2

[0327] Herein, I is a driving current flowing through the third transistor T3, that is, a driving current driving the light emitting device L, K is a constant, and Vgs is a voltage difference between the control electrode and the second electrode of the third transistor T3.

[0328] It may be seen from a derivation result of the above current formula that in the light emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3. Therefore, an influence of the threshold voltage of the third transistor T3 on the driving current is eliminated, which may ensure uniformity of display brightness of a display product, and improve an overall display effect of the display product.

[0329] The pixel driving circuit according to the present disclosure is further described in conjunction with FIGS. 30B and 38B.

[0330] In a first stage P41 referred to as a reset stage, signals of the first reset signal line Reset1, the second scan signal line G2, the first light emitting signal line EM1 and the third reset signal line Reset3 are high-level signals, and signals of the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals. When the signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is written into the first node N1, to initialize (reset) a signal of the first node N1 and clear original charges in the first node N1. Signals of the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, a signal of the second light emitting signal line EM2 is a low-level signal, the fifth transistor T5, the sixth transistor T6 and the ninth transistor T9 are turned on, and a signal of the auxiliary signal line VX is written into the third node N3, the fourth node N4, and the fifth node N5, respectively. Because a voltage value of a signal of the first node N1 and a voltage value of a signal of the third node N3 are greater than a threshold voltage of the third transistor T3, at this time, the third transistor T3 is turned on, and a signal of the auxiliary signal line VX is written into the second node N2, to initialize (reset) signals of the second node N2, the third node N3, the fourth Node N4 and the fourth node N5 and clear original charges in the second node N2, the third node N3, the fourth Node N4 and the fourth node N5. A signal of the first scan signal line G1 is a low-level signal, a signal of the first light emitting signal line EM1 is a high-level signal, and the first transistor T1 and the fourth transistor T4 are turned off. The light emitting device L does not emit light in this stage.

[0331] In a second stage P42, that is, a threshold compensation stage, signals of the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2 and the second light emitting signal line EM2 are high-level signals, and signals of the first scan signal line G1 and the second light emitting signal line EM1 are low-level signals. Signals of the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the sixth transistor T6 and the ninth transistor T9 are turned on, a signal of the auxiliary signal line VX is continuously written to the fourth node N4 and the fifth node N5, to continuously initialize (reset) signals of the fourth node N4 and the fifth node N5. A signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is continuously provided to the first second node N1, a signal of the first light emitting signal line EM1 is a low-level signal, the fourth transistor T4 is turned on, and a signal of the first power supply line VDD is written to the third node N3 through the turned-on fourth transistor T4, the second node N2 and the turned-on third transistor T3 until a voltage V3 of a signal of the third node N3 meets V3=Vref-Vth, wherein Vref is a voltage value of a signal of the reference signal line REF, and Vth is the threshold voltage of the third transistor T3, at this time, the first capacitor C1 stores a voltage difference Vth between signals of the first node N1 and the third node N3. A signal of the first scan signal line G1 is a low-level signal, a signal of the second light emitting signal line EM2 is a high-level signal, and the first transistor T1 and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0332] In a third stage P43, that is, a data writing stage, the signals of the first reset signal line Reset1, the third reset signal line Reset, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, the signal of the second scan signal line G2 is a low-level signal, the first scan signal line G1 is a high-level signal for part of a time period, and the data signal line Data outputs a data voltage. Signals of the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the ninth transistor T9 is turned on, a signal of the auxiliary signal line VX is continuously written to the fourth node N4 and the fifth node N5, to continuously initialize (reset) signals of the fourth node N4 and the fifth node N5. A signal of the first scan signal line G1 is a high-level signal, the first transistor T1 is turned on, and the data voltage of the data signal line Data is written to the first node N1. At this time, the voltage value V1 of the first node N1 meets V1=Vdata, wherein Vdata is the data voltage of the data signal line. The voltage value of the signal of the first node N1 in the present stage undergoes a jump compared to the voltage value in the previous stage. Therefore, a signal of the third node N3 also undergoes a jump under an action of the first capacitor C1 and the second capacitor C2. At this time, the voltage value V3 of the signal of the third node N3 meets V3=Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 ), where C 1 is the capacitance value of the first capacitor, C 2 is the capacitance value of the second capacitor. A signal of the second scan signal line G2 is a low-level signal, signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0333] In a fourth stage P44, that is, a second reset stage, a signal of the first light emitting signal line EM1 is a high-level signal, signals of the first scan signal line G1, the second scan signal line G2, and the second light emitting signal line EM2 are low-level signals, signals of the third reset signal line Reset3 and the first reset signal line Reset1 are high-level signals for part of a time period and are low-level signals for part of a time period, a time duration in which a signal of any of the third reset signal line Reset3 and the first reset signal line Reset1 is the high-level signal is earlier than a time duration in which the signal is the low-level signal, a signal of the second light emitting signal line EM2 is a low-level signal, the fifth transistor T5 is turned on, and then the sixth transistor T6 and the ninth transistor T9 are turned off sequentially. Although a signal of the third node N3 becomes a signal of the dynamic signal line Var, the voltage difference between signals of the first node N1 and the third node N3 remains unchanged. Signals of the first scan signal line G1 and the second scan signal line G2 are low-level signals, and a signal of the first light emitting signal line EM1 is a high-level signal, so that the second transistor T2, the first transistor T4 and the fourth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0334] In a fifth stage P45, that is, a light emitting stage, signals of the first light emitting signal line EM1, the second light emitting signal line EM2, the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals. Signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are low-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, a power supply voltage output from the first power supply line VDD provides a driving voltage to a first electrode of the light emitting device L through the turned-on fourth transistor T4, third transistor T3 and fifth transistor T5, to drive the light emitting device L to emit light, signals of the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low-level signals, the first transistor T1, the second transistor T2, the sixth transistor T6 and the ninth transistor T9 are turned off, and the light emitting device L emits light in this stage.

[0335] In a drive process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by a voltage difference between the control electrode (also the first node N1) and the second electrode (also the third node N3) of the third transistor T3. Because the voltage value V1 of the signal of the first node meets V1= Vdata-[Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 )]+ Vinit and the voltage value V3 of the signal of the third node N3 meets V3=Vinit, the driving current of the third transistor T3 is as follows. I = K * Vgs − Vth 2 = K * Vdata − Vref − Vth + Vdata − Vref * C 1 / C 1 + C 2 − Vth 2 = K * C 2 / C 1 + C 2 * Vdata − Vref 2

[0336] Herein, I is a driving current flowing through the third transistor T3, that is, a driving current driving the light emitting device L, K is a constant, and Vgs is a voltage difference between the control electrode and the second electrode of the third transistor T3.

[0337] It may be seen from a derivation result of the above current formula that in the light emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3. Therefore, an influence of the threshold voltage of the third transistor T3 on the driving current is eliminated, which may ensure uniformity of display brightness of a display product, and improve an overall display effect of the display product.

[0338] FIG. 39A is a first working timing diagram of the pixel driving circuit provided in FIG. 33A, and the pixel driving circuit according to the present disclosure is further described in conjunction with FIGS. 33A and 39A.

[0339] In a first stage P51 referred to as a reset stage, signals of the second scan signal line G2, the second light emitting signal line EM2, the first reset signal line Reset1, the third reset signal line Reset3, and the fourth reset signal line Reset4 are high-level signals, and signals of the first scan signal line G1 and the first light emitting signal line EM1 are low-level signals. When the signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is written into the first node N1, to initialize (reset) a signal of the first node N1 and clear original charges in the first node N1. Signals of the second light emitting signal line EM2, the first reset signal line Reset1, the third reset signal line Reset3 and the fourth reset signal line Reset4 are high-level signals, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8 and the ninth transistor T9 are turned on, and a signal of the dynamic signal line Var is written into the third node N3, the fourth node N4, and the fifth node N5, respectively. Because a voltage value of a signal of the first node N1 and a voltage value of a signal of the third node N3 are greater than a threshold voltage of the third transistor T3, at this time, the third transistor T3 is turned on, and a signal of the dynamic signal line Var is written into the second node N2, to initialize (reset) signals of the second node N2, the third node N3, the fourth node N4, and the fifth node N5 and clear original charges in the second node N2, the third node N3, the fourth node N4, and the fifth node N5. Signals of the first scan signal line G1 and the first light emitting signal line EM1 are low-level signals, and the first transistor T1 and the fourth transistor T4 are turned off. The light emitting device L does not emit light in this stage.

[0340] In a second stage P52, that is, a threshold compensation stage, signals of the first reset signal line Reset1, the third reset signal line Reset3, the fourth reset signal line Reset4, the second scan signal line G2 and the first light emitting signal line EM1 are high-level signals, and signals of the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals. Signals of the first reset signal line Reset1, the third reset signal line Reset3, and the fourth reset signal line Reset4 are high-level signals, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are turned on, a signal of the dynamic signal line Var or the auxiliary signal line VX is continuously written to the fourth node N4 and the fifth node N5, to continuously initialize (reset) signals of the fourth node N4 and the fifth node N5. A signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, a signal of the reference signal line REF is continuously provided to the first node N1, a signal of the first light emitting signal line EM1 is a high-level signal, the fourth transistor T4 is turned on, and a signal of the first power supply line VDD is written to the third node N3 through the turned-on fourth transistor T4, the second node N2 and the turned-on third transistor T3 until a voltage V3 of a signal of the third node N3 meets V3=Vref-Vth, wherein Vref is a voltage value of a signal of the reference signal line REF, and Vth is the threshold voltage of the third transistor T3, at this time, the first capacitor C1 stores a voltage difference Vth between signals of the first node N1 and the third node N3. Signals of the first scan signal line G1 and the second light emitting signal line EM2 are low-level signals, and the first transistor T1 and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0341] In a third stage P53, that is, a data writing stage, signals of the first reset signal line Reset1, the third reset signal line Reset3, and the fourth reset signal line Reset4 are high-level signals, signals of the second scan signal line G2, the first light emitting signal line EM1, and the second light emitting signal line EM2 are low-level signals, the signal of the first scan signal line G1 is a high-level signal for part of a time period, and the data signal line Data outputs a data voltage. Signals of the first reset signal line Reset1, the third reset signal line Reset3, and the fourth reset signal line Reset4 are high-level signals, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are turned on, a signal of the dynamic signal line Var is continuously written to the fourth node N4 and the fifth node N5, to continuously initialize (reset) signals of the fourth node N4 and the fifth node N5. A signal of the first scan signal line G1 is a high-level signal, the first transistor T1 is turned on, and the data voltage of the data signal line Data is written to the first node N1. At this time, the voltage value V1 of the first node N1 meets V1=Vdata, wherein Vdata is the data voltage of the data signal line. The voltage value of the signal of the first node N1 in the present stage undergoes a jump compared to the voltage value in the previous stage. Therefore, a signal of the third node N3 also undergoes a jump under an action of the first capacitor C1 and the second capacitor C2. At this time, the voltage value V3 of the signal of the third node N3 meets V3=Vref-Vth+(Vdata-Vref)*C 1 / (C 1 +C 2 ), where C 1 is the capacitance value of the first capacitor, C 2 is the capacitance value of the second capacitor. Signals of the second scan signal line G2, the first light emitting signal line EM1, and the second light emitting signal line EM2 are low-level signals, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. The light emitting device L does not emit light in this stage.

[0342] In a fourth stage P54, that is, a light emitting stage, signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, and signals of the first reset signal line Reset1, the third reset signal line Reset3, the fourth reset signal line Reset4, the first scan signal line G1 and the second scan signal line G2 are low-level signals. Signals of the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, a power supply voltage output from the first power supply line VDD provides a driving voltage to a first electrode of the light emitting device L through the turned-on fourth transistor T4, third transistor T3 and fifth transistor T5, to drive the light emitting device L to emit light, and signals of the first reset signal line Reset1, the third reset signal line Reset3, the fourth reset signal line Reset4, the first scan signal line G1 and the second scan signal line G2 are low-level signals, and the first transistor T1, second transistor T2, sixth transistor T6, eighth transistor T8 and ninth transistor T9 are turned off, and the light emitting device L emits light in this stage.

[0343] In a drive process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by a voltage difference between the control electrode (also the first node N1) and the second electrode (also the third node N3) of the third tra...

Claims

1. A pixel driving circuit provided in a display apparatus, comprising: a driving sub-circuit, a storage sub-circuit, a first control sub-circuit, a second control sub-circuit, and a third control sub-circuit; wherein, the driving sub-circuit is electrically connected to a first node, a second node, and a third node respectively, and configured to provide a driving current to the third node under control of signals of the first node and the second node; the storage sub-circuit is electrically connected to the first node and the third node, respectively, and configured to store a voltage difference between signals of the first node and the third node; the first control sub-circuit is electrically connected to a first scan signal line, a second scan signal line, a data signal line, a reference signal line and the first node, respectively, and configured to provide a signal of the data signal line or the reference signal line to the first node under control of signals of the first scan signal line and the second scan signal line; the second control sub-circuit is electrically connected to a first light emitting signal line, a second light emitting signal line, a first power supply line, the second node, the third node and a fourth node, respectively, and configured to provide a signal of the first power supply line to the second node and provide a signal of the third node to the fourth node under control of signals of the first light emitting signal line and the second light emitting signal line; the third control sub-circuit is electrically connected to the third node, the fourth node, at least one reset signal line, and at least one signal line of a dynamic signal line and an auxiliary signal line, respectively, and configured to adjust signals of the third node and the fourth node under control of signals of the at least one reset signal line and the at least one signal line of the dynamic signal line and the auxiliary signal line; wherein the display apparatus comprises: a first control unit, a second control unit, and a data unit, the first control unit is electrically connected to the second light emitting signal line and configured to provide a signal to the second light emitting signal line, the second control unit is electrically connected to the at least one reset signal line and configured to provide a signal to the at least one reset signal line, and the data unit is electrically connected to the dynamic signal line and configured to provide a signal to the dynamic signal line; content displayed by the display apparatus comprises at least one display frame in which a start time of at least one time period in which the first control unit provides an effective level signal to the second light emitting signal line is earlier than or equal to a start time at which the second control unit provides an ineffective level signal to the at least one reset signal line.

2. The pixel driving circuit according to claim 1, wherein a voltage value of a signal of the dynamic signal line comprises a plurality of voltage values, and a voltage value of a dynamic signal provided by the data unit to the dynamic signal line is positively correlated with a temperature of the display apparatus at at least some moments of the at least one display frame.

3. The pixel driving circuit according to claim 1, wherein the at least one reset signal line comprises: a third reset signal line; the third control sub-circuit is electrically connected to the third node, the fourth node, the third reset signal line and the dynamic signal line, respectively.

4. The pixel driving circuit according to claim 3, wherein the third control sub-circuit comprises a second capacitor and an eighth transistor; a first terminal of the second capacitor is electrically connected to the third node, and a second terminal of the second capacitor is electrically connected to the fourth node; and a control electrode of the eighth transistor is electrically connected to the third reset signal line, a first electrode of the eighth transistor is electrically connected to the dynamic signal line, and a second electrode of the eighth transistor is electrically connected to the fourth node.

5. The pixel driving circuit according to claim 3 or 4, wherein the display apparatus further comprises: a third control unit electrically connected to the first light emitting signal line and configured to provide a signal to the first light emitting signal line; in the at least one display frame, the start time of the at least one time period in which the first control unit provides the effective level signal to the second light emitting signal line is earlier than a start time at which the second control unit provides an ineffective level signal to the third reset signal line, and a start time of at least one time period in which the third control unit provides an effective level signal to the first light emitting signal line is later than the start time at which the second control unit provides the ineffective level signal to the third reset signal line.

6. The pixel driving circuit according to claim 1, wherein the at least one reset signal line comprises: a first reset signal line and a third reset signal line; the third control sub-circuit is electrically connected to the third node, the fourth node, the first reset signal line, the third reset signal line and the dynamic signal line, respectively.

7. The pixel driving circuit according to claim 6, wherein: the third control sub-circuit comprises: a second capacitor, a sixth transistor, and an eighth transistor; a first terminal of the second capacitor is electrically connected to the third node, and a second terminal of the second capacitor is electrically connected to a fifth node; a control electrode of the sixth transistor is electrically connected to the first reset signal line, a first electrode of the sixth transistor is electrically connected to the fifth node, and a second electrode of the sixth transistor is electrically connected to the fourth node; and a control electrode of the eighth transistor is electrically connected to the third reset signal line, a first electrode of the eighth transistor is electrically connected to the dynamic signal line, and a second electrode of the eighth transistor is electrically connected to the fourth node.

8. The pixel driving circuit according to claim 6, wherein the third control sub-circuit comprises: a second capacitor, a third capacitor, a sixth transistor, and an eighth transistor; a first terminal of the second capacitor is electrically connected to the third node, and a second terminal of the second capacitor is electrically connected to a fifth node; a first terminal of the third capacitor is electrically connected to the fifth node, and a second terminal of the third capacitor is electrically connected to the fourth node; a control electrode of the sixth transistor is electrically connected to the first reset signal line, a first electrode of the sixth transistor is electrically connected to the fifth node; and a second electrode of the sixth transistor is electrically connected to the fourth node; and a control electrode of the eighth transistor is electrically connected to the third reset signal line, a first electrode of the eighth transistor is electrically connected to the dynamic signal line, and a second electrode of the eighth transistor is electrically connected to the fourth node.

9. The pixel driving circuit according to claim 1, wherein the at least one reset signal line comprises: a first reset signal line and a third reset signal line; the third control sub-circuit is electrically connected to the third node, the fourth node, the first reset signal line, the third reset signal line, the dynamic signal line and the auxiliary signal line, respectively.

10. The pixel driving circuit according to claim 9, wherein the third control sub-circuit comprises: a second capacitor, a third capacitor, a sixth transistor, and an eighth transistor; a first terminal of the second capacitor is electrically connected to the third node, and a second terminal of the second capacitor is electrically connected to a fifth node; a first terminal of the third capacitor is electrically connected to the fifth node, and a second terminal of the third capacitor is electrically connected to the auxiliary signal line; a control electrode of the sixth transistor is electrically connected to the first reset signal line, a first electrode of the sixth transistor is electrically connected to the fifth node, and a second electrode of the sixth transistor is electrically connected to the fourth node; and a control electrode of the eighth transistor is electrically connected to the third reset signal line, a first electrode of the eighth transistor is electrically connected to the dynamic signal line, and a second electrode of the eighth transistor is electrically connected to the fourth node.

11. The pixel driving circuit according to claim 1, wherein the at least one reset signal line comprises: a first reset signal line and a third reset signal line; the third control sub-circuit is electrically connected to the third node, the fourth node, the first reset signal line, the third reset signal line and the auxiliary signal line, respectively.

12. The pixel driving circuit according to claim 11, wherein the third control sub-circuit comprises: a second capacitor, a third capacitor, a sixth transistor, and a ninth transistor; a first terminal of the second capacitor is electrically connected to the third node, and a second terminal of the second capacitor is electrically connected to a fifth node; a first terminal of the third capacitor is electrically connected to the fifth node, and a second terminal of the third capacitor is electrically connected to the fourth node; a control electrode of the sixth transistor is electrically connected to the first reset signal line, a first electrode of the sixth transistor is electrically connected to the fifth node, and a second electrode of the sixth transistor is electrically connected to the fourth node; and a control electrode of the ninth transistor is electrically connected to the third reset signal line, a first electrode of the ninth transistor is electrically connected to the auxiliary signal line, and a second electrode of the ninth transistor is electrically connected to the fifth node.

13. The pixel driving circuit according to any one of claims 6 to 12, wherein the display apparatus further comprises: a third control unit electrically connected to the first light emitting signal line and configured to provide a signal to the first light emitting signal line, the second control unit comprises: a first sub-control unit electrically connected to the first reset signal line and configured to provide a signal to the first reset signal line, and a second sub-control unit electrically connected to the third reset signal line and configured to provide a signal to the third reset signal line; in the at least one display frame, at least one of a start time at which the first sub-control unit provides an ineffective level signal to the first reset signal line and a start time at which the second sub-control unit provides an ineffective level signal to the third reset signal line is later than the start time of the at least one time period in which the first control unit provides the effective level signal to the second light emitting signal line and is earlier than a start time of at least one time period in which the third control unit provides an effective level signal to the first light emitting signal line, and the start time at which the first sub-control unit provides the ineffective level signal to the first reset signal line is earlier than the start time at which the second sub-control unit provides the ineffective level signal to the third reset signal line.

14. The pixel driving circuit according to claim 1, wherein the at least one reset signal line comprises: a first reset signal line, a third reset signal line, and a fourth reset signal line; the third control sub-circuit is electrically connected to the third node, the fourth node, the first reset signal line, the third reset signal line, the fourth reset signal line, the dynamic signal line and the auxiliary signal line, respectively.

15. The pixel driving circuit according to claim 14, wherein the third control sub-circuit comprises: a second capacitor, a third capacitor, a sixth transistor, an eighth transistor, and a ninth transistor; a first terminal of the second capacitor is electrically connected to the third node, and a second terminal of the second capacitor is electrically connected to a fifth node; a first terminal of the third capacitor is electrically connected to the fifth node, and a second terminal of the third capacitor is electrically connected to the fourth node; a control electrode of the sixth transistor is electrically connected to the first reset signal line, a first electrode of the sixth transistor is electrically connected to the fifth node, and a second electrode of the sixth transistor is electrically connected to the fourth node; a control electrode of the eighth transistor is electrically connected to the third reset signal line, a first electrode of the eighth transistor is electrically connected to the dynamic signal line, and a second electrode of the eighth transistor is electrically connected to the fourth node; and a control electrode of the ninth transistor is electrically connected to the fourth reset signal line, a first electrode of the ninth transistor is electrically connected to the auxiliary signal line, and a second electrode of the ninth transistor is electrically connected to the fifth node.

16. The pixel driving circuit according to claim 14 or 15, wherein the display apparatus further comprises: a third control unit electrically connected to the first light emitting signal line and configured to provide a signal to the first light emitting signal line, the second control unit comprises a first sub-control unit, a second sub-control unit and a third sub-control unit, wherein the first sub-control unit is electrically connected to the first reset signal line and configured to provide a signal to the first reset signal line, the second sub-control unit is electrically connected to the third reset signal line and configured to provide a signal to the third reset signal line, and the third sub-control unit is electrically connected to the fourth reset signal line and configured to provide a signal to the fourth reset signal line; in the at least one display frame, at least one of a start time at which the first sub-control unit provides an ineffective level signal to the first reset signal line, a start time at which the second sub-control unit provides an ineffective level signal to the third reset signal line, and a start time at which the third sub-control unit provides an ineffective level signal to the fourth reset signal line is later than the start time of the at least one time period in which the first control unit provides the effective level signal to the second light emitting signal line and earlier than a start time of at least one time period in which the third control unit provides an effective level signal to the first light emitting signal line, and the start time at which the first sub-control unit provides the ineffective level signal to the first reset signal line is earlier than at least one of the start time at which the second sub-control unit provides the ineffective level signal to the third reset signal line and the start time at which the third sub-control unit provides the ineffective level signal to the fourth reset signal line.

17. The pixel driving circuit according to claim 1, wherein the driving sub-circuit comprises: a third transistor, the first control sub-circuit comprises: a first transistor and a second transistor, the second control sub-circuit comprises: a fourth transistor and a fifth transistor, and the storage sub-circuit comprises: a first capacitor; a control electrode of the first transistor is electrically connected to the first scan signal line, a first electrode of the first transistor is electrically connected to the data signal line, and a second electrode of the first transistor is electrically connected to the first node; a control electrode of the second transistor is electrically connected to the second scan signal line, a first electrode of the second transistor is electrically connected to the reference signal line, and a second electrode of the second transistor is electrically connected to the first node; a control electrode of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the second node, and a second electrode of the third transistor is electrically connected to the third node; a control electrode of the fourth transistor is electrically connected to the first light emitting signal line, a first electrode of the fourth transistor is electrically connected to the first power supply line, and a second electrode of the fourth transistor is electrically connected to the second node; a control electrode of the fifth transistor is electrically connected to the second light emitting signal line, a first electrode of the fifth transistor is electrically connected to the third node, and a second electrode of the fifth transistor is electrically connected to the fourth node; and a first terminal of the first capacitor is electrically connected to the first power supply line, and a second terminal of the first capacitor is electrically connected to the first node; wherein the display apparatus further comprises: a fourth control unit electrically connected to the first scan signal line and configured to provide a signal to the first scan signal line, and a fifth control unit electrically connected to the second scan signal line and configured to provide a signal to the second scan signal line; in the at least one display frame, an end time at which the fifth control unit provides an effective level signal to the second scan signal line is earlier than a start time at which the fourth control unit provides an effective level signal to the first scan signal line, and the start time at which the fourth control unit provides the effective level signal to the first scan signal line is earlier than the start time of the at least one time period in which the first control unit provides the effective level signal to the second light emitting signal line.

18. The display apparatus according to claim 1, wherein the dynamic signal line is an initial signal line; a signal of the auxiliary signal line is a signal of at least one signal line of the first power supply line, the reference signal line, and the initial signal line.

19. A display apparatus comprising: sub-pixels arranged in an array, wherein at least one of the sub-pixels comprises: the pixel driving circuit according to any one of claims 1 to 18.

20. The display apparatus according to claim 19, further comprising: a temperature sensor, a control chip, and a signal transmission component, wherein the signal transmission component comprises a data unit, wherein a sub-pixel is electrically connected to the dynamic signal line; the temperature sensor is configured to detect a first temperature signal of the display apparatus; the control chip is electrically connected to the temperature sensor and the signal transmission component, respectively, and configured to acquire the first temperature signal detected by the temperature sensor, obtain a voltage offset corresponding to the at least one sub-pixel according to the first temperature signal, obtain an adjusted dynamic signal corresponding to the at least one sub-pixel according to the voltage offset corresponding to the at least one sub-pixel, and transmit the adjusted dynamic signal to the signal transmission component, and is further configured to transmit a control signal to the signal transmission component; the signal transmission component is electrically connected to the dynamic signal line and configured to provide the adjusted dynamic signal corresponding to the sub-pixel to the dynamic signal line to which the sub-pixel is connected, under control of the control signal.

21. The display apparatus according to claim 20, wherein the control chip is further configured to acquire the first temperature signal detected by the temperature sensor within a preset time interval.

22. The display apparatus according to claim 20, wherein a correspondence table between temperatures and voltage offsets is stored in the control chip, and the control chip is further configured to obtain a second temperature signal according to the first temperature signal, and obtain the voltage offset corresponding to the at least one sub-pixel by looking up the correspondence table according to the second temperature signal, wherein the first temperature signal is an analog signal, and the second temperature signal is a digital signal.

23. The display apparatus according to claim 20, wherein the control chip is further configured to acquire a current dynamic signal of the at least one sub-pixel, and obtain the adjusted dynamic signal corresponding to the at least one sub-pixel according to the current dynamic signal of the at least one sub-pixel and the voltage offset corresponding to the at least one sub-pixel.

24. The display apparatus according to claim 20, wherein voltage values of dynamic signals at a same temperature of at least two among a plurality of sub-pixels are same.

25. The display apparatus according to claim 20, wherein the signal transmission component is further configured to provide the adjusted dynamic signal corresponding to the at least one sub-pixel to a dynamic signal line, to which the at least one sub-pixel is connected, in the at least one display frame under control of the control signal.

26. A method for driving a pixel driving circuit, used to drive the pixel driving circuit according to any one of claims 1 to 18, wherein the method comprises: providing, by the driving sub-circuit, a driving current to the third node under control of signals of the first node and the second node; storing, by the storage sub-circuit, the voltage difference between the signals of the first node and the third node; providing, by the first control sub-circuit, the signal of the data signal line or the reference signal line to the first node under control of signals of the first scan signal line and the second scan signal line; providing, by the second control sub-circuit, the signal of the first power supply line to the second node and the signal of the third node to the fourth node under control of signals of the first light emitting signal line and the second light emitting signal line; and adjusting, by the third control sub-circuit, signals of the third node and the fourth node under control of signals of the at least one reset signal line and at least one of the dynamic signal line and the auxiliary signal line; wherein in the at least one display frame, a start time of at least one time period in which the first control unit provides an effective level signal to the second light emitting signal line is earlier than or equal to a start time at which the second control unit provides an ineffective level signal to the at least one reset signal line.

27. A signal processing method, applied to the display apparatus of any one of claims 19 to 25, the method comprising: acquiring a first temperature signal detected by a temperature sensor; obtaining a voltage offset corresponding to at least one sub-pixel according to the first temperature signal; obtaining an adjusted dynamic signal corresponding to the at least one sub-pixel according to the voltage offset corresponding to the at least one sub-pixel, and transmitting the adjusted dynamic signal to a signal transmission component, to enable the signal transmission component to provide the adjusted dynamic signal corresponding to the sub-pixel to a dynamic signal line connected to the sub-pixel under control of a control signal; the acquiring the first temperature signal detected by the temperature sensor comprises: acquiring the first temperature signal detected by the temperature sensor within a preset time interval; the obtaining the voltage offset corresponding to the at least one sub-pixel according to the first temperature signal comprises: obtaining a second temperature signal according to the first temperature signal, obtaining the voltage offset corresponding to the at least one sub-pixel by looking up a correspondence table according to the second temperature signal, wherein the first temperature signal is an analog signal, and the second temperature signal is a digital signal; the obtaining the adjusted dynamic signal corresponding to the at least one sub-pixel according to the voltage offset corresponding to the at least one sub-pixel comprises: acquiring a current dynamic signal of the at least one sub-pixel, and obtaining the adjusted dynamic signal corresponding to the at least one sub-pixel according to the current dynamic signal of the at least one sub-pixel and the voltage offset corresponding to the at least one sub-pixel.

Images