Surface emitting laser

Abstract

An extended vertical cavity surface emitting laser (VCSEL), includes: an epitaxially laterally overgrown semiconductor section, configured by a III-nitride active region between a hole injecting III-nitride layer and an electron injecting III-nitride layer; an angled p-type mirror on a hole injecting side; and a flat mirror comprising a nanoporous layer on an electron injecting side and a nonporous layers on an n-side, which are angled relative to the III-nitride active region.

Description

SURFACE EMITTING LASER

[0001] This invention relates to a III-nitride vertical cavity surface emitting laser (VCSEL) with nanoporus GaN DBR.

[0002] This application references a number of patent or non-patent publications as indicated throughout the specification by their reference numbers within brackets, i.e., [ ]. A list of the publications ordered according to these reference numbers can be found below in the section entitled “Non Patent Literature” or “Patent literature”.

[0003] Appl. Phys. Lett. 92, 141102 (2008)Appl. Phys. Express 12, 044004 (2019)Sci. Rep. 8, 10350 (2018)Jpn. J. Appl. Phys. 58, SC0806 (2019)Appl. Phys. Express 11, 112101 (2018)Appl. Phys. Lett. 101, 151113 (2012)ACS Photonics, 2 980-986 (2015)Sci. Rep. 7, 45344 (2017)Appl. Phys. Lett. 112, 041109 (2018)Scr. Mater, 156, 10-13 (2018)Appl. Phys. Express 2012, 5, 092104Optics Express, 27, 24717 (2019)Appl. Phys. Express, 13, 041003 (2020)Appl. Phys. Express, 14,031002 (2021)Applied Phys. Lett.119, 142103 (2021)Crystals, 11 (12) 1563, (2021)M. B. Stern and T. R. Jay, “Dry etching for coherent refractive microlens arrays,” Opt. Eng. 33, 3547-3551 (1994)

[0004] Surface emitting lasers are known as vertical cavity surface emitting lasers (VCSELs). A VCSEL comprises a semiconductor active region disposed between an n-side semiconductor region and a p-side semiconductor region, and two distributed Bragg reflectors, DBRs, which act as high reflective mirrors. The semiconductor active region, also known as gain medium, is disposed between the two DBRs to form an optical cavity. The n-side and p-side regions inject respective carriers, i.e., electron and hole, to the active region, and these carriers are recombined in the active region to generate light. Light or electromagnetic radiation thus generated is reflected many times by the DBRs to travel in the optical cavity, thereby lasing. The VCSEL provides one of the DBRs with a less reflectance mirror, which is used to emit the laser beam.

[0005] Gallium nitride (GaN) VCSELs have recently been receiving increasing research attention due to their ability to emit in the visible and ultraviolet (UV) regions. This opens a variety of new application space in displays, solid state lighting including automotive lighting and residential lighting, sensing and communications. One of the most exciting applications of all is when blue emitting GaN VCSELs coupled with phosphor device collectively functions as natural light emitting source as well as data transmission device, since VCSELs consumes less energy and have high modulation rates. This application would address AR / VR applications, smartphone and normal displays in a new dimension by adding a communication feature to each light emitting pixel.

[0006] GaAs-based Infra-red VCSELs adopted a matured manufacturing technique, whereas the III-nitride based VCSELs still lacking industrial feasibility. Continuous-wave (CW) lasing at 462 nm of electrically injected GaN VCSEL was first demonstrated in 2008 at a temperature of 77K [NPL 1]. Since then, considerable progress has been made in terms of output power, efficiency, threshold current, lasing wavelength, and room temperature stability. However, industrial feasibility still not achieved. One of the problems is n-side DBR mirror, which is in general dielectric DBR causing thermal instability in the device operation. Conventionally, a dielectric DBR is deposited on the n-side of the VCSEL after laboriously polishing off the host substrate. Alternative approaches such as epitaxial DBRs, nanoporous GaN DBRs have been grown on top of the host substrate, and long optical GaN cavity VCSELs were proposed in the literatures for better thermal stability.

[0007] These approaches were great to a certain extent, but problems such as expensive GaN substrates, increased growth times epitaxial DBR while preserving device layers quality and the expensive GaN substrate rid-off methods even for long cavity and nanoporous GaN DBR cavities need to be addressed.

[0008] VCSEL with a long optical cavity and the curved lens refocuses electric filed into the gain medium there by reducing diffraction loses that originate from the longer cavity length [NPL 2-NPL 4]. Up until 2022, long cavity designs from Sony held the performance records for CW output power of 15.8 mW, threshold current 0.25 mA, and wall plug efficiency (WPE) 9.5%. Long-optical GaN cavity VCSEL designs have accomplished impressive results by utilizing significant portion of the host substrate in the cavity design. Substrate is redesigned to curved mirror after grinding away the unnecessary portion, which is again a laborious and both time and money consuming process. In the long optical cavity designs, the curved mirror is necessary because it prevents diffraction and scattering loss. The typical gain of active region in the nitride VCSEL is ~1%, so in long optical GaN cavity diffraction loss can quickly deteriorates device performance for cavities larger than 10 micrometers. Sony curved mirror VCSEL cavity is ~28 micrometers. This will briefly be giving a peak into the amount of difficulty involved in polishing with cavities nearing towards active region.

[0009] On the other hand, epitaxial designs utilizing AlGaN / GaN or AlInN / GaN mirror pairs have also been on radar recent times especially [NPL 5-NPL 6], the later showing a superior performance due to ability of AlInN lattice match to GaN. However, requiring ~40 or more periods of AlInN / GaN layers to reach a reasonable reflectivity (>99.5% for emission side) and equally maintaining sensitive growth conditions for better quality and improved yields can make epitaxial DBR designs difficult to realize.

[0010] And most recently, nanoporous GaN DBR (NP-GaN DBR) designs [NPL 7- NPL 10] have also been gaining traction due to their relative ease of fabrication, their lattice match to GaN and their high achievable refractive index contrast. Due to this high index contrast, a realistic porosity of 36% can achieve 99.5% reflectivity with only 17 periods. Since first NP-GaN DBRs first demonstrated in 2015, multiple groups have achieved lasing with NP-GaN DBR designs. NP-GaN DBR layers provide better thermal stability than dielectric DBR mirror. However, a common problem of thinning and grinding of expensive host GaN substrate after realizing NP-GaN DBR layers on the substrate persists.

[0011] The ideal VCSEL should be capable of addressing the following concerns in an effective way 1) Better crystal quality III-nitride layers Currently most of the companies focusing on making III-nitride VCSELs on bulk GaN substrates. The best available III-nitride bulk substrates have 106defects / cm2. VCSEL active volume is small, approximately ~10 times small compared to the conventional edge emitting lasers. Therefore, better crystal quality than the existing bulk substrates quality is preferred. Moreover, bulk GaN substrates are very expensive even for the present existing quality, thus demand for more better quality escalates the price and further delays the III-nitride VCSEL into the market 2) Large size wafers needed for better yields. Generally, VCSEL is a nearly a clone of LED fabrication. Most of the LEDs were fabricated on 6-inch or lager size substrates. Also, it is a natural choice for a manufacturer to choose large size substrates for better yields and enabling a competitive price. 3) Thermal stability by providing thermal conducting DBR mirrors Also, one of the technical issues that was keeping VCSEL away from the market is placement of n-side DBR mirror. As VCSELs are surface emitting lasers and thinner along the substrate surface plane. Even though expensive bulk III-nitride substrates were used initially to form thin VCSEL device layers, the expensive III-nitride substrate must be removed from the VCSEL device for the placement of n-side dielectric DBR mirror, or substrate material friendly DBR layers should be placed before forming VCSEL device layers. Some of the approaches to circumvent VCSEL manufacturing issues. Long Cavity VCSEL: To avoid the need of removing substrate to a level that decreases yield, Sony come up with long cavity VCSEL which still keeps the significant amount of substrate in the optical cavity of VCSEL. The design provides better thermal stability due to long cavity III-nitride material, However, the design has some practicle limits on the amount of cavity length and emission mode of the cavity. Epitaxial DBR: As said earlier, InGaN / GaN or AlN / GaN epitaxial DBRs have been proposed in the literature. In such ~40 pairs of In0.82Ga0.18N / GaN lattice matched DBR mirror layers are necessary for getting reflectance above 99% due to low index contrast. Long growth time and difficult control of In and Al compositions are still concerns. Also, heat dissipation and vertical injection problems persists. Light emission side is epitaxial DBR side due to less reflectivity, so the substrate region below epitaxial DBR mirror needs some surface treatments or at times need grinding to reduce absorption and scattering loss. Nano-porous (NP) DBR: Usually nanoporous DBRs have high reflectance > 99% and simple lattice matched growth to GaN. Applicable to all the crystal orientations of GaN. Moreover, reflectance of the layers is tunable. However, as the NP layers configured parallel to the device’s active layers, which is not ideally the best configuration to extract heat and also to inject vertical carrier configuration. 4) Intra-cavity current spreading layer on the p-side VCSEL device by default faces a problem on p-side due to higher activation energy required for the p-type conductivity. Increased resistance from the p-GaN layers. Researchers minimize p-GaN layer thickness in VCSEL devices in order to eliminate Joule heating as well as optical absorption. By reducing p-GaN layer thickness and placing a current spreading layer such as transparent conducting oxides (TCO), like Indium Tin Oxide or more tunnel junctions help the design, but optical absorption still becomes a problem. Researchers cleverly placed intra-cavity conduction layers at the minimal electromagnetic field of the device, however such a fine requirements decreases yield and increases cost. Few of the above problems can be addressed by substrate removal techniques such as photo electro chemical (PEC) [NPL 11] and epitaxial lateral overgrowth (ELO) assisted thermal peel off [NPL 12- NPL 16], but not all.

[0012] Considering all these disadvantages, an object of the present invention is to provide a III-nitride VCSEL with a nanoporous GaN DBR and making the nanoporous GaN DBR more functional for improved device performance in terms of thermal and optical properties.

[0013] To overcome the limitations of prior art described above, the present invention discloses a III-nitride-based VCSEL, comprising: a III-nitride active region between a p-type (hole injecting) III-nitride layer and an n-type (electron injecting) III-nitride layer; and a flat dielectric mirror designed on or above the angled p-type III-nitride layer.

[0014] ELO growth starts by step-by-step establishment of III-nitride crystal planes, by applying a proper growth mode with optimized parameters, one can constantly preserve that plane. On top of that modulating supplied sources periodically and then doping the layers as desired can alter the growth planes more precisely in epitaxial lateral overgrowth. Combining ELO technology with a modulated growth slanted (semipolar) III-nitride layers with a designed doping levels results a high crystalline quality crystalline planes over the dielectric mask. These layers which were subjected to selective doping are later formed into porous III-nitride layers resulting a slanted NP-GaN DBR mirror.

[0015] Optical cavity thickness comprising device layers n-GaN layer, active region, p-AlGaN electron blocking layer and p-GaN layer, (and sometimes current spreading tunnel junction (p++ / n++ GaN) can be controlled during the epitaxial growth.

[0016] The VCSEL further comprises: one or more tunnel junction layers on the p-side III-nitride layer for the current injection, wherein the dielectric DBR mirror placed away from the tunnel junction at an angle.

[0017] The VCSEL further comprise: one or more transparent conducting oxide (TCO) layers on p-type III-nitride layer as an intracavity contact layer instead of tunnel junction. TCO layers may compose of ITO, ZnO.

[0018] The VCSEL further comprises an area to place a dielectric DBR mirror on or above p-type III-nitride region, wherein p-type III-nitride layer was shaped to form an angle with active layer plane.

[0019] The VCSEL further comprises the angled p-type III-nitride layer is one of the semipolar planes of the III-nitride material obtained either through physical or chemical etching. Preferably, a combination of physical, and chemical to smoothen the surface for the placement of dielectric DBR mirror layers. The surface morphology of the etched semipolar plane on p-GaN layer can be controlled by using etchants like H3PO4, KOH etc. Alternatively, acidic or basic etching method similar to c-plane Ga-polar etching with 5M NaOH. Alternatively, 98% H2SO4dip help to prepare the semipolar plane surface to place dielectric DBR mirror layers.

[0020] The VCSEL further comprises a periodic selectively doped III-nitride layers on or above dielectric mask. The selectively doped III-nitride layers are later formed into nanoporous layers and undoped bulk III-nitride layers inserted between the selectively doped remain as non-porous. The VCSEL further composed of alternatively arranged nanoporous layers which are highly doped n-type compared to the non-porous bulk III-nitride layers.

[0021] The VCSEL further composed of nanoporus and non-porous III-nitride layers arranged alternatively such that the combination constitutes a slanted n-type DBR mirror and the layers orient like a one of the III-nitride semipolar planes.

[0022] The VCSEL further composed of periodically modulated layers growth in the preparation selectively doped semipolar layers. Wherein, NH3, Ga-metal and n-type doping sources are passed / changed in periodic fashion to achieve a sharp interface between nano- and non-porous III-nitride layers boundaries.

[0023] The VCSEL further composed of non-porous bulk III-nitride layers and nanoporus III-nitride layers have a same interface with the dielectric mask and this mask was later dissolved in the device making process. This interface can provide an access for vertical current injection and thermal draining.

[0024] The VCSEL further engineered to have a smooth (sub-nanometer) interface between slanted III-nitride n-type DBR mirror and the dielectric mask. The dielectric mask material in the III-nitride layer growth is prepared using SiO2or SiN, preferably a combination of both using tools like sputter, atomic layer deposition or Plasma Enhanced Chemical Vapor Deposition (PECVD) or ion beam deposition.

[0025] The VCSEL further comprises discrete island-like III-nitride ELO base layers, such that ease of accessibility provided for the chemicals used in electrochemical etching, wherein pores formation realized in the selectively doped GaN layers via electro chemical etching.

[0026] The bulk non-porous III-nitride layer of the DBR mirror has a better thermal conductivity and electrical conductivity compared to the nanoporous III-nitride layer. Thus, when combined these layers in an alternative periodic arrangement the system is best both at functioning as a DBR mirror and as thermal heatsink and electrical injector. The host substarte crystalline orenattion for the chosen invention can be c-plane, semipolar or non-polar, but preferably, c-plane.

[0027] Fig. 1A is a schematic, wherein: Fig. 1A shows a foreign substrate with III-nitride template.Fig. 1B is a schematics, wherein: Fig. 1B shows a dielectric mask open area patterning to III-nitride growth layer.Figs. 1C is a schematic, wherein: Fig. 1C shows a schematic of a stripes design to accommodate VCSEL devices on each.Figs. 1D is a schematic, wherein: Fig. 1D is triangular lattice pattern.Figs. 1E is a schematic, wherein: Fig. 1F is an alternative approach to grow ELO base layers using patterned III-nitride templates.Figs. 1F is a schematic, wherein: Fig. 1G is an alternative approach to grow ELO base layers using patterned III-nitride templates.Figs. 2A is a schematic after the growth of base ELO III-nitride layer.Figs. 2B is a schematic after the growth of base ELO III-nitride layer.Figs. 2C is a schematic after the growth of base ELO III-nitride layer.Figs. 2D is a schematic of planarized ELO base.Fig. 3A describes various growth modes of III-nitride crystal ELO growth.Fig. 3B describes various growth modes of III-nitride crystal ELO growth.Fig. 3C describes various growth modes of III-nitride crystal ELO growth.Fig. 3D describes various growth modes of III-nitride crystal ELO growth.Fig. 3E describes various growth modes of III-nitride crystal ELO growth.Fig. 3F describes various growth modes of III-nitride crystal ELO growth.Fig. 3G describes various growth modes of III-nitride crystal ELO growth.Fig. 3H describes various growth modes of III-nitride crystal ELO growth.Fig. 3I describes various growth modes of III-nitride crystal ELO growth.Fig. 3J describes various growth modes of III-nitride crystal ELO growth.Fig. 3K describes various growth modes of III-nitride crystal ELO growth.Fig. 4A respectively show planarized ELO base layers in the shape of bars and hexagonal structures displayed alternatively doped III-nitride layers.Fig. 4B is respectively show planarized ELO base layers in the shape of bars and hexagonal structures displayed alternatively doped III-nitride layers.Fig. 5A is a schematic of the processed VCSEL design before taking off from host substrate.Fig. 5B is processed VCSEL with vertical current injection.Fig. 5C is a VCSEL with tunnel junction.Fig. 5D is processed VCSEL with tunnel junction and heat spreader.Fig. 6A is a schematic of the processed VCSEL with more than one optical cavity in the ELO bar configuration before taking off from host substrate.Fig. 6B is processed VCSEL with vertical current injection.Fig. 6C is a processed VCSEL on hexagonal pattern with different optical cavities.Fig. 6D is processed VCSEL on hexagonal pattern with a ring-like emission.Fig. 7A is a typical chip dimension from ELO bar.Fig. 7B is integration of ELO bar and hexagonal VCSELs on wafer scale.

[0028] Teachings of the present invention can be readily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Referring to the accompanying drawings, a schematic view showing a vertical cavity surface emitting laser (VCSEL), and a method for fabricating a VCSEL according to the present disclosure will be described below. To facilitate understanding, identical reference numerals are used, where possible, to designate identical elements that are common to the figures.

[0029] In the following embodiments descriptions provided to the referenced drawings The use of non- and nanoporous slanted DBR mirror over the ELO base layer and an angled DBR mirror on p-side of III-nitride VCSEL are proposed to be a viable way to improve device performance in terms of thermal, optical and electrical. Technical disclosure:

[0030] The following disclosure is divided into four sections. The first section describes the ELO base layer preparation. The second section provides information on porous and non-porous layers growth. The third section illustrates VCSEL device fabrication procedures and the advantages.

[0031] Section1: Preparation of ELO base The ELO method to form the island-like III-nitride semiconductor layers may include growth by metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), etc. The III-nitride semiconductor layers are dimensioned to create one or more of the island-like III-nitride semiconductor layers. Alternatively, the ELO III-nitride layers can made to coalesce initially, such that they can be later divided into individual devices.

[0032] ELO layer has two parts one is open region which generally have more defects compared to its counterpart extending onto an ELO mask. The counterpart extends both ways onto the ELO mask from open region termed them as ELO wings. The VCSEL light emitting aperture is made on the ELO wing. Moreover, the present invention can use hetero-substrates to grow the island-like III-nitride semiconductor layers that form the bar. For example, a GaN template grown on a hetero-substrate, such as Sapphire, Si, SiC, SiN, GaAs, Ga2O3, LiAlO2, ScAlMgO4(SAM) etc., can be used in the present invention.

[0033] Furthermore, the ELO method can drastically reduce dislocation density and stacking faults density when non Basel GaN crystal planes used, which are critical issues when using hetero-substrates. Therefore, this invention can solve many kinds of problems incurred with the use of hetero-substrates, at the same time. For example, in a laser device, the interface between ELO mask and the III-nitride template layer can be made smooth such that light emission from the interface side will not be effected.

[0034] Figs. 1A, 1B, and 1C are schematics that illustrate a method, which comprises providing a III-nitride-based substrate 10, such as a GaN-on-Si, GaN-on-Sapphire, or bulk GaN substrate, GaN-on-ScAlMgO4(SAM). In the case of a foreign substrate 10, a III-nitride template 11 can be deposited on the substrate 10, and III-nitride template 11 can be a uniform layer over the host foreign substrate 10, or the template 11 can be disposed at the open area stripe 12. A III-nitride stripe design containing substrate 10, such as the stripes shown in the schematics of Fig. 1C. The open area stripes 12 can designed as a single device by shortening its length, or a plurality of devices by increasing its length. Alternatively, as illustrated in Fig. 1D, a triangular lattice of circular opening patches can be designed on the dielectric mask 13 while openings exposing underlying III-nitride layer.

[0035] As shown in the schematics of Figs. 1C and 1D, a dielectric mask 13 is formed on or above III-nitride template 11 containing substrate 10. Specifically, the dielectric mask 13 is disposed directly in contact with the substrate 10 or is disposed indirectly through a template layer grown by MOCVD, etc.

[0036] The dielectric mask 13 can be formed from an insulator film, for example, an SiO2film, deposited upon the substrate 10, for example, by a plasma chemical vapor deposition (CVD), sputter, ion beam deposition (IBD), etc., wherein the SiO2film is then patterned by photolithography using a predetermined photo mask and etching to include opening areas as shown in Fig. 1B and 1C. The designing of this dielectric film would have an immerse effect on the later device processing and operation.

[0037] In an alternative approach, III-nitride template layer 11 on the substrate first designed as rectangular stripes or triangular circular patches and then embed them with above said dielectric mask while partially exposing top and sidewalls. The exposed III-nitride regions in Fig. 1F or the underlying growth assisting III-nitride regions in Fig. 1B formulates ELO base layers as indicated in Fig. 1A or 1E.

[0038] As shown in the schematics of Figs. 2A - 2D, epitaxial III-nitride layers 14, such as GaN-based layers, are grown by ELO on the GaN based substrate and the dielectric mask 13. The growth of the ELO III-nitride layers 14 occurs first in the opening areas on the GaN-based substrate, and then laterally from the opening areas over the dielectric mask 13. The growth of the ELO III-nitride layers is stopped or interrupted before the ELO III-nitride layers from adjacent opening areas 12 can coalesce on top of the dielectric mask 13.

[0039] Alternatively, the growth of the ELO III-nitride layers may be continued and coalesce with neighboring ELO III-nitride layers. A wing 15 of the ELO III-nitride layers is an area of reduced defect density on either side of the opening areas. In the ELO growth method, wherein a fill factor, the ratio between open area and dielectric mask, is significantly deviates from unity resulting III-nitride atoms may accumulate more at the edge of the III-nitride layer compared to the central portion of the layer as shown in Fig. 2C. Which can be seen as edge growth may serve as a disadvantage when continued for the growth of device layers. In Fig. 2D, the III-nitride ELO base layer thus deposited is polished to obtain a planer surface. As these layers surface is achieved using epitaxial growth a little chemical mechanical polishing, or dry or wet etching should be enough to obtain planarized layers.

[0040] Section 2: Nanoporus and non- DBR layers growth as ELO base Nano and non-porous layers combination as a DBR mirror on the n-side of the VCSEL is proven to be promising solutions for the GaN based VCSELs, as they can provide better thermal stability compared to dielectric DBRs and their lattice match ability to GaN is a desirable condition for growth and fabrication, additionally nano & non porous GaN DBRs provide high refractive index contrast. For example, nano porous DBR layer, where porosity ranged between 10% to 75% can provides a refractive index contrast of 0.1 to 0.9, whereas dielectric DBR contrast stays about 0.7 and epitaxial DBR contrast stays below 0.2.

[0041] Additionally, when nano- and non- porous layers arranged in a plane parallel to active region provides a thermal conductivity between 10 to 1 W / (m.K) for the mentioned porosities. It is straightforward that with increasing porosity thermal conductivity decreases as these layers are in parallel arrangement configuration with the device active region plane. Similarly, electrical conductivity scales down as 1000 (S / m) to 100 S / m due to increased electrical resistance with increases porosity. However, when the nano- and non-porous layers were arranged in a slanted fashion, such that thermal and electrical conductivities depend mainly on the bulk-interface of the non-porous layer, thermal conductivity and electrical conductivities can be largely improved, there by the VCSEL operation, yield and lifetimes. The formation of nano porous III-nitride layer was extensively studied, and the mechanism of etching was well understood [NPL 7]. At a given applied bias, the size and shape of pores is controlled via n-type doping and crystal orientation of the exposed layers to the oxalic acid solution in electrochemical etching (EC). As the etching proceeds, first applied negative bias creates a hole inversion layer at the electrolyte / n-GaN interface, second the n-GaN surface is oxidized due to the presence of holes at the inverted surface, third oxidized GaN dissolves into Ga3+and nitrogen gas and finally it migrates freely into the electrolyte leaving behind a void, called nanoporous. In the present invention the formation of porosity will be performed in the later processing of the VCSEL device, however firstly during the ELO base layers growth the alternative arrangement of nano- and non- porous layer were carefully grown with different growth mechanisms.

[0042] Fig. 3A shows GaN crystal structure with all the possible planes to simplify growth picture. The planes perpendicular to c-plane such as (10-10) (m-plane) and (11-20) (a-plane) planes, are non-polar planes and crystal planes oriented between c-plane and non-polar planes such as (20-21) (r-plane) are semipolar planes.

[0043] A base seed 30 having a r-plane and c-plane, illustrated in Fig. 3B, is formed at the initial stage of the ELO growth from the open area 12 of the dielectric mask 13. Alternatively, the III-nitride template 11 on the substrate 10 is etched in a manner such that to expose r-plane and c-plane.

[0044] After forming a base seed 30, the growth supply parameters NH3-source, Ga-source are optimized in a way that r-plane and c-plane crystal orientations grew at a better rate in time and suppressing unwanted crystal plane orientations growth. Adding time passes and dopants like Silicon-Si during only at certain time periods one could form interfaces between doped and non-doped layers of these crystal orientations.

[0045] The doped crystal orientations are then transformed into porous III-nitride layers to form a DBR mirror. As can be seen the crystal plane orientation control can be performed several ways. Fig. 3C shows c-plane and r-plane growth equally resulting a bulky III-nitride ELO base layer. In other aspect, Fig. 3D, results an impure c-plane crystal growth while maintaining large wings growth by keeping r-plane growth laterally. The crystal-plane growth of c-plane can be suppressed by supplying low amount of nitrogen source, thus leads to low V / III ratios growth regime.

[0046] Like the edge growth mentioned in the earlier section, Fig. 3E, could see a non-uniform ELO base layer, where coloring or impurity c-plane crystal orientation might be due to absorbing impurities like carbon.

[0047] Fig. 3G is an illustration for a different base seed 30, where r-plane is a complimentary plane to Fig. 3B. The growth parameters controlled such a way that r-plane can laterally enhance on dielectric mask to form better ELO wing. The c-plane crystal orientation growth can be controlled, and impurities treated. The optimized ELO base layers condition is critical.

[0048] Fig. 3B - 3K depicts the ordinary and modulated ELO growth methods. The vast difference lies in the V / III ratio, i.e by varying NH3 flow rate while keeping TMGa flow rate identical or keeping V / III as low as possible to enhance one of the r-plane growth while equally suppressing c-plane growth. High and low V / III ratios can adjust growth anisotropy and enhance lateral growth. And of course, planarization is a final tool for the surface preparation before placing VCSEL device layers on top of ELO base.

[0049] Fig. 3F and 3K shows illustrations of planarized base. R-plane semiconductor crystal plane orientated nan- porous and nano- porous III-nitride layers in the periodic super lattice have unintentionally doping (UID) GaN and n+-GaN ([Si]~1019 / cm3).

[0050] Fig. 4A and 4B shows illustrations of r-planes on the ELO wings of ELO bars and Hexagonal Close-Packed (HCP) structures respectively after planarization. Then device layers include the III-nitride n-GaN layer 17, the III nitride active layers 18, III-nitride p-type electron blocking layer (EBL) 19, the p-type III nitride layer 20 and the p++ GaN layer 21 as shown in Fig.5A. The VCSEL design of this invention can utilize several current injection methods to inject current. One can simply stop the growth at p++GaN layer 21 or use ITO as current spreading layer, or grow a n++GaN layer over p++ GaN layer 21 after some surface treatment to utilize tunnel junction.

[0051] Even though this invention utilize intra cavity layers for the current injection but the emitted light from the active region will be directed away from the intra-cavity contact layer. For this reason, as an option one may or may not include intra-cavity contact layer.

[0052] Section 3: VCSEL fabrication procedure After the growth of device layers including the ELO base with a super lattice of NP DBR 16, a current injection is prepared. Current injecting aperture 31 is formally defined during burying process of tunnel junction when tunnel junction is used, otherwise current injection area 31 is separated from the optical cavity area 32 by defining a separate pattern preferably circular on ELO wing via photo lithography. After then a protection layer is placed covering injection area 31 and optical cavity region 32. Then a slightly large mesa is prepared on a region excluding injection area 31 and an optical cavity region 32 to place a contact pad. Angle etching is performed on the p-type layer of the VCSEL’s optical cavity region 32 to meet the alignment requirement of bottom nanoporous DBR mirror deflection. The angle of the etching predetermined such that light deflected from the bottom nanoporous GaN DBR 16 falls normally on the etched p-layer. As the etched region expose r-plane surface, a chemical etchant is used to smoothen surface before placing dielectric DBR mirror 24, a 16-period dielectric DBR 24 made of periods of SiO2 / Ta2O5was deposited on this prepared surface.

[0053] Next, SiO2or a protective film was deposited (not shown) to protect devices from nanoporous etch and provide electrical isolation 24. Next, EC etching was performed on the samples by immersing them in oxalic acid against a bias voltage to etch doped n+ GaN layers in the bottom ELO base layer into DBRs. Then, p-contact pad 33 connecting current injection region 31 is selectively patterned using photolithography and then metal contact Ti / Au was deposited. Resulting device is show in in Fig. 5A.

[0054] Next the VCSEL device is separated from the host substrate either by peeling or by laser or chemical lift off methods, and blanket deposit n-contact metal 34 resulting picture shown in Fig.5B. Either the nanoporous GaN DBR region can be made light emission side or the angled p-type layer side. In this invention, the interface between the n-contact pad 34 and the n-DBR 16 is prepared using ELO growth, thus it is crystally pure and the interface surface roughness is engineered to sub-nanometer value (e.g. 2 nm) without introducing CMP or any polishing techniques. The dielectric mask 13 used is ~300 nm thick and preferably a multilayer combination between SiO2and SiN. The surface roughness of the dielectric mask 13 is designed to be below sub-nanometer so that same can be replicated on the lift off interface. As can be seen in the picture, n-side DBR mirror 16 appears flat with bulk non-porous III-nitride layer and nano-porous GaN layer forming an interface with n-contact pad 34. Thus, indicating thermal draining of the device mainly controlled by the better thermal conductivity bulk non- porous GaN layer. Similarly, electrical conductivity resistance is mainly dominated by the bulk-non-porus GaN layers and thus, the reported configuration allows vertical current injection.

[0055] In Fig. 5C describes a tunnel junction configuration for the current injection region 31. Device layers growth is continued till p++GaN and then circular patch 35 is defined to define current aperture. If necessary, ion implantation is added to enhance current injection to the active region 18. A sliced region of the device at the tunnel junction injection is show in Fig. 5C where a shadowed region 36 indicates the optical cavity regime which not directly overlaps with the current injection regime.

[0056] In Fig. 5D focusses on adding a thermal conducting layer to above discussed tunnel junction device Fig. 5C. After preparing angled p-GaN 24 for the DBR mirror placement and preparing current injection regime 31 and contact pad placement region, AlN heat spreading layer 37 is sputtered. Then as discussed earlier, p-contact pad 33 and dielectric DBR mirror 24, a 16-period dielectric DBR made of periods of SiO2 / Ta2O5is deposited on topside of the device. Next the VCSEL device is separated from the host substrate either by thermal peeling or by laser or chemical lift off methods, and blanket deposit n-contact metal 34 resulting picture shown in Fig.5D.

[0057] Fig. 6A - 6D simple variations of devices mentioned in Fig. 5A and 5B, where at least more than one ELO wing is used for the placement of current injection region. In the case of ELO bar two light emissions can be achieved by placing two current injection regions on either side of the open area 12, similarly, in the case of hexagonal crystal pattern six light emissions 38 seen in Fig. 6C or continuous ring-like light emission, as in Fig. 6D are possible. As seen in Fig. 6C base ELO layer is a n-type DBR mirror but redirects light towards the open region. Similarly in Fig. 6D, current injection can be placed like a ring, then the emission look like a ring but moved slightly inward to open region. p-contact pads 33 were placed on the outer circle as indicated and n-contact pads 34 were placed on the n-side after removing VCSEL devices from the host substrate.

[0058] Fig. 7A describes typical chip dimensions from a single ELO bar and Fig. 7B shows integrated several VCSEL devices together from ELO bars and hexagonal closed packed VCSEL units from a wafer.

[0059] Advantages: 1. Intra-cavity contact layer not overlaps with the optical cavity. 2. Nanoporius DBR layers used for better heatsinking. 3. Nanoporous DBR’s slanted configuration reduces electrical resistance of the device. 4. Angles emission possible. 5. Better thermal management. 6. Less costly large template substrates such as GaN on Sapphire can be used to get benefit. 7. GaN substrates with high-quality and larger size are very expensive. The present ELO technique can unlock the usage of foreign substrates in the production of VCSELs. 8. This invention is expected to provide a significant improvement in the performance and reduction in the manufacturing cost and eliminating complex procedures.

[0060] Applications Lighting: GaN based LEDs have led to dramatic shift in residential and automotive lighting. Lighting in combination with communication services are very desirable in the future smart city and smart infrastructures. VCSELs are better alternatives to LEDs and edge emitting laser diodes. However, not having a proper profitable mass production techniques stopping GaN VCSELs entering market. The procedures developed in the above embodiments can be used to mass produce VCSEL units that applicable in lighting applications. Visible light communication:

[0061] Laser light for potential data transfer and communication applications through light fidelity (LiFi). With the rapid increase of IoT devices the demand on data transmission continues to expand. The RF spectrum is getting saturated and new frequencies are needed to keep up with the continuously growing demand. A GaN VCSEL adoption into existing LED architecture is simpler than replacing with an edge emitting laser. Therefore, the device described in the above embodiments could serve the purpose. Near eye displays:

[0062] Near eye displays represent the next major wave of consumer electronics. They are the basis of virtual reality (VR) and augmented reality (AR) technology. Currently, micro-LEDs are predominant choice for displays, however despite the limited progress in VCSEL research, VCSELs must be introduced as miniature display and near eye display. Relatively low optical power is beneficial in maintaining eye safety. Low divergence and circular symmetry reduce additional optical elements thus leads to compactness. The 2D array integration capability of VCSELs is simpler than edge emitting lasers. Therefore, the VCSEL product made using invention can be applied in these applications.

[0063] Having described and illustrated the principle of the invention in a preferred embodiment thereof, it is appreciated by those having skill in the art that the invention can be modified in arrangement and detail without departing from such principles. We therefore claim all modifications and variations coming within the spirit and scope of the following claims.

[0064] 10 III-nitride-based substrate 11 III-nitride template 12 open area stripe 13 dielectric mask 14 III-nitride layers 15 wing 16 nanoporous GaN DBR 17 n-GaN layer 18 III nitride active layers 19 III-nitride p-type electron blocking layer (EBL) 20 p-type III nitride layer 21 p++GaN layer 23 isolation layer 24 dielectric DBR 30 base seed 31 current injection area 32 optical cavity region 33 p-contact pad 34 n-contact pad 35 circular patch 36 shadowed region 37 heat spreading layer 38 light emissions

Claims

1. An extended vertical cavity surface emitting laser (VCSEL), comprising: an epitaxially laterally overgrown semiconductor section, configured by a III-nitride active region between a hole injecting III-nitride layer and an electron injecting III-nitride layer; an angled p-type mirror on a hole injecting side; and a flat mirror comprising a nanoporous layer on an electron injecting side and a nonporous layers on an n-side, which are angled relative to the III-nitride active region.

2. The VCSEL according to claim 1, wherein the flat mirror on the electron injecting side comprises a nanoporous III-nitride based DBR.

3. The VCSEL according to claim 2, wherein the III-nitride based DBR has an interface containing alternating nanoporous and non-porous regions.

4. The VCSEL according to claim 2, wherein the III-nitride based DBR is used for vertical current injection of electrons.

5. The VCSEL according to claim 2, wherein the III-nitride based DBR is used for thermal draining.

6. The VCSEL according to claim 2, wherein the interface of the III-nitride based DBR contacts an n-contact pad.

7. The VCSEL according to claim 2, wherein the III-nitride based DBR is formed via epitaxial lateral overgrowth.

8. The VCSEL according to claim 2, wherein an interface between the III-nitride based DBR and a dielectric mask has a roughness of sub-nanometer dimensions.

9. The VCSEL according to claim 8, wherein no chemical mechanical polishing (CMP), etching or grinding is used to smoothen a surface of the III-nitride based DBR.

10. The VCSEL according to claim 1, wherein the angled mirror on p-type layer is a dielectric mirror.

11. The VCSEL according to claim 10, wherein the angled p-type layer is a semipolar plane of a III-nitride layer.

12. The VCSEL according to claim 11, wherein angled etching is used to obtain the semipolar p-type layer.

13. The VCSEL according to claim 12, wherein chemical treatment is used to prepare a smooth surface for the angled p-type layer, which is semipolar.

14. The VCSEL according to claim 1, wherein a current injection region is separate from an optical cavity region.

15. The VCSEL according to claim 14, wherein the current injection region comprises a tunnel junction.

16. The VCSEL according to claim 1, wherein a heat spreader is disposed on the p-side of the VCSEL.

17. The VCSEL according to claim 2, wherein the III-nitride based DBR directs light towards the angled p-type layer side mirror.

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