Manufacturing process for microelectronic components

Abstract

Method for manufacturing microelectronic components. The invention relates to a method for producing a plurality of transistors on a substrate comprising at least two adjacent active zones (20) separated by at least one electrical insulation zone (30), each transistor of the plurality of transistors comprising a gate (10) having a silicided portion (12), and first and second spacers (11a, 11b) on either side of the gate (10), the first spacers (11a) being located on flanks of the gate (10a) and the second spacers (11b) being located on flanks of the first spacers (11a), the method comprising the following steps: forming the gates of the transistors, forming the first spacers (11a), forming the second spacers (11b), siliciding the gates configured to form the silicided portions (12) of the gates, removing the second spacers (11b),the method being characterized in that the removal (SPT) of the second spacers is done during the siliciding of the grids and before the silicided portions (12) are completely formed. Figure for the abstract: Fig. 10B,

Description

Title of the invention: Method for manufacturing microelectronic components Technical field

[0001] The present invention relates to the field of manufacturing microelectronic components. It will find advantageous but non-limiting application in the manufacture of CMOS transistors (Complementary Metal Oxide Semiconductor type transistors). STATE OF THE ART

[0002] A conventional layout diagram of transistors in a CMOS circuit is illustrated in [Fig.lA]. The gates 10 of the transistors typically extend transversely over several active areas 20. To electrically separate the different active areas 10, for example p-type and n-type, shallow isolation trenches STI 30 (shallow trench isolation) are generally formed.

[0003] To increase the overall performance of a CMOS circuit, the integration of the transistors is done according to an increasingly dense implantation scheme. The distance d between two adjacent gates 10 is thus reduced to a minimum. To individually increase the performance of the transistors, compression or tension layers also called "stress liner" (for example CESL for "Contact Etch Stop Liner" or DSL for "Dual Stress Liner") can be deposited on the gates 10 of the transistors.

[0004] Figures 2A and 2B are respectively a diagram and a transmission electron microscopy (TEM) image of two adjacent gates 10, seen in section along an xz plane. The section plane is of the BB type as illustrated in [Fig.lA] and passes through the isolation trench 30. In these figures 2A, 2B, the transistor gates 10 comprise silicided portions 12, and are flanked by first spacers 11a and second spacers 11b. A “stress liner” layer 40 covers the gates 10 and the spacers 11a, 11b in a more or less conformal manner. Ideally, a filling layer 50 made of a dielectric material, called ILD (acronym for Inter Layer Dielectric), covers the “stress liner” 40 and fills the spaces between the flanks of two adjacent gates 10.

[0005] When the distance d between two grids is small and / or the thickness of the “stress liner” 40 is large, the height / width form factor of the spaces to be filled increases. The spaces become difficult to fill completely. This leads to the formation of “closed” cavities 31, or residual voids, or “voids” according to the commonly used English terminology, as illustrated in FIGS. 2A, 2B.

[0006] These voids 31 extend along the gates 10, from one active area 20 to the other, as schematically illustrated in [Fig.3A], and imaged in [Fig.3B]. They can have harmful consequences for the CMOS circuits. During the subsequent formation of the electrical contacts at the silicided portions, and in particular when a problem of alignment of these electrical contacts occurs, the voids can be opened and filled with metal.

[0007] Two adjacent active zones 20 normally electrically isolated from each other by the STI 30 are then short-circuited by an electrical connection via these metallized voids 31. Figures 4A, 4B schematically illustrate two short-circuit situations between different types of contacts 21, 13, 14.

[0008] [Fig.4A] represents a point contact of grid 13 misaligned along x in the direction of void 31. The metal of this contact 13 can directly or indirectly fill a part of void 31 and form a short circuit 313 with contact 21.

[0009] [Fig.4B] shows an elongated grid contact 14 straddling two adjacent grids 10. The metal of this contact 14 can directly or indirectly fill a part of the void 31 and form a short circuit 314 with the contact 21.

[0010] Figures 5A and 6A are respectively top and sectional views acquired by electron microscopy of the situation illustrated in [Fig.4A]. Figures 5B and 6B are respectively top and sectional views acquired by electron microscopy of the situation illustrated in [Fig.4B].

[0011] In view of these drawbacks, it is currently necessary to preserve a large space between two adjacent gates. One solution consists of introducing a step of etching the spacers 11b mentioned above. This makes it possible to increase the width of the spaces between the gates. This solution nevertheless causes other drawbacks, in particular by affecting the other portions of the transistors, in particular the silicon-cided portion, the semiconductor material of the active zones or the STIs.

[0012] Figures 7A to 7F illustrate the conventional steps of removing the spacers 11b, after siliciding the gates. The siliciding of the gates makes it possible to form the silicidated portions 12, i.e. based on Nickel NiSi silicide, on which the contacts 21, 13, 14 are subsequently formed ([Fig.7A]). The spacers 11b were previously formed at the level of the STIs 30 ([Fig.7B]). During the formation of the spacers 11b, the STIs 30 may be partially damaged, as illustrated in [Fig.7B]. This may lead to the formation of “open” cavities 31, i.e. which communicate with the surrounding environment. These open cavities 31 evolve during the subsequent stages of transistor manufacturing and can also contribute to the appearance of the closed voids 31 seen previously, that is to say in the form of an empty volume within a solid material.

[0013] The removal of the spacers 11b is typically done by isotropic etching ([Fig.7D]). The cavities 31 are enlarged. Undesirable metal residues 120 are redeposited at the end of this step, as illustrated in FIGS. 7C, 7D. A cleaning step, for example wet cleaning with a nitric acid-based solution, must then be carried out to remove these metal residues 120 (FIGS. 7E, 7F). This can further damage the STIs 30. This can further consume or damage some of the silicided portions.

[0014] There is therefore a need to improve current microelectronic component manufacturing techniques.

[0015] The present invention relates in particular to a method for producing transistors which at least partially overcomes the drawbacks mentioned above.

[0016] In particular, an object of the present invention is to provide a method of manufacturing transistors comprising removing the second spacers and limiting or eliminating the formation of residual voids.

[0017] Other objects, features and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other advantages may be incorporated. SUMMARY

[0018] One aspect of the invention relates to a method for producing a plurality of transistors on a substrate comprising at least two adjacent active zones separated by at least one electrical insulation zone, each transistor of the plurality of transistors comprising a gate having a silicided portion, and first spacers on either side of the gate, the first spacers being located on sides of the gate.

[0019] This method comprises the following steps: - formation of transistor grids, - training of the first spacers, - a formation of second spacers on flanks of the first spacers, - a siliciding of the gates configured to form the silicided portions of the gates, - removal of the second spacers.

[0020] Advantageously, the removal of the second spacers is done during the siliciding of the gates and before the silicidated portions are completely formed.

[0021] Thus, this removal does not affect the fully formed silicided portions. This avoids or limits the deposition of undesirable metal residues. This advantageously makes it possible to avoid the step of cleaning the metal residues.

[0022] The siliciding of the gate is typically carried out by a series of steps grouped under the name “NiSi module”. This NiSi module may in particular comprise the following sub-steps: - At least one preparatory cleaning, - A deposit of a nickel-platinum alloy NiPt, particularly at the tops of the grids, - A first thermal annealing in order to diffuse and react part of the Nickel Ni of said NiPt alloy at the level of the upper portions of the grids, - An intermediate shrinkage of the nickel-platinum alloy NiPt enriched with Platinum Pt at the end of the first thermal annealing, - A second thermal annealing, - Removal of a residual part of NiPt alloy, so as to form and / or expose the silicided portions, i.e. based on Nickel NiSi silicide.

[0023] The total or partial removal of the second spacers is done in this case before the removal of the residual part of NiPt alloy, preferably before the second thermal annealing, preferably before the deposition of the nickel-platinum NiPt alloy, and preferably before the at least one preparatory cleaning.

[0024] The invention also relates to transistors obtained by the described aspects of the method of the invention. BRIEF DESCRIPTION OF THE FIGURES

[0025] Aims, objects, as well as the characteristics and advantages of the invention will become more apparent from the detailed description of one embodiment thereof which is illustrated by the following accompanying drawings in which:

[0026] [Fig.lA] [Fig.lA] schematically illustrates, in top view, a substrate comprising active zones and adjacent electrical insulation zones, on which transistor gates are arranged.

[0027] [Fig.2A] [Fig.2A] schematically illustrates, in section, two adjacent transistors and a residual void between these transistors.

[0028] [Fig.2B] [Fig.2B] is an electron microscopy image showing, in cross-section, two adjacent transistors and a residual void between these transistors, as illustrated in [Fig.2A].

[0029] [Fig.3A] [Fig.3A] schematically illustrates, in top view, two adjacent transistors and a residual void between these transistors.

[0030] [Fig.3B] [Fig.3B] is an electron microscopy image showing, in top view, two adjacent transistors and a residual void between these transistors, as illustrated in [Fig.3A].

[0031] [Fig.4A] [Fig.4A] schematically illustrates, in top view, a first short-circuit situation via the residual vacuum illustrated in [Fig.3A].

[0032] [Fig.4B] [Fig.4B] schematically illustrates, in top view, a second short circuit situation via the residual vacuum shown in [Fig.3A].

[0033] [Fig.5A] [Fig.5A] is an electron microscopy image showing, in top view, a first short-circuit situation, as illustrated in [Fig.4A].

[0034] [Fig.5B] [Fig.5B] is an electron microscopy image showing, in top view, a second short-circuit situation, as illustrated in [Fig.4B].

[0035] [Fig.6A] [Fig.6A] is an electron microscopy image showing, in section, a first short-circuit situation, as illustrated in [Fig.4A].

[0036] [Fig.6B] [Fig.6B] is an electron microscopy image showing, in cross-section, a second short-circuit situation, as illustrated in [Fig.4B].

[0037] [Fig.7A] Figures 7A to 7F illustrate steps of removing the second spacers, according to the prior art.

[0038] [Fig.7B]

[0039] [Fig.7C]

[0040] [Fig.7D]

[0041] [Fig.7E]

[0042] [Fig.7F]

[0043] [Fig.8] [Fig.8] shows in the form of a flowchart the steps of siliciding and of removal of the second spacers, according to the prior art.

[0044] [Fig.9A] [Fig.9A] schematically illustrates in section a device comprising two adjacent grids before siliciding of the grids and removal of the second spacers.

[0045] [Fig.9B] [Fig.9B] illustrates in flowchart form the steps of siliciding and removing the second spacers, according to an embodiment of the present invention.

[0046] [Fig.9C] [Fig.9C] schematically illustrates in section a device comprising two adjacent grids after siliciding of the grids and removal of the second spacers, according to an embodiment of the present invention.

[0047] [Fig.10A] [Fig.10A] schematically illustrates in section a device comprising two adjacent grids before siliciding of the grids and removal of the second spacers.

[0048] [Fig.10B] [Fig.10B] illustrates in flowchart form the steps of siliciding and removing the second spacers, according to an embodiment of the present invention.

[0049] [Fig.10C] [Fig.10C] schematically illustrates in section a device comprising two adjacent grids after siliciding of the grids and removal of the second spacers, according to an embodiment of the present invention.

[0050] [Fig. 11 A] [Fig. 11 A] schematically illustrates in section a device comprising two adjacent grids before siliciding of the grids and removal of the second spacers.

[0051] [Fig. 1 IB] [Fig. 1 IB] illustrates in flowchart form the steps of siliciding and removing the second spacers, according to an embodiment of the present invention.

[0052] [Fig. 1 IC] [Fig. 1 IC] schematically illustrates in section a device comprising two adjacent gates after siliciding of the gates and removal of the second spacers, according to an embodiment of the present invention.

[0053] [Fig.l2A] [Fig.l2A] schematically illustrates in section a device comprising two adjacent grids before siliciding of the grids and removal of the second spacers.

[0054] [Fig.l2B] [Fig.l2B] illustrates in flowchart form the steps of siliciding and removing the second spacers, according to an embodiment of the present invention.

[0055] [Fig.l2C] [Fig.l2C] schematically illustrates in section a device comprising two adjacent gates after siliciding of the gates and removal of the second spacers, according to an embodiment of the present invention.

[0056] The drawings are given as examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily on the scale of practical applications. In particular, the relative thicknesses of the different layers and portions are not representative of reality. DETAILED DESCRIPTION

[0057] Before beginning a detailed review of embodiments of the invention, it is recalled that the invention according to its first aspect notably comprises the following optional characteristics which can be used in association or alternatively.

[0058] According to one example, the siliciding of the grids comprises the following sub-steps: - A deposition of a nickel-platinum alloy NiPt at the tops of the grids, - A first thermal annealing in order to diffuse and react part of the Nickel Ni of said NiPt alloy at the upper portions of the grids, - Removal of a residual portion of NiPt alloy so as to form the silicided portions.

[0059] According to one example, the removal of the second spacers is done before the removal of the residual part. Thus, the metal residues generated during the removal of the second spacers are eliminated during the removal of the residual part. This makes it possible to avoid a subsequent step of cleaning the metal residues. This saves a process step.

[0060] According to one example, the removal of the second spacers is done before the deposition of the nickel-platinum alloy NiPt at the tops of the grids. Thus, the metal residues generated during the removal of the second spacers are eliminated during the removal of the residual part. This makes it possible to avoid a subsequent step of cleaning the metal residues. This makes it possible to save a process step.

[0061] According to one example, the method further comprises, before the deposition of the alloy of nickel-platinum NiPt at the tops of the grids, the following sub-steps: - A preparatory thermal annealing, - At least one preparatory cleaning.

[0062] According to one example, the removal of the second spacers is carried out before the at least one preparatory cleaning. This makes it possible to avoid generating metal residues. This makes it possible to avoid a subsequent cleaning step for the metal residues. The at least one preparatory cleaning also makes it possible to remove the organic residues generated by the removal of the second spacers. If the removal of the second spacers is carried out by isotropic wet etching based on a dilute hydrofluoric acid (dHF) solution, the at least one preparatory cleaning is not necessary and can be omitted. This makes it possible to save at least one second process step.

[0063] According to one example, the removal of the second spacers is done after the at least one preparatory cleaning and before the deposition of the nickel-platinum alloy NiPt at the tops of the gates. This makes it possible to avoid generating metal residues. This makes it possible to avoid a subsequent metal residue cleaning step. If the removal of the second spacers is carried out by isotropic plasma etching from a delocalized plasma followed by sublimation annealing, the deposition of the nickel-platinum alloy NiPt can be done directly without requiring a conventional surface deoxidation step preparatory to the deposition. This makes it possible to save a second process step.

[0064] According to one example, the removal of the second spacers is done immediately before the removal of the residual part.

[0065] According to one example, the method further comprises, after the first thermal annealing, an intermediate removal of the nickel-platinum alloy NiPt enriched in Platinum Pt at the end of the first thermal annealing, followed by a second thermal annealing. The intermediate removal step essentially serves to remove an excess of metal, in particular the metal which has not reacted at the tops of the grids - the intermediate NiPt alloy - and / or on the STIs and / or on the spacers. At the end of the intermediate removal, a Ni-rich phase is retained at the top of the grids. The second thermal annealing makes it possible to continue the diffusion of nickel from the top of the grids so as to obtain the silicidated portions based on NiSi.

[0066] According to one example, the removal of the second spacers is carried out after said intermediate removal, and preferably immediately after and before the second thermal annealing. The Ni-rich phase is more robust than the underlying NiSi portion (partly silicidated) with respect to the removal of the second spacers. The part-silicided portion is therefore not damaged. The generation of metal residues is therefore limited. The metal residues are furthermore removed during the removal of the platinum. This makes it possible to avoid a subsequent cleaning step of the metal residues. This makes it possible to save a process step.

[0067] According to one example, the removal of the second spacers is done by isotropic plasma etching.

[0068] According to one example, the isotropic plasma etching is based on fluorocarbon species. This makes it possible to quickly etch nitride-based spacers while exhibiting good selectivity with respect to the silicon oxide of the STI isolation trenches.

[0069] According to one example, isotropic plasma etching is performed using a delocalized plasma followed by sublimation annealing. Such etching may be a SiCoNi® type process.

[0070] According to one example, the removal of the second spacers is done by isotropic wet etching.

[0071] According to one example, isotropic wet etching is based on a solution of dilute hydrofluoric acid (dHF) and hot phosphoric acid. This allows nitride-based spacers to be etched quickly while exhibiting good selectivity with respect to the silicon oxide of the STI isolation trenches.

[0072] According to one example, the isotropic wet etching is based on a dilute hydrofluoric acid (dHF) solution.

[0073] It is specified that in the context of the present invention, the term "on", "overcomes", "covers" or "underlying" or their equivalents do not necessarily mean "in contact with". Thus, for example, the deposition of a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but it does mean that the first layer at least partially covers the second layer by being either directly in contact with it or by being separated from it by at least one other layer or at least one other element.

[0074] A layer may also be composed of several sub-layers of the same material or of different materials.

[0075] A substrate, a layer, a device, “based” on a material M, is understood to mean a substrate, a layer, a device comprising this material M only or this material M and possibly other materials, for example alloying elements, impurities or doping elements. Thus, a spacer based on silicon nitride SiN may for example comprise non-stoichiometric silicon nitride (SiN), or stoichiometric silicon nitride (Si3N4), or even a silicon oxynitride (SiON).

[0076] In general, but not limited to, a spacer forms a ring around the grid, with a closed contour; one could therefore speak of a single spacer around the grid; however, the cross-sectional representations, and the preferred directions of the grids, mean that one also speaks of pairs of spacers. This latter terminology is adopted in this application, where in this case a pair of first spacers and a pair of second spacers are distinguished.

[0077] The present invention allows in particular the fabrication of at least one transistor or a plurality of transistors on a substrate. This substrate can be solid or "bulk" according to the English terminology, or of the semiconductor on insulator type, for example a silicon on insulator SOI substrate (acronym for "Silicon on insulator") or a germanium on insulator GeOI substrate (acronym for "germanium on insulator").

[0078] The invention can also be implemented more broadly for different microelectronic devices or components.

[0079] By component, device or element of a microelectronic device is meant any type of element produced using microelectronic means. These devices include, in particular, in addition to devices for purely electronic purposes, micromechanical or electromechanical devices (MEMS, NEMS, etc.) as well as optical or optoelectronic devices (MOEMS, etc.).

[0080] Several embodiments of the invention implementing successive steps of the manufacturing method are described below. Unless explicitly stated, the adjective “successive” does not necessarily imply, even if this is generally preferred, that the steps follow one another immediately, intermediate steps being able to separate them. Furthermore, the term “step” means the carrying out of a part of the method, and can designate a set of sub-steps.

[0081] Siliciding typically comprises a set of steps for forming NiSi-based parts or portions of the device. This set of steps, grouped under the name “NiSi module”, is illustrated in [Fig.8].

[0082] One objective of siliciding is to diffuse, then react, a metal, generally nickel, within portions of semiconductor, generally based on Si, from a source of metal, generally a NiPt alloy deposited on the surface of said portions of semiconductor. As illustrated in [Fig.8], siliciding can thus comprise one or more steps of “preparation for deposition” allowing cleaning of the surfaces, a step of “NiPt deposition”, a first “thermal annealing 1” allowing initiation of nickel diffusion, a possible intermediate step of “partial removal of NiPt” allowing removal of excess metal, a possible second “thermal annealing 2” allowing continuation or finalization of nickel diffusion, a “removal of residual part of NiPt alloy” finalizing siliciding.

[0083] The siliciding is carried out at least at the level of the upper portions of the gates of the transistors. It is generally also carried out on upper portions of sources and drains, for example raised, on either side of the transistor.

[0084] The upper portions can be progressively enriched in Ni during the siliciding to become the “silicided” portions. The silicided portions are actually silicided, i.e. fully formed, at the end of the siliciding. The upper and / or silicided portions do not necessarily have a constant concentration of nickel over their entire height. For the sake of brevity and depending on the case, the upper portions may also designate the portions “undergoing siliciding” or “intended to be silicided”. The purpose of these upper portions is perfectly clear to those skilled in the art, depending on the siliciding step with which they are associated.

[0085] Siliciding can be carried out in several stages starting from a NiPt deposit. The initially deposited NiPt alloy evolves during the siliciding stages. Typically, the nickel concentration of the initial NiPt alloy varies during the siliciding. For example, following a first thermal annealing during which the nickel diffuses, the initial NiPt alloy is enriched in Pt. The initial alloy then becomes an intermediate NiPt alloy, enriched in Pt, which can be removed by an intermediate removal. After a second thermal annealing aimed at finalizing the diffusion and reaction of the nickel within the upper portions, a residual portion of the NiPt alloy remains. This residual portion is removed at the end of the siliciding module. A distinction may be made between the initial NiPt alloy, the intermediate NiPt alloy, and the final or residual NiPt alloy, which have different nickel concentrations.The residual part is based on final NiPt alloy.

[0086] Nickel is a relatively mobile element that can diffuse rapidly depending on the thermal budget to which it is subjected. In particular, it can diffuse from metallic residues of NiPt or NiSi alloy at the base of the gates, and possibly pierce and short-circuit the junction between the source or drain, and the channel. Such a phenomenon is commonly called "NiSi piping". The metallic residues can come from a redeposition following an etching or cleaning step. These metallic residues are undesirable. It is preferable, or even necessary, to eliminate them to avoid a risk of "NiSi piping" (last step of the "classic SPT module" of a known standard process illustrated in [Fig.8]).

[0087] Another advantage of the method according to the invention is to limit or eliminate this phenomenon of “NiSi piping”. The different embodiments of the method according to the invention allow: - either to avoid metallic residues being generated when removing the second spacers (case where the removal of the second spacers is carried out before deposition of the NiPt alloy), - either to protect the portions undergoing siliciding by retaining a Ni-rich alloy on the surface of said portions (case where the removal of the second spacers is carried out before the second thermal annealing), - either to remove the metal residues at the same time as the siliciding of the upper portions is finalized (case where the removal of the second spacers is carried out before the removal of the platinum).

[0088] The method according to the invention also makes it possible to preserve the upper and / or silicided portions and to avoid their damage.

[0089] By NiPt deposition “at the tops of the gates” is meant a deposition of NiPt at least at the tops of the gates. This does not mean that the NiPt deposition is done only at the tops of the gates. Generally, the NiPt deposition is carried out on a full plate, i.e. non-selectively on all the structures present on the plate. The NiPt deposition is therefore also carried out, for example, on the sources and drains of the transistors. As an example in the context of the present invention, the siliciding subsequent to this NiPt deposition is mainly described for the gates, in particular at the tops of the gates, hence the expression.

[0090] The terms “grid pattern”, “grid stack”, “grid” are used synonymously.

[0091] In this patent application, we will preferably speak of thickness for a layer, height for a device (transistor or gate for example) and depth for a cavity or an etching. The thickness is taken in a direction normal to the main extension plane of the layer, the height and depth are taken in a direction normal to the base plane of the substrate.

[0092] Dry etching solutions, i.e. by plasma, based on fluorocarbon species suitable for removing second spacers are generally known to those skilled in the art. A CH3F / O2 plasma can typically make it possible to remove second spacers based on silicon nitride with a good etching speed and good selectivity with respect to silicon oxide.

[0093] Wet etching solutions suitable for removing the second spacers are known to those skilled in the art. Thus, a dilute hydrofluoric acid typically corresponds to a dilution of less than 30% by volume, preferably less than 20% by volume, and preferably between 1% and 5% by volume. A hot phosphoric acid typically has a temperature of between 100°C and 150°C.

[0094] The terms “substantially”, “approximately”, “of the order of” mean “to within 10%” or, when it comes to an angular orientation, “to within 10°”. Thus, a direction substantially normal to a plane means a direction having an angle of 90+10° relative to the plane.

[0095] The method of manufacturing transistors will now be described in detail through several embodiments.

[0096] In all embodiments of the manufacturing method according to the invention, the removal of the second spacers is done by isotropic etching, dry or wet. For second silicon nitride (SiN) based spacers, four etching solutions or chemistries, among others possible, hereinafter referred to as CHIM 1, CHIM 2, CHIM 3 and CHIM 4, can be used.

[0097] The CHIM 1 etching solution corresponds to an isotropic plasma etching based on fluorocarbon species, typically a CH3F / O2 mixture. Such a solution has both a good etching speed for SiN and good selectivity towards SiO2.

[0098] The CHIM 2 etching solution corresponds to an isotropic plasma etching from a delocalized plasma followed by a sublimation annealing, typically by a SiCoNi™ type process. The delocalized plasma can be based on an NF3 / NH3 mixture. The NF3 / NH3 concentration ratio can be chosen between 0.05 and 0.3, for example 0.07 or 0.12 or 0.2 or preferably 0.175 or 0.25. These last two concentration ratios present a good compromise between etching speed (in  / min) and selectivity with respect to SiO2 (SiN / SiO2), as illustrated in the following table: [Tables 1] NF3 / NH3 concentration ratio SiN etching rate (in  / min) SiO2 etching rate (in  / min) SiN / SiO2 selectivity 0.2 207 17 12.1 0.12 133 10 13.3 0.07 90 7 12.85 0.175 154 18 8.5 0.25 182 21 8.6

[0099] Other advantages of this CHIM 2 etching solution are described below.

[0100] The CHIM 3 etching solution corresponds to an isotropic wet etching based on a solution of dilute hydrofluoric acid (dHF) and hot phosphoric acid (H3PO4). Such a solution has both a good etching speed for SiN and good selectivity towards SiO2.

[0101] The CHIM 4 etching solution corresponds to an isotropic wet etching based on a dilute hydrofluoric acid (dHF) solution alone. Some advantages of this CHIM 4 etching solution are described below.

[0102] In all embodiments of the manufacturing method according to the invention, the removal of the second spacers is done during the NiSi module dedicated to siliciding, before the end of said NiSi module, which corresponds to the removal of the residual part. The first and second embodiments provide for the removal of the second spacers before the deposition of NiPt metal. This advantageously makes it possible to avoid any subsequent interaction with the NiPt metal. This in particular avoids partially pulverizing the metallized parts based on NiPt and / or NiSi. This prevents the subsequent formation of metal residues. The third and fourth embodiments provide for the removal of the second spacers before the removal of the residual part. This advantageously makes it possible to benefit from the step of removing the residual part to remove or clean the metal residues.

[0103] In all cases, a subsequent step of cleaning the metal residues is no longer necessary. This makes it possible to reduce the total number of steps in the manufacturing process. The elimination of the step of cleaning the metal residues, which is often aggressive towards silicon oxide, also makes it possible to preserve the STI isolation trenches. The silicon oxide consumption of the post-silicidation STIs is thus reduced. The height / width form factor of the spaces to be filled between two adjacent gates is reduced. This promotes subsequent filling of the spaces without the formation of voids.

[0104] The first embodiment is illustrated in Figures 9A to 9C. [Fig. 9A] illustrates in section two adjacent grids flanked by the first spacers 11a and the second spacers 11b, before siliciding the upper portions 121. [Fig. 9B] illustrates the positioning of the step of removing the second spacers 11b, also called SPT (English acronym for “Spacer Proximity Technology”), in the sequence of steps of the NiSi module. [Fig. 9C] illustrates in section two adjacent grids flanked by the first spacers 11a and comprising silicidated portions 12, as obtained at the end of the NiSi module modified by the SPT step.

[0105] According to this first embodiment, the removal of the second spacers 11b is carried out at the very beginning of the NiSi module, before the “preparation for deposition” step. Such a “preparation for deposition” step generally aims to remove the native oxide and / or the impurities, for example of organic or metallic type, at the top of the grids and / or the sources and drains. It may comprise at least one preparatory cleaning. For example, a first preparatory wet cleaning may be carried out using a dilute hydrofluoric acid solution dHF. A second dry cleaning, for example by Ar or He plasma, may be carried out directly in the deposition machine just before the metal deposition. The preparatory cleaning may therefore comprise one or the other of the dry and wet cleanings, or both.

[0106] The SPT can be produced with the different etching chemistries CHIM 1, CHIM 2, CHIM 3 and CHIM 4. Preferably, the use of the etching chemistry CHIM4 (dHF) makes it possible to replace and eliminate the “preparation for deposition” step. This makes it possible to further reduce the total number of steps in the manufacturing process.

[0107] The second embodiment is illustrated in Figures 10A to 10C. [Fig. 10A] illustrates in section two adjacent grids flanked by the first spacers 11a and the second spacers 11b, before siliciding of the upper portions 121. [Fig. 10B] illustrates the positioning of the SPT step in the sequence of steps of the NiSi module. [Fig.10] illustrates in section two adjacent grids flanked by the first spacers 11a and comprising silicided portions 12, as obtained at the end of the NiSi module modified by the SPT step.

[0108] According to this second embodiment, the removal of the second spacers 11b is carried out immediately after the “preparation for deposition” step, before the NiPt deposition step. The NiPt deposition may typically comprise, prior to the actual deposition, a preliminary soft etching aimed at removing any remaining contaminants and ensuring that there is no interfacial oxide before the deposition. This preliminary soft etching may be carried out using a SiCoNi™ type process.

[0109] The SPT can be produced with the different etching chemistries CHIM 1, CHIM 2, CHIM 3 and CHIM 4. Preferably, the use of the etching chemistry CHIM2 (SiCoNi®) makes it possible to replace and eliminate the soft etching step of the NiPt deposition. This makes it possible to further reduce the total number of steps in the manufacturing process.

[0110] The third embodiment is illustrated in Figures 11A to 11C. [Fig. 11A] illustrates in section two adjacent grids flanked by the first spacers 11a and the second spacers 11b, before siliciding of the upper portions 121. [Fig. 11B] illustrates the positioning of the SPT step in the sequence of steps of the NiSi module. [Fig. 11C] illustrates in section two adjacent grids flanked by the first spacers 11a and comprising silicidated portions 12, as obtained at the end of the NiSi module modified by the SPT step.

[0111] According to this third embodiment, the removal of the second spacers 11b is carried out before the “thermal annealing 2” step, preferably immediately after the “partial removal of the NiPt” step. The thermal annealing 2 may be a rapid thermal annealing known by the acronym RTA (Rapid Thermal Annealing) or a laser annealing. The thermal annealing 2 makes it possible in particular to finalize the diffusion and the reaction of the nickel in the upper portions 121, so as to obtain the silicided portions 12.

[0112] The SPT can be carried out with the different etching chemistries CHIM 1, CHIM 2, CHIM 3 and CHIM 4. The use of the wet etching chemistries CHIM3 (dHF + H3PO4) or CHIM4 (dHF) makes it possible to preserve the NiSi-based portions undergoing siliciding. These in fact have, before thermal annealing 2, a nickel-rich phase at the interface with the upper metal deposit. This Ni-rich phase is more resistant than the NiSi alloy with respect to said wet etching chemistries, and protects the underlying NiSi-based portions. The Ni-rich phase is in particular less sensitive to damage by so-called wet etching chemistries than the NiSi alloy, and can be more easily restored by thermal annealing 2. The use of the dry etching chemistries CHIM 1 (CH3F / O2) or CHIM2 (SiCoNi™) is preferably combined with thermal annealing 2 by laser annealing. This avoids the phenomenon of “NiSi piping”.

[0113] The fourth embodiment is illustrated in Figures 12A to 12C. [Fig. 12A] illustrates in section two adjacent grids flanked by the first spacers 11a and the second spacers 11b, before siliciding of the upper portions 121. [Fig. 12B] illustrates the positioning of the SPT step in the sequence of steps of the NiSi module. [Fig. 12C] illustrates in section two adjacent grids flanked by the first spacers 11a and comprising silicidated portions 12, as obtained at the end of the NiSi module modified by the SPT step.

[0114] According to this fourth embodiment, the removal of the second spacers 11b is carried out before the “Pt removal” step, preferably immediately after the “thermal annealing 2” step. Thermal annealing 2 may be a rapid thermal annealing known by the acronym RTA (Rapid Thermal Annealing) or a laser annealing.

[0115] The SPT can be carried out with the different etching chemistries CHIM 1, CHIM 2, CHIM 3 and CHIM 4. The use of the wet etching chemistries CHIM3 (dHF + H3PO4) or CHIM4 (dHF) makes it possible to preserve the NiSi-based silicided portions. These are in fact protected by the upper Pt-rich metal deposit, before removal of the Pt. In the case of use of the dry etching chemistries CHIM 1 (CH3F / O2) or CHIM2 (SiCoNi™), an additional laser annealing at the end of the NiSi module can be carried out. This makes it possible to avoid the phenomenon of “NiSi piping”.

[0116] Generally, the invention is not limited to the embodiments described but extends to any embodiment falling within the scope of claim 1. The invention advantageously makes it possible to reduce the total number of steps in a transistor manufacturing process, while promoting filling of the spaces between adjacent gates by ILD without residual voids. The NiSi piping phenomenon is also reduced or even eliminated by the process according to the present invention.

Claims

Claims

1. Method for producing a plurality of transistors on a substrate comprising at least two adjacent active zones (20) separated by at least one electrical insulation zone (30), each transistor of the plurality of transistors comprising a gate (10) having a silicided portion (12), and first spacers (11a) on either side of the gate (10), the first spacers (11a) being located on sides of the gate (10a), the method comprising the following steps: - formation of the transistor gates, - formation of the first spacers (11a), - formation of second spacers (11b) on the sides of the first spacers (11a), - a siliciding of the grids configured to form the silicided portions (12) of the grids, said siliciding of the grids comprising the following sub-steps: i. A deposit of a nickel-platinum alloy NiPt at the tops of the grids, ii. A first thermal annealing so as to diffuse and react a part of the Nickel Ni of said NiPt alloy at the upper portions (121) of the grids, iii. A removal of a residual part of unreacted NiPt alloy, so as to form the silicided portions (12), - a withdrawal (SPT) of the second spacers (11b), the method being characterized in that the removal (SPT) of the second spacers is carried out by isotropic plasma etching during the siliciding of the grids and before the silicided portions (12) are completely formed, immediately before the removal of the residual part, said isotropic plasma etching being carried out from a delocalized plasma followed by sublimation annealing.

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