Optoelectronic device

Abstract

Optoelectronic device The present description relates to an optoelectronic device (11) comprising a first circuit (13) including at least one light-emitting diode (LED) emitting from a first face (13i) of the first circuit and including first and second electrodes (23, 24); a second control circuit (15) of the light-emitting diode, positioned on a second face (13s) of the first circuit opposite to the first face, including first and second electrically conductive pads (31);and an electrically conductive layer (17) located at the interface between the first and second circuits, the electrically conductive layer (17) being divided into first and second parts orthogonally to the stacking of the first and second circuits, the first electrode being electrically connected to the first conductive pad via the first part of the conductive layer and the second electrode being electrically connected to the second conductive pad via the second part of the conductive layer. Figure for the abstract: Fig. 1A;

Description

Title of the invention: Optoelectronic device technical field

[0001] This description relates generally to an optoelectronic device and its manufacturing process, for example a light-emitting diode image display device and its manufacturing process. Previous technique

[0002] It is known to produce an optoelectronic device comprising at least one light-emitting diode and a control circuit for this light-emitting diode.

[0003] US patent 10468452 describes a method for manufacturing such a device comprising the simultaneous fabrication of several copies of the optoelectronic device on the same substrate and the separation of the optoelectronic devices thus fabricated. One drawback of such a method is that it involves the formation of electrodes covering the sides of the optoelectronic devices, which can be a difficult step to perform. Summary of the invention

[0004] There is a need for improvement of optoelectronic devices and their manufacturing processes.

[0005] An embodiment overcomes all or part of the drawbacks of known optoelectronic devices and their manufacturing processes.

[0006] One embodiment provides an optoelectronic device comprising a stack: of a first circuit comprising at least one inorganic light-emitting diode emitting from a first face of the first circuit and comprising first and second electrodes; and of a second control circuit for the light-emitting diode, positioned on a second face of the first circuit opposite the first face, comprising first and second electrically conductive pads, in which an electrically conductive layer, comprising the superposition of a first electrically conductive sublayer of the first circuit and a second electrically conductive sublayer of the second circuit, is located at the interface between the first and second circuits, the electrically conductive layer being divided into first and second parts orthogonally to the stacking direction of the first and second circuits, the first electrode being electrically connected to the first conductive pad via the first part of the conductive layer and the second electrode being electrically connected to the second conductive pad via the second part of the conductive layer.

[0007] According to one embodiment, the device includes at least two connectors, located on the second circuit, on the opposite side to the first circuit, intended to electrically connect the device to an external object.

[0008] According to one embodiment, the first and second parts of the conductive layer are separated by an electrical insulation trench.

[0009] According to one embodiment, the first and second conductive pads are separated by said electrical insulation trench.

[0010] According to one embodiment, the second circuit comprises metal-oxide gate field-effect transistors and comprises two parts electrically separated by said electrical isolation trench.

[0011] According to one embodiment, the parts of the second circuit are electrically connected by connections through electrically conductive tracks located on the side of the metal-oxide gate field-effect transistors opposite to the first circuit.

[0012] According to one embodiment, the electrical insulation trench has a closed shape, in a plane parallel to the second face.

[0013] According to one embodiment, the electrical insulation trench has, in a plane parallel to the second face, an open shape whose two free ends open onto one or more sides of the device.

[0014] According to one embodiment, the first circuit includes a substrate on the side of the first face.

[0015] According to one embodiment, the substrate is made of sapphire or glass.

[0016] According to one embodiment, the conductive layer is made of metal or a polymer driver.

[0017] According to one embodiment, the light-emitting diode is wire-shaped or pyramid-shaped.

[0018] One embodiment provides a structure comprising a plurality of optoelectronic devices as described above.

[0019] An embodiment provides a method for manufacturing a plurality of optoelectronic devices as described above, comprising a step a) of assembling a first plate comprising said plurality of first circuits to a second plate comprising said plurality of second circuits.

[0020] According to one embodiment, step a) of assembly is carried out by bringing the first and second sub-layers of the electrically conductive layer into full plate contact.

[0021] According to one embodiment, each first circuit is partially etched in a step b) prior to step a) so as to define a first cavity located at the location of the second electrode.

[0022] According to one embodiment, each first circuit is partially etched in a step b') prior to step a) so as to create a second cavity allowing the edges of said light-emitting diode to be defined.

[0023] According to one embodiment, the process includes a step c), between steps a) and b) or b'), in which each light-emitting diode is covered, on the side of the second face of the first circuit, with a dielectric layer open at the first and second electrodes.

[0024] According to one embodiment, between step c) and step a), each light-emitting diode is covered, on the side of the second face of the first circuit, with the first conductive sublayer.

[0025] According to one embodiment, each second circuit is covered, before step a), with the second conductive sublayer.

[0026] According to one embodiment, step a) of assembly is carried out by a non-hybrid bonding of the first conductive sublayer with the second conductive sublayer.

[0027] According to one embodiment, step a) is followed by a step d) of etching, for each optoelectronic device, a trench extending in the second plate and in the electrically conductive layer down to the dielectric layer.

[0028] According to one embodiment, step d) is followed by a step of filling the trench with an insulating material. Brief description of the drawings

[0029] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0030] [Fig.1A] [Fig.1A] illustrates a partial and schematic cross-sectional view of an embodiment of an optoelectronic device;

[0031] [Fig.1B] [Fig.1B] illustrates a partial and schematic cross-sectional view of a variant of the optoelectronic device shown in [Fig.1A];

[0032] [Fig.2] [Fig.2] illustrates a partial and schematic top view of a mode of creation of an optoelectronic device;

[0033] [Fig.3] [Fig.3] illustrates a partial and schematic top view of another mode of the realization of an optoelectronic device;

[0034] [Fig.4] [Fig.4] illustrates a step in a method of implementing a process of manufacturing of the device illustrated in [Fig.1A] or IB;

[0035] [Fig.5] [Fig.5] illustrates another step in the process;

[0036] [Fig.6] [Fig.6] illustrates another step in the process;

[0037] [Fig.7] [Fig.7] illustrates another step in the process;

[0038] [Fig.8] [Fig.8] illustrates another step in the process;

[0039] [Fig.9] [Fig.9] illustrates another step in the process;

[0040] [Fig. 10] the [Fig. 10] illustrates another step in the process;

[0041] [Fig. 11] [Fig. 11] illustrates another step in the process;

[0042] [Fig. 12] [Fig. 12] illustrates another step in the process;

[0043] [Fig. 13] [Fig. 13] illustrates another step in the process;

[0044] [Fig. 14] [Fig. 14] is a detail view of part of [Fig. 13];

[0045] [Fig. 15] the [Fig. 15] illustrates another step in the process;

[0046] [Fig. 16] the [Fig. 16] illustrates another step in the process;

[0047] [Fig. 17] [Fig. 17] illustrates a step in another method of implementing a manufacturing process for the device illustrated in [Fig. 1A] or 1B; and

[0048] [Fig. 18] [Fig. 18] illustrates another step in the process. Description of the implementation methods

[0049] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0050] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the control circuits of the light-emitting diodes of the optoelectronic devices have only been described briefly.

[0051] Unless otherwise specified, when referring to two elements connected together, this means directly electrically connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be electrically connected or be electrically connected through one or more other elements.

[0052] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0053] Unless otherwise specified, the expressions "approximately", "roughly", "about", and "in the order of" mean within 10%, preferably within 5% near. Furthermore, here we consider that the terms "insulator" and "conductor" mean respectively "electrically insulating" and "electrically conductive".

[0054] Figures IA show a partial, schematic cross-sectional view of an embodiment of an optoelectronic device 11, and [Fig. 1B] shows a cross-sectional view of a variant of the optoelectronic device 11 of [Fig. 1B]. [Fig. 2] is a partial, schematic top view of the optoelectronic device 11 of [Fig. 1A].

[0055] Figures 1A and IB show some of the internal elements of device 11.

[0056] Device 11 comprises: a first portion 13, also called an optoelectronic circuit, comprising at least one inorganic light-emitting diode (LED) emitting radiation, in particular, towards a lower face 13i of the first portion 13, the first portion 13 further comprising an upper face 13s opposite the lower face 13i; and a second portion 15, also called logic circuit, comprising a control circuit for the light-emitting diode LED, and comprising a lower face 15i and an upper face 15s opposite the lower face 15i, the lower face 15i of the second portion 15 being on the upper face 13s of the first portion 13.

[0057] According to the embodiment illustrated in Figures 1A and 1B, the device 11 comprises, at the interface between the optoelectronic circuit 13 and the logic circuit 15, a layer 17 divided horizontally, i.e. in the plane of the upper face 13s, the layer 17 comprising a stack of a first sublayer 173 located in the optoelectronic circuit 13 and a second sublayer 175 located in the logic circuit 15. As described in more detail later, the layer 17 is divided into two parts horizontally in the orientation of [Fig. 1A], i.e. in the plane of the upper face 13s.

[0058] Layer 17 is made of a conductive material, for example, a metallic material or a conductive polymer. Layer 17 is preferably made of titanium, aluminum, nickel, silver, copper, gold, or an alloy or combination of all or part of these materials.

[0059] The upper face of the sublayer 173 corresponds to the upper face 13s of the optoelectronic circuit 13 and the lower face of the sublayer 175 corresponds to the lower face 15i of the logic circuit 15.

[0060] The LED of the optoelectronic circuit 13 comprises, according to the embodiment illustrated in Figures IA and IB, at least two semiconductor layers of opposite conductivity types defining, for example, a PN junction.

[0061] The light-emitting diode (LED) thus comprises a semiconductor layer 19, of a first type of conductivity, for example, type N, and a semiconductor layer 21, of a second type of conductivity, for example, type P, different from the first type of conductivity. Layer 21 may have a dopant concentration of between 10¹⁵ and 10²⁰ dopants / cm³ and a thickness of between 5 nm and 2 pm. Layer 19 may have a dopant concentration of between 10¹⁷ and 10²⁰ dopants / cm³ and a thickness of between 50 nm and 2 pm. Layers 19 and 21 are, for example, made of compound IILV or compound ILVI, for example, GaN (gallium nitride). Layers 19 and 21 may each have a single-layer or multi-layer structure.

[0062] The light-emitting diode (LED) of the optoelectronic circuit 13 further comprises an active layer 25 located between layers 19 and 21. The active layer 25 is the layer in which most of the radiative recombinations occur, resulting in the light emission of the LED. The active layer 25 has, for example, a multi-quantum-well structure.

[0063] According to the embodiment illustrated in Figures IA and IB, the layer 19 rests on a substrate 27. More specifically, the layer 19 completely covers the upper surface of the substrate 27. The substrate 27 may be a growth substrate for the material composing the layer 19 and may be, for example, made of sapphire. Alternatively, the substrate 27 may be a transfer substrate, for example, a glass transfer substrate instead of a silicon growth substrate. Layer 25 preferably covers layer 19 and layer 25 is covered by layer 21. Layer 17 covers layer 21. The lateral edges of layers 21, 25 may have a recess 26 relative to layer 19. The device 11 further includes a conductor via 28 passing through layers 21, 25, electrically insulated from layers 21, 25, and electrically connecting the sublayer 173 of layer 17 to layer 19.According to another embodiment, the conductive via 28 is located on an edge of layers 21 and 25. The sublayer 173 has, for example, a thickness greater than 1.5 pm. In Figures IA and IB, the via 28 is shown stopping on the upper face of layer 19. As an alternative, the via 28 may penetrate layer 19 over a portion of the thickness of layer 19.

[0064] The optoelectronic circuit 13 further includes a first electrode 23, for example the anode of the LED, disposed on and in contact with the layer 21 and a second electrode 24, for example the cathode of the LED, corresponding to the contact between the via 28 and the layer 19.

[0065] The first electrode 23 is, for example, made of a metallic material such as nickel, silver, gold, aluminum, copper, titanium, or an alloy or combination thereof. of all or part of these materials. The first electrode 23 has a thickness, for example, between 200 nm and 900 nm. The first electrode 23 can have a monolayer or multilayer structure.

[0066] According to the embodiment illustrated in Figures IA and IB, the optoelectronic circuit 13 further comprises a dielectric layer 29. The dielectric layer 29 preferably covers the periphery of the first electrode 23, a part of the layer 21 not covered by the first electrode 23, the lateral edges of layers 21, 25 at the recess 26 and the via 28, and layer 19 at the recess 26 and only a part of layer 19 at the via 28. The dielectric layer 29 serves as electrical insulation, but also as passivation of the lateral edges of the active layer 25 which may in particular include quantum wells.

[0067] The layer 29 has, for example, a thickness of between 0.1 pm and 1 pm, and is made of a dielectric material such as silicon nitride or silicon dioxide or a combination of these two materials.

[0068] In the embodiment shown in Figures IA and IB, the light-emitting diode has a so-called planar structure insofar as it corresponds to a stack of layers. According to another particular embodiment, the optoelectronic circuit 13 may comprise one or more three-dimensional light-emitting diodes, for example, wire-shaped or pyramid-shaped. In particular, the LED may comprise one or more three-dimensional semiconductor elements, for example, nanowires or microwires, each three-dimensional semiconductor element being of the first type of conductivity and being covered by an active area, itself covered by a semiconductor element of the second type of conductivity.Electrode 23 can be in contact with semiconductor elements of the second type of conductivity, while semiconductor elements of the first type of conductivity can rest on a conductive layer in contact with via 28.

[0069] The logic circuit 15 includes a region 33, called the MOS circuit, comprising a first part 331 including a substrate in and on which insulated-gate field-effect transistors, also called MOS transistors, are formed. The substrate may be a semiconductor substrate or may have a silicon-on-insulator (SOI) structure. The MOS circuit 33 further includes a first interconnection network 333 located between the first part 331 and the layer 17 and comprising a stack of insulating layers between and through which conductive traces and conductive vias are arranged. In particular, the first interconnection network 333 includes electrically conductive pads 31 and 32.

[0070] The logic circuit 15 further comprises a second network of interconnections 30, located on the MOS circuit 33, on the side of the MOS circuit 33 opposite the optoelectronic circuit 13 and also able to extend through the MOS circuit 33.

[0071] The pads 32 are intended to electrically connect the MOS circuit 33 and the interconnection network 30. The pads 31 are each intended to be electrically connected to an electrode of the light-emitting diode of the optoelectronic circuit 13 via the layer 17. The electrically conductive pads 31, 32 are preferably made of titanium, aluminum, silver, nickel, copper, gold or an alloy or combination of all or part of these materials.

[0072] The device 11 further comprises an electrical insulation structure 39 including: an electrical insulation trench 391 providing horizontal electrical insulation, i.e. insulation in a plane parallel to the face 15i between two parts of the MOS circuit 33 and between two parts of the layer 17; and optionally, an insulating layer 393 covering the MOS circuit 33 on the side of the MOS circuit 33 opposite the optoelectronic circuit 13 and having the same composition as the insulation trench 391.

[0073] The insulation layer 393 is preferably located in the interconnection network 30 at the interface with the MOS circuit 33. The layer 393 and the trench 391 may have a multilayer or single-layer structure. All or part of the layer 393 and the trench 391 are preferably made of a dielectric material. By way of example, the electrical insulation trench 391 may comprise electrically insulating walls and a core made of a filling material, for example, a conductive or semiconducting material. For illustrative purposes, the insulation trench 391 is shown in Figures 2 and 3.

[0074] The trench 391 extends from the upper face of the MOS circuit 33 in the orientation of [Fig. 1A] through the MOS circuit 33 and layer 17 so as to open onto the dielectric layer 29. The trench 391 can be filled with a material having a multilayer or monolayer structure. The trench 391 is preferably filled with a dielectric material.

[0075] Preferably, there is at least one plot 31 on each side of trench 391.

[0076] Trench 391 has, according to the embodiment illustrated in [Fig. 2], an open shape opening onto at least one side of device 11, here onto two sides of device 11. Trench 391 isolates, in particular, a lateral portion of the MOS circuit 33 and a lateral portion of the conductive layer 17 connected to the second electrode 24 of the light-emitting diode. As an example, in the orientation of [Fig. 2], trench 391 is L-shaped and opens onto the top side of device 11 and onto the right side of device 11.

[0077] According to the embodiment illustrated in Figures IA and IB, the interconnection network 30 comprises a stack of insulating layers 37 covering the MOS circuit 33 on the side of the MOS circuit 33 opposite the optoelectronic circuit 13, including layer 393 when present, in which and through which conductive elements are formed, in particular conductive tracks 35 and conductive vias 36. According to one embodiment, each conductive via 36 can be connected to one of the tracks of the first interconnection network 333, for example to one of the pads 32, and thus extend through the first part 331.

[0078] According to one embodiment, there are conductive elements 35, 36 on each side of the electrical insulation trench 391. These elements, on either side of the electrical insulation trench 391, can be electrically connected, for example, by one of the conductive tracks 35, as shown in [Fig.1B].

[0079] According to the embodiment illustrated in Figures IA and IB, the logic circuit 15 further comprises connectors 41 of which at least one of the connectors 41 is connected to the first electrode 23 and at least one other of the connectors 41 is connected to layer 19.

[0080] By way of example, the connectors 41 are made of titanium, aluminum, silver, nickel, copper, gold, tin, tin-silver alloy, or an alloy or combination of all or part of these materials.

[0081] According to the embodiment shown in [Fig.1A], the connectors 41 can be located on either side of the insulation trench 391. However, the position of the connectors 41 does not depend on the position of the electrical insulation trench 391, the connectors 41 not being in particular necessarily aligned with the conductive vias 36, so that the connectors 41 can be located on the same side of the insulation trench 391 as shown in [Fig.1B]. The electrical conductors 35 can, for example, connect a connector 41 located on one side of the insulation trench 391 and a conductor via 36 located on the other side of the trench 391. In addition, as illustrated in [Fig.1B], an electrical conductor 35 can electrically connect two conductor vias 36 located on either side of the insulation trench 391 and electrically connect pads 32 of the first interconnection network 333 of the MOS circuit 33.

[0082] According to one embodiment, not shown, the MOS circuit 33 includes transistors only on one side of the isolation trench 391. The pad 31 located in the part of the MOS circuit 33 not including a transistor is then connected to the second interconnection network 30 without intermediate connection by MOS transistors.

[0083] Fig. 3 illustrates, by a top view, a variant of the device 11 illustrated in Fig. 2.

[0084] According to the embodiment illustrated in [Fig.3], the trench 391 follows, in top view, a closed curve, and thus has an annular shape isolating in particular a central island of the MOS circuit 33 and a central island of the conductive layer 17 connected to the second electrode 24 of the light-emitting diode.

[0085] Figures 4 to 16 illustrate steps in a method of implementing a manufacturing process for the device 11 illustrated in Figures IA and IB.

[0086] Figures 4 to 7 are each of the partial and schematic cross-sectional views of structures obtained at successive stages of an implementation method of the manufacturing process of a wafer comprising several copies of the optoelectronic circuit 13 illustrated in Figures IA and / or IB.

[0087] Fig. 4 illustrates a starting structure 45 from which several devices 11 are made.

[0088] Structure 45 comprises, from bottom to top, in the orientation of [Fig.4]: substrate 27; layer 19; layer 25 is active; and layer 21.

[0089] The substrate 27 corresponds, for example, to a circular semiconductor wafer having a diameter preferably on the order of 150 mm, 200 nm or 300 nm. The layers 19, 25, 21 are all formed as a full wafer so as to cover substantially the entire upper surface of the substrate 27.

[0090] Fig. 5 illustrates a structure 47 obtained at the end of the formation, for each device 11, of the first electrode 23 on the upper face of the structure 45 illustrated in Fig. 4.

[0091] The material constituting the first electrode 23 is deposited, for example, as a full plate before being etched so that, for each device 11, the first electrode 23 is retained only in the desired area. The electrode 23 is, for example, produced by the lift-off technique, which consists of depositing a layer of resin, forming patterns in the resin layer, and then depositing a metallic layer over the entire structure, including the resin patterns. The resin is then dissolved in a solvent, carrying away the portions of metal covering the resin patterns. The metallic deposition is, for example, carried out by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0092] Fig. 6 illustrates a structure 49 obtained after an etching step and deposition of the insulating layer 29 on the upper face of the structure 47 illustrated in Fig. 5.

[0093] In the step illustrated in [Fig. 6], the structure 47 is etched so as to form, for each device 11, openings 261, 281 over a height hl, greater than or equal to the sum of the thicknesses of layers 21 and 25, for example, on the order of 0.5 µm. During this etching step, a portion of layer 19 opposite the openings 261 and 281 may be etched in addition to layers 21 and 25. Only two openings 261 and one opening 281 are shown in [Fig. 6]. The openings 261 are located at the positions where a cutting operation of the devices 11 will be carried out in a subsequent step. The openings 281 are located at the positions of the vias 28.

[0094] The openings 261 have, for example, a width 11 of the order of 50 pm and the openings 281 have, for example, a width 12 of the order of 10 pm in the cutting plane of [Fig.6].

[0095] The insulating layer 29 is preferably deposited on the surface of the structure obtained after the etching of the openings 261, 281 so that the layer 29 covers the upper face of the layer 21, the upper face of the electrodes 23, the lateral edges of the openings 261, 281 and the bottom of the openings 261, 281. The thickness of the layer 29 is for example on the order of 1 pm.

[0096] The insulating layer 29 is subsequently etched, for example by wet or dry etching, in order to expose, for each device 11, a part of the electrode 23 and a part of the layer 19. The etching makes it possible to expose the layer 19 in the openings 281 over a width 13, for example, of the order of 5 pm, in the plane of the cut of [Fig.6].

[0097] Fig. 7 illustrates a structure 50 obtained after a step of deposition of a conductive layer 51 on the upper face of the structure 49 illustrated in Fig. 6 so as to form the conductive sublayer 173 and the vias 28. A wafer comprising several copies of the optoelectronic circuit 13 is thus obtained.

[0098] The conductive layer 51 is preferably deposited over the entire upper face of the structure 49 so that the conductive layer 51 covers the insulating layer 29, comes into contact with the electrodes 23 and comes into contact with the semiconducting layer 19 in the openings 281. The conductive layer 51 extends, in addition, into the openings 261.

[0099] Following the deposition step of the conductive layer 51, the structure is optionally planarized by chemical mechanical planarization (CMP).

[0100] Fig. 8 illustrates a structure 52 comprising, from top to bottom in the orientation of Fig. 8: a substrate 53; and the sublayer 175.

[0101] The substrate 53 preferably comprises several copies of the MOS circuit 33 and a zone 55 free of any electronic components.

[0102] The substrate 53 is, for example, a semiconductor wafer on and in which electronic components have been formed. The substrate 53 preferably has a diameter on the order of 100 mm, 200 mm or 300 mm. The MOS circuits 33 form the lower part of the substrate 53, in the orientation of [Fig. 8] and the area 55 is the upper part of the substrate 53, in the orientation of [Fig. 8].

[0103] The sub-layer 175 has, for example, a thickness greater than 500 nm.

[0104] Optionally, in order to planarize the lower face of the structure 52 and, more specifically, of the sub-layer 175, the latter can undergo a CMP mechano-chemical polishing.

[0105] Fig. 9 illustrates a structure 57 obtained after an assembly step of the structure 50 illustrated in Fig. 7 and the structure 52 illustrated in Fig. 8.

[0106] Structure 52 is transferred onto the upper face of structure 50. More precisely, a lower face 175i of the sublayer 175 of structure 52 is transferred onto an upper face 173s of the sublayer 173 of structure 50. The step of transferring structure 52 onto structure 50 preferably includes an alignment substep so that the MOS circuits 33 are aligned with the openings 261.

[0107] According to one embodiment, the adhesion of the sublayers 173 and 175 is achieved by non-hybrid conductive bonding, i.e., the contacting faces of the sublayers are flat, continuous, and formed of a single material. The materials composing the two sublayers are identical. Thus, 173 and 175 adhere to each other without the need for any adhesive material.

[0108] Fig. 10 illustrates a structure 59 obtained after a thinning step of the structure 57 illustrated in Fig. 9.

[0109] The thinning of the structure 57 illustrated in [Fig.9] is carried out by its upper face so as to remove the area 55 from the substrate 53 and to retain in the substrate 53 only the MOS circuits 33.

[0110] Fig. 11 illustrates a structure 61 obtained at the end of a trench formation step 63 in the structure 59 illustrated in Fig. 10, only one trench 63 being shown in Fig. 11.

[0111] The trenches 63 extend, preferably, from the upper face of the structure 61 into the MOS circuits 33, the sublayer 175 and the sublayer 173 so as to uncover the upper face of the insulating layer 29.

[0112] The trenches 63 are preferably made by a succession of two dry or wet etchings, one allowing the different layers of the MOS circuit 33 to be etched and the other allowing the sub-layers 173 and 175 to be etched. The insulating layer 29 can play the role of etching stop layer during the formation of the trenches 63.

[0113] Preferably, a single trench 63 is made by device 11, i.e. each opening 261 surrounds a single trench 63. Each trench 63 is intended to become an isolation trench 391 as shown in Figures IA, IB and 2. The trenches 63 therefore have the same shape as the isolation trenches 391.

[0114] The trenches 63 preferably have a width 14 of the order of 5 pm in the cutting plane of [Fig. 11].

[0115] Fig. 12 illustrates a structure 65 obtained at the end of a step of formation of the insulation structure 39 on the upper face of the structure 61 and in the trenches 63.

[0116] The insulation structure 39 comprising the insulation layer 393 and the insulation trenches 391 is preferably made by the successive deposition of two layers 67 and 69. The layer 67 is an insulating layer and is, for example, deposited on the upper face of the structure 61 illustrated in [Fig. 11] so that the layer 67 covers the upper face of the MOS circuits 33 and the lateral faces and the bottom of the openings 63. The layer 67 is preferably conformal and deposited by a vapor phase deposition technique.

[0117] Layer 69 is preferably deposited so as to completely cover layer 67. Layer 69, for example, fills trench 39. Layer 69 can be an insulating layer or a layer of a filling material, for example polycrystalline silicon.

[0118] Figure 13 illustrates a structure 71 obtained after a formation step, for each device 11, of the stacking of insulating layers 37, conductive tracks 35, and conductive vias 36 on and within the structure 65 illustrated in Figure 12. Figure 13 illustrates, in a very schematic way, the electronic connection of the tracks 35 to one or more metallization levels of the MOS circuit 33, represented schematically in Figure 13 by the pads 32, via the vias 36. Figure 14 is an enlargement of a portion 73 of the structure 71.

[0119] According to one embodiment, the pad 32 corresponds to a track of any one of the metallization levels of the MOS circuit 33, preferably the first level. In order to reach the track 32, each via 36 passes through, for example: layer 37; and the first part 331 of the MOS circuit 33.

[0120] The fabrication of the vias 36 preferably includes an etching step for etching the portion 331 of the MOS circuit 33 to a thickness of between 3 µm and 5 µm. The vias 36 preferably each have a width 15 greater than 6 µm. Following the etching step, the deposition of an insulating layer 81, for example of silicon dioxide, is carried out, for example, by a plasma-enhanced chemical vapor deposition (PECVD) technique. The layer 81 preferably has a thickness of approximately 0.5 µm. Following the step After the layer 81 has been deposited, it is etched so as to expose a portion of the upper face of the pads 32 (or of a pad 31 if the MOS circuit 33 does not have a transistor on one side of the insulating trench 391), at the bottom of the openings formed in the MOS circuit 33. Etching the layer 81 exposes the pads 32 over a width 16 greater than 3 µm. Following the etching of layer 81, a metallic layer 83 is deposited, for example, of aluminum, tungsten, copper, or a combination or alloy of these two materials. Layer 83 is preferably deposited by a physical vapor deposition technique. Layer 83 thus covers layer 81 and comes into contact with the pads 32. Layer 83 preferably has a thickness of approximately 1 µm. Layer 83 is subsequently etched in order to preserve it to form only the vias 36 and possibly the conductive tracks 35 as illustrated in [Fig.13].

[0121] Figure 15 illustrates a structure 85 obtained at the end of a formation step of connectors 41 on the upper face of structure 71 illustrated in [Fig. 13].

[0122] The connectors 41 are formed in contact with tracks 35. Preferably, for each device, at least one connector 41 is connected to the electrode 23 and at least one connector 41 is connected to the layer 19.

[0123] Figure 16 illustrates a plurality of devices 11 obtained at the end of a step of cutting, of structure 85 illustrated in [Fig. 15].

[0124] The structure 85 illustrated in [Fig. 15] is, for example, sawn so as to make trenches 87 by means of a blade having a thickness, for example, of the order of 40 pm.

[0125] The trenches 87 are through-cut and allow the structure 85 to be cut into unit devices 11. The trenches 87 extend, for example, in the logic circuit 15 and in the optoelectronic circuit 13 through the openings 261. The sawing step of the structure 85 can be preceded by a step of thinning the substrate 27 to a thickness of approximately 300 µm.

[0126] Figures 17 and 18 are partial and schematic cross-sectional views of structures obtained at stages of another implementation method of a manufacturing process of a variant of the optoelectronic device 11 represented in [Fig.1A].

[0127] In particular, [Fig. 17] illustrates a structure 89 obtained as a result of a trenching step 91 in the structure 61 illustrated in [Fig. 11]. The trenches 91 can be formed simultaneously with the trenches 63.

[0128] The trenches 91 preferably extend from the upper face of the structure 89 into the structure 89. The trenches 91 preferably extend through the MOS circuit 33, the sublayer 175 and the sublayer 173 so as to expose the layer 29 in the openings 261. The trenches 91 preferably have, in top view, the same dimensions and shape as the dimensions and shape of the openings. 261. In other words, during this step, the layers above layer 29 are removed directly above the openings 261.

[0129] Fig. 18 illustrates a structure 93 obtained after a step of deposition of an insulating layer 95 and a step of formation of conductive regions 97 on the upper face of the structure 93.

[0130] The insulating layer 95 is preferably a silicon dioxide layer. The insulating layer 95 is preferably deposited by PECVD to a thickness of approximately 1 µm. Openings 99 are then etched into the insulating layer 95. The structure 93 preferably includes at least one opening 99 on each side of the trench 63. The openings 99 each have, for example, a width 17 greater than 3 µm.

[0131] The metallic regions 97 are preferably made of aluminum, copper, or a combination or alloy of these two materials. The metallic regions 97 may have a single-layer or multi-layer structure. The regions 97 are preferably formed to extend into the openings 99. The regions 97 are preferably formed over a width 18 greater than 10 µm.

[0132] The regions 97 are preferably connected to metallic tracks of the MOS circuit 33 in a similar way, for example in a manner analogous to that which has been described previously in relation to [Fig. 13].

[0133] At the end of this step, connectors (not shown in [Fig. 18]), similar to the connectors 41 illustrated in [Fig. 15], are formed on and in contact with the regions 97.

[0134] An advantage of the described embodiments and implementation methods is that they allow the logic circuit 15 and the optoelectronic circuit 13 to be bonded at rather low temperatures (i.e. below 250 °C), which limits the risks of damage to the materials composing the optoelectronic circuit.

[0135] Another advantage of the described embodiments and implementation methods is that they allow for increased reliability of the bonding of the logic circuit 15 and the optoelectronic circuit 13 compared, for example, to a hybrid bonding, based on contact pads.

[0136] Yet another advantage of the embodiments and implementation methods described is that they allow the assembly of the substrate of the light-emitting diodes and the substrate of the control circuits with less positioning accuracy constraints than for a hybrid bonding.

[0137] Yet another advantage of the embodiments and implementation methods described is that, compared to US document 10468452, there are no constraints on the electrical connection between circuits 15 and 13.

[0138] Yet another advantage of the embodiments and implementation methods described is that they allow maximizing the useful surface area of ​​the LED formed on the same growth surface.

[0139] Yet another advantage of the embodiments and implementation methods described is that they limit the risks of damage to the substrate 27 since the insulation trench 391 does not extend to the substrate 27.

[0140] One advantage of the embodiments and implementation methods described is that they are compatible with the usual production lines for microelectronic components.

[0141] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0142] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Claims

1. Optoelectronic device (11) comprising a stack: of a first circuit (13) comprising at least one inorganic light-emitting diode (LED) emitting from a first face (13i) of the first circuit and comprising first and second electrodes (23, 24); and of a second circuit (15) for controlling the light-emitting diode, positioned on a second face (13s) of the first circuit opposite the first face, comprising first and second electrically conductive pads (31), in which an electrically conductive layer (17), comprising the superposition of a first electrically conductive sub-layer (173) of the first circuit (13) and a second electrically conductive sub-layer (175) of the second circuit (15), is located at the interface between the first and second circuits,the electrically conductive layer (17) being divided into first and second parts orthogonally to the stacking direction of the first and second circuits, the first electrode being electrically connected to the first conductive pad via the first part of the conductive layer and the second electrode being electrically connected to the second conductive pad via the second part of the conductive layer, and the first and second parts of the conductive layer (17) being separated by an electrical insulation trench (391).,

2. Device according to claim 1, comprising at least two connectors (41), located on the second circuit (15), on the side opposite the first circuit (13), intended to electrically connect the device (11) to an external object.

3. Device according to claim 1 or 2, in which the first and second conductive pads (31) are separated by said electrical insulation trench (391).

4. A device according to any one of claims 1 to 3, wherein the second circuit (15) comprises metal oxide gate field effect transistors and comprises two parts electrically separated by said electrical isolation trench (391).

5. Device according to claim 4, in which the parts of the second circuit (15) are electrically connected by connections by electrically conductive tracks (35) located on the side of the metal oxide gate field effect transistors opposite the first circuit (13).

6. Device according to any one of claims 1 to 5, in which the electrical insulation trench (391) has a closed shape, in a plane parallel to the second face (13s).

7. Device according to any one of claims 1 to 5, in which the electrical insulation trench (391) has, in a plane parallel to the second face (13s), an open shape whose two free ends open onto one or more sides of the device (11).

8. Device according to any one of claims 1 to 7, in which the first circuit (13) comprises a substrate (27) on the side of the first face (13i).

9. A device according to claim 8, wherein the substrate (27) is sapphire or glass.

10. A device according to any one of claims 1 to 9, wherein the conductive layer (17) is made of metal or a conductive polymer.

11. A device according to any one of claims 1 to 10, wherein the light-emitting diode (LED) is wire-shaped or pyramid-shaped.

12. Device according to any one of claims 1 to 11, in which the electrical isolation trench (391) has a width of the order of 5 pm.

13. A device according to any one of claims 1 to 12, wherein the first electrically conductive sub-layer (173) covers the entirety of the first electrode (23).

14. A structure comprising a plurality of optoelectronic devices (11) according to any one of claims 1 to 13.

15. A method of manufacturing a plurality of optoelectronic devices according to any one of claims 1 to 13, comprising a step a) of assembling a first plate comprising said plurality of first circuits (13) to a second plate comprising said plurality of second circuits (15).

16. Method according to claim 15, in which step a) of assembly is carried out by bringing into contact, full plate, the first and second sub-layers (173, 175) of the electrically conductive layer (17).

17. Method according to claim 15 or 16, in which each first circuit (13) is partially etched in a step b) prior to step a) so as to define a first cavity (281) located at the location of the second electrode.

18. Method according to any one of claims 15 to 17, in which each first circuit (13) is partially etched in a step b') prior to step a) so as to produce a second cavity (261) making it possible to define the edges of said light-emitting diode (LED).

19. Method according to claim 17 or 18, comprising a step c), between steps a) and b) or b'), in which each light-emitting diode (LED) is covered, on the side of the second face of the first circuit (13), with a dielectric layer (29) open at the first and second electrodes (23, 24).

20. Method according to claim 19, in which between step c) and step a), each light-emitting diode (LED) is covered, on the side of the second face of the first circuit (13), with the first conductive sub-layer (173).

21. Method according to claim 20, in which each second circuit (15) is covered, before step a), with the second conductive underlayer (175).

22. Method according to claim 21, in which step a) of assembly is carried out by non-hybrid bonding of the first conductive sub-layer (173) with the second conductive sub-layer (175).

23. Method according to any one of claims 15 to 22, wherein step a) is followed by a step d) of etching, for each optoelectronic device (11), a trench (63) extending in the second plate (15) and in the electrically conductive layer (17) up to the dielectric layer (29).

24. A method according to claim 23, wherein step d) is followed by a step of filling the trench (63) with an insulating material.

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