Nanostructure platform for cell interfacing and corresponding fabrication process

Abstract

The invention relates to a microprocessor comprising a cell interfacing platform, including at least one nanowire-based nanoprobe, each nanowire having a conductive end for contacting a cell. According to the invention, the nanowires are directly constructed on the passivation layer of the microprocessor. Figure 10

Description

Title of the invention: Nanostructure platform for cellular interfacing and corresponding manufacturing method.

[0001] 1. Domain

[0002] The present technique relates to the fields of nanostructures and more particularly nanostructures intended for capturing biological phenomena. More particularly, the present technique relates to a platform for measuring and stimulating neural-type cells or cardiomyocytes, and more generally to any type of cell from which it is possible to capture electrical or electrophysiological activity, which may be dissociated cell cultures (neurons, muscle cells, cardiac cells, etc.), organ tissue cultures or tissue slices (hippocampus, cerebellum, spinal cord, retina, etc.) or organoids based on cells derived from stem cells. The present technique can also be implemented in vivo, for interfacing with cells at the level of functional organs.

[0003] 2. Prior Art

[0004] The study of the electrophysiological states of excitable cells (neurons, cardiomyocytes) and the groups and networks formed by these cells makes it possible to improve the understanding of the functional and pathological states of the organs to which these cells relate. The electrophysiological state of the cell is traditionally studied with calcium imaging, which requires the use of chemical components that can disrupt cellular development and activity, as well as miniaturized devices allowing the direct measurement of electrical potentials (or currents) at the cellular level. These probes, which offer a specific affinity with cells, i.e. external membranes, or in certain cases access to the interior (cytoplasm) of the cell, thus allowing measurements of the potential variations of one or more cells in a network of cells.These probes include patch clamps with glass micropipettes, microelectrode / nanoelectrode arrays (MEAs / NEAs), and planar or nanowire-based field effect transistors (FETs), and with different materials, such as vertical nanowire arrays made of silicon (Si), platinum (Pt), iridium oxide (IrOx) etc.

[0005] Glass micropipette electrodes with a "patch-clamp" process have traditionally been used. They allow good quality measurements to be made, but on the one hand they cannot be used for a large number of cells simultaneously (due to the difficulty of implementing these probes) and on the other hand they lead to the death of cells in the relatively short term, due to the pe- penetration of the micropipette into the cell.

[0006] More recently, technological developments have made it possible to develop planar microelectrode arrays that are becoming standard platforms for studying the electrophysiological responses of cellular networks over long periods (several weeks). These microelectrode arrays have the advantage of not altering the cell envelope and therefore not causing premature cell death. However, planar microelectrode arrays have the disadvantage of being relatively large compared to that of a cell (therefore capturing information from multiple cells at the same time). More importantly, the measurement of potential variations is an important piece of data that should be measured.The main problem, however, with these existing networks and platforms is the weak cell / microelectrode interaction which induces signals (action potential) which are very degraded in terms of amplitude and therefore difficult to interpret.

[0007] Microelectrode-based platforms and networks have been the subject of significant technological developments, such as those presented in documents US7,905,013, WO2017127551 and WO2019110485.

[0008] In US7,905,013, a dielectric layer on a conductive layer is selectively wet-etched, forming contact holes with slanted walls in the dielectric layer and exposing regions of the conductive layer. IrOx nanowire neural interfaces are then grown from the exposed regions of the conductive layer. The IrOx nanowire neural interfaces each have a cross-sectional area between 0.5 and 10 micrometers, an average height between about 10 nanometers (nm) and about 10 micrometers (pm), and an average proximal end diameter in a range of about 1 nm to about 1 pm. Zhang reports probe clusters on chips ranging from 1 to 100 square millimeters. The groups each comprise from 2 to up to 12 electrodes, located in a group diameter between 5 and 50 micrometers, with the number of groups on the chip being between 2 and 100.

[0009] In WO2017127551, a neural probe sensor array is described on an insulating substrate. Such an array comprises a substrate with a metal pattern thereon. An array of vertical semiconductor nanowire probes extending away from the substrate have been patterned in a semiconductor active layer deposited on this insulating substrate. The probes are electrically addressed, individually, through the metal pattern. The metal pattern is insulated with a dielectric, and the base portions and stems of the nanowires are also preferably insulated. This platform makes it possible to individually stimulate the cells that take up residence on the nanowires.

[0010] In WO2019110485, a platform comprising both nanofets and nanowires is described. This platform is manufactured by a top-down method. More particularly, the method for manufacturing such a platform assumes the use of a base comprising a substrate on which is deposited a layer of Ipm of silicon dioxide (SiO2), itself covered with a layer of monocrystalline silicon (Si) 4-5qm thick. It is this last layer of monocrystalline silicon which is subjected to a treatment making it possible to create both the nanowires and the nanofets. The technique proposed in WO2019110485 is effective in that it makes it possible to respond to the problems posed in particular by the techniques of the prior art (US7,905,013 and WO2017127551). On the other hand, the technique of WO2019110485 suffers from a homogeneity problem linked to the monocrystalline silicon (Si) layer.Indeed, the inventors have observed, under operational conditions, that the active layer can experience, in certain circumstances, a variation in thickness of plus or minus 500 nm, or approximately ten percent of the overall theoretical thickness of the active layer. Such a variation strongly impacts the manufacturing yields of the platforms with the technique proposed in WO2019110485. In addition, this approach is only possible by using a very specific substrate (silicon on insulator), with an active layer of fixed thickness.

[0011] As for the implementation on CMOS, the document US20180169403Al sets out the commonly implemented technique. In this document the approach is the direct structuring of each pixel via a layer, added on top of the CMOS, supposedly of finite thickness, which is then structured, determining the final length of the nanostructures. In addition to the aforementioned problems, this also introduces constraints on the processes used which must be compatible with the metallic pixel leading to the CMOS. This can also introduce reliability problems on the CMOS circuit because the metallic connections leading to it are unprotected (since they are structured as such).

[0012] All these approaches also suffer from the inhomogeneity of dry etching speed to create nanostructures: at the scale of a substrate the etching speed is always faster on the peripheral zones than on the center introducing hundreds of nanometers of "over etching" at the edge compared to the center. Thus on a layer of defined thickness, it is not possible to reach the targeted height on all locations of the substrate.

[0013] In summary, the approach followed by those skilled in the art consists of structuring the vertical nanoelectrodes in a layer of defined thickness, this thickness inducing the length of the nanostructures. This approach, as presented previously, faces numerous problems such as the introduction of a uniform active layer (often associated with the use of a very specific and expensive substrate), the structuring of the layer in a homogeneous manner, the strong interaction between the creation of the interface layer on the nanostructures and the metallic accesses of this one (or of the CMOS pixels)

[0014] It is therefore necessary to propose a manufacturing technique that can be implemented on a variety of substrates that allows platforms to be obtained that ensure measurements and observations can be carried out reliably, while guaranteeing the medium or long-term survival of cell cultures and guaranteeing manufacturing reproducibility ensuring high efficiency, perfect compatibility with conventional microtechnology techniques available in foundries, while simplifying the process and therefore leading to a reduction in manufacturing costs.

[0015] 3. Summary

[0016] The present technique was constructed based on these problems of the prior art.

[0017] More particularly, the present technique relates to a microprocessor comprising a platform for cellular interfacing, comprising at least one nanoprobe based on nanowires each comprising a conductive end intended to come into contact with a cell, in which the nanowires are directly constructed on the passivation layer of the microprocessor.

[0018] According to a particular characteristic, an access line to a nanowire makes it possible to connect the nanowire directly to a transistor of the microprocessor via a via.

[0019] According to a particular characteristic, the height of the nanowires is between 2 and 20 pm.

[0020] According to another aspect, the present technique relates to a method of manufacturing a platform for cellular interfacing, the platform being manufactured on a predetermined bulk substrate, devoid of an active layer. The proposed technique is remarkable in that the method is of the top-down type, and that on the predetermined bulk substrate, devoid of an active layer, it comprises the following ordered steps:

[0021] - creation of vertical nanowires on the substrate;

[0022] - depositing a layer of insulating dielectric, when necessary;

[0023] - deposition of a layer of silicon;

[0024] - creation of access lines to the nanowires;

[0025] - siliciding of access lines and nanowires;

[0026] - metallic structuring of the access lines;

[0027] - deposition of insulating layer for measurement in liquid medium;

[0028] - selective removal of the insulating layer on the nanowires.

[0029] Thus, it is possible to provide a platform whose properties are stable and reproducible. Indeed, to the extent that the vertical structuring of the substrate takes place before the creation of the access lines (which is carried out by deposition of silicon by example), it is possible to control both the height of the vertical nanowires and the thickness of the access lines to the vertical nanowires. Controlling these two parameters thus makes it possible to have a platform whose characteristics are known and constant during manufacturing.

[0030] According to a particular characteristic, the predetermined solid substrate belongs to the group comprising: transparent substrate (for example quartz, fused silica), flexible substrate (for example polyimide), silicon (or any other semiconductor), a passivation layer (SiO, SiN) of a CMOS electronic circuit.

[0031] Thus, it is possible to manufacture a platform adapted to specific needs. In particular, it is possible to have a platform on a transparent substrate such as quartz, by carrying out vertical structuring directly on the quartz substrate, without requiring the addition of an active layer of Si type to be nanostructured, as in the prior art. It is also possible to have a platform directly constructed on CMOS type electronics, so that the electrical signals of the platform are processed, in whole or in part, directly by this platform without direct structuring of the pixels, as in the prior art.

[0032] According to a particular characteristic, the step of creating the nanowires on the predetermined solid substrate comprises:

[0033] - A photolithography step, comprising a local deposition of a resin pattern which serves as a protective mask; and

[0034] - A dry etching step by ion bombardment allowing the obtaining of vertical nanowires on the substrate, at the desired height.

[0035] Thus, it is possible to easily define what are the different structuring schemes of the vertical nanowires on the platform, while effectively controlling the final height of these nanowires. When the substrate is electrically conductive (Si for example), the nanostructuring step is followed by a full plate deposition of an insulating layer (SiO2 ...) with a thickness between 20 nm and 200 nm, a thickness allowing the subsequent deposition objectives of the other compounds to be met, while guaranteeing the usability of the platforms with respect to the biological materials studied or stimulated.

[0036] Furthermore, there may be an intermediate layer (called a hard mask) during the etching step. This layer is structured by a first etching of the resist patterns (thus defining a mask for a second etching of the nanowires). This allows the use of patterns that resist etching better than the resist and thus obtain longer nanowires more easily.

[0037] According to a particular characteristic, the step of creating the access lines to the nanowires comprises:

[0038] - A step of depositing a layer of polysilicon, full plate, by CVD;

[0039] - A photolithography step, comprising a local deposition of a resin pattern which serves as a protective mask on access lines and vertical nanowires; and

[0040] - A dry etching step by ion bombardment for removal of the layer of polysilicon in unwanted locations.

[0041] According to a particular embodiment, the polysilicon layer has a thickness of between 20 and 200 nm.

[0042] According to a particular embodiment, the polysilicon layer has a thickness of approximately 100 nm.

[0043] Thus, this thickness range makes it possible not to make the nanostructures too wide while minimizing access resistances. According to another embodiment, the polysilicon can also be replaced by amorphous silicon. Generally speaking, it can be silicon.

[0044] According to another aspect, the present disclosure relates to a platform obtained via the aforementioned method.

[0045] According to another aspect, the present disclosure relates to a microprocessor comprising or directly integrating a platform obtained in particular by means of the aforementioned method.

[0046] 4. Figures

[0047] Other characteristics and advantages will appear more clearly on reading the following description of a preferred embodiment, given as a simple illustrative and non-limiting example, and the appended drawings, among which:

[0048] - [Fig.l] [Fig.l] describes the principle of the steps implemented for the manufacturing of a platform according to the present technique;

[0049] - [Fig.2] [Fig.2] represents vertical nanowires obtained on a substrate of silicon;

[0050] - [Fig.3] [Fig.3] represents vertical nanowires obtained on a quartz substrate

[0051] - [Fig.4] [Fig.4] represents a vertical nanowire of a height significantly higher than superior to that of the nanowires of the prior art;

[0052] - [Fig.5] [Fig.5] represents an interfacing platform comprising seven nanowires vertical, composed of nanowires structured directly in the bulk Si substrate, then covered with an oxide layer (SiO2) and a Poly-Si layer which is structured to form an electrode comprising the 7 nanowires extended by an electrical access path; finally, this Si layer was selectively silicidated into PtSi. ;

[0053] - [Fig.6] [Fig.6] is a sectional view taken on the electrode of [Fig.5] re presenting two vertical nanowires, revealing the stacking of the layers thus produced according to the method of the invention;

[0054] - [Fig.7] [Fig.7] represents vertical nanowires obtained on a layer of pitch CMOS circuit sivation. The nanowires, made of SiOx, are structured in the final passivation layer of the circuit and are covered with a layer of amorphous Si (~90nm);

[0055] - [Fig.8] [Fig.8] represents a 3 nanowire electrode where a localized deposit by elec trophochemistry of a conductive organic material (PEDOT:PSS) was carried out;

[0056] - [Fig.9] [Fig.9] schematically represents the different stages of the process of the invention;

[0057] - [Fig. 10] [Fig. 10] schematically represents the different stages of the process of the invention implemented in the passivation layer of a CMOS circuit.

[0058] 5. Detailed description

[0059] As explained above, the prior techniques suffer from problems particularly related to the repeatability of manufacturing and the massive industrialization of the manufacturing of the platforms, these two constraints being important to offer economically interesting products. More particularly, the prior technique consisting of attacking an active surface of a substrate to form the nanoprobes there certainly allows satisfactory results to be obtained, but suffers from random results related to the inconsistency of the thickness of this active layer which is attacked and to variations in the attack speeds itself in directive plasma etching.

[0060] For example, when the active layer of the substrate to be etched is assumed to measure 5 pm, the prior method consists, firstly, in etching this active layer, for example over 4 pm, so as to deliver a remaining layer (for example for an access line) with a thickness of 1 pm and nanoprobes of a given height (height of at most the thickness of the active layer to be etched). However, when the thickness of the active layer is different and fluctuates on the surface of the substrate, the thickness of the active layer (for example of the access line) finally obtained is no longer constant: it can vary from one place to another on the substrate by several hundred nanometers. This is problematic because, at this thickness (hundreds of nanometers), the electrical characteristics of the platform (for example the electrical characteristics of the access line or that of the nanoprobe) vary as a function of the thickness.It follows that the electrical measurements carried out are more or less distorted and / or reliable depending on the final thickness of the active layer once “structured”. As indicated previously, for a theoretical thickness of 5 pm (5 micrometers), the variation in thickness can be plus or minus 500 nanometers. To take the example of an access line, its thickness can therefore theoretically vary from 0 to 1.5 pm, which is potentially detrimental in terms of manufacturing consistency and reproducibility.

[0061] To overcome this original problem, the inventors had the idea of ​​developing a new manufacturing process that provides more consistency in the height of the components formed on the platform and frees itself from the constraints of structuring a layer whose thickness is directly linked to the dimensions of the nanostructures manufactured. In this new process, the manufacturing paradigm is reversed so as to provide a certain reproducibility of the components: the active layer (i.e. the one in which the nanostructure is produced up to the insulator) is no longer the one used for nanostructuring. More particularly, instead of wanting to structure an active layer that is added to the substrate (in the case of an SOI or SOQ substrate) or to the CMOS pixels (in the case of integration on an electronic circuit), as is traditionally the case with previous methods, the invention consists of structuring the upper part of a very thick layer (i.e.a solid substrate, silicon, quartz, flexible substrate), then depositing an active layer of controlled thickness of the order of a hundred nanometers using a predetermined method. This deposition of an active layer ensures the consistency of the thickness of this deposit and therefore ensures that the electrical characteristics of the different devices on the platform are constant.

[0062] In relation to [Fig.l], in general, the proposed manufacturing method thus comprises, after obtaining a substrate suitable for the desired function:

[0063] - a step of structuring (E10) the substrate, to create the topology of the structures there nanoprobes;

[0064] - a step of depositing a layer of SiO2, when necessary;

[0065] possibly, a step of depositing (Eo20) an insulating layer when the substrate is conductive (case of silicon or carbon or any other semiconductor or metal, for example);

[0066] - a step of depositing (E30) an active layer on this substrate, according to a model adapted to the desired function for the platform devices; the thickness of the deposited active layer is controlled and ensures the reproducibility of the platforms obtained; the deposited active layer is for example silicon (polycrystalline silicon, also called poly-Si by LPCVD or low temperature amorphous silicon by PECVD);

[0067] - a step of defining (E40) the electrodes;

[0068] - a step of depositing (E50) a probe interface layer;

[0069] In other words, silicon is deposited in order to be able to carry out a controlled approach in nanoelectrics which is selective siliciding (as carried out below), the silicon layer is structured, then metal is deposited everywhere, which during thermal activation only reacts (Si-Metal alloy) at the places where it is in contact with the silicon. Thus, during a so-called selective chemical etching, the metal on the unreacted areas without attacking the alloy formed. The advantage is that there is no lithography step to perform; Instead, one could directly deposit a metal, then mask with resin and etch the metal on the areas not protected by the resin; This approach is less widespread in Si microelectronics foundries, but remains possible;

[0070] - a step of structuring (E60) the metallic access lines;

[0071] - a step of depositing (E60) an insulating layer;

[0072] - a step of selective removal (E70) of the insulating layer (for example on the na nosondes or any other suitable location depending on the platform considered).

[0073] Thanks to the orderly implementation of these steps, it is possible to obtain probes all having the same dimensions (i.e. having the desired heights) for capturing biological phenomena, while guaranteeing the thickness of the access lines (and therefore guaranteeing consistency of the electrical characteristics) and ensuring high reproducibility (and therefore scalability to industrial scale). In addition, the access lines are more homogeneous and lower: they are therefore no longer “guiding” for the cells in culture, which presents a definite advantage in terms of natural development of the biological sample on the platform.

[0074] Furthermore, since the techniques described are based on a “raw” substrate (i.e. not comprising an active layer), it is possible to define different probe heights depending on the desired use. More particularly, it is possible to define probes of different heights depending on the location on the same platform. It is also possible to define probe heights greater than those previously (limited by the thickness of the active layer).

[0075] The technique described implements a structuring of the nanoprobes directly on a solid substrate (Si or quartz for example). It allows this technology to be carried out in a very simple manner on substrates of high interest, such as transparent substrates (quartz) or flexible substrates, substrates of choice for in vivo applications.

[0076] The technique described makes it possible to obtain maximum chip manufacturing yield: the thickness of the access lines corresponds to the thickness of the silicon deposited (between 50 and 200 nanometers, for example 100 nm) by CVD where the thickness variation is less than 2% on the scale of the entire substrate. The thickness of the deposited silicon must be relatively thin in order to avoid excessively increasing the diameters of the nanostructures by the successive thicknesses deposited on the structures.

[0077] A partial view of a platform of nanoprobes obtained by means of the method previously described is described in relation to FIGS. 2 to 8.

[0078] [Fig.2] shows the result of direct structuring on a solid silicon substrate, before implementing the surface treatment, insulation and structuring. In this [Fig.2] seven silicon nanowires are represented, a focus being made on one of these nanowires, with a height of 3.472 pm and a diameter of 458 nm. [Fig.3] presents the result of direct structuring on a bulk quartz substrate, before implementing the surface treatment, insulation and structuring steps. In this [Fig.3] four quartz nanowires (transparent) are represented. They have a height of approximately 5.90 pm and a diameter of the order of 2 pm. [Fig.4] exposes a Si nanowire with a height of approximately 13 pm, much higher than the traditional height achievable with previous processes. [Fig.5] illustrates a portion of a platform comprising seven nanowires and an access line following the implementation of the process previously described. The 5pm scale shown in [Fig.5] allows the constant thickness of the access line to be gauged. [Fig.6] is a cross-sectional view of two nanowires of identical height after implementing the method described above. [Fig.7] represents seven nanowires etched in a CMOS chip passivation dielectric layer, with a focus on one of these nanowires, with a height of 2.22 pm and a diameter of 520 nm. The nanowires are covered with a layer of amorphous Si deposited by PECVD at low temperature (200 C).

[0079] [Fig.8] represents a 3-nanowire electrode where a localized deposition by electrochemistry of a conductive organic material (PEDOT:PSS) was carried out.

[0080] In relation to [Fig.9], the detailed steps for manufacturing a platform according to an embodiment of the manufacturing method presented previously are presented. On the left side, a top view (UV) of the substrate and on the right side a side view (LV) of the substrate are shown.

[0081] More particularly, in relation to [Fig.9], the manufacturing method comprises the following steps, which are carried out on a base comprising a silicon (Si) substrate (Sub):

[0082] - manufacturing (10) of vertical nanowires: vertical structuring of the platform;

[0083] o this manufacturing is based on a photolithography technique, comprising a local deposition of a resin pattern which serves as a protective mask (resistant nanoplot of 500 nm diameter), using a conventional organic resin (for example of the type ex: ECI 3012); and

[0084] o plasma etching (ICP-RIE deep reactive ion etching) at the desired height (from 1 to 20 pm): dry etching by bombardment of ions (from a plasma); this technique has the advantage of a strong anisotropy of the etching: the boundary between the etched and non-etched areas is most of the time rectilinear and vertical; the remaining resin is removed by chemical etching (resin from the previous sub-step);

[0085] o at the end of this first step, vertical nanowires are placed on the platform, forming groups consisting of 1 to 100 nanowires and distributed over the platform, which are reworked in the following steps in order to add the expected properties;

[0086] - optionally, a layer of insulation (thermal oxidation (11) on Si or deposition oxide) of the entire nano-structured substrate to obtain an insulating layer with a thickness of approximately 100 nm (This step is only necessary on silicon or other conductive substrate in order to be able to insulate the electrodes from each other);

[0087] - creation (12) of access lines:

[0088] o Full wafer silicon deposition by CVD; Indeed, LPCVD: allows polySi to be obtained but at a temperature between 500C0 and 600C° - a temperature which is not compatible with integration on CMOS, or on flexible substrates. As for PECVD, amorphous Si, deposited between 200C° and 300C°. The Si is a little less qualitative than by LPCVD (presence of hydrogen in the layer) but the inventors have pointed out that this is sufficient to be able to produce the Pt or Ni alloy (the selective siliciding approach described later);

[0089] o photolithography, comprising a local deposition of a resin pattern which serves as a protective mask (micrometric patterns defining the electrical contacts connecting the nanoprobes), using a conventional organic resin whose thickness is greater than the length of the nanostructures (for example of the type e.g.: AZ4562); and

[0090] o RIE etching: dry etching by bombardment of ions (from a plasma); this technique has the advantage of a strong anisotropy of the etching: the border between the etched and non-etched areas will most of the time be rectilinear and vertical; all of the nanostructures being protected by the resin, the remaining resin is removed by chemical etching (resin from the previous sub-step) the Si sheath on the nanostructures is not attacked;

[0091] o at the end of this first step, there are groups of nanostructures on a solid Si substrate covered with an insulating layer and a Si layer. On the nanostructures there is a Si sheath then a SiO2 sheath and finally the Si core. The solid Si substrate is covered with a SiO2 insulator on which access lines are structured in the deposited Si layer making it possible to address the different groups of nanostructures independently;

[0092] - Selective creation of a Si-metal alloy: example of the siliciding (13) of platinum (it is also possible to carry out the same approach classically with Ni - and other metals Ti, etc. - Ni allows the siliciding reaction to be carried out at a lower temperature (interesting for substrates more sensitive to temperature)):

[0093] o to create low resistive zones and improve the interface between the nanoprobe and the liquid medium, a step of isotropic deposition of platinum (Pt) on a full plate is carried out by PVD (from the English for “Physical Vapor Deposition”);

[0094] o an activation annealing (400°C, for 4 minutes) then allows the alloy to be created PtSi; The advantage here is that PtSi is only created when the Pt is in direct contact with the Si and not SiO2: the technique used therefore makes it possible to not have PtSi elsewhere than in the desired locations, thus allowing the measurement sensitivity of these to be maintained; it is a diffusion process and therefore exponential with the temperature. It takes a certain time at a given temperature to convert a layer of thickness e. If the temperature is higher, it will be faster. If the layer is thicker it will take longer. 400C / 4 min allows a 60 nm layer of Pt to be converted, which is suitable for the intended use.

[0095] Consequently, it is not necessary to carry out a lithography step for implantation on the metal: there is no need to cover certain areas with resin. In addition, this platinum siliciding step makes it possible to significantly increase the integration of the nanoprobes, while allowing high biocompatibility with the living environment thanks to the activation annealing of the platinum on the Si. This step can be carried out with other metals such as Ni (which has a lower alloy formation temperature), Ti, etc.

[0096] - selective etching (14) of Pt relative to PtSi with aqua regia (chemical mixture of HCl: HNO3: EDI which only etches the metal: the silicide is not attacked):

[0097] o this is a selective chemical etching step which makes it possible to etch the untransformed Pt (from the previous step) without attacking the PtSi: the Pt (untransformed) is therefore removed from the SiO2;

[0098] o The interest of PtSi is twofold: from the point of view of nanoprobes it does not oxidize (in comparison with Si alone) and makes it possible to maintain a low electrolyte / probe interface impedance over time.

[0099] - metallization (15) with aluminum (Al) allowing to reduce the resistance of the lines access:

[0100] o a conformal deposition on the entire Al platform (500 nm) followed by photolithography and chemical etching of the Al not protected by the “etch-back” resin are then implemented to metallize the access lines;

[0101] o the Ai is only retained on the access lines. The remaining resin is chemically removed;

[0102] - isolation (16) of the platform from the environment:

[0103] o An oxide (insulation oxide) is then deposited in a conformal manner to isolate the nanowires from the platform: the oxide used can be SiO2, Al2O3 or HfO2, or a specific dielectric;

[0104] o A selective removal of this insulating oxide is then carried out on the nanowires themselves;

[0105] - finally, an additional conductive layer can be selectively deposited on the nanostructure by electrochemical deposition such as a conductive organic layer (PEDOT:PSS) or metal oxide (IrOx, RuOx) in order to be able to modify the interface properties of the nanoprobes.

[0106] In an alternative application of this exemplary embodiment, described in relation to [Fig. 10], the method previously described is implemented on a CMOS circuit type chip. The steps are substantially identical to those described in relation to [Fig. 9]. More particularly, in this configuration, the dielectric passivation layer of the CMOS chip is used as a bulk substrate, making it possible to construct the nanowires (photolithography, plasma etching) directly on this dielectric passivation layer and then to create the access lines, the siliciding (etc.) without having to address the metal pixels.

[0107] In [Fig. 10], pixels of the CMOS are represented (Pix), in a schematic sectional view. According to this variant, the nanoprobes are constructed above selected pixels and then connected during step 15 of Al metallization of the access lines by a metallized via (through opening) thus connecting each selected pixel of the CMOS chip to its associated nanoprobe. More particularly, in this embodiment, a specific pattern is used to ensure that the metallized access lines of the nanoprobes come directly into contact with the pixels of the chip. This pattern is for example provided by the manufacturer of the chip (when the latter is prefabricated upstream).The scheme is then used during the vertical structuring step of the platform to not only create the vertical nanowires, as explained previously, but also to make a complete opening (via) of the passivation layer, according to the scheme provided, above pixels with which the access lines must be connected. Once this resumption of contact by metallization is carried out, the isolation (16) of the platform with respect to the medium is carried out, which makes it possible to isolate again the structured passivation layer from the CMOS and to restore the original properties of the CMOS. A selective removal of the insulation layer is then carried out on the nanoprobes. It is thus possible to create a nanoprobe platform directly on an electronic component in charge of carrying out all or part of the processing of the electrical signals passing through these nanoprobes.

[0108] Thus, CMOS technology is directly used to develop a platform that can perform large-scale parallel cellular neural coupling. For example, the number of nanowire recording sites can be significantly large, and this nanowire array is made "active" by fabricating it on top of the CMOS integrated circuit. The nanowires in each recording site are connected to their own amplifier and stimulator in the underlying integrated circuit (i.e., the integrated circuit itself assumes an array structure with a number of amplifiers and / or stimulators equivalent to the number of nanowires in the platform. On-chip electronics in the integrated circuit can be used to pursue several objectives. First, it makes parallel operation of the array of nanowire sites possible on a large scale. Second, on-chip electronics near the nanowires can increase recording sensitivity, for example by avoiding an excessively long signal path to the electronics, which can attenuate the signal or introduce noise. Thus, such a CMOS platform can be used for intracellular and massively parallel recording and stimulation of dissociated in vitro cell network cultures. Such a platform can also be used in the study of neuronal networks in vivo and the development of new types of neuroprostheses.As previously stated, the advantage of the proposed platform, particularly obtained with the manufacturing process presented, lies in the very low manufacturing variability, truly allowing scaling up and a reduction in manufacturing costs.

[0109] In a complementary manner, the invention also relates to a platform for cellular interfacing, manufactured on a predetermined solid substrate using the method previously presented. In particular, such a platform is remarkable in that the silicon layer deposited after the creation of the vertical nanowires directly on the substrate has a thickness of between 20 and 200 nm; with a preferred thickness of around 100 nm. Such a platform may also, depending on the production conditions, comprise groupings of vertical nanowires into clusters, so as to produce predefined groups for cellular measurement on the same platform. The platform may advantageously be specialized according to the biological materials to be studied / stimulated.More specifically, the positioning and spacing of the vertical nanowires is determined and selected according to the types of cells to be interfaced, and in particular the size of these cells. In addition, the surface of the platform can be treated to define hydrophilic / hydrophobic zones allowing a more precise placement of the cells studied and therefore allowing a better interfacing of these cells. Furthermore, the height of the nanowires on these platforms is between 2 and 20 pm. The height of these nanowires is, like their number and spacing, determined according to the typologies of cells to be interfaced, but also the environment in which these cells are immersed in order to guarantee their life / survival during the study phase.Furthermore, according to the present invention, the height of the nanowires can be different on the same platform, in order to allow several different typologies of cells to be integrated within the same cultures and / or to be able to interface several layers of cells of the same biological sample, thus ensuring measurements in different operational conditions, while making it possible to maintain, to a certain extent, a single cell type resolution.

Claims

Claims

1. CMOS circuit type microprocessor, comprising a platform for cellular interfacing, comprising at least one nano-probe based on nanowires each comprising a conductive end intended to come into contact with a cell, characterized in that the nanowires are directly structured within the passivation layer of the microprocessor.

2. Microprocessor according to claim 1, characterized in that an access line to a nanowire makes it possible to connect the nanowire directly to an entry point of the microprocessor via a via.

3. Microprocessor according to claim 1, characterized in that the height of the nanowires is between 2 and 20 pm.

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