Method for manufacturing an electronic circuit for self-assembly into another electronic circuit

Abstract

Method for manufacturing an electronic circuit for self-assembly to another electronic circuit. This description relates to a method for manufacturing an electronic circuit (30) comprising: - a support (32), - an assembly site (31) having a first protruding surface relative to said support intended to be assembled to an assembly site of another electronic circuit by a self-assembly process, and - a peripheral zone (39) around said assembly site, the assembly site (31) comprising at least one level, each level comprising conductive pads (34) and insulating posts (380) between the conductive pads;said manufacturing process comprising the formation of said at least one level of the assembly site, the contours, in at least one direction (X) of the principal plane (XY), of each level of the assembly site and the edges, in at least one direction (X), of the conductive pads and the insulating posts of the same level being defined in a single photolithography step of said process. Figure for the abstract: Fig. 3F;

Description

Title of the invention: Method for manufacturing an electronic circuit for self-assembly with another electronic circuit. Technical field

[0001] The present description relates in general to the three-dimensional integration of microelectronic components, and more particularly to the manufacture of electronic circuits capable of being assembled one on top of the other by a self-assembly process. Previous technique

[0002] To achieve the three-dimensional integration of microelectronic components, several techniques exist, and in particular the so-called "die-to-wafer" approach. This technique aims to use the functional chips from a wafer and transfer them, after cutting, onto another wafer which can also be pre-functionalized, that is to say, prepared for assembly with the chip.

[0003] Chip alignment on a wafer can be achieved with robotic machines that pick and position the chips, one by one, for assembly on the wafer. This technique and the associated machines are known by the Anglo-Saxon term "pick-and-place." However, due to the decreasing dimensions in three-dimensional integration, leading to an increase in the required alignment accuracy between the chip and the wafer (for example, alignment error less than 1 µm or even 0.5 µm), combined with assembly rate requirements (for example, greater than 10,000 chips per hour), this technique is becoming less and less suitable. Furthermore, its implementation involves the use of generally expensive and complex machines.

[0004] Self-assembly techniques are increasingly being considered as alternatives or complements to robotics, and in particular to the pick-and-place technique.

[0005] A known self-assembly method, allowing an electronic circuit to be aligned and then assembled on a support, consists of using a fluid as a self-alignment medium, in particular a drop of liquid.

[0006] The electronic circuit to be assembled may be a chip (die or chip in English) and correspond to an integrated circuit. The substrate generally corresponds to another electronic circuit, which may be an integrated circuit chip or an integrated circuit wafer, which may be referred to for short as a "wafer".

[0007] A method for self-assembling an electronic circuit onto a substrate can be based on confining a drop of liquid, for example water, onto a highly wettable surface (which can be referred to as a "hydrophilic" surface) located on the substrate and corresponding to the desired location of the electronic circuit. The electronic circuit can then be placed on the liquid drop, which allows it to be aligned with its location on the substrate.

[0008] The highly wettable surface can be surrounded by a low-wettable surface (which can be referred to as a "hydrophobic" surface) to promote the confinement of the liquid droplet on the hydrophilic surface. The wettability of a material can be characterized by the contact angle θ (visible in [Fig. 1]) of a liquid droplet on the material (angle θ is visible in [Fig. 1]). The smaller the contact angle, the higher the wettability of the material.

[0009] Fig. 1 represents an example of a support 100 and an electronic circuit 200 adapted to be assembled together by a self-assembly process.

[0010] The support 100 has on its upper face 100A a highly wettable assembly site 110 surrounded by a peripheral zone 190 with low wettable properties. For example, the edges 110A, 110B of the assembly site 110 form a step relative to the peripheral zone 190. The assembly site 110 forms a protrusion on a substrate 120 and comprises several conductive pads 140 flush with the surface and separated by insulating posts 130.

[0011] Similar to the support 100, the electronic circuit 200 has, on its front face 200A, which corresponds to the face intended to be attached to the upper face 100A of the support 100, a protruding assembly site 210, the dimensions of which are substantially the same as those of the assembly site 110 of the support. The assembly site 210 is surrounded by a peripheral zone 290 with low wettability. For example, the edges 210A, 210B of the assembly site 210 form a step relative to the peripheral zone 290, which can also correspond to the edges of the electronic circuit 200. As with the support 100, the assembly site is arranged on a substrate 220 and has conductive pads 240 that are flush with the surface and separated by insulating posts 23H0.

[0012] To assemble the electronic circuit 200 to the support 100, a drop G of a liquid, for example water, is placed on the assembly site 110 of the support. The electronic circuit 200 is then brought close to the assembly site 110 until its assembly site 210 comes into contact with the drop. During this approach phase, the electronic circuit may be offset or even tilted relative to the assembly area. The forces exerted by the drop on the electronic circuit then move the electronic circuit 200 to the desired alignment with the assembly site 110, generally without any external action being necessary. Once the circuit Once the electronic circuit is aligned with the substrate, a step of fixing the electronic circuit to the substrate can be implemented after the liquid has evaporated. By convention, the fixing step is considered to be part of the self-assembly process.

[0013] For certain applications, the fixing step may include, or consist of, a thermocompression or molecular bonding step. Molecular bonding (or "direct bonding") is induced by the set of attractive forces of electronic interaction between the atoms or molecules of the two surfaces to be bonded and thus makes it possible to join the two surfaces through direct contact without the use of an adhesive material.

[0014] In particular, we seek to implement a hybrid fixation step in a self-assembly process, enabling the assembly of an electronic circuit onto a substrate while ensuring electrical interconnection between the electronic circuit and the substrate. For short, we may refer to this as a hybrid self-assembly process throughout this description. In particular, the fixation step may include, or consist of, a hybrid molecular bonding step.

[0015] In the example shown, a hybrid self-assembly process must make it possible to fix the electronic circuit 200 to the support 100 by aligning not only the assembly sites 110, 210 with respect to each other, but also to bring the conductive pads 240 of the electronic circuit 200 into contact with the conductive pads 140 of the support 100.

[0016] However, with known self-assembly processes, it can be difficult to achieve correct alignment of the assembly sites while maintaining the alignment of the conductive studs. This stud alignment requirement is even more crucial when the spacing between the conductive studs decreases and / or the width of the conductive studs decreases.

[0017] There is therefore a need for a solution allowing self-assembly of an electronic circuit on another electronic circuit, which allows the alignment of the electronic circuits with respect to each other while ensuring the alignment of the conductive pads of the electronic circuit with those of the other electronic circuit, regardless of the pitch between the conductive pads and / or the widths of said conductive pads.

[0018] It is also desirable that the solution be compatible with conventional techniques for manufacturing and / or assembling electronic circuits. Summary of the invention

[0019] One object of an embodiment is to overcome all or part of the drawbacks of known self-assembly solutions, by proposing a manufacturing process for an electronic circuit adapted to be assembled by a self-assembly process with hybrid attachment to another electronic circuit.

[0020] One embodiment provides a method for manufacturing an electronic circuit extending along a main plane and comprising: - a support, - an assembly site on said support, said assembly site having a first protruding surface relative to said support intended to be assembled to an assembly site of another electronic circuit by a self-assembly process, and - a peripheral zone around said assembly site; the assembly site comprising at least one level, each level comprising conductive pads and insulating posts between the conductive pads, said conductive pads and said insulating posts being flush with said first surface of said assembly site; said manufacturing process comprising the formation of said at least one level of the assembly site; the contours, in at least one direction of the principal plane, of each level of the assembly site and the edges, in at least one direction, of the conductive pads and insulating posts of the same level being defined in a single photolithography step of said process; said photolithography step being adapted to form a resin pattern dimensioned to form, after an etching step from a face of a structure covered by said pattern, said contours and said edges.

[0021] According to one embodiment, the manufacturing process includes, for each level of the assembly site, an engraving step, subsequent to the photolithography step, said engraving step being carried out from the face of the structure covered by the resin pattern forming the engraving mask.

[0022] According to one embodiment, the resin pattern formed for each level of the assembly site is dimensioned so that the insulating posts include insulating posts at the edges of the assembly site that are wider in at least one direction of the main plane than the insulating posts located between said edges.

[0023] According to one embodiment, the resin pattern formed for at least the first level of the assembly site is dimensioned to form on the peripheral area of ​​the support of complementary posts in the insulating layer.

[0024] According to a particular embodiment, the supplementary posts are configured to decrease the wettability of the peripheral zone relative to the wettability of the assembly site. For example, the supplementary posts have a width in a direction of the main plane of between 0.5 pm and 1 pm, a height of between 50 nm and 2 pm, and two adjacent supplementary posts are separated by a spacing of between 0.5 pm and 2 pm in said direction.

[0025] According to one embodiment, the formation of a first level of the assembly site comprises: - a step of forming an insulating layer of a first dielectric material on the support; then - a photolithography step adapted to form a resin pattern on the insulating layer; then - an etching step from the face of the insulating layer covered by the pattern forming the etching mask, so as to form a plurality of trenches in said insulating layer separated from each other by insulating posts in the first dielectric material; then - a step to remove the pattern; then - a step of forming a conductive layer in a first metallic material on the engraved face of the insulating layer so as to at least fill the trenches, the first metallic material inserted into the trenches forming conductive pads separated from each other by the insulating posts; then - a polishing step, for example mechanochemical, of the conductive layer, said polishing step being adapted to bring the conductive pads flush with the same level as the insulating posts of the engraved insulating layer.

[0026] The first metallic material is, for example, copper or cobalt.

[0027] According to one embodiment, the formation of a first level of the assembly site comprises: - a step of forming a conductive layer of a second metallic material on the substrate; then - a photolithography step adapted to form a resin pattern on the conductive layer; then - an etching step from the face of the conductive layer covered by the pattern forming the etching mask, so as to form a plurality of trenches in the conductive layer and conductive pads in the second metallic material separated from each other by said trenches; then - a step to remove the pattern; then - a step of forming an insulating layer of a second dielectric material on the etched face of the conductive layer so as to at least fill the trenches, the second dielectric material inserted into said trenches forming insulating posts insulating the conductive posts from each other; then - a polishing step, for example mechanochemical, of the insulating layer, said polishing step being adapted to bring the insulating posts flush with the conductive studs.

[0028] The second metallic material is, for example, aluminium, tungsten, or an alloy based on aluminium and copper or aluminium and silicon.

[0029] According to one embodiment, the formation of the first level of the assembly site includes, prior to the step of forming the insulating layer in the first dielectric material or the conductive layer in the second metallic material, a step of forming an etching stop layer on the support, for example a silicon nitride layer.

[0030] According to one embodiment, the steps for forming the first level of the assembly site are repeated at least once so as to form another level of the assembly site comprising additional conductive pads and additional insulating posts, said additional conductive pads, respectively said additional insulating posts, being arranged opposite the conductive pads, respectively the insulating posts, of the previously formed assembly site level. In one example, said method includes a preliminary step of forming an etching stop layer on the previously formed assembly site level.

[0031] According to one embodiment, the manufacturing process includes a complementary photolithography step adapted to cover the assembly site with a complementary resin pattern, said complementary pattern extending by a dimension for example between 1 nm and 1 pm, for example 300 nm, on either side of said assembly site above the peripheral area.

[0032] According to a particular embodiment, the manufacturing process includes, subsequent to the additional photolithography step, an additional etching step, preferably wet, of a part of at least one conductive layer located on the peripheral area.

[0033] According to a particular embodiment, the manufacturing process includes a step, subsequent to the complementary photolithography step and, where applicable, to the complementary etching step, of forming a layer, for example of thickness between 1 and 300 nm, of a hydrophobic material on the peripheral area, the hydrophobic material being for example a fluorinated material, preferably fluorocarbon.

[0034] One embodiment provides an electronic circuit extending along a main plane and comprising: - a support; - an assembly site on said support, said assembly site having a first protruding surface relative to said support intended to be assembled to an assembly site of another electronic circuit by a self-assembly process; and - a peripheral zone all around said assembly site; the assembly site comprising at least one level, each level comprising conductive pads and insulating posts between the conductive pads, said pads conductors and said insulating posts flush with said first surface of said assembly site; the contours, in at least one direction of the main plane, of each level of the assembly site and the edges, in at least one direction, of the conductive pads and insulating posts of the same level being defined in a single photolithography step, adapted to form a resin pattern dimensioned to form, after an engraving step from a face of a structure covered by said pattern, said contours and said edges; the outlines of the assembly site, in at least one direction of the main plan, including insulating posts.

[0035] An embodiment provides for a self-assembly method of a first electronic circuit and a second electronic circuit, the first and second electronic circuits being manufactured by the manufacturing process according to an embodiment, the self-assembly method comprising: - a step of depositing a drop of liquid onto the first surface of the assembly site of the first electronic circuit; then - bringing the first surface of the assembly site of the second electronic circuit into contact with the first surface of the assembly site, coated with the drop of liquid, of the first electronic circuit; then - a fixing step, for example by hybrid molecular bonding or thermocompression, of the assembly site of the second electronic circuit to the assembly site of the first electronic circuit.

[0036] According to one embodiment, the second electronic circuit is cut to form an integrated circuit chip, prior to the contact step, the first electronic circuit being an integrated circuit board. Brief description of the drawings

[0037] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0038] [Fig.1] represents an example of an electronic circuit and support intended to be assembled by a self-assembly process;

[0039] [Fig.2A], [Fig.2B], [Fig.2C] and [Fig.2D] are cross-sectional views illustrating a self-assembly process of an electronic circuit on a support;

[0040] [Fig.3A], [Fig.3B], [Fig.3C], [Fig.3D], [Fig.3E] and [Fig.3F] are cross-sectional views illustrating a manufacturing process for an electronic circuit according to an embodiment;

[0041] [Fig. 3G] is a cross-sectional view illustrating a self-assembly method of two electronic circuits obtained by the manufacturing process of figures 3A to 3F;

[0042] [Fig.3H] is a top view of the electronic circuit obtained by the process of figures 3A to 3F;

[0043] [Fig.4A], [Fig.4B] and [Fig.4C] are cross-sectional views illustrating a manufacturing process for an electronic circuit according to another embodiment;

[0044] [Fig.5] represents a variant of the manufacturing process of figures 4A to 4C;

[0045] [Fig.6A] and [Fig.6B] are cross-sectional views illustrating a manufacturing process for an electronic circuit according to another embodiment;

[0046] [Fig.7A], [Fig.7B], [Fig.7C] and [Fig.7D] are cross-sectional views illustrating a manufacturing process for an electronic circuit according to another embodiment;

[0047] Figures 8A, 8B, 8C, and 8D are cross-sectional views illustrating a method for manufacturing an electronic circuit according to another embodiment. Description of embodiments

[0048] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0049] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0050] In particular, the portion of each electronic circuit known as the back end of line (BEOL) is shown, corresponding to the area where the components of the electronic circuit are interconnected with each other and / or can be interconnected with another electronic circuit, by means of one or more metallization layers. The BEOL of an electronic circuit generally comprises at least one insulating layer in which metallic traces of one or more metallization layers and conductive vias for connecting the electronic components together (not shown in the figures) are formed, as well as conductive connection pads suitable for connecting the electronic circuit with another electronic circuit. Below the BEOL, the electronic circuit generally comprises at least one substrate in and / or on which electronic components are formed, which are not shown in the figures.

[0051] In addition, certain steps of the manufacturing process (for example layer formation steps, photolithography steps, resin removal steps, etching steps...) are not detailed, these steps being within the reach of a person skilled in the art who can implement common techniques for manufacturing electronic circuits.

[0052] Unless otherwise specified, when referring to two elements connected between them, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or linked via one or more other elements.

[0053] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures or to an electronic circuit, considering that the BEOL is in the upper part.

[0054] Throughout this description, a height and a thickness refer to a dimension in a vertical direction (direction Z identified in the figures), and a width refers to a dimension along the X direction identified in the figures. A pitch, or spacing, refers in the figures to a dimension along the X direction. A pitch, or spacing, can also correspond to a dimension along the Y direction perpendicular to the X and Z directions. The X and Y directions form an XY plane designated as the principal plane of an electronic circuit.

[0055] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0056] Throughout this description, a "hydrophilic" material refers to a material with high wettability, and a "hydrophobic" material refers to a material with low wettability. Generally, the wettability of a material can be characterized by the static contact angle of a liquid drop on the material. The smaller the contact angle, the higher the wettability of the material. A material with high wettability can be considered to be one for which the static contact angle of a liquid drop on the material is less than 90°, and a material with low wettability to be one for which the static contact angle of a liquid drop on the material is greater than 90°. The wetting angle can be measured using the measuring device marketed by GBX under the name Digidrop - MCAT.

[0057] Figures 2A to 2D represent steps in a self-assembly process of an electronic circuit, for example a chip, onto another electronic circuit, for example a board.

[0058] Figure 2A shows two electronic circuits 1, 2, which may be integrated circuit boards. Each electronic circuit 1, 2 shown comprises a substrate 12, 22, for example made of silicon (Si), on which is disposed at least one first layer 13, 23 made of a dielectric material, for example silicon dioxide (SiO2). A stop-etching layer 17, 27, for example made of silicon nitride (SixNy), is arranged on the first layer 13, 23 of dielectric material. A second layer 18, 28 of dielectric material, for example silicon dioxide (SiO2), is arranged on the stop layer 17, 27. Several conductive pads 14, 24 extend substantially vertically in the second layer 18, 28 of dielectric material up to the etching stop layer 17, 27 and are flush with the upper face of said second layer. Thus, two adjacent conductive pads 14, 24 are separated by the dielectric material of the second layer 18, 28.

[0059] In [Fig. 2A], the widths of the conductive pads 14, 24 are all substantially equal, and the spacings between two adjacent pads are all substantially equal. However, it is possible to have, on the same assembly site, different areas, each with its own conductive pad size and spacing. This is referred to as “multi-pitch”.

[0060] Alignment marks 16, 26 have been formed in each of the two electronic circuits 1, 2. The marks 16, 26 are for example positioned in the second dielectric layer 18, 28 of each electronic circuit, between two conductive pads 14, 24. The alignment marks 16, 26 are positioned symmetrically between the first and second electronic circuits.

[0061] The conductive pads 14, 24 shown are for example made of copper (Cu). They can be formed by a process called "Damascene", comprising an etching step of the second dielectric layer up to the etching stop layer in order to form trenches and / or holes in said second layer, generally preceded by a photolithography step to define a resin pattern forming an etching mask, then a copper deposition step to fill the trenches and / or holes, then a polishing (or "planarization") step of the upper surface of the electronic circuit so that the conductive pads are flush with the upper face of the second dielectric layer.

[0062] Figure 2B represents a subsequent step in which the second dielectric layer 18, 28 of each electronic circuit 1, 2 has been etched on either side of the series of conductive pads 14, 24 to form an assembly site 11, 21 incorporating said conductive pads. Only dielectric posts 180, 280 remain from the second dielectric layer, arranged between two conductive pads 14, 24, or against a single conductive pad. This etching step is generally preceded by a photolithography step to define the positioning and dimensions of the etch, and thus the positioning and dimensions of the assembly site. For example, the dimensions, and in particular the widths, of the two assembly sites 11, 21 are substantially equal.

[0063] The first electronic circuit thus prepared can form a functionalized plate 10 for a self-assembly process with a chip 20.

[0064] After step 2B, the second electronic circuit 2 is cut to form a chip 20 and then this is turned over so that it can be aligned and then assembled to the plate 10.

[0065] One solution, shown in [Fig. 2C], for aligning the chip 20 with the plate 10, commonly used in the pick-and-place technique, is to control the alignment of the marks 26 of the chip 20 with respect to the marks 16 of the plate 10 using a camera in order to align the conductive pads 14 of the plate 10 with the conductive pads 24 of the chip 20. This solution can generate an offset between the assembly site 11 of the plate 10 and the assembly site 21 of the chip 20, as can be seen in [Fig. 2C]. Such a solution is not feasible in a self-assembly process.

[0066] Another solution, shown in [Fig. 2D], more suitable for a self-assembly process, is to align the edges 11A, 11B of the assembly site 11 of the plate 10 with the edges 21A, 21B of the assembly site 21 of the chip 20. However, this solution can lead to misalignment between the conductive pads 14 of the plate 10 and the conductive pads 24 of the chip 20, as can be seen in [Fig. 2D]. With such misalignment of the conductive pads, the interconnection between the chip and the plate once assembled may not be guaranteed.

[0067] This misalignment is due to the fact that each assembly site with conductive pads is formed using two photolithography / etching levels, as explained above: a first level to form the conductive pads and then a second level to form the assembly site. However, during the assembly site manufacturing process, and in particular due to the two photolithography / etching levels, misalignment can occur in the X direction (and / or in the Y direction), notably due to transformations of the underlying layers. Such misalignment between two photolithography levels can reach approximately 250 nm for an electronic circuit, and 500 nm when two electronic circuits are superimposed. This imposes a technological limit on reducing the width of the conductive pads and the interconnection pitch (separate distance between two conductive pads).

[0068] The inventors have proposed a method for manufacturing an electronic circuit intended to be assembled to another electronic circuit by a self-assembly process, making it possible to overcome all or part of the aforementioned disadvantages.

[0069] Examples of implementation of manufacturing processes will be described below. These examples are not limiting, and various variations will become apparent to those skilled in the art based on the indications in this description.

[0070] Figures 3A to 3F are cross-sectional views illustrating a method for manufacturing an electronic circuit 30 intended to be assembled by a self-assembly process into another electronic circuit obtained by a manufacturing process according to, preferably the same, method of implementation.

[0071] Figure 3A illustrates a starting structure 32 (support). It comprises a substrate 321 coated with an initial layer of dielectric material 322 with a thickness typically between approximately 50 nm and 2 pm, for example, approximately 500 nm. The substrate is, for example, silicon (Si) with a thickness between approximately 300 pm and 2000 pm, for example, approximately 725 pm. The dielectric material of the initial layer is, for example, silicon dioxide (SiO2).

[0072] Throughout this description, a layer of dielectric material may also be referred to as an "insulating layer." An insulating layer may be a monolayer or have a multilayer structure comprising a stack of insulating layers.

[0073] The initial layer of dielectric material 322 is covered with a stop layer of etching 37, for example, of silicon nitride (SixNy). Its thickness is, for example, between approximately 5 and 300 nm, for example approximately 70 nm.

[0074] The etching stop layer 37 is covered with a layer 38 of dielectric material, for example silicon dioxide (SiO2) and of thickness typically between about 100 nm and 2 pm, for example equal to about 500 nm.

[0075] A pattern 301 in resin, consisting of a succession of solid crenellations separated by holes, is produced by photolithography on the insulating layer 38.

[0076] Fig. 3B illustrates the structure obtained after etching the insulating layer 38 through the resin mask formed by the pattern 301 with a stop on the etching stop layer 37, removal of the pattern 301 and then etching the etching stop layer 37 through the etched insulating layer 38.

[0077] This results in a plurality of posts 380 made of dielectric material and trenches 306 between said posts. The plurality of insulating posts 380 defines the contours of the future assembly site 31 (shown in dashed lines in [Fig. 3B] because it is not yet finalized at this stage of the process) of the electronic circuit, as well as the locations of the future conductive pads 34 which will be made in the trenches 306.

[0078] Thus, the contours of the assembly site and the edges of the conductive pads in said assembly site (i.e., their locations and dimensions) are defined during this photolithography step, i.e., with the same photolithography layer. The contours and edges are defined in at least the X direction of the principal XY plane, but can also be defined in the Y direction of the principal plane.

[0079] Optionally, alignment markers 36 are formed in one or more of the insulating posts 380.

[0080] Fig. 3C illustrates the formation of the conducting pads 34 at the level of the trenches 306.

[0081] For this purpose, a barrier layer 302 is formed on the insulating posts 380 and the uncovered portions of the initial insulating layer 322; then a tack layer 303 of metallic material is formed on this barrier layer.

[0082] The barrier layer 302 comprises a material suitable for blocking the diffusion of the metallic material into the dielectric material, for example titanium nitride (TiN), optionally used in a bilayer with titanium (TiN / Ti) or a tantalum nitride and tantalum bilayer (TaN / Ta). Its thickness is, for example, between approximately 5 and 300 nm, for example approximately 10 nm.

[0083] The seed layer 303 is an initiation layer that allows the subsequent growth of a metallic layer by electrochemistry. For example, it is made of copper, enabling the formation of a copper layer by electrochemistry. Its thickness is, for example, between approximately 1 nm and 300 nm, for example, approximately 90 nm.

[0084] Next, a metallic layer 304, for example copper, with a thickness between 100 nm and 3 pm, for example equal to 1 pm, is grown by electrochemistry from the anchoring layer 303. The metallic material notably fills the trenches 306.

[0085] Alternatively, the metallic layer may be made of another metal, for example cobalt (Co) or a metallic alloy. The material of the bonding layer is then adapted to obtain the desired metallic layer.

[0086] The resulting structure is then polished ("planarized") to remove excess material from the metallic layer 304, thus defining a flat surface in which the metallic material in the trenches 306 is flush with the insulating posts 380. The metallic material in the trenches 306 defines the conductive studs 34. Furthermore, the polishing step can advantageously remove a portion of the barrier material layer 302 located on the insulating posts. The polishing step consists, for example, of chemical mechanical polishing (CMP).

[0087] After the polishing step, a first part 304A of the metallic layer forms conductive pads 34 between the insulating posts 380, two conductive pads thus being electrically isolated, and a second part 304B of the metallic layer extends on either side of the alternation of conductive pads 34 and insulating posts 380. The area of ​​alternation of conductive pads 34 and insulating posts 380 defines the assembly site 31 of the electronic circuit 30.

[0088] Next, as illustrated in [Fig.3D], this second part 304B of the metallic layer is removed, as well as another portion 302B of the barrier layer 302 located under said second part of the metallic layer.

[0089] This is done by engraving through a complementary motif 305 made of resin photosensitive formed on the upper surface 31S of the assembly site 31.

[0090] Advantageously, and as shown in [Fig.3D], the complementary motif 305 extends slightly, for example by a dimension between about 1 nm and 1 pm, for example about 300 nm, beyond the upper surface 31S of the assembly site 31. This extension prevents the insulating posts 380 located on the edges 31A, 31B of the assembly site 31 from also undergoing, even partial, engraving during one and / or the other of the two subsequent engraving steps.

[0091] The etching of the second part 304B of the metal layer is preferably a wet etching, for example using a solution composed of a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2).

[0092] The etching of portion 302B of the diffusion barrier 302 can be a dry etching, in particular using a plasma, or a wet etching, in particular using an "SCI" ​​type solution comprising ammonia and hydrogen peroxide.

[0093] Figure 3E illustrates a subsequent, optional step in the formation of a hydrophobic layer 35 ("hydrophobic layer"). This hydrophobic layer increases the wettability difference between the assembly site 31 and the surrounding peripheral zone 39. The hydrophobic layer 35 can be deposited by spin coating or by a vapor deposition technique. Its thickness is typically between approximately 1 nm and 300 nm.

[0094] The hydrophobic material can be a fluorinated material, preferably a fluorocarbon. By way of example, the hydrophobic material is based on CxFy type fluorocarbon compounds, where x and y are real numbers, x ranging from 1 to 5 and y ranging from 1 to 8.

[0095] Fig. 3F illustrates the electronic circuit 30 obtained after removal of the complementary motif 305.

[0096] In the case where a step of forming a layer of hydrophobic material has been carried out, this step also makes it possible to remove the part of the hydrophobic layer formed on said complementary motif, according to a so-called "lift-off" effect.

[0097] The resulting electronic circuit 30 has an assembly site 31 on the support 32, the assembly site having conductive pads 34 extending substantially vertically in the assembly site, two adjacent conductive pads being insulated from each other by an insulating post 380. The assembly site 31 is adapted to be assembled to another electronic circuit by a self-assembly process including a hybrid fixing step, for example a hybrid molecular bonding step or by thermocompression.

[0098] Optionally, the peripheral area 39 of the support 32 surrounding the assembly site 31 is coated with a hydrophobic layer 35, in order to reduce its wettability relative to the assembly site 31 and promote the confinement of a liquid droplets on the assembly site. Other solutions can be implemented to increase this difference in wettability. For example, the hydrophilicity of the assembly surface can be increased by a suitable surface treatment, such as using a UV / Ozone plasma.

[0099] Figure 3G is a cross-sectional view illustrating a self-assembly method for a first electronic circuit 30 and a second electronic circuit 30', said electronic circuits being obtained by a manufacturing process according to the example described in relation to Figures 3A to 3F. Alternatively, one or both of them may be obtained by another method described later. As shown, the second electronic circuit 30' can be cut, for example to form a chip, before being assembled with the first electronic circuit 30.

[0100] The steps of the self-assembly process are not illustrated, but they typically include: - a step of depositing a drop of a liquid, for example a drop of water, onto the assembly site 31 of the first electronic circuit 30; - a step in which the second electronic circuit 30' is brought close to the assembly site 31 of the first electronic circuit 30 until its assembly site 31' comes into contact with the drop; then, once the second electronic circuit 30' is aligned with the first electronic circuit 30: - a hybrid fixing step of the second electronic circuit 30' to the first electronic circuit 30 after evaporation of the liquid, the fixing being carried out preferably by hybrid molecular bonding or by thermocompression.

[0101] After fixing, it is possible to remove the hydrophobic layer 35, 35' formed on each peripheral area, for example by dry etching.

[0102] The manufacturing process, by defining in a single photolithography step the contours of the assembly site and the edges of the conductive pads in said site, makes it possible to ensure very good alignment of both the assembly sites and the conductive pads between two electronic circuits manufactured according to said manufacturing process.

[0103] It should be noted that, in all the figures which are cross-sectional views, the edges of the assembly site are shown along the X direction, but evidently, the edges are also in the Y direction of the principal XY plane of the electronic circuit. The electronic circuit can have a substantially symmetrical structure in both directions of the plane, as shown in [Fig. 3H], in which the insulating posts 380, the conductive pads 34 and the support 32 surrounding them are seen in top view.

[0104] Figures 4A to 4C are cross-sectional views illustrating a process according to another embodiment. As illustrated in Figure 4A, this example differs from the process previous, in that: - the insulating posts 480 include insulating posts 481 located on the edges 41A, 41B of the assembly site 41 having a width greater than insulating posts 482 located between said edges; and / or - additional posts 483 made of dielectric material are also formed in the peripheral area 49 surrounding the assembly site 41 of the same dimensions as the insulating posts 482 or of larger dimensions.

[0105] The other steps of the manufacturing process are similar to those described in relation to Figures 3A to 3F.

[0106] As illustrated in [Fig. 4B] showing the structure obtained after the polishing step, the presence of additional posts 483 made of dielectric material helps to limit, or even prevent, the dishing phenomenon of the second part 404B of the metallic layer extending on either side of the assembly site 41. This phenomenon can occur during the polishing step on excessively large copper areas and can lead to poor definition of the edges of the assembly site. Furthermore, the change in copper density between the assembly site and the surrounding area can also cause dishing at the conductive pads bordering the assembly site, potentially resulting in poor contact during assembly and a lack of bonding during the fastening step.The presence of the additional posts 483 and the insulating posts 481 located on the edges 41A, 41B of the assembly site 41, which are wider than the insulating posts 482 located between said edges, will limit or even eliminate this phenomenon.

[0107] As illustrated in [Fig.4C], after etching the second part 404B of the metallic layer, the additional posts 483 remain present in the peripheral area 49 surrounding the assembly site 4L. It is possible at this stage either to keep them or to remove them.

[0108] The supplementary posts 483 can indeed be removed by a lift-off effect through wet etching of the etching stop layer 47. During such an etching step, the portions of the etching stop layer located at the edges 41A, 41B of the assembly site 41 and / or the end posts 481 may undergo at least partial etching. It is therefore advantageous, to overcome this problem, for the end posts 481 to have a greater width than the central posts 482.

[0109] Alternatively, the additional posts 483 can be retained and used to increase the difference in wettability between the assembly site and the surrounding area (as a complement to, or alternative to, a layer of hydrophobic material deposited on the surrounding area). For this purpose, the additional posts 483 must be formed to comply with given ranges of dimensions and spacing between two adjacent complementary posts, as illustrated in [Fig. 5]. The photosensitive resin pattern is then defined to meet these size and spacing ranges, and the thickness of the dielectric material is also defined to meet a defined height for the complementary posts. Preferably, the height H of the complementary posts 483 is between approximately 50 nm and 2 pm, the width A of the complementary posts is between approximately 0.5 pm and 1 pm, and the spacing B between two adjacent complementary posts is between approximately 0.5 pm and 2 pm.

[0110] After removing the additional motif 405, the electronic circuit 40 is obtained.

[0111] The self-assembly process described in connection with [Fig.3G] can be applied to first and second electronic circuits obtained by this other example of a manufacturing process.

[0112] Figures 6A and 6B are cross-sectional views illustrating another embodiment which differs from the process described in relation to Figures 3A to 3F mainly in the steps of forming the hydrophobic layer 35 and removing the complementary resin motif 305. This is based on the structure obtained in [Fig. 3D].

[0113] As illustrated in [Fig. 6A], a layer 350 of hydrophobic material is formed on this structure. Unlike the previous embodiment, this hydrophobic layer 350 has a thickness greater than that of the protrusion of the assembly site 31 so as to cover it.

[0114] The hydrophobic layer 350 typically has a thickness of between approximately 300 nm and 3 pm. It can be formed using techniques similar to those described in relation to the hydrophobic layer 35 of [Fig. 3E] and can be made of the same materials.

[0115] The step of removing the complementary photosensitive resin motif 305, which forms the structure illustrated in [Fig. 6B], is preferably carried out by dry etching, preferably at least partially selective with respect to the metallic material of the conductive pads 34, optionally followed by a liquid chemistry step to remove the photosensitive resin residues. Such a removal step is implemented to etch both the hydrophobic material and the resin. The dry etching may be a plasma etching, in particular a nitrogen / hydrogen (N2 / H2) plasma.

[0116] Following this step of removing the complementary motif 305, the thickness of the hydrophobic layer 351 is reduced, for example to between approximately 100 and 400 nm, advantageously between approximately 10 nm and 40 nm.

[0117] The electronic circuit 30 obtained, illustrated in [Fig.6B], is substantially similar to the electronic circuit illustrated in [Fig.3F].

[0118] This alternative manufacturing process ensures that a sufficient layer of A hydrophobic material is formed over the entire peripheral zone 39 surrounding the assembly site 31, including the lateral edges of the assembly site 31, despite the presence of the overhang of the complementary resin motif 305. Furthermore, such a thickness of hydrophobic material allows for a greater margin in its consumption during the various process steps that could degrade it. This makes it possible to combine several surface treatments or to apply longer processing times, particularly to increase the wettability of the assembly site.

[0119] Figures 7A to 7D are cross-sectional views illustrating another embodiment. It differs from the previous methods in that it allows for the formation of a multi-level assembly site. This makes it possible to increase the height of the assembly site and promote the confinement of a liquid droplet on said site during the self-assembly of two electronic circuits.

[0120] For this example, we start with the structure obtained in [Fig. 4B] (illustrated mode) or 3C (unillustrated mode). We thus have a support 52 and a first level 53 of assembly site 511 on the support 52, said first level having a substantially flat surface, said assembly site 511 of the first level 53 comprising first conductive pads 54 (from a first metallic layer 504) arranged between first insulating posts 581, 582 and forming the first level of the assembly site 51. First complementary posts 583 of dielectric material are arranged in the peripheral zone 59 of the assembly site.

[0121] As illustrated in [Fig.7A], a second etching stop layer 57' is placed on the structure. The process described in connection with Figures 3A to 3C or 4A and 4B is then repeated to create on the arrest layer 57' a second level 53' of assembly site 511', said second level having a substantially flat surface, said assembly site 511' of the second level 53' comprising second conductive studs 54' (from a second metallic layer 504') arranged between second insulating posts 582', 581', the second conductive studs 54' and the second insulating posts 581', 582' being located respectively substantially directly above the first conductive studs 54 and the first insulating posts 581, 582. The assembly site 511' of the second level 53' forms the second level of the assembly site 51.Second supplementary poles 583' made of dielectric material are arranged in the peripheral zone 59 of the assembly site, substantially opposite the first supplementary poles.

[0122] Figure 7B illustrates the formation of a complementary resin pattern 505 on the second level 511' of the assembly site 51. This pattern will serve as a mask for the etching of the second part 504B' of the second metallic layer 504' and a portion of a second barrier layer (not shown) as well as the second part 504B of the first metallic layer 504 and a portion of a first barrier layer (not shown) until it opens into the support 52.

[0123] It is possible at this stage to possibly remove the additional posts 583, 583' and / or to form a layer of hydrophobic material on the structure.

[0124] As illustrated in [Fig.7C], at the end of the step of removing the complementary motif 505, an electronic circuit 50 is obtained comprising a two-level assembly site 51 on a support 52.

[0125] The set of steps described in relation to [Fig.7A] can be repeated, as many times as necessary, before implementing the steps described in relation to [Fig.7B], in order to obtain an electronic circuit 50' with an assembly site 51' with more than two levels, as illustrated in [Fig.7D].

[0126] According to alternative embodiments, the steps of this other example of an embodiment process can be adapted to incorporate variants of the previous examples.

[0127] Figures 8A to 8D are cross-sectional views illustrating another embodiment, which differs mainly from the examples described above in that the assembly site, including the conductive pads, is formed not by etching an insulating layer, but by etching a metallic layer, the manufacturing process steps being adapted accordingly.

[0128] This other example of a manufacturing process is particularly suitable for forming conductive pads in aluminium (Al), but can also be implemented to form pads in another metal, for example in titanium (Ti) or tungsten (W), or in a metal alloy, for example an aluminium and copper-based alloy (AlCu), or in an aluminium and silicon alloy (AISi).

[0129] The starting structure comprises a support 62 having a substrate 621 coated with an initial layer of dielectric material 622. The support 62 is coated with an etching stop layer 67, itself coated with a metallic layer 604. The substrate is, for example, silicon (Si). The dielectric material is, for example, silicon dioxide (SiO2). The etching stop layer is, for example, silicon nitride (SixNy). The metallic layer can be deposited by a chemical vapor deposition technique, in particular by a plasma-enhanced chemical vapor deposition (PECVD) technique. It is, for example, aluminum. Its thickness is, for example, between 50 nm and 2 pm, for example, equal to 500 nm.

[0130] As illustrated in [Fig.8A], the metallic layer 604 is then structured by photolithography and etching to form trenches 606 in said metallic layer.

[0131] The etching of the metallic layer can be a dry or wet etching, for example an etching using a FeCl3 solution in the case of aluminum engraving.

[0132] Thus, the central part 604A of the metallic layer is formed into a plurality of conductive studs 64 between two trenches 606, and the peripheral area 604B of the metallic layer is not engraved.

[0133] The plurality of trenches 606 defines the contours of the future assembly site 61 of the electronic circuit 60, and the trenches 606 define the locations of the future insulating posts between two conductive pads 64, as described further below.

[0134] Thus, the contours of the assembly site and the edges (i.e. the locations and dimensions) of the conductive pads are defined during this photolithography step, i.e. with the same level of photolithography.

[0135] The following is then placed on the structure: - a complementary etching stop layer 67', for example of silicon nitride (SixNy), formed on the conductive pads 64, on the peripheral area 604B of the metallic layer, and in the trenches 606; and - a barrier layer 602 formed on the complementary etching stop layer 67'.

[0136] The barrier layer 602 comprises a material suitable for blocking the diffusion of the metallic material into the dielectric material that will be deposited subsequently. It is, for example, titanium nitride (TiN), possibly a bilayer with titanium (TiN / Ti) or a tantalum nitride and tantalum bilayer (TaN / Ta).

[0137] Figure 8B illustrates the formation of a layer of dielectric material 68 (insulating layer) on the barrier layer 602, in particular for filling trenches 606. The dielectric material is, for example, silicon dioxide (SiO2). The insulating layer can be deposited by chemical vapor deposition, in particular by PECVD. Its thickness must be greater than the depth of the trenches 606 in order to fill them; for example, it is between approximately 50 and 3 pm, for example, approximately 1 pm.

[0138] Fig. 8C illustrates the structure obtained after a further polishing step which removes an excess part of the insulating layer 68 so as to define a flat surface in which the dielectric material 68 in the trenches 606 is flush with the conductive pads 64. The polishing step consists for example of chemical mechano-polishing (CMP).

[0139] At the end of the polishing step, the structure obtained comprises an alternation of conductive pads 64 and insulating posts 680, defining the assembly site 61 of the electronic circuit 60, the conductive pads 64 and the insulating posts 680 being able to have equal or different dimensions respectively.

[0140] As illustrated in [Fig.8D], the peripheral zone 604B of the metallic layer located on either side of the assembly site is then removed 61 as well as to the residual portion 67B of the first etching stop layer 67 located under this peripheral area 604B. This removal is carried out by etching through a complementary pattern 605 in photosensitive resin formed on the upper surface 61S of the assembly site 61 by photolithography.

[0141] As described previously, the complementary motif 605 may extend slightly beyond the upper surface 61S of the assembly site 61.

[0142] The etching of the peripheral zone 604B of the metal layer is preferably a wet etching, for example using a chemical solution composed of phosphoric acid H3PO4, acetic acid, nitric acid (HNO3) and water (H2O).

[0143] The etching of the residual part 67B of the first etching stop layer 67 can be a wet etching, in particular using a chemical solution based on phosphoric acid H3PO4.

[0144] The manufacturing process may include variants described in connection with other processes (creation of a hydrophobic layer and / or additional posts in the peripheral area, multi-level assembly site ...).

[0145] The resulting electronic circuit 60 has a support 62 and an assembly site 61 on the support, the assembly site 61 comprising conductive pads 64 extending substantially vertically within the assembly site, two adjacent conductive pads being insulated by two insulating posts 680. The assembly site 61 is adapted to be assembled to another electronic circuit by a self-assembly process including a hybrid fastening step. The peripheral area 69 of the support 62 surrounding the assembly site 61 of the electronic circuit 60 may be coated with a layer of hydrophobic material and / or include additional posts.

[0146] For all embodiment examples, and more generally for an electronic circuit obtained by a manufacturing process according to an embodiment, the following dimensions may fall within the following ranges: - heights of insulating posts (or heights of conductive pads): 50 nm to 2 pm; - widths of insulating posts: 10 nm to 100 pm; - widths of the conductive pads: 10 nm to 100 pm; - thickness of the hydrophobic material layer: 1 nm to 2 pm.

[0147] For all embodiment examples: - the step(s) of forming the etching stop layer(s) may be omitted; or - the (first) etching stop layer can be formed between the substrate and the initial insulating layer; or - the (first) arrest layer can be formed on a level of the substrate, for example between two layers of substrate.

[0148] More generally, an etching stop layer can be disposed at a cor- corresponding to the desired engraving depth.

[0149] In some cases, the initial insulating layer may be omitted and / or the initial insulating layer and the (first) insulating layer may be a single insulating layer (single-layer or multi-layer structure).

[0150] Furthermore, for processes similar to the manufacturing processes described in relation to Figures 3 to 7, the insulating layer etching step may include or be followed by etching the initial insulating layer and / or etching the substrate to a given depth. Similarly, for processes similar to the manufacturing process described in relation to Figure 8, the metallic layer etching step may include or be followed by etching the initial insulating layer and / or etching at least a portion of the substrate. This is advantageous when a greater assembly site height is desired, particularly one exceeding 500 µm.

[0151] It is clear from all the embodiments, examples, and variants that the manufacturing process, by defining the contours of the assembly site and the edges (i.e., the locations and dimensions in at least one direction of the principal plane) of the conductive pads in a single photolithography level, avoids the risk of misalignment that exists when two photolithography levels are used to create, on the one hand, the edges of the conductive pads and, on the other hand, the contours of the assembly site. Thus, very good alignment of both the assembly sites and the conductive pads between two electronic circuits is ensured. Furthermore, this simplifies the formation of the assembly site.Furthermore, the process is easily adaptable, according to the desired electronic circuits, in particular according to the desired configurations of the assembly sites and / or the peripheral areas of said sites, which can be simply achieved by adapting the shape and dimensions of the pattern formed by photolithography (or patterns formed when there are several levels of assembly site).

[0152] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art. In particular: - the electronic circuit may include several assembly sites on its support, particularly when several other electronic circuits need to be assembled to the electronic circuit; - the markings in the insulating layer between the conductive pads can be omitted.

Claims

Demands

1. Method of manufacturing an electronic circuit (30, 40, 50, 50') extending along a principal plane (XY) and comprising: - a support (32, 42, 52), - an assembly site (31, 41, 51) on said support, said assembly site having a first surface (31S) protruding from said support intended to be assembled to an assembly site (31') of another electronic circuit (30') by a self-assembly process, and - a peripheral zone (39, 49, 59) around said assembly site; the assembly site (31, 41, 51) comprising at least one level (511, 511'), each level comprising conductive pads (34, 44, 54, 54') and insulating posts (380, 480, 580, 580') between the conductive pads, said conductive pads and said insulating posts being flush with said first surface of said assembly site; said manufacturing process comprising the formation of said at least one level of the assembly site; the contours, in at least one direction (X) of the principal plane (XY), of each level of the assembly site and the edges, in at least one direction (X), of the conductive pads and insulating posts of the same level being defined in a single photolithography step of said process; said photolithography step being adapted to form a resin pattern (301) dimensioned to form, after an etching step from a face of a structure covered by said pattern, said contours and said edges; training at least at one level of the assembly site including first-level (511) training comprising: - a step of forming an insulating layer (38, 48, 58) of a first dielectric material on a support (32, 42, 52); then - a photolithography step adapted to form a pattern (301) in resin on the insulating layer (38, 48, 58); then - an etching step from the face of the insulating layer (38, 48, 58) covered by the pattern (301) forming the etching mask, so as to form a plurality of trenches (306, 406) in said insulating layer separated from each other by insulating posts (380, 480, 580) of the first dielectric material; then a step of removing the pattern (301); then - a step of forming a conductive layer (304, 404, 504) in a first metallic material on the engraved face of the insulating layer (38, 48, 58) so as to at least fill the trenches, the first metallic material inserted into the trenches forming conductive studs (34, 44, 54) separated from each other by the insulating posts; then - a polishing step, for example mechanochemical, of the conductive layer (304, 404, 504), said polishing step being adapted to bring the conductive studs (34, 44, 54) flush with the insulating posts (380, 480, 580) of the engraved insulating layer, the conductive studs and the insulating posts defining the assembly site (31, 41, 51); the manufacturing process further comprising: - an additional step of engraving a part (304B, 404B, 504B) of the conductive layer (304, 404, 504) located on the peripheral area (39, 49, 59) through an additional pattern (305, 405, 505) in resin covering the assembly site (31, 41, 51);then a step of removing the complementary pattern, so that the assembly site (31, 41, 51) forms a protrusion in relation to the support (32, 42, 52).;

2. A manufacturing method according to claim 1, the resin pattern formed for each level (511, 511') of the assembly site (41, 51, 61) being dimensioned so that the insulating posts (480, 580, 580') comprise insulating posts (481, 581, 581') at the edges of the assembly site (41, 51) wider in at least one direction (X) of the principal plane (XY) than the insulating posts (482, 582, 582') located between said edges.

3. A manufacturing method according to claim 1 or 2, the resin pattern formed for at least the first level (511) of the assembly site (41, 51) being dimensioned to form on the peripheral area (49, 59) of the support (42, 52) additional posts (483, 583) in the insulating layer (48, 58).

4. Method according to claim 3, the additional posts (483) being configured to decrease the wettability of the peripheral area (49) relative to the wettability of the assembly site (41), for example the additional posts having a width (A) in a direction (X) of the main plane (XY) of between 0.5 pm and 1 pm, a height (H) of between 50 nm and 2 pm, and two adjacent additional posts being separated by a spacing (B) of between 0.5 pm and 2 pm in said direction.

5. A manufacturing method according to any one of claims 1 to 4, the first metallic material being copper or cobalt.

6. A manufacturing method according to any one of claims 1 to 5, the formation of the first level (511) of the assembly site (31, 41, 51) comprising, prior to the step of forming the insulating layer (38, 48, 58) in the first dielectric material, a step of forming an etching stop layer (37, 47, 57) on the support (32, 42, 52), for example a silicon nitride layer.

7. A manufacturing method according to any one of claims 1 to 6, wherein the steps of forming the first level (511) of the assembly site (51) are repeated at least once, before the additional etching step, so as to form another level (511') of the assembly site comprising other conductive pads (54') and other insulating posts (580'), said other conductive pads, respectively said other insulating posts, being arranged opposite the conductive pads, respectively the insulating posts, of the level of the assembly site previously formed; said method comprising, for example, a preliminary step of forming an etching stop layer (57') on the level of the assembly site previously formed.

8. A manufacturing method according to any one of claims 1 to 7, comprising a supplementary photolithography step adapted to form the supplementary pattern (305, 405, 505, 605) in resin, said supplementary pattern extending by a dimension for example between 1 nm and 1 pm, for example 300 nm, on either side of said assembly site above the peripheral area (39, 49, 59).

9. A manufacturing method according to any one of claims 1 to 8, the additional engraving step being wet engraving.

10. A manufacturing method according to any one of claims 1 to 9, comprising a step, subsequent to the additional etching step, of forming a layer (35), of thickness for example between 1 and 300 nm, of a hydrophobic material on the peripheral area (39), the hydrophobic material being for example a fluorinated material, preferably fluorocarbon.

11. A method for self-assembling a first electronic circuit (30) and a second electronic circuit (30'), the first and second electronic circuits being manufactured according to the manufacturing method of any one of claims 1 to 10, the self-assembly method comprising: - a step of depositing a drop of liquid onto the first surface (31S) of the assembly site (31) of the first electronic circuit (30); then - bringing the first surface of the assembly site (31') of the second electronic circuit (30') into contact with the first surface of the assembly site (31), coated with the drop of liquid, of the first electronic circuit (30); then - a fixing step, for example by hybrid molecular bonding or thermocompression, of the assembly site (31') of the second electronic circuit (30') to the assembly site (31) of the first electronic circuit (30).

12. Self-assembly method according to claim 11, the second electronic circuit (30') being cut to form an integrated circuit chip prior to the contact step, the first electronic circuit (30) being an integrated circuit board.

Images