Radio Frequency Switch
The described manufacturing process addresses the challenges of high RON resistance and capacity in radio frequency switches by forming specific layers and filling cavities, resulting in efficient operation at high frequencies with reduced leakage.
Patent Information
- Application Number
- FR2022000145
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2022-01-10
- Publication Date
- 2025-05-02
- Estimated Expiration
- 2042-01-10
AI Technical Summary
Existing radio frequency switches face challenges in achieving low RON resistance and intrinsic capacity, which are critical for rapid switching and minimizing leaks at high frequencies.
A manufacturing process involving the formation of a silicide layer, an insulating layer with a cavity, a metal layer in the cavity, and filling with a driver material, specifically designed to reduce RON resistance and capacity in radio frequency switches.
The process effectively reduces RON resistance and intrinsic capacity, enabling radio frequency switches to operate efficiently at frequencies greater than 100 MHz with reduced leakage when blocked.
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Abstract
Description
Title of the invention: Radio Frequency Switch Technical field
[0001] The present description relates generally to radio frequency switches and their manufacturing methods. Prior art
[0002] A switch is an electronic component or device that allows or does not allow the connection between two nodes of a circuit. A radio frequency switch is a switch adapted to switch, that is to say to alternate between the open and closed states, at a frequency included in the radio frequency range. Summary of the invention
[0003] One embodiment overcomes all or part of the drawbacks of known radio frequency switches.
[0004] One embodiment provides a method of manufacturing a device comprising a radio frequency switch, the method comprising:
[0005] the formation of a first silicide layer on a second conductive or semiconductive layer;
[0006] forming a third insulating layer on the first layer;
[0007] the formation in the third insulating layer of a cavity reaching the first silicide layer;
[0008] the formation of a fourth metal layer in the cavity in contact with the first silicide layer;
[0009] non-oxidizing annealing; and
[0010] filling the cavity with a conductive material.
[0011] According to one embodiment, the switch is a transistor.
[0012] According to one embodiment, the second conductive or semiconductive layer is one of the transistor drain region, the transistor source region, and the transistor gate.
[0013] According to one embodiment, the switch is capable of switching at a frequency greater than 100 MHz.
[0014] According to one embodiment, the fourth metal layer completely covers the walls and the bottom of the cavity.
[0015] According to one embodiment, the first silicide layer is made of an alloy of silicon and cobalt.
[0016] According to one embodiment, the fourth metal layer is made of titanium.
[0017] According to one embodiment, the conductive material is tungsten.
[0018] According to one embodiment, steps d and e are separated by the formation of a fifth conductive layer covering the fourth metal layer.
[0019] According to one embodiment, the fifth conductive layer is made of titanium nitride.
[0020] According to one embodiment, the annealing is carried out in nitrogen.
[0021] According to one embodiment, the duration of the annealing is between 30 seconds and 10 minutes.
[0022] According to one embodiment, the annealing is carried out at a temperature between 700°C and 800°C.
[0023] According to one embodiment, the annealing is carried out at a temperature substantially equal to 765°C for substantially 30 seconds. Brief description of the drawings
[0024] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:
[0025] [Fig.l] schematically represents an example of a device comprising a radio frequency switch;
[0026] [Fig.2] represents a device after a step of an embodiment of a method of manufacturing a device of the type of the device of [Fig.l];
[0027] [Fig. 3] represents a device after another step of an embodiment of a method of manufacturing a device of the type of the device of [Fig. 1]; and
[0028] [Fig. 4] shows a device after another step of an embodiment of a method for manufacturing a device of the type of the device of [Fig. 1]. Description of the embodiments
[0029] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.
[0030] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.
[0031] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.
[0032] In the following description, when referring to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.
[0033] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.
[0034] [Fig. 1] schematically represents at least partially an example of a device comprising a radio frequency switch 10. The device is for example a switch. The device comprises for example a plurality of switches such as the switch 10. The switch 10 is, in the example of [Fig. 1], a transistor, for example an insulated gate field effect transistor or MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
[0035] The transistor 10 is formed in a semiconductor substrate 12, for example made of silicon. The substrate 12 is for example a bulk substrate or a semiconductor on insulator (SOI or Semiconductor On Insulator) type substrate.
[0036] The substrate comprises a well 14 doped with a first conductivity type, for example P type. Regions 16 and 18, doped with a second conductivity type, for example N type, are formed in the well 14. The regions 16 and 18 are flush with an upper face of the substrate 12. The regions 16 and 18 constitute the source and drain regions of the transistor 10. The regions 16 and 18 are separated by a region 20 of the well 14 doped with the first conductivity type. The region 20 constitutes a channel region of the transistor 10.
[0037] The transistor 10 further comprises a gate 22, resting on the substrate. The gate 22 comprises for example an insulating layer, or gate insulator, in contact with the region 20 and a block of conductive material, for example polycrystalline silicon, resting on the gate insulator and being separated from the region 20 by the gate insulator.
[0038] Transistor 10 comprises spacers 24 covering the side walls of gate 22. The spacers partially cover regions 16 and 18.
[0039] The transistor 10 is covered by an insulating layer 26. The layer 26 is made of a dielectric material, for example silicon oxide or silicon nitride.
[0040] Layer 26 is crossed by vias, or contacts, 28. Regions 16, 18 and gate 22 are each in contact with a contact 28, so as to be able to receive a voltage. Contacts 28 make it possible to connect the different parts of the transistor, i.e. the gate, the drain and the source, to voltage application nodes.
[0041] Transistor 10 is a radio frequency switch. In other words, transistor 10 is capable of operating at a frequency in the radio frequency range. In other words, transistor 10 is capable of switching, i.e., alternating between the on and off states, at a frequency in the radio frequency range. By radio frequencies, we mean frequencies greater than 100 MHz, for example between between 100 MHz and 300 GHz, for example between 100 MHz and 10 GHz.
[0042] When operating a switch such as that of [Fig.l], the efficiency of the switch is conditioned by two operating criteria. One of these criteria is the intrinsic resistance Ron of the transistor 10. The other criterion is the intrinsic capacitance Coff of the transistor 10.
[0043] A low value of resistance Ron allows rapid switching of the switch. A low value of the capacitance Coff makes it possible to limit leakage when the transistor is blocked. In the case of a radio frequency switch, we therefore seek to form transistors having low values of these criteria. In particular, we seek to form transistors having a low resistance Ron so as to support a switching frequency in the radio frequency range.
[0044] Figures 2 to 4 represent preferably successive steps of a method of manufacturing a device of the type of the device of [Fig.l].
[0045] [Fig.2] represents a device after a step of an embodiment of a method of manufacturing a device of the type of the device of [Fig.l].
[0046] During this step, the switch 10 is formed. In other words, the substrate 12 is doped so as to obtain the source and drain regions 16, 18 and the channel region 20. In addition, the gate 22 is formed on the region 20. The spacers 24 are formed on the side walls of the gate 22.
[0047] Silicide layers 29 are then formed in the semiconductor or conductive materials, i.e. in regions 16, 18 and in gate 22. Layer 29 is for example an alloy of silicon and cobalt, for example CoSi2. In regions 16 and 18, the silicide layers 29 are located at the upper face of substrate 12. In other words, layers 29 are flush with the upper face of substrate 12. In gate 22, layer 29 is located at the upper face of the gate conductor, preferably made of polycrystalline silicon.
[0048] The formation of the silicide layers 29 comprises, for example, the deposition of a layer (not shown) comprising the chemical component present in the silicide with the silicon. For a silicide made of an alloy of silicon and cobalt, said layer is made of cobalt. Said layer preferably covers the entire structure, and in particular covers the regions 16 and 18 and the gate 22. The formation of the layers 29 then comprises an annealing process causing the cobalt to react with the silicon of the regions 16 and 18 and the polycrystalline silicon of the gate, so as to form the silicide layers 29. The layer (not shown) is then removed, for example by selective etching.
[0049] A protective layer 30 is then formed on the structure. The layer 30 is for example made of an electrically insulating material, for example silicon nitride. The layer 30 covers in particular the regions 16 and 18. The layer 30 also covers the gate 22 and the spacers 24, in particular the upper face of the gate 22.
[0050] Layer 26 is then formed on layer 30. Layer 26 covers in particular the portions of layer 30 located opposite regions 16 and 18 and grid 22.
[0051] Cavities 32 are formed in the layer 26, and in the layer 30, at the locations of the contacts 28. The cavities 32 pass through the layer 26 and the layer 30, from an upper face of the layer 26 to a lower face of the layer 30 in contact with the layer 29. Thus, the bottom of the cavities 32 is formed by portions of the layers 29. The cavities 32 therefore uncover the layer 29 at the locations of each contact 28.
[0052] [Fig. 3] represents a device after another step of an embodiment of a method of manufacturing a device of the type of the device of [Fig. 1].
[0053] During this step, a stack of layers 34, 36 is formed conformally on the walls and the bottom of the cavities 32. In other words, a layer 34 is formed conformally on the walls and the bottom of each cavity 32. The layer 34 is thus in contact with the side walls of each cavity 32 and with the portion of the layer 29 located at the bottom of each cavity 32. A layer 36 is then formed conformally on the layer 34 located in each cavity 32.
[0054] Layer 34 is a metal layer, preferably made of a material that reacts with the substrate when thermal energy is applied, for example titanium. Layer 36 is a conductive layer, for example a metal nitride layer, for example a titanium nitride layer. Preferably, layer 36 is an alloy comprising the material of layer 34.
[0055] The layers 34 and 36 are for example formed over the entire structure, the portions located outside the cavities 32 then being removed.
[0056] The step of [Fig. 3] then comprises a non-oxidizing annealing step. This annealing step causes a reaction between the layer 34 and the layer 29 of each cavity 32. In other words, the chemical elements of the silicide layer 29 and the metal layer 34 mix, which reduces the resistance between the layer 36 and the region on which the contact is located, i.e. the region 16, 18 or the gate 22.
[0057] The annealing step is a step of heating the device in a non-oxidizing gaseous environment. In other words, the space in which the device is located during annealing comprises only non-oxidizing gases, for example inert gases. For example, the annealing is carried out in an environment comprising only nitrogen.
[0058] The presence of an oxidizing gas during annealing would cause oxidation of layers 34 and 36 and increase the resistance between layer 36 and the region on which the contact is located.
[0059] Preferably, the annealing time is between 30 seconds and 10 minutes, for example between 30 seconds and 3 minutes. Annealing for a longer time would result in a significant risk of altering dopant concentrations in the substrate.
[0060] Preferably, the annealing temperature is between 700°C and 800°C. Annealing carried out at a higher temperature would lead to a significant risk of damaging the layer 26 and making it less insulating.
[0061] The annealing is for example carried out in nitrogen (N2), at a temperature substantially equal to 765°C and for a duration substantially equal to 30 seconds.
[0062] [Fig.4] represents a device after another step of an embodiment of a method of manufacturing a device of the type of the device of [Fig.l].
[0063] During this step, the cavities 32 are filled, preferably entirely, with a conductive material 38, for example a metal, for example tungsten.
[0064] As a variant, one or more contacts 28 may be formed by a different manufacturing method. Thus, at least a first contact among the contact facing the gate 22, the contact facing the drain and the contact facing the source is formed according to an embodiment described previously comprising the annealing step between the formation of the layer 36 and the filling of the cavity with the material 38, the other contact(s) being formed by a method not comprising said annealing. The other contact(s) are then preferably formed after the formation of the first contact(s).
[0065] An advantage of the described embodiments is that they make it possible to reduce the resistance Ron when the switch operates in radio frequency mode, i.e. when the switch switches at a frequency in the radio frequency range. The resistance Ron is not modified when the switch does not switch.
[0066] A surprising advantage of the described embodiments is that the Coff capacity is reduced.
[0067] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, although the switch depicted in the figures is a transistor and the embodiments are of particular interest for transistors, the described method can be used to form contacts of other elements of a radio frequency switch, for example, diodes, bipolar transistors, etc.
[0068] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.
Claims
Claims
1. A method of manufacturing a device comprising a radio frequency switch (10), the method comprising: a. forming a first silicide layer (29) on a second conductive or semiconductive layer (16, 18, 22); b. forming a third insulating layer (26) on the first layer (29); c. forming in the third insulating layer (26) a cavity (32) reaching the first silicide layer (29); d. forming a fourth metal layer (34) in the cavity (32) in contact with the first silicide layer (29); e. non-oxidative annealing for a period of between 30 seconds and 10 minutes and at a temperature of between 700°C and 800°C; and f. filling the cavity (32) with a conductive material (38).
2. The method of claim 1, wherein the switch (10) is a transistor.
3. The method of claim 2, wherein the second conductive or semiconductive layer is one of the drain region (16, 18) of the transistor, the source region (16, 18) of the transistor, and the gate (22) of the transistor.
4. A method according to any one of claims 1 to 3, wherein the switch (10) is capable of switching at a frequency greater than 100 MHz.
5. A method according to any one of claims 1 to 4, wherein the fourth metal layer (34) completely covers the walls and the bottom of the cavity (32).
6. A method according to any one of claims 1 to 5, wherein the first silicide layer (29) is made of an alloy of silicon and cobalt.
7. A method according to any one of claims 1 to 6, wherein the fourth metal layer (34) is titanium.
8. A method according to any one of claims 1 to 7, wherein the conductive material (38) is tungsten.
9. A method according to any one of claims 1 to 8, wherein steps d and e are separated by the formation of a fifth conductive layer (36) covering the fourth metal layer.
10. The method of claim 9, wherein the fifth conductive layer (36) is titanium nitride.
11. A method according to any one of claims 1 to 10, wherein the annealing is carried out in nitrogen.
12. A method according to any one of claims 1 to 11, wherein the annealing is carried out at a temperature substantially equal to 765°C for substantially 30 seconds.