Driver for insulated-gate transistor with delay time compensation circuit
A delay compensation circuit for power transistors addresses response delays by redirecting current through diodes and transistors, improving response times and reducing voltage/current variations, thus enhancing component reliability.
Patent Information
- Application Number
- FR2022001807
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2022-03-02
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2042-03-02
AI Technical Summary
Existing power electronics components experience delays in responding to commands due to charging and discharging processes, leading to excessive voltage and current variations that can damage the components.
A delay compensation circuit is introduced, comprising specific diodes, transistors, and capacitors to redirect current during the initialization and shutdown processes of power transistors, reducing delays without significantly altering voltage and current variations.
The solution effectively reduces delays in power transistor response times, enhancing component reliability and reducing electromagnetic disturbances while maintaining current and voltage variations within safe limits.
Smart Images
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Abstract
Description
Title of the invention: Driver for insulated gate transistor with delay time compensation circuit
[0001] The field of the invention is that of power electronic module controls for controlling the operation of power electronic components. In a known manner, power modules comprise electronic components handling high powers and therefore require particular attention in their design and monitoring during their lifetime and use.
[0002] More specifically, the invention relates to the control of power electronic components and to the management of the delay between a command issued by a driver of the power electronic component and the response of the power component with respect to the command issued.
[0003] In a known manner, the initialization of an opening of a power electronics component or the initialization of a closing of this power electronics component is not immediate following the emission of this command from the associated driver. Indeed, a power electronics component requires for example a certain duration in order to charge or discharge, or even in order to induce the necessary voltage at the gate of the power electronics component in accordance with the command emitted by the driver. Therefore, delays may be observed, linked for example to the charging or discharging of the power electronics component. A command from the driver also induces, for example by commanding an opening or a closing of the power electronics component, an increase or a decrease in the voltage and the current passing through the power electronics component.However, the resulting voltage and current variations are, at least partially, dependent on the time required for the power component to respond to the command given to it. Therefore, reducing the delay required for the power electronics component to respond to a driver command increases the variation in current and voltage experienced by the power electronics component. Too significant a variation in voltage and / or current can damage the power electrical component or even destroy it. Therefore, managing, and particularly compensating for, the delay of the power component following a command while having little or no impact on the variation in current and voltage experienced by the power component during initialization of the command is a major issue.
[0004] [Fig. 1] shows a power stage 2 comprising a driver 4 and a power transistor 6 driven by the driver 4. The power transistor 6 is a semi-conductor component conductor composed of three terminals: a collector c, an emitter e and a gate g connected to the driver 6. The power transistor 6 is an insulated gate bipolar transistor (IGBT). Alternatively, the power transistor 6 is a field-effect transistor (in English, metal oxide semiconductor field-effect transistor or MOSFET) and therefore comprises a drain, a source and a gate connected to the driver 4. Therefore, for a field-effect transistor, the drain can be assimilated to the collector c, the source can be assimilated to the emitter e. Generally, the management of the delays between the emission of the command from the driver 4 and the reaction, for example the initialization of an opening or a closing, of the power transistor 6 is not taken into consideration and only a resistance of the gate Rg is positioned between the driver 4 and the gate g of the power transistor 6.
[0005] It has thus been envisaged, as shown in [Fig.2], in order to reduce the increase in the voltage and the decrease in the current flowing through the power electronics component when the power transistor 6 opens for example, to position: - in derivation of the resistance of the gate Rg, a first passing diode DI as well as a first capacitor Cl, both in derivation, that is to say forming two separate electrical loops, one with respect to the other. By passing diode, we understand that the diode lets the current pass, when the anode of the diode faces the direction of the current, in the direction of the gate g of the power transistor 6. Indeed, the first capacitor Cl having to be charged, a large voltage difference is observable between the voltage at the control and the voltage at the first capacitor Cl.From then on, a current derived from the gate resistance Rg can be observed with a redirection of the current, coming from the driver, to the first capacitor Cl and to the first passing diode Dl. The current derived from the gate resistance Rg is effective until the first capacitor Cl is fully charged. From then on, the first capacitor Cl transforms into an open switch and the current derived disappears. - a second passing diode D2 in series with a second capacitor C2 connecting the collector c to the gate g of the power transistor 6. In addition, a second resistor R2 is positioned in derivation of the second passing diode D2.
[0006] It is also possible to reduce the decrease in voltage and the increase in current flowing through the power electronics component when the power transistor 6 is closed by exchanging the first pass diode D1 and the second pass diode D2 with blocking diodes, i.e. diodes preventing the current from flowing towards the gate g of the power transistor 6, when the cathode of the diode faces the direction of the current.
[0007] Nevertheless, these solutions have inherent delays in the first order, in the capacitive equivalent of the power transistor, linked to the opening and / or closing of the power electronics component.
[0008] Indeed, when opening or closing the power transistor, delays can be identified: - A delay tl between the opening command issued by the driver and the decrease in voltage at the collector of the power transistor Vc. - A delay t2 to observe the saturation of the insulated gate power transistor. - A delay t3 associated with the increase in the voltage at the gate Vg to reach the maximum value Vgmax imposed by the control of driver 4. - A delay t4 between the closing command issued by the driver and the increase in voltage at the collector of the power transistor Vc. - A delay t5 to observe the delay in desaturation of the power transistor. - A delay t6 associated with the reduction of the voltage at the gate Vg to reach the minimum value Vgmin imposed by the driver command 4. - A delay tf which represents the time required for the voltage at the collector Vc to decrease, i.e. the transition from a voltage equivalent to 90% of the maximum voltage at the collector Vcmax to a voltage equivalent to 10% of the maximum voltage at the collector Vcmax. - A delay tr which represents the time required for the increase of the voltage at the collector Vc, i.e. the passage from a voltage equivalent to 10% of the maximum voltage at the collector Vcmax to a voltage equivalent to 90% of the maximum voltage at the collector Vcmax.
[0009] The delays t1, t2, t3, t4, t5, t6 are represented in [Fig.7].
[0010] Thus, during an initialization of an opening of the power transistor, the delays t1, tf, t2 and t3 follow one another, significantly increasing the time required to initialize the opening of the power transistor. Similarly, the delays t4, t5, tr and t6 also follow one another during the closing of the power transistor.
[0011] The invention aims to overcome all or part of the problems mentioned above by proposing a device for compensating for the pure delays linked to the initialization of the power transistor in response to a command from the driver which also has the advantage of not modifying and / or inducing a rapid voltage and / or current variation which could degrade the power transistor. More precisely, the invention makes it possible to reduce the delays t1, t2, t3, t4, t5 and t6 without impacting the delays tf and tr, making it possible to maintain the same voltage and current variations and not to increase electromagnetic disturbances.
[0012]
[0013]
[0014]
[0015] For this purpose, the subject of the invention is a power stage comprising a power transistor and a driver, the power transistor comprising a collector, a gate and an emitter, the power transistor being configured to switch from a so-called saturated state to a so-called blocked state and vice versa according to a command from the driver, the power stage comprising a resistor Rg positioned between the driver and the gate of the power transistor, the power stage comprising a delay compensation circuit positioned in derivation of the resistor Rg, the delay compensation circuit comprising: - a conduction initialization delay compensation circuit, configured to derive the current from the resistance Rg during an initialization of a saturation of the power transistor, - a conduction stop initialization delay compensation circuit, configured to derive the current from the resistance Rg during an initialization of a blocking of the power transistor, - a delay compensation circuit configured to divert the current from the resistor Rg when the power transistor is close to the saturated state. According to one aspect of the invention, the conduction initialization delay compensation circuit comprises: - A first signal diode configured to receive a control signal from the driver through its anode, - A first signal transistor connected to the cathode of the signal diode via an emitter of the first signal transistor, the signal transistor comprising a base and a collector connected to the gate of the power transistor, - A first resistor, connected to the emitter of the first signal transistor and to the base of the first signal transistor, - A first signal capacitor connected to the base of the first signal transistor and to the gate of the power transistor. According to one aspect of the invention, the first signal transistor is a PNP bipolar transistor. According to one aspect of the invention, the first signal transistor is a P-channel MOSFET transistor.
[0016] According to one aspect of the invention, the conduction shutdown initialization delay compensation circuit comprises: - A second signal transistor connected to the gate of the power transistor via a collector of the second signal transistor, the second signal transistor comprising a base and an emitter, - A second signal diode connected by its cathode to the driver and by its anode to the emitter of the second signal transistor, - A second resistor, connected to the emitter of the second signal transistor and to the base of the second signal transistor, - A second signal capacitor connected to the gate of the power transistor and to the base of the second signal transistor.
[0017] According to one aspect of the invention, the second power transistor is an NPN bipolar transistor.
[0018] According to one aspect of the invention, the second power transistor is an N-channel MOSFET transistor.
[0019] According to one aspect of the invention, the circuit for compensating for delays linked to the charging and / or discharging of the power transistor comprises: - A third signal diode configured to receive a control signal from the driver through its anode, - A third signal transistor connected to the cathode of the third signal diode via an emitter of the third power transistor, the third signal transistor comprising a base and a collector connected to the gate of the power transistor, - A third resistor connected to the base of the third signal transistor and to the emitter of the third signal transistor, - A diode connected by its cathode to the collector of the power transistor and by its anode to the base of the third signal transistor via a third signal capacitor and a fourth resistor, the third signal capacitor and the fourth resistor being positioned in shunt relation to each other.
[0020] The invention will be better understood and other advantages will appear on reading the detailed description of an embodiment given by way of example, a description illustrated by the attached drawing in which:
[0021] [Fig. 1] [Fig. 1] represents a power stage comprising a driver and a power transistor according to the state of the art;
[0022] [Fig.2] [Fig.2] represents the power stage comprising the driver, the transistor of power and a regulation circuit at the opening of the power transistor according to the state of the art;
[0023] [Fig.3] [Fig.3] represents a power stage comprising a driver, a transistor power and a delay compensation circuit linked to the initialization of the power transistor according to the invention;
[0024] [Fig.4] [Fig.4] represents an architecture of a delay compensation circuit initialization of conduction of the delay compensation circuit of the power transistor according to the invention;
[0025] [Fig.5] [Fig.5] represents an architecture of a delay compensation circuit configured to derive the current from the resistor Rg when the power transistor is close to the saturated state;
[0026] [Fig.6] [Fig.6] represents an architecture of a circuit for compensating for conduction stop initialization delays of the power transistor delay compensation circuit according to the invention;
[0027] [Fig.7] [Fig.7] represents a timing diagram comparing the delays of a transistor power in response to a command according to the state of the art and the delays of a power transistor in response to a command according to the invention.
[0028] For the sake of clarity, the same elements will bear the same references in the different figures.
[0029] [Fig. 3] represents a power stage 20 according to the invention, comprising a power transistor 60 and a driver 40. The power transistor 60 is an insulated gate bipolar transistor comprising a collector c', an emitter e' and a gate g'. The power transistor 60 is configured to switch from a so-called saturated state to a so-called blocked state and vice versa according to a command from the driver 40. The power stage 20 also comprises a resistor Rg' positioned between the driver 40 and the gate g' of the power transistor 60.
[0030] The power stage 20 comprises a delay compensation circuit 80 positioned in derivation from the resistor Rg' comprising a conduction initialization delay compensation circuit 82, configured to derive the current from the resistor Rg' during an initialization of a saturation of the power transistor 60. The conduction initialization delay compensation circuit 82 thus makes it possible to limit the delay linked to the initialization of an opening of the power transistor 60 and precisely the delays t1 and / or t3.
[0031] The compensation circuit 80 also comprises a conduction stop initialization delay compensation circuit 84, configured to derive the current from the resistor Rg' during an initialization of a blocking of the power transistor 60. The conduction stop initialization delay compensation circuit 84 thus has the advantage of reducing the delay linked to the initialization of a closing of the power transistor 60 and precisely the delays t4 and / or t6. Furthermore, the conduction stop initialization delay compensation circuit 84 is positioned in bypass with respect to the conduction initialization delay compensation circuit 82.
[0032] In addition, the delay compensation circuit 80 comprises a delay compensation circuit 86 configured to divert the current from the resistor Rg' when the power transistor 60 is close to the saturated state, i.e. for a voltage lower than 10 Volts and reduce the delays t2 and / or t5. The delay compensation circuit 86 is also positioned in derivation from the delay compensation circuit conduction initialization circuit 82 and conduction stop initialization delay compensation circuit 84.
[0033] In order to limit the delay tl between the initialization at the opening of the power transistor of the driver control and the decrease in the voltage at the collector of the power transistor Vc and the delay t3 associated with the increase in the voltage at the gate Vg to reach the maximum value Vgmax imposed by the driver control 40, the conduction initialization delay compensation circuit comprises, as shown in [Fig.4]: - A first signal diode D10 configured to receive, by its anode, a control signal from the driver 40. The first signal diode D10 is conductive with respect to the direction of the current towards the gate g' of the power transistor 60.
[0034] The conduction initialization delay compensation circuit 82 comprises a first signal transistor T10 connected to the cathode of the first signal diode D10 via an emitter eTM of the first signal transistor T10. The signal transistor T10 also comprises a base bTi0 and a collector '-Vio connected to the gate g' of the power transistor 60.
[0035] The conduction initialization delay compensation circuit 82 also comprises a first resistor RIO, connected to the emitter of the first signal transistor T10 and to the base of the first signal transistor T10 and a first signal capacitor CIO connected to the base A / |O of the first signal transistor and to the gate g' of the power transistor 60.
[0036] The first diode D10 thus allows the circulation of current from the driver 40 in a single direction, towards the gate g' of the power transistor 60.
[0037] The first signal transistor T10 is a PNP bipolar transistor. Thus, the current from the driver 40 passes through the first signal diode D10 before going to the emitter erw of the first signal transistor T10. However, since the first signal capacitor CIO is discharged, a large voltage differential is observable between the armature of the first signal capacitor CIO facing the current in the direction of the current, i.e. in the direction of the gate g' of the power transistor 60, and the driver 40. From then on, the current is directed towards this armature of the capacitor CIO and thus passes through the emitter e™ and the base ^rio of the first signal transistor T10.
[0038] The current thus passes through the first signal transistor T10 and exits via the base bTW and the collector 6Vio in order to flow respectively towards the first signal capacitor CIO and towards the gate g' of the power transistor 60. However, as a reminder, the conduction initialization delay compensation circuit 82 is positioned in shunt with respect to the gate resistance Rg' as shown in [Fig.3], the initialization delay compensation circuit of conduction 82 thus allows a redirection of the current coming from the driver 40 so as to divert the current from the gate resistor Rg' during the charging of the first signal capacitor CIO. In addition, the equivalent resistance formed by the association of the gate resistor Rg' and the conduction initialization delay compensation circuit 82 has a current resistance lower than the sole resistance of the gate Rg' allowing more current to be supplied from the driver 40 to the power transistor 60. Therefore, the gate g' of the power transistor 60 receives more current from the driver 40 and thus allows an initialization of an opening of the power transistor in a reduced time compared to a configuration as shown in [Fig.l] and 2.
[0039] This current draw and redirection of the current towards the conduction initialization delay compensation circuit 82 and towards the gate g' of the power transistor 60 ceases once the first signal capacitor CIO is fully charged. In addition, we can observe that advantageously, when the first signal capacitor CIO is fully charged and the shunt current ceases, the voltage measured at the collector of the power transistor Vc is a voltage equivalent to 10% of the maximum voltage at the collector Vcmax. Thus, the power transistor is opened within a reduced time.
[0040] Furthermore, the first signal diode D10, the first signal transistor T10, the first resistor RIO and the first signal capacitor CIO are low-level components, i.e., simple electronic components on the market. As an indicative example, the first signal diode D10 is a 1A / 50V signal diode, the first signal transistor T10 is a 1A / 50V PNP bipolar signal transistor, the first resistor RIO is a 10kQ 1 / 4W 50V low-level resistor or the first signal capacitor CIO is a 1nF / 50V low-level capacitor. Thus, the conduction initialization delay compensation circuit 82 also has the advantage of being a simple circuit to implement.
[0041] Alternatively, the first signal transistor T10 is a P-channel MOSFET transistor. Therefore, the conduction initialization delay compensation circuit 82 is activated with an offset. Indeed, in the case of using a MOSFET field effect transistor, the operating range of this type of transistor is between 2 Volts and 20 Volts whereas a PNP bipolar transistor operates according to a voltage range defined between 0 Volts and 20 Volts. Therefore, it is necessary to operate with higher voltages between gate g' and emitter e'.
[0042] [Fig. 5] represents the delay compensation circuit 86 linked to the charging and / or discharging of the power transistor 60. The delay compensation circuit 86 comprises a third signal diode D30 configured to receive, by its anode, the control signal from the driver 40. Indeed, the delay compensation circuit 86 is positioned in shunt with respect to the conduction initialization delay compensation circuit 82 and with respect to the gate resistance Rg'.
[0043] The delay compensation circuit 86 comprises a third signal transistor T30 connected to the cathode of the third signal diode D30 via an emitter of the third signal transistor eT30. The third signal transistor T30 also comprises a base &r30 and a collector cr30 connected to the gate g' of the power transistor 60.
[0044] In addition, the delay compensation circuit 86 comprises a third resistor R30 connected to the base bT30 of the third signal transistor T30 and to the emitter er30 of the third signal transistor so as to be in shunt with respect to the emitter er30 of the third signal transistor T30 and a diode D connected, by its cathode, to the collector of the power transistor 60 and, by its anode, to the base bT30 of the third signal transistor T30 via a third signal capacitor C30 and a fourth resistor R40, the third signal capacitor C30 and the fourth resistor R40 being positioned in shunt with respect to each other.
[0045] Furthermore, the diode D makes it possible to inform when the power transistor 60 is in a state of saturation. Indeed, the physical characteristics of the diode D, stated below, allow the diode D to become conductive when the power transistor 60 is saturated. Therefore, the diode D being conductive, a current then flows between the base bT3ü of the third signal transistor T30 and the emitter er30 of the third signal transistor T30 making it possible to observe the derivation of the current with respect to the resistance Rg of the power transistor 60 and thus inducing a rapid increase in the voltage at the gate Vg, which is interpreted as a reduction in the delays t2' and t5' compared to the delays t2 and t5, as shown in [Fig.7].
[0046] Similar to [Fig.4], the third signal capacitor C30 allows a redirection of the current towards the third signal transistor T30 in order to divert the current from the gate resistor Rg' during saturation or desaturation of the power transistor 60.
[0047] More precisely, in response to the control signal provided by the driver 40, the voltage at the gate requires a minimum time in order to evolve, that is to say increase in the case of a command to observe the saturation of the power transistor or decrease in the case of a command to observe a desaturation of the power transistor. These times are represented by the delays t2, for the case of a saturation command of the power transistor, and t5, for the case of a desaturation command of the power transistor.
[0048] This current draw and redirection of the current towards the delay compensation circuit 86 and towards the gate g' of the power transistor 60 advantageously makes it possible to see the voltage increase, or decrease, more quickly at the gate g' of the power transistor 60 thus reducing the delays t2, or t5.
[0049] This current draw and redirection of the current towards the delay compensation circuit 86 and towards the gate g' of the power transistor 60 ceases once the third signal capacitor C30 is fully charged. Furthermore, we can observe that advantageously, when the third signal capacitor C30 is fully charged and the shunt current ceases, the voltage measured at the gate g' of the power transistor 60 is a voltage equivalent to the control signal from the driver 40. Thus, the saturation or desaturation of the power transistor, depending on the control provided by the driver 40, is produced in a shorter time.
[0050] Furthermore, the third signal diode D30, the third signal transistor T30, the third resistor R30, the fourth resistor R40 and the third signal capacitor C30 are low-level components, i.e., simple electronic components on the market. As an indicative example, the third signal diode D30 is a 1A / 50V signal diode, the third signal transistor T30 is a 1A / 50V PNP bipolar signal transistor, the third resistor R30 and the fourth resistor R40 are 10kQ 1 / 4W 50V low-level resistors or the third signal capacitor C30 is a lnF / 50V low-level capacitor. In a different manner, the diode D which is connected to the collector of the power transistor 60 must withstand higher voltages. Therefore, the diode D can be a 1A / 1000V fast diode.
[0051] Finally, in a similar manner to [Fig. 4], and in order to limit the delay t4 between the initialization to closing of the power transistor of the driver control and the increase in the voltage at the collector of the power transistor Vc and the delay t6 associated with the decrease in the voltage at the gate Vg to reach the minimum value Vgmin imposed by the control of the driver 40, the conduction stop initialization delay compensation circuit 84 comprises, as shown in [Fig. 6], a second signal diode D20, the cathode of which is connected to the driver 40, blocking with respect to the direction of the current towards the gate g' of the power transistor 60.
[0052] The conduction shutdown initialization delay compensation circuit 84 includes a second signal transistor T20 connected to the anode of the second signal diode D20 via an emitter eT20 of the second signal transistor T20. The second signal transistor T20 is an NPN bipolar transistor and also includes a base and a collector ct2q connected to the gate g' of the power transistor 60.
[0053] The conduction shutdown initialization delay compensation circuit 84 also includes a second resistor R20, connected to the emitter er2O of the second signal transistor T20 and to the base ^7-20 of the second signal transistor T20 and a second signal capacitor C20 connected to the base / Yzo of the second signal transistor T20 and to the gate g' of the power transistor 60.
[0054] Thus, when the driver 40 provides a conduction stop command, a voltage differential is observable between the voltage at the gate g' and the plates of the second signal capacitor C20. Therefore, this voltage difference allows the second signal capacitor C20 to charge, making it possible to reduce the time required to decrease the voltage at the gate g' of the power transistor 60, i.e. the delays t4 and t6.
[0055] Furthermore, the second signal diode D20, the second signal transistor T20, the second resistor R20 and the second signal capacitor C20 are low-level components, i.e., simple electronic components on the market. As an indicative example, the second signal diode D20 is a 1A / 50V signal diode, the second signal transistor T20 is a 1A / 50V NPN bipolar signal transistor, the second resistor R20 is a 10kQ 1 / 4W 50V low-level resistor or the second signal capacitor C20 is a 1nF / 50V low-level capacitor. Thus, the conduction stop initialization delay compensation circuit 84 also has the advantage of being a simple circuit to implement.
[0056] Alternatively, the second signal transistor T20 is an N-channel MOSFET transistor. Therefore, the conduction shutdown initialization delay compensation circuit 84 is activated with an offset. Indeed, as stated previously, in the case of using a MOSFET field effect transistor, the operating range of this type of transistor is between 2 Volts and 20 Volts whereas an NPN bipolar transistor operates according to a voltage range defined between 0 Volts and 20 Volts. Thus, it is necessary to operate with higher voltages between gate g' and emitter e'.
[0057] According to a variant, the first signal diode D10 and / or the second signal diode D20 and / or the third signal diode D30 are Schottky diodes or PN junction diodes or even PIN diodes.
[0058] In addition, the delay compensation circuit 80 has the advantage of making it possible to increase the switching frequency of the insulated gate power transistor 60 by reducing the delays t1, t2, t3, t4, t5 and t6.
[0059] The delay compensation circuit 80 also has the advantage of making it possible to reduce conduction losses by reducing the delays t2 and t5.
[0060] Finally, [Fig.7] represents a timing diagram comparing the delays of a power transistor in response to a command according to the state of the art and the delays of a power transistor in response to a command according to the invention. More precisely, the timing diagram presents an initialization of conduction of the power transistor submitted by a command from the driver followed by an initialization of a stop of conduction of the power transistor also subjected to a driver control signal, first according to the state of the art and then according to the invention.
[0061] Thus, the control signal Cde supplied by the driver 40 takes the form of a square wave signal whose high level induces an initialization of a conduction of the power transistor 60 and whose low signal induces an initialization of a stopping of the conduction of the power transistor. In response to this control signal Cde, the voltage Vg at the gate g' increases, in the case of an initialization of conduction, or decreases, in the case of a stopping of the conduction of the power transistor. These initializations induce, as stated previously, the delays t1, t2, t3, t4, t5, t6.However, as visible on the timing diagram, the delays tl, t2, t3, t4, t5, t6 representing the delay or time delay for the actions mentioned above, namely the initialization of conduction or the stopping of conduction of the power transistor, visible at the collector of the power transistor via the collector voltage Vc and the collector current le, for operation according to the state of the art are visually greater than the delays tl', t2', t3', t4', t5', t6' presenting the delays necessary for operation with the delay compensation circuit 80. .
[0062] Thus, as an indicative example, without compensation, the time required for the power transistor to turn on is equivalent to 456 nanoseconds and the time required for the power transistor to turn off is equivalent to 355 nanoseconds. Conversely, with the action of the delay compensation circuit 80, the time required for the power transistor to turn on is equivalent to 125 nanoseconds and the time required for the power transistor to turn off is equivalent to 106 nanoseconds, highlighting a reduction in the cumulative pure delays of approximately 580 nanoseconds.
Claims
Claims
1. Power stage (20) comprising a power transistor (60) and a driver (40), the power transistor (60) comprising a collector (c'), a gate (g') and an emitter (e'), the power transistor (60) being configured to switch from a so-called saturated state to a so-called blocked state and vice versa according to a command of the driver (40), the power stage (20) comprising a resistor Rg positioned between the driver (40) and the gate (g') of the power transistor (60), the power stage (20) comprising a delay compensation circuit (80) positioned in derivation of the resistor Rg, the delay compensation circuit (80) comprising: - a conduction initialization delay compensation circuit (82), configured to derive the current from the resistance Rg during an initialization of a saturation of the power transistor (60), - a conduction stop initialization delay compensation circuit (84), configured to derive the current from the resistance Rg during an initialization of a blocking of the power transistor (60), - a delay compensation circuit configured to divert the current from the resistance Rg when the power transistor is close to the saturated state (86), the conduction initialization delay compensation circuit (82) comprising: - A first signal diode (D10) configured to receive by its anode a control signal from the driver (40), - A first signal transistor (T 10) connected to the cathode of the signal diode (D10) via an emitter or source (eTW) of the first signal transistor (T10), the signal transistor (T 10) comprising a base or gate ( &rio), and a collector or drain (ct 1 o) connected to the gate (g') of the power transistor (60), - A first resistor (RIO), connected to the emitter or source (eno) of the first signal transistor (T 10), and to the base or gate (^rio) of the first signal transistor (T10), A first signal capacitor (CIO) connected to the base or gate (&rio) of the first signal transistor (T 10), and to the gate (g') of the power transistor (60).
2. The power stage (20) of claim 1, wherein the first signal transistor (T 10) is a PNP bipolar transistor.
3. The power stage (20) of claim 1, wherein the first signal transistor (T 10) is a P-channel MOSFET transistor.
4. Power stage (20) according to one of claims 1 to 3, wherein the conduction stop initialization delay compensation circuit (84) comprises: - A second signal transistor (T20) connected to the gate (g') of the power transistor (60) via a collector or a Crap drain of the second signal transistor (T20), the second signal transistor (T20) comprising a base or a gate (^no) and an emitter or a source (eT20), - A second signal diode (D20) connected by its cathode to the driver (40) and by its anode to the emitter or the source (er20) of the second signal transistor (T20), - A second resistor (R20), connected to the emitter or the source (eT20) of the second signal transistor (T20) and to the base or the gate (^720) of the second signal transistor (T20),- A second signal capacitor (C20) connected to the gate (g') of the power transistor (60) and to the base or gate (^7-20) of the second signal transistor (T20).,
5. The power stage (20) of claim 4, wherein the second power transistor (T20) is an NPN bipolar transistor.
6. The power stage (20) of claim 4, wherein the second power transistor (T20) is an NT channel MOSFET transistor
7. IN. Power stage (20) according to one of claims 1 to 6, in which the circuit for compensating for delays linked to the charging and / or discharging of the power transistor (86) comprises: - A third signal diode (D30) configured to receive by its anode a control signal from the driver (40), A third signal transistor (T30) connected to the cathode of the third signal diode (D30) via an emitter (^ / 30) of the third signal transistor (T30), the third signal transistor (T30) comprising a base (bT3Q) and a collector (cr30) connected to the gate (g') of the power transistor (60), A third resistor (R30) connected to the base (bT30) of the third signal transistor (T30) and to the emitter (eT30) of the third signal transistor (T30), A diode (D) connected by its cathode to the collector (c') of the power transistor (60) and by its anode to the base (&7-30) of the third signal transistor (T30) via a third signal capacitor (C30) and a fourth resistor (R40), the third signal capacitor (C30) and the fourth resistor (R40) being positioned in shunt relation to each other.