Interconnection substrate and method for manufacturing such a substrate

Abstract

Interconnection substrate and method of manufacturing such a substrate This description relates to an interconnection substrate (300) comprising: - a thermomechanical support (310) through which at least one electrical interconnection hole (311) passes; - a first interconnection network (330a) on a first face (310a) of the support; and- a second interconnection network (330b) on a second face (310b) of the support; each interconnection network comprising:- at least one interconnection level, each interconnection level comprising at least one metallic track (331a, 333a, 331b, 333b) from which extends at least one metallic via (332a, 334a, 332b, 334b), the at least one metallic track and the at least one metallic via being embedded in a layer of insulation so that the at least one via is flush with the surface of said layer of insulation furthest from the support;and at least one metallic trace (335a, 335b) protruding from the insulation layer of the last interconnection level; the metallic vias being adapted to connect two adjacent levels and / or the last level with at least one protruding metallic trace. Figure for the abbreviation: Fig. 3;

Description

Description Title of the invention: Interconnecting substrate and method for fa- building of such a substrate technical field

[0001] — This description generally relates to electronic devices and more specifically an interconnection substrate suitable for maintaining and connecting electrical connecting an electronic component, for example an electronic chip, to a circuit electronic. Previous technique

[0002] — A substrate suitable for maintaining and integrating electrically into an electronic circuit An electronic chip is known, for example, by the term "IC substrate" in English, or integrated circuit substrate.

[0003] — An integrated circuit substrate can, in particular, be an intermediate product allowing the integration of one or more chips into a printed circuit board (PCB for "Printed") Circuit Board (in English). It generally includes an interconnection network electrical suitable for electrically connecting the chip(s) and the PCB.

[0004] — An example of an integrated circuit substrate may comprise several layers of me- Taliques forming metallic tracks isolated from each other at least partially by insulating layers, with the metal tracks at different levels being connected by metallic vias, said tracks and vias forming an interconnection network within the substrate.

[0005] — For many applications, for example, for RF applications (Radio Frequency), improvements to such a substrate can be sought, by for example, to improve its rigidity, strength and / or to allow flexibility in the dimensions and materials of said substrate, and in particular in the dimensions of the interconnection network. Summary of the invention

[0006] There is a need for an interconnecting substrate and a manufacturing process of such a substrate, which makes it possible to meet the improvement needs described above- previously.

[0007] One embodiment overcomes all or part of the drawbacks of known substrates.

[0008] One embodiment provides an interconnecting substrate comprising: - a thermomechanical support through which at least one interconnection hole passes electric; - a first interconnection network on one side of the support and electrically connected tricement at one end of at least one electrical interconnection hole; And - a second interconnection network on a second face of the support and electrically connected to the second end of at least one interconnection hole; each interconnection network comprising: - at least one interconnection level, each interconnection level comprising at least one metallic track from which extends at least one metallic via, the at least one metallic track and the at least one metallic via being embedded in a layer of insulation such that the at least one via is flush with the surface of said insulation layer furthest from the support; and - at least one protruding metallic trace on the insulating layer of the last interconnection level; the metal vias being suitable to electrically connect two adjacent levels and / or the top level with at least one protruding metal track. According to one embodiment, at least one track of the first level of each interconnection network is connected to one of the two ends of at least one electrical interconnection hole. One embodiment provides a method for manufacturing an interconnecting substrate, the method comprising: - the provision of a thermomechanical support through which at least one electrical interconnection hole passes; - the formation of at least one level of a first interconnection network on a first face of the support and at least one level of a second interconnection network on a second face of the support, such that the first interconnection network is electrically connected to a first end of at least one interconnection hole and the second interconnection network is electrically connected to the second end of at least one interconnection hole; the formation of each interconnection level comprising: the formation of at least one metallic track by metallization, the formation of at least one metallic via by column metallization from said at least one metallic track, then the encapsulation of said at least one metallic track and said at least one metallic via in a molding resin so as to form an insulating layer, said encapsulation being adapted to bring the at least one metallic via flush with the surface of said insulating layer furthest from the support; and - the formation of at least one protruding metallic track on the insulation layer of the last level of each interconnection network; the metal vias being suitable to electrically connect two adjacent levels and / or the top level with at least one protruding metal track. According to one embodiment, the coating process includes a molding step adapted to embed at least one metal track and at least one metal via, possibly followed by a polishing step of the insulation layer so as to make at least one metal via flush with the surface of said insulation layer furthest from the support. According to one embodiment, each of the first and second faces of the thermomechanical support is coated with a first germination layer, and the formation of the first level of each interconnection network comprises: - the formation of at least one first metallic track by selective metallization from the first germination layer; - the formation of at least one first metallic via by column metallization from said at least one first metallic track; - the removal of at least a portion of the first germination layer, for example by engraving; then - the coating of said at least one first metallic track and said at least one first metallic via in a molding resin so as to form a first layer of insulation. According to one embodiment, the process includes the formation of a second level of the first and / or second interconnection network, said formation comprising: - the formation of a second germination layer on the first insulating layer; - the formation of at least one second metallic track by selective metallization from the second germination layer; - the formation of at least one second metallic via by column metallization from said at least one second metallic track; - the removal of at least a portion of the second germination layer, for example by engraving; then - the coating of said at least one second metallic track and said at least one second metallic via in a molding resin so as to form a second layer of insulation. According to one embodiment, the process includes the formation of at least a third level of the first and / or second interconnection network, said formation including the reiteration of the previous steps. According to one embodiment, the formation of at least one interconnection level, for example the first level of the first and / or second interconnection network, further includes the formation of at least one metallization line adapted to ensure electrical continuity with the outside of the substrate for the metallization formation of a track and / or a metallic via. According to a particular embodiment, the process includes the formation of a second level of the first and / or second interconnection network, said formation comprising: - the formation of at least a second metallic track by selective metallization on the first layer of insulation; - the formation of at least one second metallic via by column metallization from said at least one second metallic track; then - the coating of said at least one second metallic track and said at least one second metallic via in a molding resin so as to form a second layer of insulation. For example, in this particular embodiment, each interconnection network thus formed includes, in its first level, a metallization line. According to a particular embodiment, the process includes at least a third level of the first and / or second interconnection network, said formation including the reiteration of the previous steps. According to one embodiment, metallization includes, for example, electrolytic deposition and / or growth. According to one embodiment, selective and / or column metallization is carried out through a pattern comprising at least one opening. The following embodiments may be applied to the substrate and / or the process. According to one embodiment, the first interconnection network and the second interconnection network have the same number of levels. According to one embodiment, the first interconnection network and the second interconnection network have different numbers of levels. According to one embodiment, the tracks and vias are made of copper, nickel, tungsten, or aluminum. According to one embodiment, the molding resin is an epoxy resin and / or a thermosetting resin, for example initially in powder, film or liquid form. Brief description of the drawings These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the attached figures, among which: [Fig.1] is a cross-sectional view of an example of a core-layered substrate; [Fig.2A] is a cross-sectional view of an example of a molded interconnect substrate assembled to a manufacturing support; Figure [Fig. 2B] is a cross-sectional view of an example of two interconnecting substrates. molded similar to the substrate of [Fig.2A], detached from the manufacturing support; [Fig.3] is a cross-sectional view representing a substrate according to one embodiment; [Fig.4A], [Fig.4B], [Fig.4C], [Fig.4D], [Fig.4E], [Fig.4F], [Fig.4G], [Fig.4H], [Fig.4I], [Fig.4J], [Fig.4K], [Fig.4L] and [Fig.4M] are cross-sectional views representing steps in an example of a substrate manufacturing process according to the embodiment of [Fig.3]; Figures [Fig. 5A], [Fig. 5B], [Fig. 5C], [Fig. 5D], [Fig. 5E] and [Fig. 5F] are cross-sectional views representing steps of another example of a substrate manufacturing process according to a different embodiment: [Fig.6] is a cross-sectional view illustrating a complementary step of a variant of a substrate manufacturing process according to another embodiment; Figure [Fig. 7] is a cross-sectional view representing a substrate according to another method of realization: [Fig.8] is a cross-sectional view representing an electronic circuit comprising a substrate according to one embodiment. Description of the implementation methods The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties. For clarity, only the steps and elements necessary for understanding the described embodiments have been shown and are detailed. In particular, the fabrication of the core is not detailed. Furthermore, an interconnection network may include other conductive lines besides the traces and vias described herein, in a manner known to those skilled in the art. Unless otherwise specified, when referring to two connected elements, this means directly connected without any intermediate elements other than conductors, and when referring to two coupled elements, this means that these two elements can be connected or linked through one or more other elements. In the description that follows, when referring to absolute positional qualifiers, such as the terms front”, back”, “top”, “bottom”, “left”, “right”, etc., or relative positional qualifiers, such as the terms “above”, “below”, “superior”, “inferior”, etc., or to orientational qualifiers, such as the terms “horizontal”, “vertical”, etc., unless otherwise specified, it refers to the orientation of the figures. In the description that follows, when referring to a “track” or “metallic track”, it refers broadly to any metallic imprint (“pattern”) (in English) substantially horizontal in an electrical interconnection network, which also includes vias, or metallic vias, substantially vertical to connect tracks together. A track may thus consist of, or be designated by, a narrow metallic pad (thin track, typically between 5 and 50 µm wide), a metal pad, and / or a metallic stud, for example a metallic stud under a via. When referring to a "selective" metal deposit or "selective" metallization, it refers to a localized metal deposit or localized metallization, usually through openings in a pattern, as opposed to a full (or continuous) metal deposit or full (or continuous) metallization. Unless otherwise specified, the expressions 'approximately', 'roughly', 'significantly', and 'on the order of' mean within 10%, preferably within 5%. An example of substrate 100, illustrated in [Fig.1], is a core laminate substrate. The substrate 100 is formed from a core 110. The core 110 is typically a layer of an organic material, for example, a pre-impregnated material or an epoxy resin, reinforced with fibers, for example, glass fibers. The core 110 has several through holes 111, the walls of each hole being coated with metal 112 and the hole filled with an insulating material 114, forming electrical interconnection holes. Each face of the core 110 is coated with a first metallic layer 131, generally a metal foil. The core is thus metallized on each of its faces. A stack of a first layer of insulation 121 surmounted by a second metallic layer 132 is deposited on each first metallic layer 131, i.e. on each metallized face of the core 110, then the stack is hot-rolled and / or under pressure. This stack is drilled, for example by laser or mechanical drilling, to form through holes 123, said holes then being filled with metal to form first metallic vias 133, allowing the metallic tracks (formed by the metallic layers) of two consecutive levels to be electrically connected to each other. A second layer of insulation 122 can be formed on each second metallic layer 132, usually surmounted by a third metallic layer (not shown), this new stack being laminated and then drilled to form through holes 124, said holes then being filled with metal to form second vias 134. Multiple stacks of metal and insulating layers, perforated with holes and filled with metal to form vias, can thus be formed on each face of the core. has represented two stacks on each face of the core in [Fig.1], but there could be only one stack on one and / or the other of the faces, or more than two. Each final metallic layer (the third in the example described) generally serves as a base for forming discontinuous metallic tracks 136 protruding from the upper surface 100a and the lower surface 100b of the substrate. These protruding metallic tracks 136 are generally formed by selective metal deposition ("pattern plating"), usually by depositing a resin pattern with openings onto each third metallic layer, and then depositing the metal through these openings. Generally, after removing the pattern, the third metallic layer is etched down to the second insulating layer 122 in the areas left empty by pattern removal, so as to eliminate the risk of short circuits. A layer of masking varnish 152 can then be formed on each face of the substrate to protect the protruding metal tracks 136. Each layer of varnish can subsequently be removed and / or partially etched to define access areas for the tracks 136. In one example, the metal is copper. The insulator is typically a pre-impregnated material or resin, for example, an epoxy resin. As an example, the insulator is an ABF resin (Ajinomoto Build-up Film). The core helps to stiffen the layered substrate, and thus, for example, to reduce the deformation and / or fragility of said substrate. However, this laminated substrate and its manufacturing process generally do not allow much flexibility in the shapes and dimensions of the vias, the thicknesses and widths of the metal tracks, and / or the spacing between the metal tracks. Furthermore, this laminated substrate requires the use of a significant amount of pre-impregnated material or resin, for example, ABF resin, and it is often not possible to use an alternative material in such a lamination manufacturing process. This makes the production of such a substrate dependent on a material that may be in high demand, resulting in an increase in the price of that material and therefore in the manufacturing cost of the substrate. Another example of substrate 200, 201 and a method for manufacturing such a substrate, illustrated in Figures 2A and 2B, is a molded interconnect substrate. The substrate 200, 201 is formed starting from a metallic support 210 having an upper face 210a and a lower face 210b. Continuous metallic tracks 231 and discontinuous tracks 232, 234 are formed from the support 210, either on one face 210a of the support 210 ([Fig.2A]), or on both faces 210a, 210b of the support 210 ([Fig.2B]), the metallic tracks being of two levels consecutive tracks are separated by a layer of resin insulation 220 traversed by metallic vias 233 allowing the tracks to be connected to each other. The tracks and vias together form a multi-level electrical interconnection network 230. On the lower face 200b, 201b of the substrate (the surface initially in contact with the support 210) and on the upper face 200a, 201a of the substrate, the metallic tracks 232, 234 formed are preferably discontinuous to avoid the risk of short circuits. For the lower face of the substrate, a thin, continuous metallic layer 240 is generally deposited on the support 210, forming an adhesion and germination layer; this layer is removed after detachment from the support. A metallic layer and / or a metallic track can be formed by a full-layer metallization technique, or continuous layer, ("panel plating") and / or by a selective metallization technique ("pattern plating"), for example through openings, or metallization zones, in a pattern formed by a photolithography technique. The metal vias are formed by a pillar plating technique, each via being formed from a metal track. Similar to selective metal plating, pillar plating can be carried out selectively through openings in a pattern formed by a photolithographic technique. A metallization technique may include, for example, electrolytic deposition (electroplating) and / or electroless deposition, allowing metal growth from a nucleation layer, in the presence of an electrical supply (electrolytic) or not (electroless). When a level of the interconnection network is formed (comprising the metal track(s) and the via(s)), a layer of resin 220 molds the track / via assembly. The molding resin layer thus formed can then be polished to bring each via 233 flush with the surface of said resin layer, possibly before forming another level of the interconnection network on said surface of said resin layer. For example, the metal for the tracks and the tack and germination layer is copper, and the molding resin is an epoxy resin. Next, each substrate 200, 201 is separated from the support 210, and the adhesion and germination layer 240 is removed, for example by etching, to avoid the risk of short circuit. This molded substrate and its manufacturing process allow more flexibility in the shapes and dimensions of the vias, in the thicknesses and dimensions of the metal tracks, and in the thicknesses of the insulating layers. Furthermore, this layered substrate allows the use of insulating materials other than Pre-impregnated material or ABF type resin. This allows you to choose a resin from among the molding resins, which may be more readily available and / or have other interesting properties (for example thermal, mechanical, electrical…). However, this substrate is less strong and / or less rigid than a core-laminated substrate, and may, for example, be more prone to deformation or even breakage, particularly with temperature changes. To prevent deformation or breakage, the substrate's dimensions are generally limited. The inventors propose a substrate and a manufacturing process for such a substrate that meets the improvement needs described above and overcomes all or part of the drawbacks of the substrates described previously. In particular, the inventors propose a substrate and a manufacturing process for such a substrate that stiffens and / or solidifies the substrate, for example, reducing the risk of deformation and / or breakage of said substrate, while allowing greater flexibility in the shapes and dimensions of the vias, the thicknesses and widths of the metal tracks, the spacing between the metal tracks, and the choice and dimensions of the insulating material. Embodiments of a substrate and examples of manufacturing processes for a substrate according to an embodiment will be described below. The embodiments described are not exhaustive, and various variations will become apparent to those skilled in the art based on the information provided in this description. One might speak of an interconnect substrate, for example, an integrated circuit substrate. Figures 3 to 7 are XZ cross-sectional views taken at a given elevation along the Y direction; therefore, not all vias are visible in these figures, as some vias are formed at a different elevation along the Y direction. Furthermore, although not visible in these figures, a person skilled in the art will understand that the tracks also extend along the Y direction for a certain length. Furthermore, when referring to a height or thickness, it refers to a dimension in the Z direction marked on the figures, and when referring to a width, it refers to a dimension in the X direction marked on the figures. The [Fig.3] is a cross-sectional view representing a substrate 300 according to a method of realization. The substrate 300 comprises a core 310 (thermomechanical support) having two opposing faces: an upper face 310a (first face) and a lower face 310b (second face). The core 310 may be a single layer or multilayer made of an organic material, for example a prepreg material or an epoxy resin, reinforced with fibers, for example glass fibers, a ceramic material, or a multilayer of prepreg and copper. The core 310 is pierced with several through holes 311 connecting its two opposite faces 310a, 310b. The lateral walls of each hole 311 are coated with a metallic covering 312 and the holes are filled with an insulating material 314, forming electrical interconnection holes through the core. On each face 310a, 310b of the core 310, the substrate 300 includes an electrical interconnection network 330a, 330b adapted to achieve electrical continuity between the core, in particular between the interconnection holes 311 of the core, and each of the upper 300a and lower 300b faces of the substrate, so as to achieve electrical continuity between said upper and lower faces of the substrate. Each interconnection network 330a, 330b comprises one or more interconnection levels (for example two levels N1, N2 identified in [Fig.4M]), each level comprising at least one substantially horizontal metallic track 331a, 333a, 331b, 333b from which extends at least one substantially vertical metallic via 332a, 334a, 332b, 334b, the track(s) / via(s) assembly of said level being embedded in a layer of molding resin insulation of a height suitable so that each via is flush with the free surface of the insulation layer, i.e. the thickness of the insulation layer of a level is substantially equal to the height of the vias, plus the thickness of the tracks, of the same level. In these embodiments, the first level of an interconnection network is considered to be the level closest to the core, and the last level is considered to be the level furthest from the core. Obviously, if there is only one level, the first level is the same as the last level. Similarly, the first track(s), the first via(s), and the first insulating layer correspond to the first level of an interconnection network, and the last track(s), the last via(s), and the last insulating layer correspond to the last level of an interconnection network. At least one first track of each interconnection network is connected, for example connected to the electrical interconnection holes 311 passing through the core 310. Each interconnection network 330a, 330b further includes, on the upper face 300a (first face) of the substrate or on the lower face 300b (second face) of the substrate, metallic tracks 335a, 335b protruding on the last layer of insulation formed 322a, 322b (visible in [Fig.4M]). In other words, the substrate 300 comprises, on each face 310a, 310b of the core 310, a stack 320a, 320b of at least one layer of molding resin insulator in which are embedded tracks and vias of an interconnection network 330a, 330b and on which are formed metallic tracks 335a, 335b protruding from the interconnection network 330a, 330b. The metallic vias of each interconnection network are configured to connect electrically two consecutive levels of interconnection and / or the last level of interconnection with said protruding metallic tracks. In the embodiment shown, the protruding metal tracks 335a, 335b are not embedded in resin, which allows, for example, the substrate to be electrically connected to another component and / or two components to be connected to each other via said substrate. Metallic tracks can be formed by a full-layer metallization technique (panel plating) and / or by a selective metallization technique (pattern plating), for example through openings, or metallization zones, in a pattern formed by a photolithography technique. Each metal via is formed by a pillar plating technique from a metal track forming a seed layer. As with selective metal plating, pillar plating can be carried out selectively through openings in a pattern formed by a photolithographic technique, generally a different pattern, with finer openings, than the pattern used for the metal track from which the via is formed. A metallization technique may include, for example, electrolytic deposition (electroplating) or electroless deposition, allowing metal growth from a nucleation layer, in the presence of an electrical supply (electrolytic) or not (electroless), or even include, for example, an additive manufacturing technique. The metal can be copper, nickel, tungsten, or even aluminum. The metallic tracks can have thicknesses ranging from approximately 10 to 100 micrometers. Metallic vias can have heights ranging from approximately 10 to 100 micrometers. The insulation layers can be formed using a molding technique for each level of an interconnection network (track(s) and via(s) of each level) with a suitable molding resin, in order to horizontally insulate the metal tracks from each other and vertically the vias from each other. The molding is optionally followed by polishing so that each via is flush with the free surface of the insulation layer; the entire molding / polishing process can be referred to as embedding. The molding resin can be an epoxy resin and / or a thermosetting resin. The molding resin may initially be in powder form for melting, as a film, or as a liquid, depending on the molding technique used. The substrate, according to one embodiment, and the manufacturing process of said substrate, make it possible to obtain a more rigid and solid substrate, due to the presence of the core maintained within said substrate, while allowing greater flexibility in the shapes and dimensions of vias, in the thicknesses and dimensions of metal tracks, and even in the thicknesses of insulating layers, due to the use of metallization and molding techniques. In addition, the substrate and the manufacturing process according to one embodiment allow the use of a resin chosen from molding resins as an insulating material, which allows for a wide choice of insulating materials, and can also give the substrate interesting properties (e.g. thermal, mechanical and / or electrical). In other words, the substrate and the manufacturing process according to a method of realization make it possible to combine the advantages of the two previously described techniques, of laminated substrate with core and of molded interconnect substrate, or at least to limit the disadvantages of each of the said techniques, by retaining the core for the strength and / or rigidity of the substrate, while taking advantage of the technique of the molded interconnect substrate. However, a difficulty with such a combination arises from the fact that the metallic adhesion and germination layer cannot be removed, unlike in the previously described molded interconnect substrate technique, where the support is detached from the substrate, and the substrate surface covered with this metallic adhesion and germination layer is then accessible so that it can be easily removed. The inventors therefore developed a manufacturing process adapted to form an interconnection network between the core and each lower and upper surface of the substrate, while avoiding the generation of a short circuit. Examples of manufacturing processes are given in the following description. These examples are described using copper as the metal example, bearing in mind that the manufacturing process can be adapted by a person skilled in the art for other metals. To avoid making this description too cumbersome, the steps for forming the interconnection network 330a on the upper face 310a of the core 310 (upper interconnection network, or first interconnection network) are primarily described. It should be noted that the steps for forming the interconnection network 330b on the lower face 310b of the core (lower interconnection network, or second interconnection network) are similar and can be carried out simultaneously with, or alternately with, those of the upper interconnection network. Those skilled in the art will be able to adapt the description for forming the lower electrical interconnection network 330b based on the information provided for the upper interconnection network 330a, also referring to the figures. Figures 4A to 4M are cross-sectional views representing steps in an example process for manufacturing a substrate 300 according to the embodiment of [Fig.3]. Figure 4A illustrates the initial structure, comprising a 310 core pierced with Several through holes 311. The side walls of each hole 311 are coated with a metallic coating 312, and the coated holes are filled with an insulating material 314, forming electrical interconnection holes through the core. In addition, each upper 310a and lower 310b face of the core is coated with a thin layer of copper 341a, 341b, forming a first adhesion and germination layer. In one example, the 310 core is supplied with the thin copper layers 341a and 341b. In another example, the 310 core is not supplied with the thin copper layers. In this case, the thin copper layers can be formed, for example, by laminating a copper foil to each face of the core, or by depositing an adhesion layer followed by a nucleation layer, for example, by electroless deposition. It is specified that, when referring to a layer in this description, it may be a single layer or a multilayer. To avoid making the rest of the description too long, when a germination layer is referred to, it can be a germination and attachment layer, generally a multilayer. For example, the first attachment and germination layer, as well as the attachment and germination layers described later in this description, have a thickness on the order of a micrometer. Figure [Fig. 4B] illustrates a structure obtained at the end of: - a first step of selective copper metallization ("Cu pattern plating") from the first germination layer 341a, for example through openings (metallization zones) in a pattern previously formed by a photolithography technique on said first germination layer, so as to form first copper tracks 331a; then - a first copper pillar plating stage, from each first copper 331a track (forming a germination layer), for example through openings (copper growth zones) in a pattern, so as to form first copper 332a vias. Selective copper metallization may include, or consist of, an electrolytic deposition / growth technique, which requires the nucleation layer to be connected to an electrical source. When selective metallization is performed using an aperture pattern, the apertures can, for example, be filled with an electrolytic bath. For instance, the electrolytic technique allows for thicknesses ranging from tens to hundreds of micrometers in a reasonable time. Alternatively, selective copper metallization may include, or consist of, an electroless deposition technique, in which case the nucleation layer is not necessarily connected to an electrical source. For example, the electroless technique makes it possible to obtain thicknesses on the order of a micrometer in a reasonable time. Copper column metallization may include, or consist of, an electrolytic deposition / growth technique. Similar to selective metallization, column metallization can be performed selectively through apertures in a pattern formed by a photolithography technique, typically a different pattern than the one formed to create the copper track from which the via is formed. Figure 4C illustrates a structure obtained after a first etching step of the first seed layer 341a. This etching is adapted to etch and remove the copper from said first seed layer without removing the copper from the first traces 331a and the first vias 332a. This is made possible, in particular, by the thinness of the seed layer. This etching step is, for example, a wet acid etch. Figure 4D illustrates a structure obtained after a first molding step of the first tracks 331a and the first vias 332a using a molding resin, thus forming a first insulating layer 32a on and around said first metal tracks and vias. The quantity of molding resin used must be sufficient so that the metal tracks and vias are embedded in said insulating resin layer. Thus, the thickness of the resin layer is greater than or equal to the height of the first level N1 of the network 330a. In the example shown, the thickness of the resin layer is greater than the height of the first level N1 of the network 330a. In other words, the first insulating layer 321a extends vertically beyond the first vias 332a. In the example considered, the molding stage involves pouring a powdered resin onto the tracks and vias, melting it, and then hardening it. In another example, the molding stage might involve laminating a resin film onto the tracks and vias, which is particularly well-suited to large structures. Yet another example might involve using a liquid thermosetting resin that is poured onto the tracks and vias and then hardened by heating. Figure 4E illustrates a structure obtained after a first polishing step of the first insulating layer 321a made of molding resin, such that the first vias 332a are flush with the polished surface of said first insulating layer. In one example, this polishing step employs mechanical and / or chemical polishing. This gives us a first level N1 of the 330a interconnection network. We can then form a second level N2 by reproducing the steps of figures 4A to 4E again, as described below in relation to figures 4F to 4. Figure 4F illustrates a structure obtained after a step of deposition of a second thin layer of copper 342a forming a second nucleation layer on the first insulating layer 32 la. This second germination layer can be formed by depositing an adhesion layer and then a germination layer, for example by electroless deposition. Figure 4G illustrates a structure obtained after a second step of selective copper metallization, starting from the second nucleation layer 342a to form second copper tracks 333a, similarly to the first step of selective copper metallization; and then a second step of copper column metallization from each second copper track 333a, to form second copper vias 334, similarly to the first step of copper column metallization. The second tracks 333a can be wider than the first tracks 331a, as shown, for example, in order to connect two first tracks together via first metal vias. Fig. 4H illustrates a structure obtained after a second etching step of the second germination layer 342a, similarly to the first etching step. Fig. 41 illustrates a structure obtained after a second molding step of the second tracks 333a and the second vias 334a using the molding resin, thus forming a second insulating layer 322a of resin, similarly to the first molding step. Fig. 4J illustrates a structure obtained after a second polishing step of the second 322a layer of molding resin, similarly to the first polishing step. This results in a second level N2 of the 330a interconnection network. Fig. 4K illustrates a structure obtained after a step of deposition of a third thin layer of copper 343a forming a third germination layer on the second insulating layer 322a, similarly to the step of deposition of the second germination layer 342a. Fig. 4L illustrates a structure obtained at the end of a third step of selective copper metallization from the third germination layer 343a so as to form third copper tracks 335a, similarly to the first step of selective metallization. Figure 4M illustrates a structure obtained after a third etching step of the third nucleation layer 343a, similar to the first etching step. The third copper tracks 335a protrude above the second insulator layer 322a and are not embedded in the molding resin. The structure obtained, visible in [Fig.4M], is similar to the structure of substrate 300 in [Fig.3]. Several structures can thus be manufactured simultaneously and similarly in The two directions of the XY plane, within a matrix of structures, can be used, in particular, to share electrical connections for electrolytic metallization. The matrix can be a panel. A panel can be cut into several strips. The panel or strips can be cut into several units, for example by cutting a strip or panel flush with each unit structure, as illustrated by the dashed arrows. Figures 5A to 5F are cross-sectional views representing steps of another example of a manufacturing process for a substrate 500 according to one embodiment. This other example of the process differs from the example in Figures 4A to 4M mainly in that no germination layer is deposited from the second level of interconnection, and in that metallization lines are formed at the edges of the structure at the same time as the copper tracks at the first level of interconnection. A metallization line is suitable for ensuring electrical continuity between a metallic nucleation layer (or a metallic track forming a nucleation layer) and an electrical source external to the structure, for example, when metallization is carried out by an electrolytic deposition / growth technique, and when there is no continuous nucleation layer extending to an edge of the structure to ensure such continuity. Within the same level and / or from one level to another, this electrical continuity can be supplemented by an arrangement of metallic tracks and / or metallic vias already formed within the structure and connected to at least one metallization line. We start from the same structure as that described in relation to [Fig. 4A]: the initial structure comprises a core 510 pierced with several through holes 511. The lateral walls of each hole 511 are coated with a metallic coating 512, and the coated holes are filled with an insulating material 514, forming electrical interconnection holes through the core. Each upper 510a and lower 510b face of the core is coated with a thin layer of copper 541a, 541b, forming an adhesion and germination layer. Fig. 5A illustrates a structure obtained after a first step of selective copper metallization on the upper face 510a of the core 510, so as to form first copper tracks 531a, as well as metallization lines 536a (“plating line”) at the edges of the structure. Figure 5B illustrates a structure obtained after a first copper column metallization step from each first track 531a, so as to form first copper vias 532a, similarly to the column metallization step described in relation to Figure 4B, and an etching step of the first nucleation layer 541a, similarly to the etching step described in relation to with the [Fig.4C]. Figure [5C] illustrates a structure obtained at the end of: - a first molding step of the first tracks 531a, the metallization lines 536a and the first vias 532a using a molding resin, thus forming a first insulating layer 521a on and around said first metal tracks, said metallization lines and said first vias, in a manner similar to the molding step described in relation to [Fig. 4D]; then - a first polishing step, similar to the polishing step described in relation to [Fig.4E]. This gives us a first level Nl of the 530a interconnection network. A second interconnection level N2 can then be formed by repeating the steps in Figures 5A to 5C, but without forming second metallization lines, as described below in relation to Figures SD and SE. According to one variant, second metallization lines can be formed at one or more edges of the structure, at the same time as the second copper tracks at the second interconnection level, for example if this is necessary to ensure electrical continuity for the electrolytic metallization formation of tracks and / or metallic vias of the second interconnection level. Fig. 5D illustrates a structure obtained after a second step of selective copper metallization on the first insulating layer 521a so as to form second copper tracks 533a, and then a second step of column metallization of copper from each second track 533a so as to form second copper vias 534a. Fig. 5E illustrates a structure obtained after a second molding step of the second tracks 533a and the second vias 534a using the molding resin, thus forming a second insulating layer 522a of resin, and then a second polishing step. This results in a second N2 level of the 530a interconnection network. It would thus be possible to implement more than two levels. Figure [Fig. 5F] illustrates a structure obtained after a third step of selective metallization of copper on the second insulating layer 522a so as to form third tracks 535a in copper. The third tracks 535a [form protrusions above the second layer of insulator 522a, and are not embedded in the molding resin, which allows for example to electrically connect the substrate with another component and / or to connect two components to each other via said substrate. This other example of a process makes it possible to do without certain germination layer etching steps. The resulting structure, visible in [Fig.5F], differs from the substrate 300 of [Fig.3] mainly by the presence of the metallization lines 536a, 536b. The presence of these metallization lines at the edges of the structure 500 can facilitate a finishing step of the substrate, for example a plating step of the upper and / or lower face of the structure, particularly in the case of nickel-gold plating by electrolytic metallization, by allowing electrical continuity. Several structures can thus be manufactured simultaneously and identically in both directions of the XY plane, for example, within a single panel. This allows, in particular, the sharing of electrical connections for electrolytic metallization. The panel can then be cut into several strips. The strips can be cut into several units. When cutting the structure into strips or units, these metallization lines can be eliminated by adapting the cutting width to the width of said lines, as illustrated by the arrows and the vertical dashed lines. Fig. 6 is a cross-sectional view illustrating a supplementary step of a variant of a manufacturing process for a substrate 600 according to one embodiment. This variant is described as a variant to the process in Figures 3A to 3M, but it can be applied to any other example of a manufacturing process, and more broadly to a manufacturing process according to a manufacturing method. It includes a further step, subsequent to the formation of the protruding metal tracks 335a, 335b, of forming a layer of solder mask 652a, 652b on the last layer of insulator 322a, 322b and on said protruding metal tracks, either on each of the upper 600a and lower 600b faces of the substrate 600 as shown, or on only one of these faces. This solder mask layer can subsequently be removed and / or partially etched to define access areas to certain protruding metal tracks. In Figures 3 to 6, the upper and lower interconnection networks are essentially symmetrical, notably having the same number of levels, but this configuration is not exhaustive. An example is given in [Fig. 7], which represents a 700 substrate in which the upper interconnection network 730a has a single NI level, while the lower interconnection network 730b has two NI levels, N2. Other configurations will become apparent to the person in the field. Figure 8 is a cross-sectional view of an electronic circuit 800 comprising an interconnect substrate 802, which may be selected from one of the substrates 300, 500, 600, 700 described previously, or more broadly be a substrate according to an embodiment. This shows an example of an assembly that can implement a substrate according to an embodiment. The 802 substrate forms an intermediate product that allows for the assembly of a chip of integrated circuit 804 to a printed circuit board 806 (PCB), using a flip chip assembly technique. Alternatively, the chip could be assembled using a wire bonding technique. The chip 804 is assembled to the substrate 802 via bosses 808 connecting pads formed in a contact surface of the chip 804 to pads formed in a contact surface of the substrate 802, for example the tracks 335a of the substrate 300 of [Fig.3]. The substrate 802 is assembled to the PCB 806 via bosses 810 connecting pads formed in one contact surface of the PCB 806 substrate to pads formed in another contact surface of the substrate 802, for example the tracks 335b of the substrate 300 of [Fig.3]. These two assemblies can be referred to in English by the terminology "Ball Grid Array" (BGA). The chip 804 can be encapsulated in a cover 812 assembled to the substrate 802, for example using an adhesive 814. Other components, for example a surface-mount type component 816, can be encapsulated and assembled to the substrate. Various embodiments and variations have been described. A person skilled in the art will understand that some features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art. Finally, the practical implementation of the described methods and variants is within the reach of the person in the trade, based on the functional indications given above.

Claims

Demands

1. Interconnection substrate (300; 500; 600; 700) comprising: - a thermomechanical support (310; 510) through which at least one hole passes electrical interconnection (311; 511); - a first interconnection network (330a; 530a; 730a) on a first face (310a; 510a) of the support and electrically connected to a the first end of at least one electrical interconnection hole; and - a second interconnection network (330b; 530b; 730b) on a second side (310b; 510b) of the support and electrically connected to the second end of at least one interconnection hole; each interconnection network comprising: - at least one level of interconnection, each level of interconnection including at least one metallic track (331a, 333a, 331b, 333b; 531a, 533a, 531b, 533b) from which extends at least one via me- Tallic (332a, 334a, 332b, 334b; 532a, 534a, 532b, 534b), the at least a metal track and at least one metal via being embedded in a layer of insulation (321a, 322a, 321b, 322b; 521a, 522a, 521b, 522b) so that at least one via is flush with the surface of said layer of the insulation furthest from the support; and - at least one metallic track (335a, 335b; 535a, 535b; 735a, 735b) protruding from the insulating layer (322a, 322b; 522a, 522b) of the final level of interconnection; the metal vias being suitable for electrically connecting two adjacent levels and / or the last level with at least one track me- protruding thallus.

2. Interconnecting substrate (300; 500; 600; 700) according to claim 1, in which at least one first-level track of each network The interconnection is connected to one of the two ends of at least one electrical interconnection hole.

3. Method for manufacturing an interconnect substrate (300; 500; 600; '700), the process comprising: - the supply of a thermomechanical support (310; 510) through which at least one electrical interconnection hole (311; 511); - the training of at least one level of a first network interconnection (330a; 530a; 730a) on a first face (310a; 510a) of the support and at least one level of a second network interconnection (330b; 530b; 730b) on a second side (310b; 510b) of the support, such that the first interconnection network be electrically connected to one end of at least one hole interconnection and that the second interconnection network is connected electrically at the second end of at least one hole interconnection; the formation of each level of interconnection including: the formation of at least one metallic track by metallization, the formation of at least one metallic via by column metallization at starting from said at least one metallic track, then the coating of said at least one metallic track and said at least one metallic via in a molding resin so as to form an insulating layer, said the coating being adapted to bring at least one metallic via to the surface surface of said insulating layer furthest from the support; and - the formation of at least one metallic track (335a, 335b; 535a, 535b; 735a, 735b) protruding from the insulating layer of the last level of each interconnection network; the metal vias being suitable for electrically connecting two adjacent levels and / or the last level with at least one track me- protruding thallus.

4. A method according to claim 3, wherein the coating comprises a molding step adapted to embed at least one metal track and the at least one metallic via, possibly followed by a step of polishing the insulating layer so that at least a metallic via on the surface of said outermost insulating layer support.

5. A method according to claim 3 or 4, wherein each of the first and the second face of the thermomechanical support is coated with a first germination layer (341a, 341b; 541a, 541b), and the first level (N1) training for each interconnection network understand : - the formation of at least one first metallic track (331a, 331b; 531a, 531b) by selective metallization from the first layer of germination; - the formation of at least one first metallic via (332a, 332b; 532a, 532b) by column metallization from said at least one first metallic track; - the removal of at least a portion of the first layer of ger- mination, for example by engraving; then - the coating of said at least a first metallic track and of said to minus a first metallic via in a molding resin in a way to form a first insulating layer (321a, 321b; 521a, 521b).

6. A method according to claim 5, comprising the formation of a second level of the first and / or second network interconnection, said training comprising: - the formation of a second germination layer (342a, 342b) on the first layer of insulation (321a, 321b); - the formation of at least one second metallic track (333a, 333b) by selective metallization from the second layer of ger- mination; - the formation of at least one second metallic via (334a, 334b) by column metallization from said at least a second track metallic; - the removal of at least a portion of the second layer of ger- mination, for example by engraving; then - the coating of said at least a second metallic track and said at least a second metallic via in a molding resin of in order to form a second layer of insulation (321a, 321b).

7. A method according to claim 6, comprising the formation of at least a third level of the first and / or second network interconnection, said training including the reiteration of the steps of claim 6.

8. A method according to any one of claims 3 to 7, wherein the formation of at least one level of interconnection, for example the first level of the first and / or second interconnection network, further includes the formation of at least one metallization line (536a, 536b) adapted to ensure electrical continuity with the outside of the substrate for the metallization formation of a track and / or a via metallic.

9. The method according to claim 8 in its dependence on claim- instruction 5, comprising the training of a second level of the first and / or the second interconnection network, said formation including: - the formation of at least one second metallic track (533a, 533b) by selective metallization on the first layer of insulation (521a, 521b); - the formation of at least one second metallic via (534a, 534b) by column metallization from said at least a second track metallic; then - the coating of said at least a second metallic track and said at least a second metallic via in a molding resin of in order to form a second layer of insulation (522a, 522b).

10. A method according to claim 9, comprising the formation of at least a third level of the first and / or second network interconnection, said training including the reiteration of the steps of claim 9.

11. A method according to any one of claims 3 to 10, wherein the Metallization includes, for example, a deposition and / or a electrolytic growth.

12. A method according to any one of claims 3 to 11, wherein the Selective and / or columnar metallization is achieved through a pattern including at least one opening.

13. Substrate according to claim 1 or 2, wherein the first network The interconnection network and the second interconnection network have the same number of levels.

14. | Substrate according to claim 1 or 2, wherein the first network interconnection and the second interconnection network have different quantities of levels.

15. Substrate according to any one of claims 1, 2, 13 and 14, in which the tracks and vias are made of copper, nickel, tungsten, or aluminum.

16. A method according to any one of claims 3 to 12, wherein the Molding resin is an epoxy resin and / or a thermosetting resin. can be cut, for example initially in powder, film or form liquid.