Programmable Read-Only Memory
The programmable read-only memory cell design with a thicker peripheral insulating layer and varying dopant concentrations addresses the issue of inconsistent breakdowns, ensuring reliable binary value storage by predicting the breakdown location.
Patent Information
- Application Number
- FR2022002466
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2022-03-21
- Publication Date
- 2024-12-20
- Estimated Expiration
- 2042-03-21
AI Technical Summary
Existing programmable read-only memories (PROM) suffer from variability in threshold values due to unpredictable breakdown locations in the insulating layer, leading to inconsistent binary value storage.
A programmable read-only memory cell design featuring a first insulating layer with a peripheral part thicker than a central part, and regions with varying dopant concentrations, ensuring predictable breakdown locations for reliable binary value storage.
The design allows for consistent and predictable breakdowns in the insulating layer, reducing variability in threshold values and enhancing the reliability of binary value storage.
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Abstract
Description
Title of the invention: Programmable read-only memory technical field
[0001] The present description relates generally to memory cells and more specifically to memory cells of the programmable read-only memory type. Previous technique
[0002] A programmable read-only memory (in English, PROM for Programmable Read Only Memory, or OTP for One Time Programmable) is a type of read-only memory that can be programmed only once.
[0003] There are several types of PROM memories, including a so-called fusible type corresponding to memory cells in which an insulating layer is damaged by an electrical breakdown. The memory cell therefore contains a first binary value when the insulator is not damaged and another binary value when the insulator is damaged. Summary of the invention
[0004] One embodiment overcomes all or part of the disadvantages of known programmable read-only memories.
[0005] One embodiment provides for a programmable read-only memory cell comprising a first insulating layer located between a semiconductor casing and a second conductive or semiconductor layer, the first insulating layer comprising a peripheral part and a central part, the peripheral part having a thickness greater than the thickness of the central part.
[0006] According to one embodiment, the box is in contact with the first layer and the second layer is in contact with the first layer.
[0007] According to one embodiment, the box and the second layer are not in contact.
[0008] According to one embodiment, the thicknesses of the central and peripheral parts of the first layer are substantially constant.
[0009] According to one embodiment, the thickness of the peripheral part of the first layer is at least one and a half times greater than the thickness of the central part of the first layer.
[0010] According to one embodiment, the box comprises first and second regions, the second region being more heavily doped than the first region, the central part being in contact with the second region.
[0011] According to one embodiment, the second region surrounds a portion of the first region, the central part resting solely on the second region and on said portion of the first region.
[0012] According to one embodiment, a peripheral portion of the second region is covered by the peripheral part.
[0013] According to one embodiment, the portion of the second region not covered by the central part is covered by the peripheral part.
[0014] According to one embodiment, the concentration of dopants in the second region is at least twice that of the first region.
[0015] According to one embodiment, the smallest dimension, in the plane of the top face of the box, of the portion of the central part of the first layer located opposite the second region is at least equal to 0.5 pm.
[0016] According to one embodiment, the box comprises a third region, more heavily doped than the second region, surrounding the second region and comprising at least a portion not covered by the first layer.
[0017] According to one embodiment, the cell includes at least one conductive contact in contact with the third region.
[0018] According to one embodiment, the ratio between the width of the peripheral part and the central part is greater than or equal to 2.
[0019] According to one embodiment, the second layer only covers the first layer. Brief description of the drawings
[0020] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:
[0021] Figure 1 represents an embodiment of a memory cell of a programmable read-only memory; and
[0022] [Fig. 2] represents a view of the embodiment of [Fig. 1] in plane BB of [Fig. 1]; and
[0023] [Fig.3] is a view of the embodiment of [Fig.1] in the BB plane of [Fig.1]. Description of the implementation methods
[0024] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.
[0025] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.
[0026] Unless otherwise specified, when referring to two elements connected between them, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or linked via one or more other elements.
[0027] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.
[0028] Unless otherwise specified, the expressions "approximately", "about", "meaning" "Suitably" and "of the order of" mean to within 10%, preferably to within 5%.
[0029] Figure 1 represents an embodiment of a memory cell 10 of a programmable read-only memory. Figure 2 shows a view of the embodiment of Figure 1 along plane BB of Figure 1. Figure 1 is a cross-sectional view of the memory cell 10 of a programmable read-only memory along plane AA of Figure 2. Figure 3 is a view in plane CC of Figure 1.
[0030] The cell 10 is formed in and on a box 12. The box 12 is made of a semiconductor material, for example silicon. The box 12 is doped with a first type of conductivity, for example type N. The box 12 is, for example, in a bulk substrate, for example doped with the same type of conductivity as the box 12. Alternatively, the box 12 is formed in a semiconductor-on-insulator (SOI) substrate.
[0031] The box 12 includes a region 14. Region 14 is a heavily doped region of the first type of conductivity. In other words, region 12 is doped with the same type of doping as the box 12. The height of region 14 is less than the height of the box 12. Region 14 is flush with an upper face of the box 12. Figure 3 shows a plan view of the upper face of the box 12. Region 14 is therefore visible there.
[0032] Region 14 rests on a region 16 of the chamber. Region 14 is more heavily doped than region 16. For example, the concentration of dopants in region 14 is at least ten times greater than the concentration of dopants in region 16. Region 14 is located throughout the periphery of the chamber 12. Region 14 therefore forms a closed contour.
[0033] The housing 12 includes a region 18. Region 18 is a doped region with the same type of conductivity as regions 14 and 16. Region 18 is more heavily doped than region 16, for example, at least twice as heavily doped. In other words, the concentration of dopants in region 18 is at least twice the concentration of dopants in region 16. Region 18 is, for example, less heavily doped than region 14.
[0034] Region 18 is flush with the upper face of the box 12. Region 18 has a thickness less than the thickness of region 14. Region 18 rests on region 16.
[0035] Region 18 is located inside the contour formed by region 14. Region 18 is thus surrounded by region 14. Region 18 is in lateral contact with region 14. For example, the contact, or interface, between regions 14 and 18 completely surrounds region 18.
[0036] Region 18, for example, surrounds a region 20. Region 20 is flush with the upper surface of the housing 12. Region 20 is a portion of region 16 and is preferably in contact with the portions of region 16 on which regions 14 and 18 rest. Region 20 is less heavily doped than regions 14 and 18. For example, region 20 is at least half as heavily doped as region 18. In other words, the dopant concentration of region 20 is lower, for example, at least half, than the dopant concentration of region 18. The dopant concentration of region 20 is, for example, substantially equal to the dopant concentration of the rest of region 16.
[0037] The memory cell 10 comprises an insulating layer 22, for example made of an oxide, for example silicon oxide. The layer 22 rests on the housing 12. The layer 22 completely covers the region 20. The layer 22 at least partially, preferably completely, covers the region 18. The layer 22 partially covers, for example, the region 14.
[0038] Layer 22 comprises a first part, or central part, 22a, and a second part, or peripheral part, 22b. Layer 22 preferably comprises only the first and second parts. The separation between parts 22a and 22b is shown by dashed lines in Figures 2 and 3. Part 22a is surrounded, preferably entirely, by part 22b in a plane parallel to the upper face of the box 12.
[0039] Part 22a has a thickness less than the thickness of part 22b. Preferably, the thickness of part 22b is at least one and a half times greater than the thickness of part 22a, for example, at least twice as great. The thickness of part 22a is preferably constant. Similarly, the thickness of part 22b is preferably constant.
[0040] Parts 22a and 22b preferably have a common, flat lower face. Said lower face is preferably in contact with the box 12. The upper faces of parts 22a and 22b, that is to say the faces opposite the lower face, are preferably parallel to each other.
[0041] Part 22a preferably completely covers region 20. Part 22a at least partially, preferably partially, covers region 18. Region 18 is, for example, in contact with a whole peripheral portion of part 22a, more closely precisely with the lower face of the peripheral portion of layer 22. Region 22b, for example, partially overlaps region 18. Region 22b, for example, completely overlaps the peripheral portion of region 18. Region 18, for example, is completely overlapped by part 22a and part 22b. Part 22a preferably rests only on regions 18 and 20. Part 22b, for example, partially overlaps region 14. Preferably, at least a portion of region 14 is not overlapped by layer 22.
[0042] Layer 22 is covered, preferably entirely, by a layer 24. Layer 24 is made of a conductive or semiconducting material, for example, polycrystalline silicon. Layer 24 preferably covers only layer 24. Thus, the lateral walls of layer 24 are, for example, coplanar with the lateral walls of layer 22, i.e., the lateral walls of part 22b. Layer 24 is, for example, in contact with the entire upper surface of layer 24. Layer 24 is separated from the box 12 by layer 22. Thus, layer 24 is not in contact with the box 12.
[0043] The cell 10 further comprises spacers 26 covering the lateral walls of layers 22 and 14. The spacers preferably cover all the lateral walls of layers 22 and 24. Preferably, at least a part of the region 14 is not covered by layer 22 or the spacers 26.
[0044] The cell 10 includes conductive vias, or contacts, 28. The region 14 is in contact with at least one via 28. In the example of Figures 1 to 3, the region 14 is in contact with two vias 28. The layer 24 is in contact with at least one via 28, for example a single via 28.
[0045] Preferably, the distance between two points of part 22b separated by part 22a is at least 1.5 pm. For example, the distance between two points of region 18 separated by part 20 is at least 0.5 pm. Thus, the smallest dimension, in the plane of the upper face of the box 12, of the portion of part 22a opposite region 18 is, for example, at least 0.5 pm. The ratio between the width of part 22b and the width of part 22a is, for example, greater than or equal to 2. In other words, the width of part 22b is at least twice the width of part 22a. The width of part 22b is understood to be the distance between the outer side wall of part 22b, i.e. the side wall furthest from part 22a, and the inner side wall, i.e. the interface between parts 22a and 22b.The width of part 22a is defined as the distance between two lateral walls of part 22a in the plane in which the width of part 22b is measured.
[0046] During a memory cell programming step, a current flows through the cell between layer 24 and region 14, passing through layer 22 and region 18. The current value is high enough to cause the cell to crack or break. the material of layer 22, that is to say, damage it, preferably only in one location. Thus, in said location, the material of layer 22 is no longer electrically insulating.
[0047] In order to determine the data stored by the cell, the resistance between layer 24 and region 14 is determined, for example. The memory cell is considered to store a first binary value if the resistance is high, for example above a threshold, which corresponds to the case where the material of layer 22 has not been cracked, and a second binary value if the resistance is low, for example below the threshold, which corresponds to the case where the material of layer 22 has been cracked.
[0048] In the embodiment shown in Figures 1 to 3, the break in the material of layer 22 appears in the portion of part 22a opposite region 18. Indeed, the break appears along the path most accessible to the current, that is, the path with the lowest resistance. The path through the portion of part 22a opposite region 20 has a higher resistance than the path through the portion of part 22a opposite region 18, region 20 being less doped than region 18. The path through the portion of part 22b opposite region 18 or region 14 has a higher resistance than the path through the portion of part 22a opposite region 18, part 22b being thicker than part 22a.
[0049] It is therefore possible to predict the location of the break. Moreover, the location is substantially in the same portion of layer 22 regardless of the memory cell.
[0050] One could have chosen to form a flat layer 22, that is, one having a constant thickness over its entire surface. However, it would not have been possible to predict the location of the break. The breaks could then be located in different places within the insulating layer, which would lead to variability from one cell to another in the threshold value between the first and second binary values.
[0051] Furthermore, during the cell manufacturing process, various steps can damage layer 22, and more specifically its periphery. For example, steps that can cause damage to layer 22 include substrate doping, spacer formation, layer 24 etching, etc. The damage caused is not identical in all memory cells. Thus, if layer 22 is a planar layer, breaks can occur in its periphery and lead to variations in the threshold value.
[0052] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to the person skilled in the art. craft. In particular, although regions 14, 18, 20 and layers 22, 24 have substantially rectangular shapes when viewed from above, it is understood that regions 14, 18, 20 and layers 22, 24 could have other shapes when viewed from above, for example circular, oval or quadrilateral shapes with rounded corners.
[0053] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.
Claims
Claims
1. A programmable read-only memory cell (10) comprising a first insulating layer (22) located between a semiconductor well (12) and a second conductive or semiconductor layer (24), the first insulating layer (22) comprising a peripheral portion (22b) and a central portion (22a), the peripheral portion (22b) having a thickness greater than the thickness of the central portion (22a), wherein the well (12) comprises first (16) and second (18) regions, the second region (18) being more heavily doped than the first region (16), the central portion (22a) being in contact with the second region (18).
2. The cell of claim 1, wherein the box (12) is in contact with the first layer (22) and the second layer (24) is in contact with the first layer (22).
3. Cell according to claim 1 or 2, in which the box (12) and the second layer (24) are not in contact.
4. Cell according to any one of claims 1 to 3, in which the thicknesses of the central (22a) and peripheral (22b) parts of the first layer (22) are substantially constant.
5. A cell according to any one of claims 1 to 4, wherein the thickness of the peripheral portion (22b) of the first layer (22) is at least one and a half times greater than the thickness of the central portion (22a) of the first layer (22).
6. Cell according to any one of claims 1 to 5, in which the second region (18) surrounds a portion (20) of the first region (16), the central part (22a) resting only on the second region (18) and on said portion (20) of the first region (16).
7. A cell according to any one of claims 1 to 6, wherein a peripheral portion of the second region (18) is covered by the peripheral portion (22b).
8. Cell according to any one of claims 1 to 7, in which the portion of the second region (18) not being covered by the central part (22a) is covered by the peripheral part (22b).
9. A cell according to any one of claims 1 to 8, wherein the dopant concentration of the second region (18) is at least twice that of the first region (16).
10. Cell according to any one of claims 1 to 9, in which the smallest dimension, in the plane of the upper face of the box (12), of the portion of the central part (22a) of the first layer (22) located opposite the second region (18) is at least equal to 0.5 pm.
11. Cell according to any one of claims 1 to 10, in which the box (12) comprises a third region (14), more heavily doped than the second region (18), surrounding the second region (18) and comprising at least one portion not covered by the first layer (22).
12. Cell according to claim 11, comprising at least one conductive contact (28) in contact with the third region (14).
13. Cell according to any one of claims 1 to 12, in which the ratio between the width of the peripheral part (22b) and the central part (22a) is greater than or equal to 2.
14. A cell according to any one of claims 1 to 13, wherein the second layer (24) only covers the first layer (22).