FLASH memory device

Abstract

FLASH Memory Device This description relates to a FLASH memory device (100) comprising: - a FLASH memory (104) including an array of non-volatile memory cells (208) and volatile memory (206); - a FLASH memory interface (106) arranged outside the FLASH memory (104); - a first communication bus (214) connecting the FLASH memory interface (106) and the memory cell array (208); and - a second communication bus (114) connecting the FLASH memory interface (106) and the volatile memory (206). Figure for the abbreviation: Fig. 2

Description

Title of the invention: FLASH memory device Technical field

[0001] This description relates generally to FLASH memory devices and their operating methods. Prior art

[0002] FLASH memories are rewritable semiconductor mass memories. They generally comprise an array of memory cells. FLASH memories can be implemented in a multitude of devices, such as memory cards, computers, smartphones or even vehicles. FLASH memories include operating programs, which may require modifications. Summary of the invention

[0003] There is a need to have devices comprising one or more FLASH memories whose operating programs can be modified.

[0004] One embodiment overcomes all or part of the drawbacks of known FLASH memories.

[0005] One embodiment provides a FLASH memory device comprising: - a FLASH memory comprising a matrix of non-volatile memory cells and a RAM memory; - a FLASH memory interface arranged outside the FLASH memory; - a first communication bus connecting the FLASH memory interface and the memory cell array; and - a second communication bus connecting the FLASH memory interface and the RAM memory.

[0006] One embodiment provides a method for accessing, in a FLASH memory device, FLASH memory using a FLASH memory interface arranged external to the FLASH memory, the FLASH memory comprising an array of non-volatile memory cells and a RAM memory, the method comprising: - accessing data stored in the memory cell array via a first communication bus connecting the FLASH memory interface and the memory cell array; and - access data stored in RAM memory via a second communication bus connecting the FLASH memory interface and RAM memory.

[0007] According to one embodiment, the memory cell array is configured to store at least one RAM memory configuration value and a program patch, the method comprising: obtaining, by the FLASH memory interface via the first bus, between a power-up and a boot procedure of the device, said RAM memory configuration value and, based on said RAM memory configuration value, obtain a program patch from the FLASH memory and load it into the RAM memory of the FLASH memory through the second communication bus.

[0008] According to one embodiment, the FLASH memory device further comprises a coupling module connecting output lines of a processing unit, external to the FLASH memory device, to access lines of said RAM memory of the FLASH memory.

[0009] According to one embodiment, the FLASH memory further comprises a non-volatile memory comprising a control program of a write / programming controller and / or comprising adjustment parameters of the memory cell matrix; the write / programming controller being configured to implement steps of programming, erasing and verifying data from the memory.

[0010] According to one embodiment, the coupling module further connects output lines of the processing unit to access lines of the non-volatile memory.

[0011] According to one embodiment, the FLASH memory interface comprises an interface for writing / reading data to be written to the memory cell array of the FLASH memory, or to be read from the memory cell array of the FLASH memory.

[0012] According to one embodiment, the second communication bus is a synchronous bus.

[0013] According to one embodiment, the FLASH memory further comprises at least one register storing a configuration value of the FLASH memory and / or storing adjustment parameters of the memory cell matrix.

[0014] According to one embodiment, the coupling module further connects output lines of the processing unit to access lines of said register.

[0015] According to one embodiment, the RAM memory configuration value and the program patch are stored in a control area of ​​the FLASH memory whose access is protected.

[0016] According to one embodiment, the FLASH memory interface comprises a finite state machine configured to manage the obtaining of the program patch as well as its restitution to the communication bus.

[0017] According to one embodiment, the FLASH memory interface comprises a module for translating virtual addresses into physical addresses.

[0018] According to one embodiment, the coupling module is a bus addressing matrix.

[0019] Another embodiment provides a FLASH memory device comprising: - a FLASH memory comprising: an array of non-volatile memory cells and a RAM memory; wherein the array of non-volatile memory cells is configured to store at least one RAM memory configuration value and a program patch; - a FLASH memory interface arranged outside the FLASH memory; - a communication bus between the FLASH memory interface and at least part of the FLASH memory; the FLASH memory interface being configured to: obtaining, between a power-up and a boot procedure of the device, said RAM memory configuration value; and depending on the RAM memory configuration value, obtain said program patch from FLASH memory and load it into said RAM memory via the communication bus.

[0020] Another embodiment provides a method of booting a FLASH memory comprising, a RAM memory, and an array of non-volatile memory cells configured to store at least one RAM memory configuration value and a program patch, the method comprising: obtaining, through a FLASH memory interface arranged outside the FLASH memory, between a power-up and a boot procedure of the device, said RAM memory configuration value and, based on said RAM memory configuration value, obtaining a program patch from the FLASH memory and loading it into the RAM memory of the FLASH memory through a communication bus between the FLASH memory interface and at least a portion of the FLASH memory.

[0021] According to one embodiment, the FLASH memory interface comprises a module for translating virtual addresses into physical addresses of the FLASH memory.

[0022] According to one embodiment, the FLASH memory interface comprises an interface for writing / reading data to be written to the memory cell array of the FLASH memory, or to be read from the memory cell array of the FLASH memory.

[0023] According to one embodiment, the communication bus is a synchronous bus.

[0024] According to one embodiment, the FLASH memory further comprises a memory non-volatile including a control program of a controller writing / programming controller, the writing / programming controller being configured to implement steps of programming, erasing and verifying data from the memory.

[0025] According to one embodiment, the FLASH memory further comprises at least one register storing a configuration value of the FLASH memory.

[0026] According to one embodiment, the RAM memory configuration value and the program patch are stored in a control area of ​​the FLASH memory whose access is protected.

[0027] According to one embodiment, the FLASH memory interface comprises a finite state machine configured to manage the obtaining of the program patch, as well as its restitution to the communication bus. Brief description of the drawings

[0028] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0029] [Fig.l] schematically represents an example of a FLASH memory device according to an embodiment of the present description;

[0030] [Fig.2] schematically represents a FLASH memory and a FLASH memory interface of [Fig.1] according to an embodiment of the present description;

[0031] Figure 3 schematically represents the FLASH memory and the interface of FLASH memory of [Fig.1] according to another embodiment of the present description;

[0032] [Fig.4] represents a method of starting the FLASH memory of [Fig.2] or 3;

[0033] Figure 5 represents an example of the implementation of a step in the process of the [Fig.4] ;

[0034] Figure 6 schematically represents an example of a memory device FLASH according to another embodiment of this description; and

[0035] [Fig.7] represents, in block form, an example of the implementation of a method for accessing the FLASH memory of the device in [Fig.6];

[0036] [Fig.8] represents, in the form of blocks, an example of implementation of a method of reading the FLASH memory of the device of [Fig.6];

[0037] [Fig.9] represents, in the form of a timing diagram, an example of implementation of a method for writing the FLASH memory of the device of [Fig.6]; and

[0038] [Fig. 10] represents, in the form of a timing diagram, an example of implementation of a method for reading the FLASH memory of the device of [Fig.6]. Description of the embodiments

[0039] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0040] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0041] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0042] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0043] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0044] [Fig.l] shows an exemplary FLASH memory device 100, comprising a FLASH memory 104 (FLASH MEMORY) in communication with a FLASH memory interface 106 (FLASH INTERFACE), and configured to write or read data to and from the FLASH memory 104.

[0045] The FLASH memory interface 106 is configured, for example, to provide in particular the management of writing and reading data to and from the FLASH memory 104.

[0046] The device 100 further comprises, for example, a processing unit 110 (CPU) comprising one or more processors under control of instructions stored in an instruction memory 112 (INSTR MEM). The instruction memory 112 is for example of the random access type (RAM). The processing unit 110 and the memory 112 communicate, for example, via a system bus 140. The FLASH memory 104 is, for example, connected to the system bus 140 via the FLASH memory interface 106 and via a communication bus 114 connecting the FLASH memory interface 106 to the FLASH memory 104. In one example, the device 100 further comprises an input / output interface 108 (I / O interface) connected to the system bus 140.

[0047] [Fig.2] schematically represents the FLASH memory 104 and the interface of FLASH memory 106 of [Fig.l] in more detail according to another embodiment of the present description.

[0048] According to the example of [Fig.2], the FLASH memory 104 comprises, for example, an array 208 of non-volatile memory cells. The FLASH memory 104 further comprises, for example, a volatile memory 206 (RAM), for example of the RAM type. The array 208 of non-volatile memory cells is for example configured to store a RAM memory configuration value 202 (CONFIGURATION BITS), this value being composed, for example, of one or more bits. The RAM memory configuration value 202, which may be in the form of one or more bits, indicates whether or not a program patch 204 (PATCH) of the FLASH memory is available to be applied. This patch 204 is, for example, stored in the array 208 of non-volatile memory cells.

[0049] The program patch 204 is, for example, a correction code for an operating program of the FLASH memory 104. The operating program of the FLASH memory 104 is, for example, stored in a non-volatile memory 212 (ROM) of the FLASH memory 104. The non-volatile memory 104 also comprises, for example, adjustment parameters of the memory cell matrix 208. The patch 204 makes it possible, for example, to modify the execution of the operating program of the FLASH memory 104. According to one example, the patch 204 is stored on several rows or columns of the memory cell matrix.

[0050] In an example not shown, the configuration value 202 and / or the program patch 204 are stored in one or more non-volatile registers of FLASH memory 104 outside of the memory cell array 208.

[0051] The communication bus 114 allows data communication between the FLASH memory interface 106 and at least a portion of the FLASH memory 104. According to one example, the communication bus 114 is configured to be able to communicate with the RAM memory 206. According to one example, the communication bus 114 is a synchronous bus, which allows ease of implementation. According to another embodiment, the communication bus 114 is of the asynchronous type. The bus comprises, for example, selection signals (SEL) and / or signals for activating the writing of data (WEN) in the FLASH memory 104 and / or signals (ADD) containing a physical address of the FLASH memory 104 and / or data input and output signals (DIN / DOUT) and / or clock signals (HCLK).

[0052] The FLASH memory interface 106 is, for example, arranged outside the FLASH memory 104. In this case, this makes it possible to design the memory interface 106 and the FLASH memory 104 differently. The FLASH memory interface 106 is, for example, part of a System On Chip (SOC).

[0053] According to the example of [Fig.2], the FLASH memory interface comprises, for example, a module for translating virtual addresses 232 (ADDRESS TRANSLATION MODULE) into physical addresses of the FLASH memory 104 and / or an interface 238 for writing / reading (W / R) data to be written to the array 208 of memory cells of the FLASH memory 104 and to be read from the array 208 of memory cells of the FLASH memory 104.

[0054] According to the example of [Fig.2], a general communication bus 214 implements, for example, the communication between the FLASH interface 106 and the FLASH memory 104 of data to be written, by the write / read interface 238, in the matrix 208 of non-volatile memory cells of the FLASH memory 106 and / or of data read, by the write / read interface 238, in the matrix 208 of non-volatile memory cells of the FLASH memory 106.

[0055] According to one example, the FLASH memory interface 106 is configured to retrieve the program patch 204 from the FLASH memory 104. According to one example, the retrieval of the patch 204 is obtained after the FLASH memory interface has read and interpreted the configuration value 202 stored in the FLASH memory 104. The FLASH memory interface 106 is, for example, further configured to load, into the RAM memory 206 of the FLASH memory 104, the patch 204 via the communication bus 114.

[0056] According to one example, the FLASH memory interface is configured to obtain the RAM memory configuration value 202 between a power-up (POWER UP) and a boot procedure of the device 100 (BOOT), and before the boot of said FLASH memory. This makes it possible to apply the patch 204 before the FLASH memory 104 starts its operating program.

[0057] According to the example of [Fig.2], the configuration value 202 and the patch 204 are, for example, stored in a control area 210 of the FLASH memory which is an area reserved for storing configuration parameters and access to which is protected, access being permitted for example only to profiles having administrator rights.

[0058] [Fig.3] schematically represents the FLASH memory 104 and the interface of FLASH memory 106 of [Fig.l] according to another embodiment of the present description.

[0059] In the example of [Fig. 3], the memory cell matrix, the program patch, the configuration value, the RAM and ROM memories, and the FLASH memory control area are, for example, similar to those described in relation to [Fig. 2]. In the example of [Fig. 3], the FLASH interface is, for example, similar to that described in relation to [Fig. 2], except that the FLASH memory interface also includes a finite state machine 330 (FSM). In the example of [Fig. 3], the communication buses 114 and 214 are, for example, similar to those of [Fig. 2].

[0060] In the example of [Fig. 3], a position counter 322 (COUNTER ROWS) is arranged in the memory cell array 208. In an example not shown, the position counter 322 of the memory cell array 208 is arranged outside the memory cell array 208. The position counter 322 tracks, for example, the last position of a memory cell column of the memory cell array 208 that has been refreshed, in particular the one that was refreshed last. The position counter 322 is used, for example, by a write / program controller 320 (PEC) configured to implement a control program stored in the non-volatile memory 212 ROM of the FLASH memory 104. The control program includes, for example, steps for programming, erasing and verifying memory data, such as an algorithm for programming / erasing the memory cells of the matrix 208.The algorithm determines, for example, the fastest and most qualitative way to program and / or erase the memory cells of the matrix 208. Verification steps are furthermore, for example, implemented by this algorithm. In one example, the control program composes in whole or in part the operating program of the FLASH memory 104.

[0061] According to the example of [Fig.3], the FLASH memory further comprises registers 324 (REGS) storing configuration values ​​of the FLASH memory 104 and / or storing adjustment parameters of the memory cell array 208. The registers 324 may further comprise, for example, redundancy information. The registers 324 are, for example, formed in particular with T-type flip-flops.

[0062] According to the example of [Fig.3], the finite state machine 330 (FSM) of the interface of FLASH memory 106 is configured to manage the obtaining of the program patch 204 from the FLASH memory 104, as well as its restitution to the RAM memory 206 via the communication bus 114. This makes it possible, for example, to retrieve the patch 204, without using software from the FLASH memory which would only be operational after the boot procedure of the device 100. This further makes it possible to provide the patch 204, also without using software from the FLASH memory which would only be operational after booting the device 100, to the RAM memory 206 of the FLASH memory 104, and this before the boot procedure of the device 100.

[0063] [Fig.4] shows a method of booting the FLASH memory of [Fig.2] or 3. This method is implemented, for example, by the FLASH memory interface 106.

[0064] In a step 402 (AFTER POWER UP AND BEFORE BOOT READ A DEDICATED FLASH CONFIGURATION BIT), the FLASH memory interface 106 comes, for example, to read the configuration value 202 from the FLASH memory. This step 402 takes place after power-up but before the boot procedure of the device 100 and the FLASH memory 104. This step can be implemented for example by the finite state machine 330.

[0065] In a step 404 (IS PATCH AVAILABLE?), the FLASH memory interface 106 determines, based on the configuration value 202, whether the patch 204 is available in the FLASH memory before its startup process. If yes (branch Y), then a step 406 (DUMP PATCH FROM FLASH MACRO) is performed. If no (branch N), then the process ends, for example, with an end-of-process step 410 (END).

[0066] During step 406, all or part of the patch 204 is retrieved by the FLASH memory interface 106, for example, via the finite state machine 330. The patch 204 is then, for example, stored within the FLASH memory interface 106.

[0067] Following step 406 (LOAD PATCH IN RAM), patch 204 is returned to communication bus 114, for example, with finite state machine 330. Communication bus 114 then communicates patch 204 to RAM 206 of FLASH memory 104. Patch 204 can then be implemented by FLASH memory 104 to correct or replace the control program stored in non-volatile memory 212 before its startup procedure begins.

[0068] [Fig.5] represents an example of implementation of step 406 of the method of [Fig.4],

[0069] In a step 506 (SET FIRST LINE OF THE PATCH), the patch 204 is scanned, for example, at the level of a part of the patch 204 corresponding to its first line.

[0070] In a subsequent step 508 (DUMP PATCH LINE FROM FLASH MACRO), for example, the portion of the patch 204 retrieved in step 506 is retrieved by the FLASH memory interface 106.

[0071] In a following step 510 (LOAD PATCH IN RAM), the part of the patch 204, recovered in step 508, is delivered to the communication bus 114 and stored in the RAM memory 206.

[0072] In a step 514 (END OF PATCH?), the FLASH memory interface determines whether the reading of the patch 204 is complete (Y branch) or whether there are other parts of the patch 204 to be read (N branch). In the case of the Y branch, step 410 is performed. In the case of the N branch, a step 512 (INCREMENT FLASH LINE) is implemented. In this step 512, another part of the patch 204 is read, for example by incrementing the markers corresponding to the lines of the patch 204. After step 512, steps 508, 510 and 514 are implemented again until reaching the reading, for example, the entire patch 204.

[0073] [Fig.6] schematically represents an example of a memory device FLASH 600 according to another embodiment of the present description.

[0074] In the example of [Fig. 6], the FLASH memory device 600 is similar, for example, to that of FIGS. 1, 2 and 3. In particular, several elements of the device 600 are the same as elements of the device 100 of FIGS. 1, 2 and 3, and these elements are referenced by the same references and will not be described again in detail.

[0075] The FLASH memory device 600 further comprises a coupling module 606 connecting output lines of the processing unit 110 to access lines of the FLASH memory interface 106. The connection provided by the coupling module 6060 allows, for example, access, by the processing unit 110, to the RAM memory 206 via the FLASH memory interface 106. In one example, the coupling module 606 comprises a bus addressing matrix, which takes as input a bus, for example of the AHB (Advanced High-performance Bus) type, comprising the output lines of the processing unit 110. The coupling module 606 comprises, for example, as output, an output bus 604, for example of the AHB type, connected to the second bus 114, for example via the FLASH memory interface 106. The coupling module 606 is, for example, hard-coded.In one example, the coupling module 606 connects, for example, output lines of the processing unit 110 to access lines of the non-volatile memory 212, for example via the FLASH memory interface 106 and the second bus 114. In another example, the coupling module 606 connects, for example, output lines of the processing unit 110 to access lines of the register 324, for example via the FLASH memory interface 106 and the second bus 114.

[0076] Figure 7 schematically represents an example of the implementation of a method of accessing the FLASH memory of the device in [Fig.6].

[0077] In a step 702 (ADDRESS VALIDATION), the processing unit 110 launches, for example, a request, or requests, to an address of the FLASH memory 104 which is retranscribed, via the coupling module 606 and by the virtual address translation module 232, into an address corresponding to the register 324 and / or the RAM memory 206 and / or the ROM memory 212. At the output of the coupling module 606, the request is carried by the bus 604 to the FLASH memory interface 106. The request comprises, for example, known control signals according to the AHB bus protocol: hsel, htrans, hready, hprot or haddr. The requested address is for example analyzed by the FLASH memory interface 106 for validation. If the address matches the address of one of the memories 206 or 212 or register 324 then the address is validated.

[0078] In a step 704 (STORE ADDRESS PHASE IN REGISTERS), when the address is validated, it is stored in one or more registers of the FLASH memory interface 106. A clock signal hclk is used, for example, for storing the address in the registers.

[0079] In a step 706 (ACCESS TO RAM, ROM, REG), an instruction to put the FLASH memory in test mode (testmode) is sent, for example, to the FLASH memory 104. Then, the request for access to the memories 206, 212 or to the register 324 of the FLASH memory 104 is implemented, for example, via the bus 114, with for example the known command signals: sel, wen, dataout and / or addr, and using the address stored in step 704 in the FLASH memory interface 106, and translated, for example, by the virtual address translation module 232.

[0080] [Fig.8] represents, in block form, an example of implementation of a method for reading the FLASH memory of the device of [Fig.6].

[0081] In a step 808 (RETRIEVE DATA FROM RAM, ROM, REG TO FLASH INTERFACE), the data from the memory 206 or 212 or from the register 324 are sent, for example, via the bus 114, for example via a data bus datain the bus 114, to the FLASH memory interface 106.

[0082] In a step 810 (SEND RETRIEVED DATA TO GPU), the obtained data is redirected, for example, via the bus 604, for example via a data bus rdata of the bus 604, to the processing unit 110.

[0083] The methods of [Fig.7] and 8 allow access to data in the FLASH memory, for example during test modes, to be facilitated and the FLASH memory to be easily repaired and / or adjusted.

[0084] [Fig. 9] represents, in the form of a timing diagram, an example of implementation of a method for writing the FLASH memory of the device of [Fig. 6]. [Fig. 9] illustrates in particular an example of access to the RAM memory a set of signals generated internally by the FLASH memory interface 106 on the basis of the signals present on the bus 604: - a HSELr_RAM bus selection signal; - an address signal HADDRr; - a transmission signal HTRANSr indicating the current transfer type, in which, for example: '00' indicates no transfer in progress: IDLE; '01' indicates a transfer in progress: BUSY; '10' indicates a transfer of a data item or the first data item in a data burst: NONSEQ; and '11' indicates a transfer of a data item in a data burst: SEQ_; - a HWRITEr write enable signal; - an HSIZEr access size signal; - a HREADYOUTr signal indicating that a transfer is completed on the bus and a HREADYr signal indicating that the previous transfer is complete; - a HWDATAr write data bus; - a HRDATAr read data bus; and - a HRESPr response signal.

[0085] In addition, [Fig.9] illustrates a set of signals transmitted on the bus 114 to the FLASH memory: - an HCLK clock signal; - a SEL_REGS bus selection signal; - an address signal ADDREGS; - a WEN_REGS write validation signal; - an output data signal DOUTREGS; and - an input data signal DINREGS.

[0086] Before a time tl, which corresponds to a rising edge of the selection signal HSELr_RAM and a rising edge of the clock signal HCLK, the bus 604 is inactive. For example, the signals on the bus 604 have, for example, the following values ​​while the bus 604 is inactive from the writing point of view (all the numerical values ​​in [Fig.9] are for example expressed in hexadecimal): HSELr_RAM=low level, HADDRr=0000, HTRANSr=0, HWRITEr=low level, HSIZEEr=0, HREADTOUTr=high level, HREADYr=high level, HWDATAr=00000000, HRDATAr=000000000, HRESPr=low level. Similarly, before time tl, bus 114 is also inactive from a write point of view, and the signals provided by the FLASH memory interface to bus 114 to the FLASH memory are for example: SEL_REGS=low level, ADDREGS=FFF, WEN_REGS=high level, DGUTREGS=0001, DINREGS=3F80.

[0087] Between time t1 and a time t2, which corresponds to an address phase, a write instruction is received by the bus 604. The write operation comprises an address phase during a first clock cycle HCLK between time t1 and time t2, and a data phase during a second clock cycle between time t2 and a time t3.

[0088] During the address phase, the bus 114 remains inactive, and the following signals are, for example, modified following the signals present on the bus 604: HSELr_RAM=high level, HADDRr=0004, HTRANSr=2, HWRITEr=high level, HSIZEEr=1. These signals correspond, in this example, to a 16-bit write to a virtual address whose least significant bits are 0004. When the signal HSELr_RAM goes high, this makes it possible, for example, to select the address corresponding to the RAM memory 206 of the FLASH memory 104. For example, the FLASH memory interface detects that the signal HSEL is activated on the bus 604, and that the address HADDR on the bus 604 corresponds to the address of the registers of the RAM memory 206, and activates therefore the selection signal HSELr_RAM. The FLASH memory interface 106, for example, decodes the address provided by the control unit 110 and stores it at the value HADDRr, for example here 0004. When HTRANSr=2, this makes it possible to calculate the address of the registers of the RAM memory 206 during the data phase. When HWRITEr is at the high level, this implies that the operation is a write to a register designated by the virtual address. When HSIZEr is equal to 0, the size of the data to be written is equal to, for example, 8 bits. When HSIZEEr is equal to 1, the size of the data to be written is equal to, for example, 16 bits. When HSIZEEr is equal to 2, the size of the data to be written is equal to, for example, 32 bits.

[0089] The data phase is triggered by a rising edge of the clock signal HCLK at time t2. Between time t2 and time t3, the bus 604 becomes inactive again, for example, and the following signals are modified, for example, as follows: HSELr_RAM=low level, HADDRr=lFEC, HTRANSr=0, HWRITEr=low level. The signal HSIZEr is, for example, not valid during the data phase. Between time t2 and time t3, the signal SEL_REGS is set to a high level, which makes it possible to select the registers in which the data are written. Between time t2 and time t3, the ADDREGS signal changes to the value of the physical address of the RAM memory 206, for example 082. Indeed, the virtual address translation module 232 of the FLASH memory interface 106 is for example configured to translate the virtual address 0004 known to the control unit 110 into physical address 082 in the RAM memory 206.The WEN_REGS signal is for example set low, which activates, for example, writing. Between time t2 and time t3, the DINREGS signal, which contains the data from HWDATAr to be written, for example here 0002, is written, for example, by reducing the number of bits presented on the 604 bus to only the 16 least significant bits.

[0090] After time t3, buses 604 and 114 become inactive, for example. The following signals are modified, for example, as follows: HADDRr=0000, HSIZEEr=0, HWDATAr=00000000, SEL_REGS=low level, ADDREGS=FFF, WEN_REGS=high level, DINREGS=3F80. The fact that the signals ADDREGS and DINREGS are, in the example given, respectively at the value FFF and 3F80 before t2 and after t3, is independent of the data writing process.

[0091] [Fig. 10] represents, in the form of a timing diagram, an example of implementation of a method for reading the FLASH memory of the device of [Fig.6]. [Fig. 10] illustrates in particular the same signals as those illustrated in [Fig.9], but for the case of a reading operation.

[0092] Before a time t5, which corresponds to a rising edge of the clock signal HCLK and the signal HSELr_RAM, the signals of the bus 604, for example, have the following values: HSELr_RAM=low level, HADDRr=0000, HTRANSr=0, HWRITEr=low level, HSIZEr=0, HREADTOUTr=high level, HREADYr=high level, HWDATAr=OOOOOOOO, HRDATAr=OOOOOOOOOO, HRESPr=low level. Before time t5, the signals on bus 114 to the FLASH memory interface are set to the following levels, for example: SEL_REGS=low level, ADDREGS=FFF, WEN_REGS=high level, DGUTREGS=0001, DINREGS=3F80.

[0093] Between time t5 and a time t6, which corresponds to a rising edge of the clock signal HCLK for example shifted by one clock cycle with respect to t5, the following values ​​are modified for example: HSELr_RAM=high level, HADDRr=0004, HTRANSr=2, HSIZEr=1, SEL_REGS=high level, ADDREGS=082, WEN_REGS=high level, DINREGS=0000. This makes it possible to translate the address of the RAM memory 206 requested by the control unit 110 into the physical address to be read from the registers of the RAM memory 206 of the FLASH memory 104, here the physical address 082.

[0094] Between time t6 and a time t7, which corresponds to a rising edge of the clock signal HCLK for example shifted by one clock cycle with respect to t6, the following signals are modified for example: HADDRr=0000, HTRANSr=0, HSIZEr=0, HWDATAr=00000002, HRDATAr=00000002, SEL_REGS=low level, ADDREGS=FFF, DGUTREGS=0002, DINREGS=3F80. This makes it possible to read the data, for example here 0002, stored in the registers of the RAM memory 206 of the FLASH memory 104 using the bus 114, via the signal DOUTREGS, and to send them to the bus 604 where they are for example contained in the signal HRDATAr. In the example in [Fig.10], the data from DOUTREGS =0002 is sent to HRDATAr, which becomes 00020002. In this example, the 16-bit data 0002 in DOUTREGS is copied to the high 16 bits and low 16 bits of HRDATAr.The skilled person could, in another example, leave the DOUTREGS data on either the high-order bits or the low-order bits.

[0095] After time t7, the following signals are modified for example: HRDATAr=00000000, HWDATAr=00000000.

[0096] The fact that the ADDREGS and DINREGS signals are, in the given example, respectively at the value FFF and 3F80 before t5 and after t6, is independent of the data reading process.

[0097] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, although the examples mention the implementation of a configuration value 202 for the FLASH memory 104, those skilled in the art could implement several configuration values, for example in the form of several configuration bits. The type of the bus 604 is, for example, of the AHB type. In this case, the corresponding instructions can be coded differently than those described in the examples of Figures 9 and 10. The addresses of the registers, RAM and ROM memories of the FLASH memory are, for example, different from those given as examples in Figures 9 and 10.

[0098] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. FLASH memory device (100) comprising: - a FLASH memory (104) comprising a matrix of non-volatile memory cells (208) and a volatile memory (206); - a FLASH memory interface (106) arranged outside the FLASH memory (104); - a first communication bus (214) connecting the FLASH memory interface (106) and the memory cell array (208); and - a second communication bus (114) connecting the FLASH memory interface (106) and the volatile memory (206); the memory cell array (208) being configured to store at least one volatile memory configuration value (206) and a program patch (204); the device being configured to implement the following steps: -obtaining, by the FLASH memory interface (106) via the first bus, between a power-up and a boot procedure of the device (100), said volatile memory configuration value (206) and, - depending on said volatile memory configuration value (206), obtaining the program patch (204) from the FLASH memory (104) and loading it into the volatile memory (206) of the FLASH memory (104) through the second communication bus (114).

2. A method for accessing, in a FLASH memory device (100), the FLASH memory (104) using a FLASH memory interface (106) arranged outside the FLASH memory (104), the FLASH memory comprising an array of non-volatile memory cells (208) and a volatile memory (206), the method comprising: - accessing data stored in the array of memory cells (208) via a first communication bus connecting the FLASH memory interface (106) and the array of memory cells (208); and - accessing data stored in the volatile memory (206) via a second communication bus (114) connecting the FLASH memory interface (106) and the volatile memory (206); the array of memory cells (208) being configured to store at least one volatile memory configuration value (206) and a program patch (204), the method comprising: - obtaining, by the FLASH memory interface (106) via the first bus, between a power-up and a boot procedure of the device (100), said volatile memory configuration value (206) and, - depending on said volatile memory configuration value (206), obtaining a program patch (204) from the FLASH memory (104) and loading it into the volatile memory (206) of the FLASH memory (104) through the second communication bus (114).

3. Device according to claim 1, the FLASH memory device further comprising a coupling module (606) connecting output lines of a processing unit (110), external to the FLASH memory device (100), to access lines of said volatile memory (206) of the FLASH memory (104).

4. Device according to any one of claims 1 or 3, wherein the FLASH memory (104) further comprises a non-volatile memory (212) comprising a program for controlling a write / programming controller (320) and / or comprising parameters for adjusting the memory cell array (208); the write / programming controller (320) being configured to implement steps of programming, erasing and verifying data from the memory.

5. Device according to claim 4 in its dependency on claim 3, in which the coupling module (606) further connects output lines of the processing unit (110) to access lines of the non-volatile memory (212).

6. Device according to any one of claims 1 or 3 to 5, wherein the FLASH memory interface (106) comprises a write / read interface (238) for data to be written to the memory cell array of the FLASH memory, or to be read from the memory cell array of the FLASH memory (104).

7. Device according to any one of claims 1 or 3 to 6, in which the second communication bus (114) is a synchronous bus.

8. Device according to any one of claims 1 or 3 to 7, in which the FLASH memory (104) further comprises at least one register (324) storing a configuration value of the FLASH memory (104) and / or storing adjustment parameters of the memory cell array (208).

9. Device according to claim 8 in its dependency on claim 3, in which the coupling module (606) further connects output lines of the processing unit (110) to access lines of said register (324).

10. A device according to any one of claims 1 or 3 to 9, wherein the volatile memory configuration value (206) and the program patch (204) are stored in a control area (210) of the FLASH memory (104) whose access is protected.

11. A device according to any one of claims 1 or 3 to 10, wherein the FLASH memory interface (106) comprises a finite state machine (330) configured to manage obtaining the program patch (204) as well as its restitution to the communication bus (114).

12. Device according to any one of claims 1 or 3 to 11, in which the FLASH memory interface (106) comprises a module for translating virtual addresses (232) into physical addresses.

13. Device according to any one of claims 3, or 4 to 12 in its dependency on claim 3, in which the coupling module (606) is a bus addressing matrix.

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