INTEGRATED CIRCUIT PACKAGE

Abstract

Integrated circuit package, comprising a support substrate (1) and a cover (2) fixed on a first face (F1) of the support substrate and defining with the support substrate a housing (3) containing at least one electronic chip (4) having a first face (41) equipped with electrically conductive projecting elements (5) in electrical cooperation without soldering with electrically conductive contact pads (6) located on the first face of the support substrate, said at least one chip comprising a second face (42) opposite the first face of the chip and defining with the cover a first space (ESP1) filled with a first shape memory material (7) in the austenitic state. Figure for the abstract: Fig 1

Description

Title of the invention: INTEGRATED CIRCUIT PACKAGE

[0001] Implementations and embodiments of the present invention relate to the field of microelectronics, in particular the field of packaging of integrated circuits, and more particularly packages comprising integrated circuits mounted on a flip chip (FC) type according to an English acronym well known to those skilled in the art.

[0002] An electronic chip intended to be mounted upside down on one face, typically the upper face, of a carrier substrate, comprises a front face equipped with projecting elements, typically electrically conductive bumps and a rear face opposite the front face.

[0003] In the "flip chip" type assembly, the bumps on the front face of the chip are soldered to contact pads on the upper face of the carrier substrate.

[0004] “Flip Chip” type devices with large chips are subject to damage due to mechanical stresses caused during the manufacturing of these devices. Indeed, due to the different thermal expansion coefficients between the chip and the carrier substrate, the manufacturing flow including heating / cooling steps creates known failures such as cracks, fissures, delaminations.

[0005] Existing solutions for preventing such failures are based on a specific set of materials (for example, filling material known to those skilled in the art under the English term “Underfill”) or on laser-assisted bonding (LAB).

[0006] However, such options are expensive or not effective enough.

[0007] There is therefore a need to propose a more satisfactory solution to reduce as much as possible or even eliminate these failures during the manufacture of packages containing flip-mount chips.

[0008] According to one embodiment and implementation, it is proposed to insert a shape memory material, compressed in the martensitic state, advantageously thermally conductive, between the rear face of the chip and the cover of the package, then during the manufacture of the package, to heat the package, for example to finalize the fixing of the cover on the support substrate, to a temperature higher than the end temperature of the transition to the austenitic state of the shape memory material, so that the latter expands to return to its initial shape so as to completely fill the space between the rear face of the chip and the cover and thus exert pressure on the cover, which will create a spring effect and push the projecting elements (bumps) of the chip against the contact pads of the support substrate of the package.

[0009] Correct electrical cooperation is therefore obtained without welding between the bumps and the contact pads of the carrier substrate, even if the carrier substrate deforms.

[0010] According to one aspect, an integrated circuit package is proposed, comprising a support substrate and a cover fixed on a first face, for example the upper face, of the support substrate and defining with the support substrate a housing containing at least one electronic chip having a first face, for example the front face, equipped with projecting elements, for example electrically conductive bumps in electrical cooperation without soldering with electrically conductive contact pads located on the first face of the support substrate.

[0011] Said at least one chip comprises a second face, for example the rear face, opposite the first face of the chip and defining with the cover a first space filled with a first shape memory material.

[0012] Such a package structure therefore makes it possible to have a chip that is not physically welded to the support substrate or mechanically attached to the cover (which allows a reduction in stresses and deformations by mechanically releasing the structure). The electrical connections between the protruding elements (bumps) and the contact pads of the support substrate are maintained throughout the life of the component via this shape memory material which provides a spring effect tending to push the chip towards the support substrate.

[0013] This first shape memory material is advantageously thermally conductive, which also makes it possible to maintain a thermal connection between the chip and the cover throughout the life of the component.

[0014] The first face of the chip defines with the first face of the carrier substrate a second space advantageously free of filling material or adhesive material.

[0015] According to a particularly advantageous embodiment, the projecting elements are in electrical cooperation with said contact pads via a second electrically conductive shape memory material.

[0016] A spring effect is thus also obtained on the side of the projecting elements, which, combined with the spring effect provided by the first shape memory material, further improves the good electrical conductivity between the projecting elements and the contact pads of the support substrate.

[0017] The first shape memory material and the second shape memory material are advantageously identical and may contain, for example, an alloy of nickel and titanium (“Nitinol”).

[0018] The first shape memory material and the second shape memory material contain a first amount of non-porous nickel titanium alloy and a second amount of porous nickel titanium alloy.

[0019] The presence of a quantity of porous alloy makes it possible to increase the elongation capacity of the shape memory material, which helps to compensate for movements of the carrier substrate and / or the cover.

[0020] Thus the second quantity of porous alloy is for example less than or equal to 10% of the total quantity of nickel and titanium alloy, which makes it possible to have an elongation capacity of the order of 10% which makes it easy to compensate for movements of the carrier substrate and / or the cover usually of the order of a few microns.

[0021] The porous nickel and titanium alloy has, for example, a modulus of elasticity between 10 GPa and 100 GPa.

[0022] The first shape memory material and the second shape memory material also advantageously contain copper in an amount less than or equal to 5% of the total amount of the corresponding shape memory material.

[0023] The presence of copper is advantageous from the point of view of the mechanical behavior of the shape memory material since it allows, in small quantities, to reinforce the bidirectional effect of the shape memory material.

[0024] The first shape memory material has, for example, an end-of-transition temperature to the austenitic state of between 40°C and 100°C.

[0025] According to another aspect there is provided a method of manufacturing an integrated circuit package, comprising the following steps (a) providing at least one electronic chip having a first face equipped with electrically conductive protruding elements, b) providing a support substrate having a first face equipped with electrically conductive contact pads, c) turning the chip over and electrically cooperating the protruding elements with the electrically conductive pads without soldering, d) providing a first layer of a first shape memory material in a martensitic state and having an initial thickness, e) deforming the first layer so as to give it a second thickness less than the initial thickness and depositing the first layer thus deformed on a second face of the flipped chip opposite the first face, f) fixing a cover on the first face of the support substrate so as to cover the first deformed layer while leaving a space between the first deformed layer and the cover, g) completing the fixing of the cover on the support substrate by heating the structure obtained in step f) to a temperature higher than the end temperature of the transition to the austenitic state of the first shape memory material so that the first layer tends to regain its initial thickness and fills said space, ensuring a pressure on the hood.

[0026] The first shape memory material is advantageously thermally conductive.

[0027] According to an advantageous embodiment, the method comprises between step b) and step c) a deposition on the contact pads of a layer of a second electrically conductive shape memory material identical to the first shape memory material deformed in the martensitic state, and step c) comprises turning the chip over and making the protruding elements cooperate electrically without soldering with the electrically conductive pads via the layer of the second shape memory material, and in which in step g) the thickness of the layer of the second shape memory material increases so as to ensure pressure on said protruding elements.

[0028] The first shape memory material contains, for example, an alloy of nickel and titanium.

[0029] Other advantages and characteristics of the invention will appear on examining the detailed description of embodiments and implementations, which are in no way limiting, and the appended drawings in which:

[0030] [Fig.l];

[0031] [Fig.2] ;

[0032] [Fig.3] ; and

[0033] [Fig.4] ;

[0034] schematically illustrate modes of implementation and embodiment of the invention.

[0035] In [Fig.l], the reference BT designates an integrated circuit package.

[0036] This BT housing comprises a support substrate 1, of conventional structure and known per se, comprising a first face F1, typically the upper face of the support substrate.

[0037] The lower face of the support substrate, opposite the upper face F1, is generally provided with solder balls intended to be soldered onto tracks of a printed circuit board.

[0038] The BT box also includes a cover 2, also of conventional structure and known per se.

[0039] This cover 2 is fixed to the first face F1 of the support in particular by means of an adhesive material 8 such as glue.

[0040] The cover 2 defines with the support substrate 1 a housing 3 containing at least one electronic chip 4.

[0041] The chip 4 comprises a first face 41, typically the front face, equipped with electrically conductive protruding elements 5 such as bumps or pillars, for example made of copper.

[0042] The chip 4 also comprises a second face 42, opposite the first face 41, typically the rear face of the chip.

[0043] The chip 4 is a flip chip, i.e. the front face 41 faces the support substrate 1 while the rear face 42 faces the cover 2.

[0044] The rear face 42 of the chip 4 is located at a distance dl from the cover 2 and defines with the latter a first space ESP1 entirely filled with a first shape memory material 7 which is here in the austenitic state.

[0045] By way of non-limiting example, the first shape memory material 7 may contain an alloy of nickel and titanium known to those skilled in the art under the name “Nitinol”, in which the titanium and nickel are approximately present in the same percentages.

[0046] The chemical formula of Nitinol is for example Nil4Til 1. However, shape memory materials having other compositions may also be referred to in practice by the term "Nitinol".

[0047] A shape memory material has a property well known to those skilled in the art.

[0048] It is recalled that this shape memory property is defined as the ability of a sample of this material having undergone significant deformation to recover its initial shape in the austenitic state by heating to a temperature higher than the temperature at the end of the transition to the austenitic state, a temperature known to those skilled in the art under the English expression “austenite finish”.

[0049] Thus, the end temperature of the transition to the austenitic state of Nitinol is of the order of 50°C to 100°C.

[0050] Nitinol is a shape memory material that is both thermally and electrically conductive.

[0051] Its thermally conductive nature allows it to contribute to the heat dissipation of the housing.

[0052] As illustrated very schematically in [Fig.l], the BT housing comprises electrically conductive contact pads 6, distributed over the first face F1 of the carrier substrate.

[0053] And, the projecting elements 5 are in electrical cooperation without welding with these contact pads 6.

[0054] More specifically, in the embodiment of [Fig.l], the protruding elements 5 are in contact with a second shape memory material 9, which is in this case identical to the first shape memory material 7. In other words, the second shape memory material 9 also contains Nitinol.

[0055] And, since Nitinol is electrically conductive, the protruding elements 5, in contact with the Nitinol layer 9 which covers the corresponding contact area 6, are in good electrical cooperation with these contact pads 6.

[0056] And this electrical cooperation is carried out without welding.

[0057] Furthermore, as illustrated in [Fig. 1], the first face 41 of the chip 4 defines with the first face F1 of the carrier substrate a second space ESP2 devoid of filling material (“underfill”) or adhesive material such as glue.

[0058] We now refer more particularly to [Fig.2] which schematically illustrates a zoom of the zone ZA of [Fig.l].

[0059] As can be seen in [Fig.2], the layer 9 of shape memory material is trapped in an insulating enclosure 10, known to those skilled in the art by the Anglo-Saxon term “Solder Mask”.

[0060] The shape memory material 9 is here also in its austenitic state and creates a spring effect exerting a thrust on the projecting element 5 according to the arrow F2.

[0061] At the same time, as illustrated schematically in [Fig. 3], the shape memory material 7 located between the rear face 42 of the chip 4 and the cover 2 exerts a spring effect which tends to push the chip 4 along the arrow F1, in the direction of the support substrate.

[0062] The combination of these two spring effects leads to very good electrical contact between the end 50 of the projecting elements 5 and the layer 9 of the shape memory material and therefore very good electrical cooperation between the projecting element 5 and the corresponding underlying contact pad 6, without it being necessary to carry out any welding at the level of the projecting elements.

[0063] Obtaining these spring effects will now be described with particular reference to [Fig.4] which very schematically illustrates the steps of the manufacturing process of the BT box of [Fig.l].

[0064] In step STa, the electronic chip 4 is provided having its first face 41 equipped with the electrically conductive protruding elements 5.

[0065] In step STb, the support substrate 1 is provided having its first face F1 equipped with the electronically conductive contact pads 6.

[0066] Then, in step STc, the chip 4 is turned over to make the protruding elements 5 cooperate electrically without soldering with the electrically conductive pads 6.

[0067] When it is also planned to use a shape memory material 9 on the side of the projecting elements, a step STbl is provided between step STb and step STc, in which a layer of shape memory material 9 is deposited on the contact pads, which has been deformed to the martensitic state, in compression so as to have a height H2 less than the height H1 mentioned in [Fig.2].

[0068] And, in this case, in step STc, after turning over the chip, there is a seamless electrical cooperation of the protruding elements with the corresponding electrically conductive pads 6 via the layer of this material to shape memory.

[0069] Then, in step STd, a first layer of the shape memory material 7 is provided having an initial thickness dO greater than the distance dl mentioned in [Fig.l].

[0070] Then, in step STe, this first layer is deformed in the martensitic state by compression, so as to give it a second thickness d2 less than the initial thickness dO, this second thickness d2 also being slightly less than the distance dl mentioned in [Fig.l].

[0071] As an indication, for a given distance dl, a second thickness d2 will be chosen which is less than the distance dl, for example of the order of 1% to 5% of the distance dl less.

[0072] Then, the first layer thus deformed is deposited on the rear face 42 of the flipped chip.

[0073] In step STf, the cover 2 is then fixed to the support substrate 1 using the glue 8, which is, for example, a pre-polymerized glue.

[0074] As the thickness of the shape memory material layer 7 is slightly less than the distance dl between the rear face of the chip and the cover 2, there remains a space between this layer 7 and the cover which allows it to be fixed to the support substrate while covering the chip.

[0075] Finally, the fixing of the cover on the support substrate is completed in step STg by heating the structure obtained in step STf to a temperature higher than the end temperature of the transition to the austenitic state of the shape memory material. This heating makes it possible on the one hand to completely polymerize the adhesive 8 and on the other hand to pass the shape memory material into its austenitic state so that it regains its initial shape, in this case so that the layer of material 7 increases in thickness to tend to regain its initial thickness which is greater than the distance dl.

[0076] As a result, the space ESP1 is completely filled by the shape memory material 7 and this ensures its spring effect as illustrated schematically in [Fig.3].

[0077] When the layer 9 of shape memory material has also been deposited in the enclosure 10, heating to the temperature above the end temperature of the transition to the austenitic stage leads to an increase in the thickness of the layer 9 which causes the spring effect illustrated in [Fig.2].

[0078] As an indication, in the STG step, the housing will be heated to a temperature of around one hundred degrees, depending on the materials used.

[0079] The housing according to these embodiments and implementations therefore uses a shape memory material, for example nitinol, playing the role of a spring allowing correct electrical cooperation between the projecting elements 5 and the underlying contact pads of the support substrate, without welding, even in the event of warping of the support substrate.

[0080] There is no welding at the level of the protruding elements 5 and consequently no stress transmitted to the chip.

[0081] There is no filler material in the structure and no stress appearing during the life of the product.

[0082] The invention is not limited to the modes of implementation and embodiment which have just been described but embraces all variants thereof.

[0083] Thus, it is possible to use for shape memory materials 7 and 9, non-porous Nitinol and porous Nitinol, which makes it possible to increase the elongation capacity of the shape memory material.

[0084] It is also possible that the shape memory material also contains copper in an amount less than or equal to 5% of the total amount of the corresponding shape memory material.

[0085] Indeed, the presence of copper in small quantities makes it possible to reinforce the bidirectional effect of the shape memory material.

Claims

Claims

1. Integrated circuit package, comprising a support substrate (1) and a cover (2) fixed on a first face (F1) of the support substrate and defining with the support substrate a housing (3) containing at least one electronic chip (4) having a first face (41) equipped with electrically conductive projecting elements (5) in electrical cooperation without soldering with electrically conductive contact pads (6) located on the first face of the support substrate, said at least one chip comprising a second face (42) opposite the first face of the chip and defining with the cover a first space (ESP1) filled with a first shape memory material (7), in which the projecting elements are in electrical cooperation with said contact pads via a second electrically conductive shape memory material (9).

2. A housing according to claim 1, wherein the first shape memory material (7) is thermally conductive.

3. Package according to claim 1 or 2, in which the first face of the chip defines with the first face of the carrier substrate a second space (ESP2) devoid of filling material or adhesive material.

4. Housing according to one of the preceding claims, in which the first shape memory material (7) and the second shape memory material (9) are identical.

5. A housing according to claim 4, wherein the first shape memory material (7) and the second shape memory material (9) contain an alloy of nickel and titanium.

6. A housing according to claim 5, wherein the first shape memory material (7) and the second shape memory material (9) contain a first amount of non-porous nickel titanium alloy and a second amount of porous nickel titanium alloy.

7. The housing of claim 6, wherein the second amount is less than or equal to 10% of the total amount of nickel and titanium alloy.

8. A housing according to claim 6 or 7 wherein the porous alloy of nickel and titanium has a modulus of elasticity of between 10 GPa and 100 GPa.

9. Housing according to one of claims 5 to 8, in which the first

10.

11. shape memory material (7) and the second shape memory material (9) also contain copper in an amount less than or equal to 5% of the total amount of the corresponding shape memory material. Housing according to one of the preceding claims, in which the first shape memory material (7) has an end temperature of transition to the austenitic state of between 40°C and 100°C. A method of manufacturing an integrated circuit package, comprising the following steps: (a) providing at least one electronic chip having a first face equipped with electrically conductive protruding elements, b) providing a support substrate having a first face equipped with electrically conductive contact pads, c) turning the chip over and electrically cooperating without soldering the protruding elements with the electrically conductive pads, d) providing a first layer of a first shape memory material in a martensitic state and having an initial thickness, e) deforming the first layer so as to give it a second thickness less than the initial thickness and depositing the first layer thus deformed on a second face of the flipped chip opposite the first face, f) fixing a cover on the first face of the support substrate so as to cover the first deformed layer while leaving a space between the first deformed layer and the cover, g) completing the fixing of the cover to the support substrate by heating the structure obtained in step f) to a temperature higher than the end temperature of the transition to the austenitic state of the first shape memory material so that the first layer tends to regain its initial thickness and fills said space while ensuring pressure on the cover, the method comprising between step b) and step c) a deposition on the contact pads of a layer of a second electrically conductive shape memory material identical to the first shape memory material deformed in the martensitic state, and in which step c) comprises turning the chip over and making the protruding elements cooperate electrically without soldering with the electrically conductive pads via the layer of the second shape memory material, and in which in step g) the thickness of the layer of the second shape memory material increases so as to ensure pressure on said protruding elements.

12. The method of claim 11, wherein the first shape memory material is thermally conductive.

13. A method according to either of claims 11 or 12, wherein the first shape memory material contains an alloy of nickel and titanium.

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