Process for treating a polycrystalline silicon carbide wafer
The surface treatment of polycrystalline silicon carbide wafers through precise grinding and polishing addresses the inconsistency in the Smart Cut™ process, reducing rejection rates and costs by ensuring consistent bonding with monocrystalline substrates.
Patent Information
- Application Number
- FR2022008872
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2022-09-05
- Publication Date
- 2025-11-28
- Estimated Expiration
- 2042-09-05
AI Technical Summary
The Smart Cut™ process for transferring a monocrystalline silicon carbide layer onto a polycrystalline silicon carbide substrate is hindered by inconsistent surface preparation, leading to high rejection rates and significant waste of expensive polycrystalline wafers due to incomplete layer transfer.
A surface treatment process for polycrystalline silicon carbide wafers involving characterization, material removal through grinding and polishing to achieve precise surface roughness, followed by bonding with a monocrystalline substrate, with iterative corrections if necessary to meet specifications.
Reduces the rejection rate and waste by ensuring consistent surface preparation, thereby optimizing the Smart Cut™ process and minimizing the environmental impact and costs associated with polycrystalline wafer usage.
Smart Images
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Abstract
Description
Title of the invention: Process for treating a polycrystalline silicon carbide wafer technical field
[0001] The field of the invention is that of polycrystalline silicon carbide wafers intended to serve as supports for thin films of monocrystalline silicon carbide. Previous technique
[0002] Silicon carbide (SiC) is increasingly used in power electronics applications, particularly to meet the needs of emerging areas of electronics such as electric vehicles. Power devices and integrated power supply systems based on monocrystalline SiC can effectively handle a much higher power density than their traditional silicon counterparts, and with smaller active area dimensions.
[0003] Monocrystalline SiC substrates for the microelectronics industry remain expensive and difficult to source in large sizes. Therefore, it is advantageous to use layer transfer solutions to fabricate composite structures typically comprising a monocrystalline SiC thin film on a lower-cost support substrate. A well-known thin-film transfer solution is the Smart Cut™ process. This process, for example, allows the fabrication of a composite structure comprising a monocrystalline SiC thin film, taken from a monocrystalline SiC donor substrate (mSiC), in contact with a polycrystalline SiC recipient substrate (pSiC).
[0004] This receiving substrate is a pSiC wafer obtained from a relatively thick pSiC slab (generally referred to as a slab) (for example, 0.6 to 3 mm thick). The pSiC slab is formed by deposition of pSiC onto a growth substrate (for example, a graphite substrate), typically by chemical vapor deposition at a temperature between 1100°C and 1400°C. Following removal of the growth substrate, the pSiC slab undergoes a wafering process, which includes various cleaning, etching, grinding, and polishing steps, resulting in one or more pSiC wafers with a desired shape (in particular, a beveled edge) and thickness. Sawing may also be performed during this process, especially when several wafers need to be manufactured from the same slab.The thickness of the poly-SiC wafer. crystalline material thus manufactured is, according to the SEMI standard, 350 qm + / - 25 qm.
[0005] The Smart Cut™ process applied to SiC requires specific surface preparation prior to bonding, typically using the ADB technique (acronym for the Anglo-Saxon term "Atomic Diffusion Bonding"), of the donor (mSiC) and recipient (pSiC) substrates. This surface preparation aims to create a specific surface condition, characterized by its roughness over a spatial frequency range from 5x5 µm to 150x50 µm.
[0006] However, this surface preparation does not appear to be perfectly reproducible, since many pSiC wafers prepared in this way risk leading to incomplete transfer of the mSiC layer during the Smart Cut™ process. Therefore, in practice, a preliminary sorting of the pSiC wafers prepared in this way is carried out to reject those that do not meet the expected roughness specifications required by the bonding process. The rejection rate proves to be significant, even though pSiC wafers are expensive and their manufacture requires a considerable amount of energy. Description of the invention
[0007] The invention aims to reduce this rejection rate in order to reduce the cost of the Smart Cut™ process applied to SiC and its environmental impact.
[0008] To this end, the invention proposes a process for treating a polycrystalline silicon carbide wafer, comprising: - the characterization of the surface roughness of a front face of the polycrystalline silicon carbide wafer; - when the surface condition characterized does not meet a predetermined specification for the bonding of the polycrystalline silicon carbide wafer with a monocrystalline silicon carbide substrate with the front face at the bonding interface, the reduction, by removal of material from the front face of the polycrystalline silicon carbide wafer, of the surface roughness of the front face.
[0009] Some preferred but not limiting aspects of this process are as follows:
[0010] - the material removal from the front face removes a thickness of material comprising between 3 and 10 pm;
[0011] - the removal of material from the front face includes grinding;
[0012] - the grinding comprises successively coarse grinding and fine grinding;
[0013] - coarse grinding is carried out with a grinding wheel whose abrasive grain size is characterized by a mesh of less than 5000;
[0014] - fine grinding is carried out with a grinding wheel whose abrasive grain size is ca characterized by a mesh greater than 5000;
[0015] - fine grinding removes a thickness of material less than 3 µm;
[0016] - the material removal from the front face further includes, following grinding, a polishing of the front face;
[0017] - the polishing is a chemical or mechano-chemical polishing;
[0018] - polishing removes a thickness of material less than 1 pm;
[0019] - the polycrystalline silicon carbide wafer presents, after correction of the state of the front face surface, a thickness of 350 pm + / - 25 pm;
[0020] - the polycrystalline silicon carbide wafer presents, before correction of the state of front face surface, a thickness of 365 pm + / - 10 pm;
[0021] - the polycrystalline silicon carbide wafer is obtained from a thinning double-sided polycrystalline silicon carbide plate;
[0022] - the characterization of the surface condition of the front face of the carbide insert polycrystalline silicon includes a haze measurement by light scattering;
[0023] - it further comprises, after correction of the surface condition of the front face, the bonding of the polycrystalline silicon carbide wafer with the monocrystalline silicon carbide substrate with the front face of the polycrystalline silicon carbide wafer at the bonding interface;
[0024] - it further comprises, after correction of the surface condition of the front face and Before bonding, a repeat of the surface characterization of the front face and: - when the surface condition characterized by the repeated characterization does not meet the predetermined specification, an additional correction, by material removal, of the surface condition of the front face; or - when the surface condition characterized by the reiteration of the characterization meets the predetermined specification, the execution of said bonding. Brief description of the drawings
[0025] Other aspects, objectives, advantages and features of the invention will become more apparent from the following detailed description of preferred embodiments thereof, given by way of non-limiting example, and made with reference to the accompanying drawings in which [Fig. 1] is a diagram illustrating different stages of a Smart Cut™ process incorporating a treatment of a pSiC wafer according to the invention.
[0026] DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS
[0027] The invention relates to a method for processing a pSiC wafer intended to serve as a substrate for a thin mSiC film. This method may include a preliminary step of forming the wafer from a pSiC slab. To do this, the pSiC slab is subjected to a wafering process. This process may, in particular, include double-sided thinning of the slab and possibly The plate is flattened to correct any curvature. Thinning can be achieved by grinding. This grinding process may involve a series of steps: coarse grinding to reduce the thickness to approximately 400 µm, rough grinding to reduce it to approximately 360 µm, and fine grinding to remove the last few microns of material. The different grinding stages are distinguished by the size of the grinding wheel grit used, with the grit becoming progressively smaller in each successive stage.
[0028] In one possible embodiment, the wafer produced from the pSic plate has a thickness of 350 µm + / - 25 µm, thus meeting the SEML standard
[0029] In another possible embodiment, the wafer produced from the pSiC plate has a thickness distribution shifted towards 365 pm, for example, a thickness of 365 pm + / - 10 pm. This embodiment allows the final thickness of the pSiC wafer to remain compliant with the SEMI standard, while, according to the invention described below, one or more surface finish correction operations are performed on the pSiC wafer to ensure the proper implementation of the Smart Cut™ process following its bonding with an mSiC substrate.
[0030] As shown in [Fig. 1], the process according to the invention can thus include an RI step of supplying a pSiC wafer. The process according to the invention further includes a step (designated by R2 in [Fig. 1]) consisting of characterizing the surface condition of a front face of the pSiC wafer, typically a characterization of the roughness of this front face. This characterization may in particular include a haze measurement by light scattering. Such a haze measurement makes it possible to characterize the surface roughness of the front face of the pSiC wafer. This haze is obtained using a method that utilizes the optical reflectivity properties of the surface to be characterized and corresponds to an optical signal scattered by the surface due to its microroughness. Haze measurement can, for example, be carried out using the Surfscan SP1 inspection system from KLA-Tencor or the SICA88 inspection system from Lasertec.
[0031] The method according to the invention then comprises a step of determining whether the characterized surface condition meets a predetermined specification for bonding, with the front face at the bonding interface, the pSiC wafer to an mSiC substrate. In one possible embodiment, this determination consists of verifying whether the measured haze level is below a predetermined threshold.
[0032] If the surface condition of the front face meets the predetermined specification, the process according to the invention continues with the bonding (designated by C in [Fig. 1]), for example according to the ADB technique, of the pSiC wafer with an mSiC substrate, the front face of the pSiC wafer being at the bonding interface. In accordance with the In the Smart Cut™ process, the mSiC substrate is then detached (designated by D in [Fig. 1]) along a pre-formed embrittlement plane (designated by ion implantation) by thermal treatment, mechanical action, or a combination of these methods. This detachment transfers a thin layer of mSiC onto the pSiC wafer, thus forming a composite structure. In [Fig. 1], DI represents the supply of the mSiC substrate, and D2 represents the ion implantation that embrittles it. Following detachment D and the transfer of the thin layer of mSiC onto the pSiC wafer, the composite structure undergoes a finishing treatment (designated by F in [Fig. 1]), and the remaining mSiC substrate may be recycled R for reuse.
[0033] If the surface condition of the front face does not meet the predetermined specification, the process according to the invention includes a step (designated by R3 on the [Fig.1]) of correction, by removing material from the front face of the pSiC wafer, of the surface condition of this front face.
[0034] This material removal from the front face can remove a thickness of between 3 and 10 µm. It can be achieved by grinding the front face. It should be noted that, unlike the prior double-sided thinning of the pSiC wafer, the grinding of the pSiC wafer can be performed here only on the front face intended to be bonded to the mSiC substrate. This grinding of the front face only is made possible by the double-sided grinding performed beforehand during the wafering process, which allowed the stresses between the front and back faces to be balanced.
[0035] The grinding process may consist of successive coarse and fine grinding. The coarse grinding may be carried out with a grinding wheel whose abrasive grain size is characterized by a mesh size of less than 5000. The coarse grinding preferably removes a thickness of material less than 10 µm, for example a thickness of 5 µm.
[0036] Fine grinding can be carried out with a grinding wheel whose abrasive grain size is characterized by a mesh greater than 5000, for example a mesh between 8000 and 1200. Fine grinding preferably removes a thickness of material less than 3 µm.
[0037] In one possible embodiment, the material removal from the front face may further include, following grinding, polishing of the front face. This polishing may be chemical or mechano-chemical. The polishing preferably removes a thickness of material less than 1 µm.
[0038] It is understood that if this correction of the surface finish of the front face intended to be bonded removes, for example, a thickness of material of 10 µm, then preferable that the pSiC wafer initially has a greater thickness than that expected by the standard, for example a thickness of 365 pm, so that after correction it has the thickness of 350 pm expected by the standard or so that it can undergo several surface finish correction operations while maintaining a final thickness greater than the lower limit of 325 pm expected by the standard.
[0039] Indeed, in one possible embodiment, following an initial correction of the surface finish of the front face intended to be bonded, the process includes a repetition of the surface finish characterization of the front face. Then, the process includes: - when the surface condition characterized by the repeated characterization does not meet the predetermined specification, an additional correction, by material removal, of the surface condition of the front face; or - when the surface condition characterized by the reiteration of the characterization meets the predetermined specification, the bonding is carried out.
[0040] The process according to the invention may include one or more additional corrections, each preceded by a characterization of the surface condition. Each additional correction is preferably identical to the first correction. With 5 to 10 µm removed at each correction, a first correction and up to 3 additional corrections can typically be carried out while maintaining a final thickness conforming to the SEMI standard.
[0041] The process according to the invention can also be repeated to process a set of wafers and constitute a batch of wafers suitable for bonding with a single-crystal SiC substrate. Thus, the invention extends to a process for manufacturing a batch of single-crystal silicon substrates, for example, substrates each having a thickness of 350 µm + / - 25 µm, comprising: - the supply of a set of polycrystalline silicon carbide wafers, for example wafers each with a thickness of 365 pm + / - 10 pm; - for each of the plates in the set: • the characterization of the surface roughness of a front face of the plate; • when the characterized surface condition meets a predetermined specification for bonding the wafer with a single-crystal silicon carbide substrate with the front face at the bonding interface, the addition of the wafer to said batch; • when the characterized surface condition does not meet the said predetermined specification, the reduction, by removing a thickness of material of the front face of the plate, the surface roughness of the front face and then the addition of the plate to said batch.
[0042] The wafers from the batch thus formed can then be bonded with a polycrystalline SiC substrate.
Claims
1. Demands A process for treating a polycrystalline silicon carbide wafer, comprising successively: - the characterization (R2) of a surface roughness of a front face of the polycrystalline silicon carbide wafer; - when the characterized surface roughness meets a predetermined specification for the bonding (C) of the polycrystalline silicon carbide wafer with a monocrystalline silicon carbide substrate with the front face at the bonding interface: the realization of said bonding; - when the surface roughness characterized does not meet the said predetermined specification: the reduction (R3), by removing a thickness of material between 3 pm and 10 pm from the front face of the polycrystalline silicon carbide wafer, of the surface roughness of the front face; the reiteration of the characterization of the surface roughness of the front face; when the surface roughness characterized by the reiteration of the characterization meets the said predetermined specification, the execution of the said bonding.
2. A method according to claim 1, wherein the material removal from the front face comprises grinding.
3. A method according to claim 2, wherein the grinding comprises successively coarse grinding and fine grinding.
4. Method according to claim 3, wherein the coarse grinding is carried out with a grinding wheel whose abrasive grain size is characterized by a mesh size of less than 5000.
5. A method according to any one of claims 3 and 4, wherein the fine grinding is carried out with a grinding wheel whose abrasive grain size is characterized by a mesh greater than 5000.
6. A method according to any one of claims 3 to 5, wherein fine grinding removes a thickness of material less than 3 pm.
7. A method according to any one of claims 3 to 6, wherein the material removal from the front face further comprises, following grinding, polishing of the front face.
8. A method according to claim 7, wherein the polishing is a chemical or mechano-chemical polishing.
9. A method according to any one of claims 7 and 8, wherein the polishing removes a thickness of material less than 1 µm.
10. A method according to any one of claims 1 to 9, wherein the polycrystalline silicon carbide wafer has, after correction of the surface condition of the front face, a thickness of 350 pm + / - 25 pm.
11. A method according to any one of claims 1 to 10, wherein the polycrystalline silicon carbide wafer has, before correction of the surface condition of the front face, a thickness of 365 pm + / - 10 pm.
12. A method according to any one of claims 1 to 11, wherein the polycrystalline silicon carbide wafer is obtained by double-sided thinning of a polycrystalline silicon carbide plate.
13. A method according to any one of claims 1 to 12, wherein the characterization of the surface condition of the front face of the polycrystalline silicon carbide wafer includes a haze measurement by light scattering.
14. A method according to any one of claims 1 to 13, wherein when the surface roughness characterized by the reiteration of the surface roughness characterization of the front face does not meet said specification, an additional correction, by material removal, of the surface roughness of the front face.
15. A process for manufacturing a batch of polycrystalline silicon carbide wafers, each having a thickness of 350 µm + / - 25 µm, comprising: - the supply of a set of polycrystalline silicon carbide wafers, each with a thickness of 365 pm + / - 10 pm; - for each of the plates in the set, successively: • the characterization (R2) of a surface roughness of a front face of the plate; • when the characterized surface roughness meets a predetermined specification for the bonding (C) of the wafer with a single-crystal silicon carbide substrate with the front face at the bonding interface, the addition of the wafer to said batch; • when the characterized surface roughness does not meet not to said predetermined specification: the reduction (R3), by removing a thickness of material between 3 pm and 10 pm from the front face of the polycrystalline silicon carbide wafer, of the surface roughness of the front face; the reiteration of the characterization of the surface roughness of the front face; when the surface roughness characterized by the reiteration of the characterization meets said predetermined specification, the addition of the wafer to said lot.