EEPROM memory device with “shared voltage” architecture.

Abstract

The memory plane comprises columns of memory words, formed respectively on each row of the memory plane by groups of memory cells. All the state transistors of the memory cells of a memory word are controlled on their gate by a control element (CGSWij). All the control elements of the same row are driven by a first control signal (CLj) coming from a first RS type latch device (DISV1) associated with said row. In order to write data into a memory word, first row control means (MPLR1), associated with a selected row, give the first control signal (CLj) an erasure voltage corresponding to a first logic state of the first control signal and then a programming voltage corresponding to a second logic state of the first control signal (CLj) without modifying the state of the output terminal (OUT) of the first latch device (DISV1) between the erasure and the programming of the memory word.Figure for abstract: Fig 2.

Description

Title of the invention: EEPROM memory device with “shared voltage” architecture.

[0001] Embodiments relate to non-volatile memories, for example electrically erasable and programmable memories, called EEPROM memories, in particular memories having a “split voltage” type architecture for their erasure and their programming and more particularly the control of the signals controlling, through inverter type control elements, the gates of the state transistors of the memory cells of the memory words during the write cycles comprising erasures of these memory words followed by programming of these memory words.

[0002] In EEPROM memories, the logic value of a bit stored in a memory point is represented by the value of the threshold voltage of a floating-gate transistor, which can be modified at will by programming or erasing operations. Programming or erasing a floating-gate transistor involves injecting or extracting electrical charges into the gate of the transistor by tunneling (the "Fowler-Nordheim" effect) using a high voltage.

[0003] In erasure this high voltage can be of the order of 9 to 20 volts, for example 15 volts.

[0004] This high voltage, necessary for writing EEPROM memories, is very restrictive in terms of the technological sector and the reliability of the product.

[0005] Indeed, the lithographic reduction, that is to say the increase in the etching fineness, leads to a reduction in the operating voltages, and this high voltage becomes more problematic in terms in particular of leaks from the source / substrate and drain / substrate junctions or located in the channel between drain and source of the transistors as well as in terms of stresses on the gate oxides (“gate stress”), or even breakdown of these gate oxides of the transistors.

[0006] Consequently, these risks of premature aging and / or breakdown of transistors have a direct impact on the reliability of the product.

[0007] This is why the so-called "split voltage" solution mentioned above can be used. More precisely, the high voltage required for programming the memory planes is shared between a positive voltage and a negative voltage so that the difference between the positive voltage and the negative voltage corresponds to a sufficient high programming voltage.

[0008] Such a solution allows a relaxation of the constraint on the voltage resistance of the transistors.

[0009] The X (row) driving is more complex in a shared voltage type architecture than in a conventional architecture because two different signals must be decoded per physical row of memory cells, namely the driving signal of the word lines which control the gates of the access (or selection) transistors of the memory cells, and the driving signals of the gates of the state transistors of the memory cells of the memory words through inverter control elements.

[0010] There is therefore a need to improve the row-drive circuits of non-volatile memories having a shared voltage architecture, in particular in terms of current consumption and number of transistors.

[0011] According to one aspect, there is provided a non-volatile memory device with a shared voltage type architecture, for example an EEPROM type memory.

[0012] This memory device comprises a matrix memory plane comprising columns of memory words.

[0013] These memory words are formed respectively on each row of the memory plane by groups of memory cells (each memory cell forming 1 bit of the memory word).

[0014] Each memory cell comprises a state transistor having a control gate and a floating gate and a selection or access transistor.

[0015] All the state transistors of the memory cells of a memory word are controlled on the gate by a control element (typically an inverter).

[0016] All the control elements of the same row are controlled by a first control signal coming from a first RS type locking device (“flip flop” in English), associated with said row.

[0017] The memory device further comprises a row decoder configured to, in order to write data into a memory word, select the row containing this memory word.

[0018] The memory device also comprises first row-driving means, associated with said selected row, and configured to, in order to write the data in the memory word, confer to the first driving signal an erasure voltage corresponding to a first logic state of the first driving signal then a programming voltage corresponding to a second logic state of the first driving signal, without modifying the state of the output terminal of the first latch device associated with this selected row between the erasure and the programming of the memory word.

[0019] Thus, in practice, the first locking device is powered between a first supply voltage or high voltage, and a second supply voltage or low voltage.

[0020] During an erase operation, the high voltage is typically of the order of 15 volts while low voltage is typically around 3 volts.

[0021] During a programming operation, the high voltage is typically of the order of 3 volts while the low voltage is typically a negative voltage, for example equal to -5 volts.

[0022] Thus, for a selected row, during a write cycle, comprising an erasure followed by a programming, the first control signal passes successively from the low logic state (corresponding to the low voltage) to the high logic state (corresponding to the high voltage), although the value of this high voltage is here equal to the value of the low voltage in the erasure operation.

[0023] And, here, the switching between the logic state of the first control signal in the erasure operation and the logic state of this control signal in the programming operation, is carried out without modifying the state of the output terminal of the first latch device associated with this selected row between erasure and programming, whereas in the prior art, the logic state of this output terminal was modified between erasure and programming.

[0024] This resulted in the prior art in a risk of collapse of the supply voltage of the latch device associated with the control elements connected to the gates of the state transistors with risks of erroneous switching of the output state of the latch device as well as current peaks in the middle of the write cycle.

[0025] This also results in a reduction in current consumption.

[0026] According to one embodiment, the first row-control means comprise a first control circuit having a first circuit input connected to the output terminal of the first latch device, a second circuit input capable of receiving a first control signal and a first circuit output capable of delivering the first control signal whose logic state depends on the value of the first control signal, and a first control stage configured to deliver this first control signal.

[0027] Thus, here, the switching of the logic state of the first control signal is carried out by a control circuit connected downstream of the locking device.

[0028] According to one embodiment, the first control circuit comprises

[0029] - a logic gate of the EXCLUSIVE NOT OR type having a first input of gate connected to said first circuit input, a second gate input connected to the second circuit input and a gate output, and

[0030] -a first inverter connected between the gate output and the first circuit output.

[0031] Thus, in this embodiment, the switching of the logic state of the first control signal is carried out using a NOT OR EXCLUSIVE logic gate connected downstream of the locking device.

[0032] The lines delivering the respective first control signals are quite capacitive and their switching results in significant current draws. The most compact EXCLUSIVE OR NOT gates use six transistors with the disadvantage of passing the output current back to the input. It is therefore advantageous to avoid this.

[0033] The presence of an inverter at the output of the EXCLUSIVE NOR gate makes it possible to achieve this goal. In fact, the inverter behaves like an output buffer stage. As a result, the switching current on the line carrying the first control signal is not seen by the output of the EXCLUSIVE NOR gate and therefore not seen on the inputs of this gate.

[0034] This EXCLUSIVE NOR gate-inverter assembly can be realized with eight transistors (six for the gate and two for the inverter), which is particularly compact.

[0035] For comparison, an EXCLUSIVE OR gate (logically equivalent to the EXCLUSIVE NOT OR-inverter gate assembly) made with a scheme that does not pass the output current to its inputs, would require the use of a number of transistors greater than eight.

[0036] According to one embodiment, the memory plane comprises R rows and the memory device comprises

[0037] -M first locking devices, each first locking device being associated with a block of N rows, R being equal to the product of N by M, as well as

[0038] -for each first locking device, N first row-control means respectively associated with the N rows of the row block associated with this first locking device.

[0039] The row decoder then comprises a block decoding circuit configured to select a first locking device from among the M first locking devices and a first row decoding circuit configured to select a row from among the N rows of the block of rows associated with the selected first locking device.

[0040] According to one embodiment, the block decoding circuit is connected to the initialization input of each first locking device and the first row decoding circuit comprises, within each first control circuit, a first logic gate connected as input on the one hand to the first circuit input and on the other hand to a first decoding input capable of receiving a row decoding signal, this first logic gate being connected as output to the second input of the EXCLUSIVE NOT OR logic gate.

[0041] According to one embodiment, all the memory cell selection transistors of the same row are driven by a second drive signal from a second RS type latch device associated with said row.

[0042] The row decoder is then configured to, in order to program a data item into a memory word, select the row containing this memory word and the memory device then comprises second row-driving means, associated with said selected row, and configured to, in order to program the data in the memory word, confer a selection voltage to the second driving signal.

[0043] The second control means advantageously comprise a second control circuit having a first circuit input connected to the output terminal of the second locking device and a second circuit output capable of delivering the second control signal.

[0044] Again, this second control circuit is connected downstream of the second locking device.

[0045] And, the second control circuit here advantageously comprises a second inverter whose output is connected to the second circuit output.

[0046] According to one embodiment, each pair formed by the first locking device and the second locking device is associated with the same block of N rows.

[0047] The memory device then comprises, for each second locking device, N second row-driving means respectively associated with the N rows of the block of rows associated with this second locking device and the row decoder comprises, in addition to the block decoding circuit configured to select a pair of first and second locking devices from among the M pairs, a second row decoding circuit configured to select a row from among the N rows of the block of rows associated with the selected second locking device.

[0048] According to one embodiment, the block decoding circuit is connected to the initialization input of each second locking device and the second row decoding circuit comprises within each second control circuit a second logic gate connected at the input on the one hand to the first circuit input and on the other hand to a second decoding input capable of receiving a row decoding signal, this second logic gate being connected at the output to the second inverter.

[0049] The first logic gate and the second logic gate are advantageously NAND gates.

[0050] It is possible to use any type of conventional and known locking device, such as for example those which use a 6-transistor scheme of the volatile memory point type (SRAM).

[0051] Such locking devices are initialized (“set” in English) or reset (“reset” in English) under the nominal supply voltage Vdd of the integrated circuit, which requires a conductivity of the N channels of the NMOS transistors to be much higher than the conductivity of the P channels of the PMOS transistors.

[0052] This conductivity condition is obtained by adjusting the width / length (W / L) of the transistors.

[0053] However, it is planned to use low-power memories powered under a supply voltage Vdd of the order of 1.2 volts or less in the future.

[0054] However, the conductivity condition mentioned above requires, for slow NMOS transistors and fast PMOS transistors, a large channel length for the PMOS transistors or a large channel width for the NMOS transistors.

[0055] It is therefore necessary to size the transistors as indicated above in the event that certain transistors actually produced turn out to be slow NMOS transistors and / or fast PMOS transistors.

[0056] This therefore leads to an increase in the size of the transistors as well as to significant gate capacitances.

[0057] Furthermore, if some transistors actually produced turned out to be fast NMOS transistors and / or slow PMOS transistors, slow switching of the latch device between the delivery of the high voltage and the delivery of the low voltage and vice versa would be obtained, because the PMOS transistors would then be undersized and would then conduct a very low current.

[0058] Thus, current SRAM type latch devices cannot operate at a voltage Vdd which would be equal to the greater of the threshold voltage of the NMOS transistors and the absolute value of the threshold voltage of the PMOS transistors.

[0059] They also exhibit very unstable operation at a low voltage Vdd in the limit transistor configurations (speed or slowness of MOS transistors), which leads to an increase in the gate surface area and an increase in the risk of breakdown of the gate oxide, as well as in certain cases to a long switching time.

[0060] It is therefore preferable, in certain applications, to use a compact latch device, capable of operating under a low voltage Vdd, not presenting any current conflict between NMOS and PMOS transistors, and capable of reducing as much as possible the stresses in the gate oxides ("gate stress") of the PMOS transistors, such as for example a latch device of the type described in the French patent application filed under No. 2205502 to which the person skilled in the art may possibly refer.

[0061] Thus, it is advantageously proposed to use a controllable, fully CMOS RS flip-flop, in combination with a control module capable of managing the initialization and reinitialization of the flip-flop as well as the values ​​and the time sequencing of the different voltages used by the flip-flop in its different operating phases.

[0062] According to one embodiment, the locking device is capable, on command, of deliver and maintain on its output terminal either a high voltage, for example 15 volts, or a low voltage, for example 3.5 volts.

[0063] The locking device according to this embodiment comprises a latch flip-flop capable of being supplied between a first supply voltage and a second supply voltage lower than the first supply voltage.

[0064] The latch flip-flop has first and second flip-flop inputs and a flip-flop output connected to the output terminal of the latch device.

[0065] The locking device also includes a configured control module - to position the latch flip-flop in an initialized state or in a reset state when the first supply voltage has a first value (for example a Vdd value equal to 1.2 volts or even less) lower than the low voltage then, - the latch flip-flop being positioned to confer the high voltage to the first supply voltage and the low voltage to the second supply voltage and to deliver simultaneously from a delivery instant, to the two flip-flop inputs, two input voltages corresponding in theory to a forbidden logic state, under delivery conditions such that these two input voltages do not in reality translate for said flip-flop into the forbidden logic state, so as to deliver and maintain on the flip-flop output the high voltage or the low voltage (depending on the initial positioning "initialized" or "reinitialized" of the flip-flop).

[0066] Those skilled in the art know that a forbidden logic state for an RS flip-flop results in the simultaneous application of an initialization (“set”) and reset condition to the two flip-flop inputs.

[0067] When the RS flip-flop comprises NOR logic gates, this forbidden logic state results in the application of two voltages to the two flip-flop inputs seen by the NMOS transistors of the flip-flop whose gates are connected to these two flip-flop inputs, as logic states “1”.

[0068] But the conditions for delivering these two input voltages are such that they actually make it possible to avoid the forbidden logic state.

[0069] By way of example, these delivery conditions include, at the instant of delivery and subsequently, the satisfaction of a relationship between the values of these two input voltages, the value of the second supply voltage, and the threshold voltage of the NMOS transistors of the flip-flop whose gates are connected to the two flip-flop inputs.

[0070] The high voltage and the low voltage have values corresponding to those used in erase or program phases of non-volatile memory cells.

[0071] The first value of the first supply voltage is at least equal to the largest value between the threshold voltage of the NMOS transistors and the value absolute of the threshold voltage of the PMOS transistors of the locking device.

[0072] It is also advantageously less than or equal to 1.2 Volts.

[0073] According to one embodiment, the latch flip-flop comprises a first logic gate and a second logic gate, advantageously NOR gates.

[0074] According to one embodiment, the first logic gate has a first gate input coupled to the first flip-flop input, a second gate input and a first gate output.

[0075] The second logic gate has a first gate input coupled to the first gate output, a second gate input coupled to the second flip-flop input, and a second gate output coupled to the second gate input of the first logic gate and the flip-flop output.

[0076] The first and second logic gates comprise NMOS transistors having their gate connected to the first flip-flop input or to the second flip-flop input and the control module is advantageously configured to, when the flip-flop is positioned (in its initialized or reset state), deliver from said delivery time, on each flip-flop input said corresponding input voltage having a value lower than the value of the second supply voltage increased by the threshold voltage of the NMOS transistors.

[0077] This makes it possible to obtain a gate-source voltage of these transistors lower than their threshold voltage, which blocks them and therefore avoids the forbidden logic state of the flip-flop while avoiding leaks from these NMOS transistors.

[0078] It would be possible to deliver at said delivery time and at least temporarily, on each flip-flop input said input voltage having a value equal to the value of the second supply voltage increased by the threshold voltage of the NMOS transistors. A forbidden logic state would still not be obtained because such input voltages would not be seen as representative of a logic state "1" but this would generate current leaks at the level of the NMOS transistors.

[0079] According to one embodiment, the control module comprises a first NAND logic gate, capable of being supplied between a first auxiliary voltage and a second auxiliary voltage.

[0080] The first logic gate has a first gate input capable of receiving a latch initialization logic signal, a second gate input capable of receiving a control signal, and a first gate output coupled to the first latch input.

[0081] The control module also comprises a second NAND logic gate, capable of being supplied between the first auxiliary voltage and the second auxiliary voltage.

[0082] This second NAND logic gate has a first gate input capable of receiving the control signal, a second gate input adapted to receive a latch reset logic signal, and a second gate output coupled to the second latch input.

[0083] The control module also comprises control means configured to, depending on different operating phases of the flip-flop (for example flip-flop in the inactive state, initialization of the flip-flop, reinitialization of the flip-flop, and once the flip-flop is initialized or reinitialized, delivery and maintenance at the output of the high voltage or the low voltage of the latch flip-flop), - assign a logical value to the control signal, -deliver the initialization signal in its active or inactive logic state, -deliver the reset signal in its inactive or active logic state, and -manage the values ​​of the first supply voltage, the second supply voltage, the first auxiliary supply voltage and the second auxiliary supply voltage.

[0084] Other advantages and characteristics of the invention will appear on examining the detailed description of modes of implementation and embodiment, which are in no way limiting, and the appended drawings in which:

[0085] [Fig.l]

[0086] [Fig.2]

[0087] [Fig.3]

[0088] [Fig.4]

[0089] [Fig.5]

[0090] [Fig.6]

[0091] [Fig.7], and

[0092] [Fig. 8]

[0093] schematically illustrate embodiments and implementations of the invention.

[0094] In [Fig.l], the reference DM designates a non-volatile memory device with a shared voltage type architecture comprising a matrix memory plane PM comprising rows and columns of memory cells CEL.

[0095] A row decoder RDEC as well as a column decoder CDEC, of ​​classic structure, are associated with this memory plane PM.

[0096] The row decoder, an example structure of which will be described in more detail below, is configured to select a row of the memory plane.

[0097] As schematically illustrated in [Fig.2], each memory cell comprises an access or selection transistor TA and a state transistor TR having a floating gate and a control gate.

[0098] All the access transistors TA of the same row of cells are connected by their respective grids to a word line WLj and are controlled on their grids by a signal WLj. (for simplification purposes, the word line and the signal delivered on this word line will be designated by the same reference WLj).

[0099] The sources of the state transistors TR are connected to a controlled source line SL whose potential is typically grounded during the erasure or reading phases but which is positive of the order of a few volts during the programming operations of these memory cells.

[0100] As illustrated in this [Fig.2], the memory plane PM typically comprises MTMi memory words on each row. Each MTMi memory word comprises several memory cells, here p memory cells.

[0101] Also, we speak of memory word columns.

[0102] Thus, the memory words MTMi located on each row belong to column i of memory words and the access transistors TA of the p memory cells of these memory words MTMi are respectively connected to bit lines BLp.i, BLp.i+1,... BLp.i+p-1.

[0103] As indicated above, the source line SL, dedicated to column i and therefore to the corresponding memory word MTMi, connects the sources of the state transistors TR of the memory word MTMi.

[0104] All the state transistors TR of the memory cells of a memory word MTMi are controlled on their gates by a control element CGSWij comprising here an inverter including an NMOS transistor TN and a PMOS transistor TP.

[0105] And, all the control elements CGSWij of the same row j are driven by a first driving signal CLj delivered on a line CLj (here again, for the purposes of simplification, the reference CLj of the line corresponds to the reference of the driving signal carried on this line).

[0106] As will be seen in more detail below, this first control signal CLj comes from a first RS type locking device, referenced DISV1, associated with row j, via first row control means MPLR1.

[0107] Similarly, the second control signal WLj comes from a second RS type locking device, referenced DISV2, via second row control means MPLR2.

[0108] If we now return to the inverter CGSWij, we see that the input of this inverter is controlled by the first control signal CLj.

[0109] The substrate of the transistor TP is biased by a voltage BP and the substrate of the transistor TN is biased by a voltage BN.

[0110] Furthermore, the source of the transistor TP is biased by a voltage DPi and the source of the transistor TN is biased by a voltage DNi.

[0111] As will be seen in more detail below, in order to write data into the word- MTMi memory, -the row decoder RDEC is configured to select row j containing this memory word, and -the first row control means MPLR1, associated with this selected row j, are configured to give the first control signal CLj an erasure voltage corresponding to a first logic state of the first control signal CLj then a programming voltage corresponding to a second logic state of the first control signal CLj, and this without modifying the state of the output terminal OUT of the first locking device DISV1 associated with this selected row j between the erasure and the programming of the memory word MTMi.

[0112] We will return in more detail below to the values ​​of the different voltages of this control signal CLj corresponding to its respective logic states.

[0113] Although it is possible to provide a first locking device and first row-control means per row j, it is particularly advantageous to provide, as illustrated very schematically in [Fig.3], a first locking device DISV1 associated with N rows, for example eight rows.

[0114] Thus, if the memory plane PM comprises R rows, with R equal to the product of M by N, we therefore have M blocks of N rows and M first locking devices DISV 1 respectively associated with the M blocks of N rows.

[0115] The first row-driving means MPLR1 then comprise N first structurally identical driving circuits CPLT0-CPLT7 (N is equal to 8 here), each having a first circuit input ECR1 connected to the output terminal OUT of the corresponding first locking device DISV 1. Furthermore, each first driving circuit has a circuit output SCR1 delivering the corresponding first driving signal CLj (j = 0 to 7).

[0116] Each first control circuit CLPTi also comprises a second circuit input ECR2 capable of receiving a first control signal controlHV delivered by a first control stage ETCM1.

[0117] And, as will be seen in more detail below, the logic state of the first control signal CLj depends on the value of the first control signal controlHV.

[0118] The first locking device DISV 1 has an initialization input Set and a reset input Reset.

[0119] The locking device is furthermore supplied between a first supply voltage Vplus and a second supply voltage Vminus which is lower than the supply voltage Vplus.

[0120] In erasure, once the latch device DIS1 has been initialized, the first supply voltage Vplus rises to a high voltage value, for example 15 volts, while the second supply voltage Vminus rises to a low voltage value, for example 15 volts. voltage, for example 3 volts.

[0121] For a selected row j, the voltage of the first control signal CLj, associated with this selected row, is equal to the low voltage, i.e. 3 volts in this example. This therefore corresponds to a low logic state.

[0122] During the programming operation which follows the erasure operation in the write cycle of the memory word considered, the first supply voltage Vplus is for example 3 volts while the second supply voltage Vminus is a negative voltage, for example equal to -5 volts.

[0123] And, for a selected row j, the value of the voltage of the signal CLj delivered on this selected row, is worth, in the programming step, 3 volts which corresponds to the high programming voltage Vplus. The first control signal CLj therefore has this time the high logic state.

[0124] We therefore see that between the erasure step and the programming step, the logic state of the first control signal has changed.

[0125] It has transitioned from low logic state to high logic state.

[0126] On the other hand, as will be seen in more detail below, this was done without the logic state of the output signal delivered on the output terminal OUT of the first locking device DISV1 having changed.

[0127] In fact, this change of logic state of the first control signal CLj was carried out thanks to the value of the first control signal controlHV.

[0128] During the erase operation, the selection of the column i containing the memory word MTMi is carried out using the value of the voltage Dpi.

[0129] More precisely, for a selected column, the Dpi value is equal to the high voltage, for example 15 volts while for an unselected column and a selected row, the value of this voltage is equal to 3 volts.

[0130] For the programming operation, the selection of column i containing the word MTMi located on the selected row is carried out using the value of the voltage DNi.

[0131] More precisely, this voltage is -5 volts to select column i of the selected row j while it is 3 volts to not select column i of a selected row.

[0132] The values ​​of the substrate voltages BN and BP are respectively 3 volts and 15 volts for an erasure operation, whether for a selected column and / or row or not.

[0133] For the programming operation, the values ​​of the voltages BN and BP are respectively -5 volts and 3 volts whether for the selection or non-selection of a column and / or a row.

[0134] We now refer more particularly to [Fig.4] to describe an example of the embodiment of a first CPLT0 control stage.

[0135] This comprises a logic gate PL2 of the EXCLUSIVE NOT OR type having a first gate input ENP1 connected to the first circuit input ECR1, via a logic gate PLI NOT AND and a second gate input ENP2 connected to the second circuit input ECR2, as well as a gate output connected to the input of a first inverter INV1 whose output is connected to the first circuit output SCRL

[0136] The logic gate PLI also receives on its other input, connected to a first decoding input EDC1, a first decoding signal P0HVCL0 making it possible to select or not the row associated with this first CPLTO control circuit.

[0137] The logic gate PLI thus forms a first row decoding circuit and allows, in combination with the first row decoding signal P0HVCL0, to select or not this row.

[0138] More precisely, if the logic value of the first decoding signal P0HVCL0 is equal to 1, the row is selected. On the other hand, if this logic value is equal to 0, the row is not selected.

[0139] If we now refer more particularly to [Fig.5], we see that the row decoder comprises a CDCBLC block decoding circuit, here comprising an AND logic gate, connected at the output to the initialization input Set of the first locking device DISV1.

[0140] In this example, a first input of the AND gate CDCBLC receives a PI wire among eight. A second input receives a P2 wire among eight which makes it possible to select a DISV1 locking device among M (M=64 here) devices.

[0141] The combination of this CDCBLC gate and the NON AND PLI gate of the CPLT1 control circuit therefore makes it possible to select a row from among 512 rows.

[0142] The reset input Reset of the first locking device DISV 1 is capable of receiving a reset signal RstCL.

[0143] As indicated above, a write cycle in a memory word begins with an erasure phase of this memory word.

[0144] In this regard, for erasure, after the first locking device has been initialized, it will deliver on its output terminal OUT the voltage Vplus (15 volts). The logic output of the output terminal OUT is therefore the high state.

[0145] The corresponding row having been selected (the signal POHVCL0=1), the output of the NOT AND PLI gate is equal to 0.

[0146] The first control signal controlHV also has a low logic state. As a result, the output of the EXCLUSIVE NOR gate PL2 has a high logic state (the delivered voltage is the voltage Vplus equal to 15 volts).

[0147] Therefore, the output of the inverter INV1 is in the low state (voltage equal to 3 volts). Therefore, the first control signal CL0 has a low logic state and a voltage equal to Vminus (3 volts).

[0148] For the programming phase, the first locking device DISV1 is this time powered between the voltage Vplus (3 volts) and the voltage Vminus (-5 volts). The output of the first locking device delivers the voltage Vplus (3 volts) which again corresponds to a high logic state of this output signal.

[0149] The output of the logic gate NOT AND PLI is therefore always 0. However, this time, the first control signal controlHV has a voltage equal to Vplus which corresponds to its high logic state. Consequently, the output of the logic gate PL2 is in the low logic state. Consequently, the output of the first inverter INV1 is in the high logic state (it has the voltage Vplus equal to 3 volts).

[0150] The same applies to the first control signal CL0 which has the voltage Vplus corresponding to the high state of this signal.

[0151] There has therefore been between the erasure and the programming of the memory word a modification of the logic state of the first control signal CL0 without modification of the logic state of the output terminal OUT of the first locking device DISV1.

[0152] We now refer more particularly to [Fig.6].

[0153] All the memory cell selection transistors of the same row are driven by a second drive signal WL0 (for row 0). This second drive signal comes from a second RS type latch device DISV2, which may have a structure similar to that of the first device DISV1.

[0154] In order to program data into a memory word, -the row decoder is configured to select the row containing this memory word, and, as illustrated in [Fig.2], - second row control means MPLR2 associated with the selected row are configured to provide the second control signal WLj with a selection voltage, which is typically a high voltage, for example 13 volts.

[0155] As illustrated in [Fig.6], these second row-drive means MPLR2 comprise a second drive circuit CPTL20 having, with the exception of the EXCLUSIVE NOT OR logic gate, a structure similar to that of the first drive circuit CPTL0.

[0156] More precisely, a NAND logic gate PL12, forming a second row decoding circuit receiving on an input connected to a second decoding input EDC2, a second decoding signal P0HVWL0, is connected on its other input to the first circuit input ECR12 itself connected to the output of the corresponding second latch device DISV2.

[0157] The output of gate PL12 is connected to the input of a second inverter INV2 whose output is connected to the output of circuit SCR 12 which delivers the second control signal WL0 (for row 0).

[0158] Although it is possible to use, for the locking devices DISV1 and DISV2, any type of locking device, for example a locking device of the SRAM type, it is particularly advantageous to use a locking device of the type described in the aforementioned French patent application No. 2205502 and an example of embodiment of which is illustrated in [Fig.7].

[0159] This DISV latch device comprises a latch flip-flop of the RS type referenced BSV, supplied between the first supply voltage Vplus and the second supply voltage Vminus and having a first flip-flop input A, a second flip-flop input B and a flip-flop output 0UTN2 connected to the output terminal OUT.

[0160] Here the flip-flop output 0UTN2 forms the output terminal OUT of the DISV device.

[0161] The BSV latch comprises a first logic gate N0R1 and a second logic gate N0R2, which here are NOR gates.

[0162] The first logic gate N0R1 has a first gate input ENR10 coupled to the first flip-flop input A, a second gate input ENR11 and a first gate output OUTN1.

[0163] The second logic gate N0R2 has a first gate input ENR20 coupled to the first gate output OUTN1, a second gate input ENR21 coupled to the second flip-flop input B and the second gate output OUTN2 coupled to the second gate input ENR11 of the first logic gate N0R1 as well as to the flip-flop output OUT.

[0164] The device DISV also comprises a control module MCM configured in particular to position the latch flip-flop BSV in an initialized state or in a reset state when the first supply voltage Vplus has a first value Vdd which is lower than the low voltage LV and which can be as low as the largest value between the threshold voltage of the NMOS transistors of the device and the absolute value of the threshold voltage of the PMOS transistors of the device, for example of the order of 0.9 volts.

[0165] When the flip-flop BSV is positioned in its “initialized” or “reset” state, the control module is configured to impart the high voltage HV to the first supply voltage Vplus and the low voltage LV to the second supply voltage Vminus and to deliver and maintain on the flip-flop output OUTN2 the high voltage HV or the low voltage LV, depending on the initial positioning state of the flip-flop.

[0166] In this regard, the control module is configured to deliver simultaneously at a delivery time and subsequently, to the two flip-flop inputs A and B, two input voltages corresponding in theory to a forbidden logic state, but under delivery conditions such that these two input voltages do not translate into reality for said flip-flop by the forbidden logic state.

[0167] The forbidden logic state is a state which results in the simultaneous application of an initialization (“set”) and reset condition to the two flip-flop inputs A and B.

[0168] In the example described, the BSV flip-flop comprises NOR gates.

[0169] Consequently, the forbidden logic state is translated in theory for such a flip-flop, by the application of two voltages to the two flip-flop inputs seen by the NMOS transistors of the flip-flop whose gates are connected to these two flip-flop inputs A and B, as representative of a logic state “1”.

[0170] As an example, the delivery conditions mentioned above (leading to this theoretical forbidden logic state not being translated in reality for the flip-flop by the forbidden logic state) include the satisfaction at said delivery time and subsequently, of a relationship between the values ​​of these two input voltages, the value of the second supply voltage and the threshold voltage of the NMOS transistors of the flip-flop whose gates are connected to the two flip-flop inputs.

[0171] More precisely, the first and second logic gates NOR1 and NOR2 comprise NMOS transistors having their gate connected to the first flip-flop input A or to the second flip-flop input B and the control module is advantageously configured to, when the flip-flop is positioned (in its initialized or reset state), deliver from said delivery time, on each flip-flop input said corresponding input voltage having a value lower than the value of the second supply voltage increased by the threshold voltage of the NMOS transistors.

[0172] These delivery conditions make it possible to obtain a gate-source voltage of these transistors lower than their threshold voltage, which blocks them and therefore avoids the forbidden logic state of the flip-flop while avoiding leaks from these NMOS transistors.

[0173] Hardware-wise, the control module comprises for example a first NAND logic gate referenced NAND1, powered between a first auxiliary voltage VdVp and a second auxiliary voltage VgVm, and coupled at the output to the first flip-flop input A.

[0174] The control module also comprises a second NAND logic gate referenced NAND2, supplied between the first auxiliary voltage VdVp and the second auxiliary voltage VgVm, and coupled at the output to the second flip-flop input B.

[0175] The first NAND logic gate NAND1 has a first gate input END 10 capable of receiving a logic signal SetN for initializing the latch, a second gate input END11 capable of receiving a control signal NoGsN, and a first gate output OUTD1 coupled to the first flip-flop input A.

[0176] The second NAND logic gate NAND2 has a first gate input END20 capable of receiving the control signal NoGsN, a second gate input END21 capable of receiving a logic signal ResetN for resetting the latch flip-flop, and a second gate output OUTD2 coupled to the second flip-flop input B.

[0177] The control module MCM also comprises control means MCTRL configured to, depending on different operating phases of the latch flip-flop, assign a logic value to the control signal NoGsN, deliver the initialization signal SetN in its active or inactive logic state, deliver the reset signal ResetN in its inactive or active logic state and manage the values ​​of the first supply voltage Vplus, the second supply voltage Vminus, the first auxiliary supply voltage VdVp and the second auxiliary supply voltage VgVm.

[0178] This management, carried out for example in particular by a state machine, includes a time sequencing of these different voltage values.

[0179] [Fig.8] illustrates an example of using these locking devices of [Fig.7] in a configuration of the type illustrated in [Fig.6].

[0180] More precisely, each first locking device DISV1 is controlled by the control signal CLnoGsN while each second locking device DISV2 is controlled by the control signal WLnoGsN.

[0181] The inputs END10 and END21 of the two NAND gates NAND1 and NAND2 respectively receive a reset signal PCRN. The output of the logic gate NAND CDCBLC (which here allows a block of two devices DISV1 and DISV2 to be selected from 64 blocks) is connected to the gate inputs END22 and END13 of the two NAND gates NAND12 and NAND11 of these two latch devices so as to initialize these devices.

[0182] The NOR gates of the DISV2 latch device and the gates of the CPLT20-CPLT27 driver circuits are powered between the VWLdec voltage and the SW_gnd2 voltage.

Claims

Claims

1. Non-volatile memory device with a “shared voltage” type architecture, comprising a matrix memory plane (PM) comprising columns of memory words, these memory words (MTMi) being formed respectively on each row of the memory plane by groups of memory cells, each memory cell comprising a state transistor (TR) having a control gate and a floating gate and a selection transistor (TA), all the state transistors of the memory cells of a memory word being controlled on their gate by a control element (CGSWij), all the control elements of the same row being driven by a first drive signal (CLj) from a first RS-type latch device (DISV1) associated with said row, a row decoder (RDEC) configured to, in order to write data into a memory word, select the row containing this memory word and first row-drive means (MPLR1),associated with said selected row and configured to, in order to write the data in the memory word, give the first control signal (CLj) an erasure voltage corresponding to a first logic state of the first control signal then a programming voltage corresponding to a second logic state of the first control signal (CLj) without modifying the state of the output terminal (OUT) of the first locking device (DISV1) associated with this selected row between the erasure and the programming of the memory word.,

2. Memory device according to claim 1, wherein the first row-drive means (MPLR1) comprises a first drive circuit (CPLTO) having a first circuit input connected to the output terminal of the first latch device, a second circuit input capable of receiving a first control signal (ControlHV) and a first circuit output capable of delivering the first drive signal (CLj) whose logic state depends on the value of the first control signal, and a first control stage (ETCM1) configured to deliver this first control signal.

3. A memory device according to claim 2, wherein said first driving circuit comprises -a logic gate of the EXCLUSIVE NOR type (PL2) having a first gate input connected to said first circuit input, a second gate input connected to the second circuit input and a gate output, and -a first inverter (INV1) connected between the gate output and the first circuit output.

4. Memory device according to one of the preceding claims, in which the memory plane comprises R rows, and the memory device comprises -M first lock devices (DISV1), each first lock device being associated with a block of N rows, R being equal to the product of N by M, as well as -for each first lock device, N first row-driving means respectively associated with the N rows of the block of rows associated with this first lock device, and the row decoder comprises a block decoding circuit (CDCBLC) configured to select a first lock device from among the M first lock devices and a first row decoding circuit (PLI) configured to select a row from among the N rows of the block of rows associated with the selected first lock device.

5. Memory device according to claims 3 and 4, wherein the block decoding circuit (CDCBLC) is connected to the initialization input of each first latch device (DISV1) and the first row decoding circuit comprises within each first control circuit, a first logic gate (PLI) connected as input on the one hand to the first circuit input and on the other hand to a first decoding input (EDC1) capable of receiving a row decoding signal (POHVCLO), and connected as output to the second gate input of the EXCLUSIVE NOT OR logic gate.

6. Memory device according to one of the preceding claims, in which all the selection transistors of the memory cells of the same row are driven by a second driving signal (WLj) from a second RS type latch device (DISV2) associated with said row, the row decoder being configured to, in order to program a data item in a memory word, select the row containing this memory word and the memory device comprises second row driving means (MPLR2), associated with said selected row and configured to, in order to program the data item in the memory word, confer a selection voltage to the second driving signal (WLj).

7. Device according to claims 2 and 6, in which the second row-driving means comprise a second driving circuit (CPLT20) having a first circuit input connected to the output terminal of the second locking device and a second circuit output capable of delivering the second driving signal.

8. A memory device according to claim 7, wherein said second driving circuit comprises a second inverter (INV2) whose output is connected to the second circuit output.

9. Memory device according to one of claims 6 to 8, taken in combination with claim 4, in which each pair formed by the first locking device (DISV1) and the second locking device (DISV2) is associated with the same block of N rows, and the memory device comprises for each second locking device, N second row-driving means respectively associated with the N rows of the block of rows associated with this second locking device, and the row decoder comprises, in addition to the block decoding circuit (CDCBLC) configured to select a pair of first and second locking devices from among the M pairs, a second row decoding circuit (PL 12) configured to select a row from among the N rows of the block of rows associated with the selected second locking device.

10. Memory device according to claim 9, in which the block decoding circuit (CDCBLC) is connected to the initialization input of each second locking device and the second row decoding circuit comprises within each second driving circuit, a second logic gate (PL 12) connected at the input on the one hand to the first circuit input and on the other hand to a second decoding input (EDC2) capable of receiving a row decoding signal (P0HVWL0) and connected at the output to the second inverter.

11. A memory device according to claims 5 and 10, wherein the first logic gate (PLI) and the second logic gate (PL 12) are NAND gates.

12. Memory device according to one of the preceding claims, in which the first latch device is capable on command of delivering and maintaining on its output terminal (OUT) either a high voltage or a low voltage, and comprises - a first RS type latch flip-flop (BSV) capable of being supplied between a first supply voltage (Vplus) and a second supply voltage (Vminus) lower than the first supply voltage and having a first (A) and a second (B) flip-flop input and a flip-flop output (0UTN2) connected to the output terminal (OUT), and - a control module (MCM) configured o to position the first latch flip-flop in an initialized state or in a reset state when the first supply voltage (Vplus) has a first value lower than the low voltage then, o the first latch flip-flop being positioned, to confer the high voltage to the first supply voltage (Vplus) and the low voltage to the second supply voltage (Vminus) and to deliver simultaneously from a delivery instant, to the two flip-flop inputs, two input voltages corresponding in theory to a forbidden logic state, under delivery conditions such that these two input voltages do not translate in reality for said first flip-flop by the forbidden logic state, so as to deliver and maintain on the flip-flop output the high voltage or the low voltage.

13. A memory device according to claim 12, wherein the control module comprises -a first NAND logic gate (NAND1), capable of being supplied between a first auxiliary voltage (VdVp) and a second auxiliary voltage (VgVm), having a first gate input (END 10) connected to the output of the block decoding circuit, a second gate input (END11) capable of receiving a third control signal (NoGsN), and a first gate output (OUTD1) coupled to the first flip-flop input (A), -a second NAND logic gate (NAND2), capable of being powered between the first auxiliary voltage (VdVp) and the second auxiliary voltage (VgVm), having a first gate input (END20) capable of receiving the third control signal (NoGsN), a second gate input (END21) capable of receiving a logic signal (ResetN) for resetting the first latch, and a second gate output (OUTD2) coupled to the second latch input (B), - control means (MCTRL) configured to, depending on different operating phases of the first latch, assign a logic value to the third control signal, deliver the reset signal in its inactive or active logic state and manage the values ​​of the first supply voltage (Vplus), the second supply voltage (Vminus), the first auxiliary supply voltage (VdVp) and the second auxiliary supply voltage (VgVm).

14. A memory device according to claim 12 or 13, taken in combination with claim 6, wherein the second latch device (DISV2) has a similar architecture to that of the first latch device (DISV1).

15. Memory device according to one of the preceding claims, being a memory device of the EEPROM type.

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