Piezoelectric substrate on insulator (POI) and process for manufacturing a piezoelectric substrate on insulator (POI)

Abstract

The invention relates to a piezoelectric substrate on insulation (POI) (130, 138, 144, 152, 166) comprising a support substrate (100) including a trapping layer (102) on a free surface (104) of the support substrate (100), a piezoelectric layer (106), an intermediate structure (110) positioned sandwiched between the piezoelectric layer (106) and the trapping layer (102) of the support substrate (100), wherein the intermediate structure (120) includes at least one Tantalate Oxide (Ta2O5)-based metallic element diffusion barrier layer (122, 122') having a thickness tEM greater than a predetermined thickness, said predetermined thickness being determined as a function of the thickness of the trapping layer (102) such that the dose of metallic element in the trapping layer (102) is below a predetermined threshold dose.The invention also relates to a method for manufacturing such a piezoelectric substrate on an insulator (POI) (130, 138, 144, 152, 166). Figure for the abstract: Figure 1.

Description

Title of the invention: Piezoelectric substrate on insulator (POI) and method for manufacturing a piezoelectric substrate on insulator (POI)

[0001] The invention relates to a piezoelectric substrate on insulator (POI) and a method for manufacturing such a piezoelectric substrate on insulator (POI).

[0002] A piezoelectric substrate on insulator (POI) is used for acoustic wave devices, such as sensors, filters or other, because it allows good performance thanks to better Q quality values ​​and electromechanical coefficients k compared to other state-of-the-art substrates.

[0003] Such a substrate comprises a thin layer of piezoelectric material on a dielectric layer, itself arranged on a support substrate. For certain applications, a trapping layer is placed between the support substrate and the dielectric layer. The trapping layer is typically a non-crystalline layer exhibiting structural defects such as dislocations, grain boundaries, amorphous zones, gaps, inclusions, and / or pores. These structural defects form traps for charges that may circulate in the material. The trapping layer thus exhibits high resistivity, resulting in reduced charge conduction within the layer, and consequently, a reduced current within the trapping layer. The trapping layer helps to reduce losses due to parasitic conduction effects at the interface between the support substrate and the dielectric layer.Indeed, the trapping layer serves to reduce the lifespan of charges in this region.

[0004] In the fabrication of such a piezoelectric substrate on insulation (POI), a donor substrate is used in which a piezoelectric material substrate is bonded to a handling substrate. The donor substrate then undergoes a piezoelectric substrate thinning step to form a thinner piezoelectric layer before being bonded to the support substrate. Finally, the transfer of a thin piezoelectric layer onto the support substrate is achieved mechanically or thermally at a fracture zone previously created in the piezoelectric layer of the donor substrate. A final heat treatment of the resulting POI is necessary to repair any damage to the transferred piezoelectric layer during the fracturing step.

[0005] However, this final annealing results in the diffusion of metallic elements (Li, Fe, Cu, Ni) from the piezoelectric layer to the trapping layer. When the metallic elements diffuse into the trapping layer, they will neutralize (occupying) electrical traps present in the trapping layer. This neutralization of the electrical traps in the trapping layer results in a degradation of the electrical performance of said trapping layer, in particular a reduction of the Q factor and radio frequency performance, and consequently also that of the POI substrate thus produced.

[0006] One object of the invention is thus to remedy the aforementioned drawbacks and in particular to design a piezoelectric substrate on insulator (POI) which has better characteristics for use in acoustic wave devices.

[0007] The object of the invention is realized by a piezoelectric substrate on insulation (POI) comprising a support substrate, in particular a silicon-based substrate, comprising a trapping layer on a free surface of the support substrate, in particular a layer based on polycrystalline or amorphous or porous silicon, a piezoelectric layer, in particular a layer of Lithium Tantalate (LiTaO3) or Lithium Niobate (LiNbO3) and an intermediate structure positioned sandwiched between the piezoelectric layer and the trapping layer of the support substrate, in which the intermediate structure comprises at least one diffusion barrier layer of metallic elements, in particular Lithium, based on Tantalum Oxide (Ta2O5) having a thickness tEM greater than a predetermined thickness,said predetermined thickness being determined as a function of the thickness of the trapping layer in such a way that the dose of metallic element in the trapping layer is less than a predetermined threshold dose, in particular a threshold dose of metallic element less than 10¹² at / cm², in particular less than 5*10⁻¹⁰ at / cm².

[0008] The presence of the metallic element diffusion barrier structure between the piezoelectric layer and the trapping layer reduces the diffusion of metallic elements from the piezoelectric layer to the trapping layer during the manufacturing process. This reduces the phenomenon of charge trapping in the trapping layer by metallic elements. The trapping layer in the final substrate (POI) therefore exhibits high resistivity, resulting in a substrate (POI) with improved performance.

[0009] The threshold thickness of the barrier layer is determined as a function of the thickness of the trapping layer and the threshold dose of metallic element present in the trapping layer for which the trapping layer still has electrical characteristics which allow a POI substrate with improved performance to be obtained.

[0010] According to one embodiment of the invention, the barrier layer may have a thickness of between 5 nm and 150 nm, and the thickness of the trapping layer is between 50 nm and 5 pm. The barrier layer is a much thinner layer than the trapping layer.

[0011] According to one embodiment of the invention, the intermediate structure may comprise at at least one dielectric layer, in particular based on silicon dioxide or silicon nitride (SiN) or silicon oxynitride (SiOxNy), in contact with at least one barrier layer. The dielectric layer ensures good adhesion in the POI substrate between the piezoelectric material and the supporting substrate.

[0012] According to a variant of the invention, the metallic element diffusion barrier layer can be positioned sandwiched between two dielectric layers.

[0013] According to one embodiment of the invention, the intermediate structure may further comprise a second barrier layer. A second barrier layer makes it possible to obtain a substrate (POI) with improved electrical characteristics and therefore with better performance for SAW applications. Indeed, the second barrier layer may be a second diffusion barrier layer of the same metallic element as the first diffusion barrier layer from the piezoelectric layer to the trapping layer, or the second barrier layer may be a diffusion barrier layer of a different metallic element than the first barrier layer in the composite substrate.

[0014] According to one embodiment of the invention, the second barrier layer can be a hydrogen diffusion barrier layer, in particular based on Silicon Oxynitride (SiOxNy), Silicon Nitride (SiN), or Aluminum Nitride (AIN). In a piezoelectric-on-insulator (POI) substrate, hydrogen diffusion into the piezoelectric layer and / or the trapping layer occurring during heat treatment steps in the manufacturing process of such a substrate also reduces the performance of the POI substrate. Thus, the presence of a hydrogen barrier layer makes it possible to reduce hydrogen diffusion within the POI substrate during its manufacturing and to obtain a POI substrate with improved performance.

[0015] According to one embodiment of the invention, the intermediate layer may comprise at least one layer with a hydrogen concentration below 10²⁰ at / cm³, in particular below 10¹⁸ at / cm³. A layer with a hydrogen concentration below 10²⁰ at / cm³ corresponds to a hydrogen diffusion barrier layer. Thus, the POI substrate has improved performance due to the presence of such a layer in its structure.

[0016] The object of the invention is also realized by a process for manufacturing a piezoelectric substrate on an insulator (POI) described above, comprising the steps of providing a support substrate, in particular a silicon-based substrate, comprising a trapping layer, in particular a layer based on polycrystalline, amorphous, or porous silicon; providing a substrate comprising a piezoelectric layer, in particular a piezoelectric layer based on Lithium Tantalate (LiTaO3) or Lithium Niobate (LiNbO3); and forming an intermediate structure on the substrate comprising a piezoelectric layer and / or on the support substrate, the formation of the intermediate structure comprising the formation of at least one barrier layer of metallic element, in particular Lithium, based on Tantalum Oxide (Ta2O5), the barrier layer having a thickness tEM greater than a predetermined thickness, said predetermined thickness being determined as a function of the thickness of the trapping layer in such a way that the dose of metallic element in the trapping layer is less than a predetermined threshold dose, in particular a threshold dose of metallic element, even more in particular a dose of Lithium, in particular a threshold dose less than 1.2* 1012 at / cm2, in particular less than 5*10" at / cm2, and assembling the substrate comprising a piezoelectric layer with the support substrate.

[0017] Thus, the step of forming an intermediate structure on the substrate comprising a piezoelectric layer and / or the supporting substrate in the process according to the invention makes it possible to form a barrier layer against the diffusion of metallic elements to reduce the diffusion of metallic elements from the piezoelectric layer to the trapping layer during the heat treatment steps of the process. With this process, a substrate can be obtained that effectively reduces the negative effect of the diffusion of metallic elements to the supporting substrate, and in particular to the trapping layer of the supporting substrate.

[0018] According to one embodiment of the invention, the intermediate structure formation step may further include the formation of a second barrier layer. The second barrier layer may be a barrier layer of metallic elements or a barrier layer of another element in the structure, in particular a non-metallic element. With this method, a substrate can be obtained that makes it possible to reduce even more effectively the negative effect of element diffusion towards the supporting substrate by reducing both the diffusion of metallic elements from the piezoelectric layer and the diffusion of other elements into the structure of the POI substrate.

[0019] According to one embodiment of the invention, the intermediate structure formation step may further include a layer formation step with a hydrogen concentration below 10²⁰ at / cm³, in particular below 10¹⁸ at / cm³. The formation of a layer with a reduced hydrogen concentration limits hydrogen diffusion into the structure during subsequent heat treatment, a treatment known to facilitate hydrogen diffusion towards the piezoelectric layer and / or the trapping layer.

[0020] According to one embodiment of the invention, the step of forming the second barrier layer may include the formation of a layer based on Silicon Nitride (SiN), Silicon Oxynitride (SiOxNy), or Aluminum Nitride (AIN). A layer based on such a material makes it possible to create a hydrogen diffusion barrier. towards the piezoelectric layer and / or the trapping layer.

[0021] According to one embodiment of the invention, the process may further comprise a step of forming a dielectric layer on the support substrate and / or on the substrate comprising a piezoelectric layer before the assembly step, such that the bonding interface is an oxide-oxide interface. The assembly interface of the support substrate with the substrate comprising a layer is made at the interface between two dielectric layers, with oxide-oxide bonds, in particular a Si-O-Si bond, which is a type of bond known to be stable. Thus, the piezoelectric substrate on insulation obtained by the process according to the invention exhibits a stable bond between the piezoelectric layer and the support substrate.

[0022] According to one embodiment of the invention, the manufacturing process may further comprise a step of forming a dielectric layer of a first material on the substrate and / or of a second material different from the first material on the substrate comprising a piezoelectric layer before the assembly step. For example, the first material is based on Silicon Nitride, in particular Si3N4, and the second material is based on Silicon Oxynitride (SiOxNy), in particular SiON. Thus, the bonding interface is a Si3N4-SiOxNy bonding interface. Such an interface offers advantages in terms of the acoustic impedance of the fabricated structure while also being a stable assembly interface.

[0023] The invention and its advantages will be explained in more detail below by means of preferred embodiments and with reference in particular to the following accompanying figures, in which the reference numbers identify features of the invention.

[0024] [Fig.1] schematically represents a method for manufacturing a piezoelectric substrate on insulator (POI) according to a first embodiment of the invention.

[0025] [Fig.2a] schematically represents a process for manufacturing a piezo substrate electrical on insulation (POI) according to a second embodiment of the invention.

[0026] [Fig.2b] schematically represents a process for manufacturing a donor substrate and a donor substrate according to a first variant of the second embodiment of the invention.

[0027] [Fig.2c] schematically represents a process for manufacturing a piezo substrate electrical on insulation (POI) according to a second variant of the second embodiment of the invention.

[0028] [Fig.3] schematically represents a process for manufacturing a piezo substrate electrical on insulation (POI) according to a third embodiment of the invention.

[0029] The invention will be described in more detail using advantageous embodiments in an exemplary manner and with reference to the drawings. The embodiments The described configurations are simply possible configurations and it should be borne in mind that the individual features as described above may be provided independently of each other or may be omitted altogether when implementing the present invention.

[0030] Fig. 1 schematically illustrates a method for manufacturing a piezoelectric substrate on insulator (POI) according to the first embodiment of the invention.

[0031] The process for manufacturing a piezoelectric substrate on an insulator (POI) begins with step I) of providing a support substrate 100, in particular a bulk substrate. A bulk substrate is a substrate based on a single material typically with a thickness between 200 µm and 1 mm.

[0032] The support substrate 100 may be a substrate based on Silicon, Sapphire, Aluminum Nitride (AIN), Silicon Carbide (SiC), or Gallium Arsenide (GaAs). The support substrate 100 may be a crystalline or polycrystalline substrate.

[0033] The support substrate 100 comprises a trapping layer 102 deposited on a free surface 104 of the support substrate by a deposition technique, for example, atmospheric pressure vapor deposition (LPCVD) or plasma-assisted or non-plasma-assisted chemical vapor deposition (CVD). The deposition temperature is between 200°C and 1100°C. The trapping layer 102 is a silicon-based layer, for example, based on polycrystalline silicon, amorphous silicon, or porous silicon, polished or unpolished. The thickness tp of the trapping layer 102 is between 5 nm and 5 pm.

[0034] The trapping layer 102 is therefore a non-crystalline layer exhibiting structural defects such as dislocations, grain boundaries, amorphous zones, interstices, inclusions, and / or pores. These structural defects form traps for charges that may circulate within the material, for example, at incomplete or dangling chemical bonds. The trapping layer 102 thus exhibits high resistivity, resulting in reduced charge conduction within the layer, and consequently, a reduced current within the trapping layer.

[0035] In step II) of the process according to the first embodiment, a substrate comprising a piezoelectric layer 106 is provided. Preferably, this is a thick layer of piezoelectric material 108 of a thickness ti provided on a base substrate 110.

[0036] The piezoelectric material 106 can be a Lithium-rich piezoelectric material, for example, Lithium Tantalate (LiTaO3) or Lithium Niobate (LiNbO3).

[0037] The substrate comprising a piezoelectric layer 106 may have first undergone a or several steps of cleaning, brushing or polishing its free surface to remove particles or dust and thus obtain a cleaner and better quality free surface to subsequently carry out a successive layer deposition.

[0038] According to the invention, a step III) of depositing an intermediate structure 120 on the free surface 102a, preferably directly on the free surface 102a, of the trapping layer 102 of the support substrate 100 is carried out.

[0039] Step III) of deposition of the intermediate structure 120 includes the formation of at least one metal element diffusion barrier layer 122. The barrier layer 122 may be a Lithium 122 diffusion barrier layer.

[0040] The barrier layer 122 can, according to the invention, be an amorphous layer based on Tantalum Oxide (Ta2O5) deposited by an ALD (Atomic Layer Deposition) technique or by PE-ALD (Plasma Enhanced Atomic Layer Deposition or in French: Plasma-Activated Layer Deposition), or by LPCVD (Low Pressure Chemical Vapor Deposition), by MOCVD (Metal-Organic Chemical Vapor Deposition), or by PECVD (Plasma Enhanced Chemical Vapor Deposition).

[0041] In this case, the deposition temperature by ALD is between 25°C and 350°C or for LPCVD between 500 and 800°C, by MOCVD between 500 and 800°C or for PECVD between 250 and 400°C followed by a heat treatment at 700°C.

[0042] The barrier layer 122 has a thickness tEM greater than a predetermined thickness, said predetermined thickness being defined as a function of the thickness tp of the trapping layer 102 in such a way that the dose of metallic element in the trapping layer 102 is less than a threshold dose of metallic element causing the degradation of the trapping layer 102.

[0043] To calculate the threshold dose of metallic element, a person skilled in the art will be able to calculate the diffusion slope of the metallic element from its diffusion coefficient and thus adjust the thickness tEM of the barrier layer 122 in order to ensure that a predetermined dose threshold of metallic element in the trapping layer 102 is not exceeded. This calculation also depends on the heat treatments applied to the structure during the manufacturing process and also on the thickness of the trapping layer 102.

[0044] For example, for a layer of Lithium Tantalate (LiTaO3) or Lithium Niobate (LiNbO3) and for a trapping layer 102 having a thickness tp of 1 pm, the threshold dose of Lithium in the trapping layer 102 must be less than 10¹² at / cm². For a trapping layer 102 with a thickness tp of the order of 0.5 pm, the The threshold dose for Lithium will be more in the order of 5*10" at / cm2.

[0045] To obtain these values, the thickness tEM of the barrier layer 122 must be between 5nm and 150nm, in particular between lOnm and lOOnm.

[0046] During step lia) a weakening zone 112 is formed in the piezoelectric layer 108 of the substrate comprising a piezoelectric layer 106 so as to delimit the piezoelectric layer 114 to be transferred from the remainder 116 of the piezoelectric layer 108 of the substrate comprising a piezoelectric layer 106.

[0047] This step 1a) of forming a weakened zone 112 is carried out by implanting 118 atomic or ionic species into the piezoelectric layer 108 of the substrate comprising a piezoelectric layer 106. The atomic or ionic implantation is performed such that the weakened zone 112 is located within the piezoelectric layer 108 and separates a piezoelectric layer 116 from the remainder 114 of the piezoelectric layer 108. The atomic or ionic species are implanted at a determined depth t3 of the piezoelectric layer 108, which determines the thickness t3 of the piezoelectric layer 114 to be transferred. The thickness t3 is typically between 50 nm and 1.2 pm, in particular on the order of 800 nm. The implantation dose of atomic or ionic species is between 1016 at / cm2 and 1017 at / cm2.The support substrate 100 obtained after step III) is then assembled with the donor substrate 110 obtained after step 1a) during assembly step IV) to obtain a heterostructure 124 corresponding to the support substrate - donor substrate assembly. Here, the assembly occurs by molecular adhesion.

[0048] The assembly of the substrate comprising a piezoelectric layer 106 on the support substrate 100 is made such that the barrier layer 122 of the intermediate structure 120 is positioned sandwiched between the piezoelectric layer 114 of the substrate comprising a piezoelectric layer 106 and the trapping layer 102 of the support substrate 100. The contact interface 126 is located between the piezoelectric layer 114 and the intermediate structure 122 of the support substrate 100.

[0049] Next, a step V) of transferring the piezoelectric thin film 114 is carried out. For this, a step of fracturing the donor substrate 124 by supplying thermal energy, with a heat treatment between 100°C and 300°C in an atmosphere of Ar or N2, and / or mechanical at the level of the embrittlement zone 112 to obtain a POI substrate comprising a piezoelectric layer 114 of a thickness t3 typically between 50nm and Ipm, in particular on the order of 600nm.

[0050] A heat treatment of the piezoelectric substrate on insulation (POI) 122 obtained after step V) is carried out to repair the damage caused to the piezoelectric layer 114 transferred during the fracturing step. This heat treatment is carried out at a temperature between 400 and 600°C, in particular on the order of 500° C, in an atmosphere of Ar, O2 or N2.

[0051] During these heat treatments during the production of the POI substrate, a diffusion of metallic elements can take place from the piezoelectric layer 114 towards the trapping layer 102.

[0052] Thanks to the presence of the barrier layer 122, the diffusion of metallic elements from the piezoelectric layer 114 to the trapping layer 102 is reduced, since the barrier layer 122 acts as a barrier layer against the diffusion of metallic elements. Thus, the passivation of charge traps in the trapping layer 102 by metallic elements from the piezoelectric layer 114 is reduced, and the trapping layer 102 retains its ability to reduce parasitic currents.

[0053] In a variant of the process according to the first embodiment, the intermediate structure 120 is formed by a plurality of layers of Tantalum Oxide (Ta2O5) and layers based on another Oxide, for example a Silicon Oxide or a Silicon Nitride (SiN) or a Silicon Oxynitride (SiOxNy), intercalated with each other. The thickness of each Oxide layer is between 5 nm and 100 nm.

[0054] In a variant of the method according to the first embodiment, the intermediate structure 120, here the metallic element diffusion barrier layer 122, is formed on the piezoelectric layer 108 of the substrate comprising a piezoelectric layer 106 instead of being formed on the support substrate 100. In this case, the step of forming the barrier layer 122 is carried out before or after the step of forming the embrittlement zone 112 in the piezoelectric layer 108. The assembly interface of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is then made at the interface located between the barrier layer 122 of the substrate comprising a piezoelectric layer 106 and the trapping layer 102 of the support substrate 100.

[0055] In another embodiment of the method according to the first embodiment, the intermediate structure 120, here the barrier layer 122, can be provided on the substrate comprising a piezoelectric layer 106 and on the support substrate 100. In this case, the step of forming the barrier layer 122 is carried out before or after the step of forming the embrittlement zone 112 in the piezoelectric layer 108. The assembly interface of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is then made at the interface between two barrier layers. Assembling the substrate comprising a piezoelectric layer with the support substrate by assembling two barrier layers is advantageous for the assembly, since the assembly takes place between two layers of the same material.

[0056] In an embodiment of the process, instead of carrying out step 1a) of forming the embrittlement zone in the piezoelectric layer 108 of the substrate comprising a piezoelectric layer 106, after step III), step IV) of assembly is carried out directly between the substrate comprising a piezoelectric layer 106 and the substrate support 100. A thinning step IVa) (not illustrated) is then carried out to reduce the thickness of the substrate comprising a piezoelectric layer 106. This thinning step can be a grinding step of the substrate comprising a piezoelectric layer 106 to obtain a piezoelectric layer 114 of a thinner thickness than the piezoelectric layer 108.

[0057] In addition, other treatments of the free surface 128 of the piezoelectric layer 114 can be carried out to improve the quality of the free surface 128 of the piezoelectric layer 114.

[0058] The piezoelectric substrate on insulator (POI) 130 illustrated in step V) of [Fig.1] obtained with the support substrate 100, the trapping layer 102, the metallic element diffusion barrier layer 122 and the piezoelectric layer 114 corresponds to the substrate according to the invention according to the first embodiment also.

[0059] Fig. 2a schematically represents a method for manufacturing a piezoelectric substrate on insulator (POI) according to a second embodiment of the invention.

[0060] In this second embodiment, the only difference with the process according to the first embodiment is that the deposition step III) of the intermediate structure 120 includes in addition a step IIIa) of formation of a dielectric layer 132 on, in particular in direct contact with, at least one barrier layer 122. Thus, the intermediate structure 120 comprises a barrier layer for diffusion of metallic element 122 and a dielectric layer 132.

[0061] The other steps I) to V) are the same as in the first embodiment, except that in step IV) the assembly is carried out between the dielectric layer 132 and the substrate comprising a piezoelectric layer 106. All features common with the first embodiment and its variant and using the same reference numbers as above will not be described again, but reference is made to their detailed description above.

[0062] The dielectric layer 132 is, for example, a silicon oxide-based layer. But the dielectric layer 132 can also be a Silicon Nitride (Si3N4) layer, or a layer comprising a combination of Silicon Nitride and Silicon Oxide (SiOxNy), or a superposition of a Silicon Oxide layer and a combination of Silicon Nitride and Silicon Oxide (SiOxNy), or a superposition of a Silicon Oxide layer and a Silicon Nitride layer.

[0063] The dielectric layer 132 is produced by a deposition technique such as chemical vapor deposition (CVD) or low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD), or by oxidation heat treatments. PVD deposition involves deposition temperatures between ambient temperature and 400°C, while PECVD involves deposition temperatures between 150°C and 400°C. LPCVD deposition involves deposition temperatures between 600 and 700°C. The dielectric layer 132 is deposited on, in particular in direct contact with, the barrier layer 122.

[0064] A heat treatment, also called densification treatment, can be carried out after the deposition of the dielectric layer 132 to degas the excess Hydrogen formed during deposition, Hydrogen which occupies the traps in the trapping layer 102. In addition, or as an alternative, a surface treatment can be carried out to improve the quality of the surface of the deposited dielectric layer 132.

[0065] The dielectric layer 132 is, for example, a layer based on Silicon dioxide. But the dielectric layer 132 can also be a layer comprising a combination of Silicon Nitride and Silicon Oxide (SiOxNy), or a superposition of a Silicon Oxide layer and a combination of Silicon Nitride and Silicon Oxide (SiOxNy), or even a Silicon Nitride (Si3N4) layer, or a layer comprising a combination of Silicon Nitride and Silicon Oxide (SiOxNy), or a superposition of a Silicon Oxide layer and a Silicon Nitride layer.

[0066] Thus, during the assembly step V), the substrate comprising a piezoelectric layer 106 is assembled with the support substrate 100 to form the heterostructure 134, by bringing the dielectric layer 132 into contact with the piezoelectric layer 108 of the substrate comprising a piezoelectric layer 106. Thus, in this second embodiment, the assembly interface 136 is located between the piezoelectric layer 108 and the dielectric layer 132 of the support substrate 100.

[0067] In one embodiment, the dielectric layer 132 may be a layer having a hydrogen concentration of less than 1020 at / cm3, in particular less than 1018 at / cm3. After the deposition step of the dielectric layer 132 carried out at a temperature typically between ambient temperature and 7000°C, depending on the deposition technique used, a densification annealing may be carried out to reduce the hydrogen concentration in this dielectric layer 132. For example, if the dielectric layer is produced by PVD deposition, the temperature is between ambient temperature and 400°C, for PECVD deposition, between 150°C and 400°C, for LPCVD deposition between 600°C and 7000°C, and for thermal oxidation, the temperature is between 800°C and 1000°C.

[0068] This annealing is performed under a low-hydrogen atmosphere, i.e., below 5 ppm, and exposes the silicon oxide-based dielectric layer 132 to a temperature well above its deposition temperature. This can be a neutral or oxidizing atmosphere. Preferably, this temperature is above 800°C, typically between 800°C and 100°C. The annealing is continued for at least one hour, and preferably for several hours, in order to exodiffuse the hydrogen from the dielectric layer 132, and possibly from the trapping layer 102. At the end of This densification annealing, the dielectric layer 132 has a hydrogen concentration of less than 1020 at / cm3.

[0069] In one embodiment, the dielectric layer 132 can be provided on the piezoelectric layer 108 of the substrate comprising a piezoelectric layer 106 instead of being provided on the support substrate 100. In this case, the step of forming the dielectric layer 132 is carried out after or before the step of forming the embrittlement zone 112 in the piezoelectric layer 108. In this case, the assembly of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is carried out at the interface between the dielectric layer 132 of the piezoelectric substrate 106 and the intermediate structure 120 of the support substrate 100.

[0070] In another embodiment, a dielectric layer can be provided on both substrates, the substrate comprising a piezoelectric layer 106 and on the support substrate 100. In this case, the step of forming the dielectric layer is carried out before or after the step of forming the embrittlement zone 112 in the piezoelectric layer 108. The assembly of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is then carried out at the interface between two dielectric layers.

[0071] For example, with oxide-oxide type bonds, in particular a Si-O-Si type bond, which allows for a stable molecular force bond.

[0072] In another embodiment, a dielectric layer of a first material may be provided on the substrate comprising a piezoelectric layer 106, and a dielectric layer of a second material may be provided on the support substrate 100, the first material being different from the second material. For example, the dielectric layer provided on the substrate comprising a piezoelectric layer 106 is a Si3N4 layer, while the dielectric layer provided on the support substrate 100 is a SiOxNy layer, in particular SiON. Thus, the assembly of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is then carried out at the interface between two Si3N4-SiOxNy dielectric layers, which allows for a stable bond.

[0073] In one embodiment, the dielectric layer 132 and the barrier layer 122 of the intermediate structure 120 can be provided on the piezoelectric layer 108 of the substrate comprising a layer 106 instead of being provided on the support substrate 100. In this case, the step of forming the intermediate structure 120 is carried out before or after the step of forming the embrittlement zone 112 in the piezoelectric layer 108. In this case, the assembly of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is carried out at the interface between the dielectric layer 132 of the intermediate structure 120 on the substrate comprising a piezoelectric layer 106 and the trapping layer 102 of the support substrate 100.

[0074] The piezoelectric substrate on insulator (POI) 138 illustrated in step V) of [Fig.2a] obtained with the support substrate 100, the trapping layer 102, the metallic element diffusion barrier layer 122, the dielectric layer 132 and the piezoelectric layer 114 corresponds to the substrate according to the invention according to the second embodiment also.

[0075] In one embodiment, illustrated in [Fig. 2b], the formation step IIa) of a dielectric layer 132' is carried out before the formation step III) of at least one barrier layer 122'. The dielectric layer 132' and the barrier layer 122' are formed in the same way as the dielectric layer 132 and the barrier layer 122 described previously in [Fig. 2a]. Thus, the intermediate structure comprises the dielectric layer 132' and the metal element diffusion barrier layer 122'.

[0076] Thus, during the assembly step IV), the substrate comprising a piezoelectric layer 106 is assembled with the support substrate 100 to form the heterostructure 140 by bringing the barrier layer 122' into contact with the piezoelectric substrate 106. Thus, in this variant, the assembly is carried out at the interface 142 between the substrate comprising a piezoelectric layer 106 and the barrier layer 122' of the support substrate 100.

[0077] In one embodiment, the barrier layer 122' can be provided on the piezoelectric layer 108 of the substrate comprising a layer 106 instead of being provided on the support substrate 100. In this case, the step of forming the barrier layer 122' is carried out before or after the step of forming the embrittlement zone 112 in the piezoelectric layer 108. In this case, the assembly of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is carried out at the interface between the barrier layer 122' on the substrate comprising a piezoelectric layer 106 and the dielectric layer 132' of the support substrate 100.

[0078] In another embodiment, the barrier layer 122' can be provided on the substrate comprising a piezoelectric layer 106 and on the support substrate 100. In this case, the step of forming the barrier layer 122' is carried out before or after the step of forming the embrittlement zone 112 in the piezoelectric layer 108. The assembly of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is then carried out at the interface between the two barrier layers 122'.

[0079] In another embodiment, the barrier layer 122' and the dielectric layer 132' of the intermediate structure can be provided on the piezoelectric layer 108 of the substrate comprising a layer 106 instead of being provided on the support substrate 100. In this case, the intermediate structure formation step is carried out before or after the embrittlement zone 112 formation step in the piezoelectric layer 108. In this case, the assembly of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is carried out at the interface between the layer barrier 122' of the intermediate structure on the substrate comprising a piezoelectric layer 106 and the trapping layer 102 of the support substrate 100.

[0080] The piezoelectric substrate on insulator (POI) 144 illustrated in step V) of [Fig.2b] comprises in this order the support substrate 100, the trapping layer 102, the dielectric layer 132', the metallic element diffusion barrier layer 122' and the piezoelectric layer 114 according to this variant of the second embodiment of the invention.

[0081] In a second variant of the second embodiment illustrated in [Fig. 2c], a step IIlb) of forming a dielectric layer 146 is added compared to the embodiment illustrated in [Fig. 2b]. During this step, the dielectric layer 146 is formed on the piezoelectric layer 108 of the substrate comprising a piezoelectric layer 106 after the step lia) of forming the embrittlement zone 112 in the piezoelectric layer 108.

[0082] The dielectric layer 146 is, for example, a Silicon Oxide-based layer. But the dielectric layer 146 can also be a Silicon Nitride (Si3N4) layer, or a layer comprising a combination of Silicon Nitride and Silicon Oxide (SiOxNy), or a superposition of a Silicon Oxide layer and a Silicon Nitride layer or a combination of a Silicon Oxide layer, a Silicon Nitride layer and a Silicon Oxynitride (SiOxNy) layer.

[0083] The dielectric layer 146 is produced by a deposition technique such as chemical vapor deposition CVD or LPCVD, plasma-assisted PECVD or physical vapor deposition PVD or by oxidation heat treatment.

[0084] A surface treatment can be performed to improve the surface quality of the deposited dielectric layer 146. Thus, during assembly step IV), the substrate comprising a piezoelectric layer 106 is assembled with the support substrate 100 to form the heterostructure 148 by bringing the barrier layer 122' into contact with the dielectric layer 146. Thus, in this embodiment, the assembly is carried out at the interface 150 between the dielectric layer 146 of the substrate comprising a piezoelectric layer 106 and the barrier layer 122' of the support substrate 100. Thus, the barrier layer 122' is sandwiched between the two dielectric layers 132' and 146.

[0085] In the same way as in the variants of the process according to the first embodiment, the dielectric layer 146 can be provided on the support substrate 100 on the barrier layer 122' instead of being provided on the substrate comprising a piezoelectric layer 106. In this case, the assembly of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is made at the interface between the dielectric layer 146 of the support substrate 100 and the piezoelectric layer 108 of the substrate comprising a piezoelectric layer 106.

[0086] In the same way as in the other variants of the method according to the first mode In realization, the dielectric layer can be provided on the piezoelectric substrate 106 and on the support substrate 100. The assembly of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is then made at the interface between two dielectric layers of the same material, with oxide-oxide type bonds, in particular a Si-O-Si type bond, which allows a stable molecular force bond.

[0087] As in the other variants, a dielectric layer of a first material can be provided on the substrate comprising a piezoelectric layer 106, and a dielectric layer of a second material can be provided on the support substrate 100, the first material being different from the second material. For example, the dielectric layer provided on the substrate comprising a piezoelectric layer 106 is a Si3N4 layer, while the dielectric layer provided on the support substrate 100 is a SiOxNy layer, in particular SiON. Thus, the assembly of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is then carried out at the interface between two Si3N4-SiOxNy dielectric layers, which allows for a stable bond.

[0088] In the same way as in the other variants of the second embodiment, one or more layers of the intermediate structure can be provided on the piezoelectric substrate 106 instead of on the support substrate 100.

[0089] The piezoelectric substrate on insulator (POI) 152 illustrated in step V) comprises the support substrate 100, the trapping layer 102, the dielectric layer 132', a metallic element diffusion barrier layer 122', the second dielectric layer 146 and the piezoelectric layer 114 corresponds to the substrate according to the invention in this second variant of the second embodiment.

[0090] Figure [Fig. 3] schematically represents a method for manufacturing a piezoelectric substrate on insulator (POI) according to a third embodiment of the invention.

[0091] In this third embodiment, step III) of forming the intermediate structure 120 of the process according to [Fig.2a] further includes a step IIIc) of forming a second barrier layer 154 after step IIIa).

[0092] All other steps I), II), lia), III), Ilia), IV) and V) are the same as in the second embodiment according to [Fig.2a], except that in step IV) the assembly takes place between the second barrier layer 154 and the piezoelectric substrate 106. All features common with the first or second embodiment and their variants and using the same reference numbers as above will not be described again, but reference is made to their detailed description above.

[0093] The intermediate structure 120 thus comprises a first barrier layer 122 for diffusion of metallic element, a dielectric layer 132 and a second barrier layer 154, 156, 158, 160.

[0094] This second barrier layer 154, 156, 158, 160 is deposited on the dielectric layer 132, which is deposited on the first barrier layer 122. Thus, the first barrier layer 122 and the second barrier layer 154 are separated by the dielectric layer 132.

[0095] During the assembly step IV), the second barrier layer 154, 156, 158, 160 is brought into contact at the interface 162 with the substrate comprising a piezoelectric layer 106 to form the donor substrate 164.

[0096] The second barrier layer 154 may be a second barrier layer 156 for diffusion of a metallic element. In this case, the second barrier layer 156 is formed in the same way as the first barrier layer 122. The second barrier layer 156 for diffusion of a metallic element may have the same properties, such as thickness or material, as the first barrier layer 122, or, alternatively, the first barrier layer 122 and the second barrier layer 156 may be different, with different materials and / or different thicknesses. For example, the first diffusion barrier layer 122 may be Tantalum Oxide (Ta2O5) or Tantalum Nitride (TaN), and the second diffusion barrier layer 156 may be Silicon Carbon Nitride (SiCN) or Aluminum Oxide (Al2O3), or vice versa.

[0097] According to a first variant, the second barrier layer 154 can be a hydrogen diffusion barrier layer 158 to limit the diffusion of hydrogen towards the piezoelectric substrate 106 and / or towards the trapping layer 102 of the support substrate 100. The hydrogen diffusion barrier layer 158 can be based on Silicon Oxynitride (SiOxNy) or Aluminium Nitride (AIN). This second barrier layer 158 based on Silicon Oxynitride (SiOxNy) or Aluminium Nitride (AIN) is formed by a PECVD (in English: "Plasma Enhanced Chemical Vapor Deposition", in French: "Déposition chimique en phase vapeur actif par plasma") or PVD (in English: "Physical Vapor Deposition", in French: "Déposition physique en phase vapeur") or ALD (in English: "Atomic layer Deposition", in French: "Déposition Atomique par couche") deposition technique, with a thickness between 5nm and 100nm.

[0098] Indeed, in a POI substrate, another source of degradation of the radio frequency and electrical performance of the substrate is the diffusion of hydrogen towards the piezoelectric layer and / or towards the trapping layer during the manufacturing process of the POI substrate. The hydrogen can come from various sources, for example from the bonding interface due to the hydrophilic nature of the bonding layers with the silicon-based substrate, or from the silicon oxide-based layer, which is rich in hydrogen due to its manufacturing process.

[0099] During heat treatment, such as during a deposition step or a step Due to fracturing, carried out during the manufacturing process at temperatures of around 500°C, hydrogen, as the metallic element of the piezoelectric layer 114, can diffuse to the trapping layer 102 and neutralize the charge traps of the trapping layer 102. Furthermore, hydrogen can also diffuse within the piezoelectric layer / substrate, where its presence can lower the Curie temperature, potentially causing local ferroelectric domain reversal. This local ferroelectric domain reversal phenomenon affects the propagation of acoustic waves in the piezoelectric material.

[0100] According to a second embodiment, the hydrogen diffusion barrier layer 158 is a silicon oxide-based layer 160. In this second embodiment, the second barrier layer 160 has a hydrogen concentration of less than 1020 at / cm³, in particular less than 10¹⁸ at / cm³. This can be achieved by deposition of silicon oxide using a plasma-enhanced vapor deposition (PECVD) technique, such as plasma-enhanced chemical vapor deposition (CVD) or low-pressure chemical vapor deposition (LPCVD), or physical vapor deposition (PVD), or by oxidation heat treatments. PVD deposition includes deposition temperatures between ambient temperature and 400°C, while PECVD includes deposition temperatures between 150°C and 400°C. LPCVD deposition involves deposition temperatures between 600 and 700°C.In this case, the dielectric layer 160 exhibits a significant hydrogen concentration of over 1020 at / cm3.

[0101] To reduce the hydrogen concentration in this second silicon oxide-based barrier layer 160, a densification anneal is applied. This anneal is performed under a low-hydrogen atmosphere, i.e., below 5 ppm, and exposes the silicon oxide-based layer 160 to a temperature above its deposition temperature. This can be a neutral or oxidizing atmosphere. Preferably, this temperature is above 800°C, typically between 800°C and 900°C. The annealing is continued for at least one hour, and preferably for several hours, in order to exodiffuse the hydrogen from the dielectric layer 160, and possibly from the trapping layer 102. At the end of this densification anneal, the dielectric layer 160 has a hydrogen concentration below 1020 at / cm³.

[0102] Such densification annealing can also lead to a reduction in the diffusivity of hydrogen, i.e. the ability of this species to diffuse into the material constituting the dielectric layer 160, so that hydrogen even in a concentration greater than 1020 at / cm3 is less likely to diffuse towards the trapping layer 102. Thus, the trapping layer 102 also has a reduced hydrogen concentration, in particular less than 1018 at / cm3.

[0103] In a variant of this embodiment, one or more layers of the intermediate structure 120, i.e. the dielectric layer 132, the barrier layer 122 and the second barrier layer 154, 156, 158, 160 can be provided on the piezoelectric substrate 106 instead of on the support substrate 100. In this variant, the order of deposition of the layers is carried out in such a way that the final POI substrate obtained after assembly and fracturing has the same sequence of layers, i.e. the same order of the deposited layers, as the POI substrate 166 obtained for the embodiment described above.

[0104] In another variant of this embodiment of the invention, a dielectric layer can be provided on both substrates, the substrate comprising a piezoelectric layer 106 and on the support substrate 100. The assembly interface of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is made at the interface between two dielectric layers, with oxide-oxide type bonds, in particular a Si-O-Si type bond, which is a type of bond known to be stable.

[0105] In another embodiment of this invention, a dielectric layer of a first material may be provided on the substrate comprising a piezoelectric layer 106, and a dielectric layer of a second material may be provided on the support substrate 100, the first material being different from the second material. For example, the dielectric layer provided on the substrate comprising a piezoelectric layer 106 is a Si3N4 layer, while the dielectric layer provided on the support substrate 100 is a SiOxNy layer, in particular SiON. Thus, the assembly of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is then carried out at the interface between two Si3N4-SiOxNy dielectric layers, which allows for a stable bond.

[0106] The piezoelectric substrate on insulator (POI) 166 illustrated in step V) of [Fig.3] produced by the manufacturing process according to the invention, comprises the support substrate 100, the trapping layer 102, the first barrier layer 122 for diffusion of metallic element, the dielectric layer 132, the second barrier layer 154 and the piezoelectric layer 114 and thus forms a POI substrate 166 according to the third embodiment.

[0107] The embodiments described are simply possible configurations and it should be borne in mind that the individual features of the different embodiments can be combined with each other or provided independently of each other.

Claims

Demands

1. Piezoelectric substrate on insulation (POI) comprising: - a support substrate (100), in particular a silicon-based substrate, comprising a trapping layer (102) on a free surface (104) of the support substrate (100), in particular a layer based on polycrystalline, amorphous, or porous silicon; - a piezoelectric layer (114), in particular a layer of Lithium Tantalate (LTO) or Lithium Niobate (LNO); - an intermediate structure (120) positioned sandwiched between the piezoelectric layer (114) and the trapping layer (102) of the support substrate (100), wherein the intermediate structure (120) comprises at least one barrier layer (122, 122') for the diffusion of a metallic element, in particular Lithium, based on Tantalate Oxide (Ta2O5) comprising a thickness tEM greater than a predetermined thickness.said predetermined thickness being determined as a function of the thickness of the trapping layer (102) in such a way that the dose of metallic element, in particular the dose of Lithium, in the trapping layer (102) is less than a predetermined threshold dose, in particular a threshold dose of metallic element, even more particularly a threshold dose of Lithium, less than 1012 at / cm2, in particular less than 5*10" at / ,

2. cm. The piezoelectric substrate on insulator (POI) according to claim 1, wherein the metallic element diffusion barrier layer (122, 122') has a thickness between 5nm and 150nm, in particular between 10nm and 100nm, and the thickness tp of the trapping layer (102) is between 50nm and 5pm.

3. The piezoelectric substrate on insulator (POI) according to claim 1 or 2, wherein the intermediate structure (120) comprises at least one dielectric layer (132, 132'), in particular based on Silicon dioxide or Silicon Nitride (SiN) or even Silicon Oxynitride (SiOxNy), in contact with at least one barrier layer (122, 122') of metallic element diffusion.

4. The piezoelectric substrate on insulator (POI) according to any one of the preceding claims, wherein the barrier layer (122') is positioned sandwiched between two dielectric layers (132', 146).

5. The piezoelectric substrate on insulator (POI) according to one of the claims previous indications, in which the intermediate structure (120) further comprises a second barrier layer (154, 156, 158, 160).

6. The piezoelectric substrate on insulator (POI) according to claim 5, wherein the second barrier layer (154) is a hydrogen diffusion barrier layer (156), in particular based on Silicon Oxynitride (SiOxNy) or Silicon Nitride (SiN) or Aluminium Nitride (AIN).

7. The piezoelectric substrate on insulation (POI) according to any one of the preceding claims, wherein the intermediate structure (120) comprises at least one layer (158) with a hydrogen concentration less than 1020 at / cm3, in particular less than 1018 at / cm3

8. Cili. A method for manufacturing a piezoelectric substrate on an insulator (POI) (130, 138, 144, 152, 160) according to any one of claims 1 to 7, comprising the steps of: - providing a support substrate (100), in particular a silicon-based substrate, comprising a trapping layer (102), in particular a layer based on polycrystalline, amorphous, or porous silicon; - providing a substrate comprising a piezoelectric layer (106), in particular a piezoelectric layer (108) based on lithium tantalate (LTO) or lithium niobate (LNO); - forming an intermediate structure (120) on the substrate comprising a piezoelectric layer (106) and / or on the support substrate (100), the formation of the intermediate structure (120) comprising the formation of at least one metallic element diffusion barrier layer (122, 122'), in particular lithium-based Tantalate oxide (Ta2O5) comprising a thickness tEM greater than a predetermined thickness,said predetermined thickness being determined as a function of the thickness of the trapping layer (102) in such a way that the dose of metallic element, in particular the dose of Lithium, in the trapping layer (102) is less than a predetermined threshold dose, in particular a threshold dose of metallic element, even more in particular a dose of Lithium, less than 10¹² at / cm², in particular less than 5*10⁻¹⁰ at / cm², and - assembling the substrate comprising a piezoelectric layer (106) with the support substrate (100).

9. The method for manufacturing a piezoelectric substrate on an insulator (POI) (138, 152, 160) according to claim 8, wherein the step of formation of the intermediate structure (120) further includes the formation of a second barrier layer (154, 156, 158, 160).

10. The method for manufacturing a piezoelectric substrate on an insulator (POI) (138, 152, 160) according to claim 8 or 9, wherein the step of forming the intermediate structure (120) further comprises a step of forming a layer (158) with a hydrogen concentration less than 1020 at / cm3, in particular less than 1018 at / cm3

11. Cili. The method of manufacturing a piezoelectric substrate on insulator (POI) (138, 152, 160) according to claim 9 or claim 10 with claim 9, wherein the step of forming the second barrier layer (154) comprises the formation of a layer (156) based on Silicon Oxynitride (SiOxNy), or Silicon Nitride (SiN) or Aluminium Nitride (AIN).

12. The method of manufacturing a piezoelectric substrate on insulator (POI) (130, 138, 144, 152, 160) according to any one of claims 8 to 11, further comprising a step of forming a dielectric layer (132, 146) on the support substrate (100) and / or on the substrate comprising a piezoelectric layer (106) before the assembly step, such that the bonding interface is an oxide-oxide bonding interface.

13. The method of manufacturing a piezoelectric substrate on insulator (POI) (130, 138, 144, 152, 160) according to any one of claims 8 to 11, further comprising a step of forming a dielectric layer (132, 146) of a first material on the support substrate (100) and / or of a second material different from the first material on the substrate comprising a piezoelectric layer (106) before the assembly step.

14. The method of manufacturing a piezoelectric substrate on insulator (POI) (130, 138, 144, 152, 160) according to claim 13, wherein the first material is based on Silicon Nitride, in particular Si3 N4, and the second material is based on Silicon Oxynitride (SiOxNy), in particular SiON.

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