QFN TYPE HOUSING CONTAINING TWO ELECTRONIC CHIPS OF DIFFERENT SUBSTRATES

Abstract

According to one aspect, a package (BT) is proposed comprising: - a mounting plate (SUB1) having a first part (TPAD) capable of dissipating heat and a second part (SPAD1, SPAD2) capable of transmitting or receiving electrical signals, - an encapsulation (RES) housing a first electronic chip (P1) having a first semiconductor substrate (SUBST1) and configured to release a first quantity of heat during operation, as well as a second electronic chip (P2) having a second semiconductor substrate (SUBST2) and configured to release a second quantity of heat during operation, the first chip (P1) being thermally coupled to the first part (TPAD) and electrically coupled to the second chip (P2) as well as to the second part (SPAD2) at least by means of connecting wires (WB1, WB2),the second chip (P2) being thermally coupled to the first part (TPAD) and electrically coupled to the second part (SPAD1) via at least one matrix of connecting balls (BP1, BP2). Figure for the abbreviation: Fig 1,

Description

Title of the invention: QFN TYPE HOUSING COMPRISING TWO ELECTRONIC CHIPS OF DIFFERENT SUBSTRATES

[0001] Some embodiments and implementation methods relate to the field of microelectronics, in particular the field of packaging of integrated circuits, and more particularly the management of constraints of electronic chips (in English "die").

[0002] An electronic chip is a semiconductor device that performs electrical functions within a package. In particular, the electronic chip is typically made from a substrate. The substrate material can vary from one chip to another and can be chosen to enable the electronic chip to perform specific electrical functions.

[0003] Several electronic chips having a different material substrate can sometimes be used together in order to simultaneously perform the specific electrical functions of each of the electronic chips, as for example in applications related to the 5G (fifth generation) telecommunication standard.

[0004] However, each of these electronic chips may present different constraints depending on the material of the substrate of the electronic chips.

[0005] By way of example, an electronic chip made from a gallium nitride (GaN) substrate can be used for functions involving relatively high power. Such an electronic chip typically has electronic components capable of withstanding high voltages. The main drawback of these electronic components is that they generate a relatively large amount of heat during the operation of the electronic chip. In particular, the heat generated by these components can negatively impact the operation of the electronic chip if this heat is not sufficiently dissipated within the package.

[0006] Consequently, it is common practice to design a package whose structure is specifically adapted to the constraints of the electronic chip, such as heat dissipation.

[0007] In this regard, the heat generated by the gallium nitride substrate electronic chip can be dissipated by a flat, pinless package (better known by the acronym "QFN" for "Quad Fiat No-leads package"). Indeed, the flat, pinless package is a conventional type of package that efficiently dissipates the heat from the electronic chip via a flat metal plate arranged in the center of a connection grid (referred to as a "lead frame" in English).

[0008] On the other hand, the flat, pinless package structure is not suitable for other electronic chips, such as an electronic chip made from a silicon (Si) substrate with other electrical functions and requiring dense and complex electrical routing. Indeed, when the silicon substrate electronic chip has connections that are far too complex to be connected to the connection grid of such a package, pad array packages (better known by the acronym "LGA" for "Land Grid Array") or ball array packages (better known by the acronym "BGA" for "Bail Grid Array") are used instead.

[0009] It is therefore necessary to design several packages for each electronic chip according to its constraints. Indeed, each type of package mentioned above has a structure that may be compatible with one electronic chip but not necessarily with another electronic chip.

[0010] Thus, the flat, pinless package does not have a structure capable of handling the connection of the silicon substrate electronic chip, which is often too complex for this type of package.

[0011] Similarly, pellet matrix or bead matrix type packages do not have a structure that allows sufficient dissipation of the heat produced by a gallium nitride substrate electronic chip.

[0012] This therefore poses a design problem leading in particular to a larger size of a system having to incorporate these separate boxes as well as an increase in manufacturing costs.

[0013] There is therefore a need to propose a solution to this problem.

[0014] According to one embodiment and implementation method, a housing is proposed in which the structure is compatible with the constraints of each of the aforementioned electronic chips and allows to house together within this single package chips having different constraints in particular in terms of heat dissipation and routing of the connectors.

[0015] According to one aspect, a housing is proposed, typically a flat, pinless housing (so-called "QFN" housing), comprising:

[0016] - a mounting plate having a first part, for example central, suitable for dissipate heat and a second part, for example peripheral, capable of transmitting and / or receiving electrical signals,

[0017] - an encapsulation housing a first electronic chip having a first substrate semiconductor and configured to dissipate a first quantity of heat during operation, and a second electronic chip having a second semiconductor substrate and configured to dissipate a second quantity of heat during operation, the two semiconductor substrates being different and the second quantity of heat being less than the first quantity of heat,

[0018] the first chip being thermally coupled to the first part and electrically coupled to the second chip as well as to the second part at least by means of connecting wires, the second chip being thermally coupled to the first part and electrically coupled to the second part by means of at least a first matrix of connecting balls.

[0019] The housing, typically of the flat and pinless type, allows for the housing of a first electronic chip, which can be, for example, an electronic chip having a substrate containing gallium nitride, capable of producing a relatively large amount of heat.

[0020] This package has the advantage of also being able to house a second electronic chip which is not normally designed to be assembled in a classic flat and pinless package, typically a chip with a complex connector.

[0021] In particular, the package is adapted to both the thermal constraints of the first chip and the electrical connection constraints of the second chip.

[0022] Consequently, the first chip and the second chip can coexist in a single package and can be electrically coupled to each other within it. Electrical coupling between the first chip and the second chip by at least connecting wires makes it possible, in particular, to improve the impedance ratio between the two chips and thus optimize signal transmission between them.

[0023] According to one embodiment, the first substrate comprises gallium nitride and the second substrate comprises silicon.

[0024] Gallium nitride is used for the manufacture of electronic components operating at high power and / or high frequencies that can emit a relatively large amount of heat. Silicon is used for the manufacture of other types of electronic components, such as components using CMOS technology, which may sometimes require a complex connection interface typically provided in conventional ball-matrix or pellet-matrix packages.

[0025] According to one embodiment, the first quantity of heat corresponds to a dissipated power of several Watts, for example 5 Watts.

[0026] According to one embodiment, the second quantity of heat corresponds to a power dissipated less than 1 Watt, for example 0.6 W.

[0027] According to one embodiment, the housing comprises a support, for example an interposer (using a term known to those skilled in the art) having a mounting face and a fixing face opposite the mounting face, the fixing face being connected to the first part and to the second part of the mounting plate via the first matrix of connecting balls, the mounting face being connected to the second chip via a second matrix of connecting balls.

[0028] The support includes an interconnection network configured to electrically couple the first ball matrix, the second ball matrix and the first chip.

[0029] The support allows the second electronic chip to be connected to the electrical contacts located in the second part of the mounting plate. Indeed, the interconnection network of the support may include several conductive tracks, integrated into one or more dielectric layers, allowing the connecting balls of the first matrix to be electrically connected to the connecting balls of the second matrix. In particular, the distance separating the connecting balls of the second matrix (the "pitch") allows the connecting balls to be aligned with the electrical contacts present on the second part of the mounting plate.

[0030] Furthermore, the interconnection network also provides conductive tracks allowing the transmission of signals between the first chip and the second chip.

[0031] According to one embodiment, the electrically conductive connecting wires comprise first connecting wires and second connecting wires.

[0032] The first electronic chip has a rear face fixed to the first part of the mounting plate by a layer of thermally conductive glue and a front face electrically connected to the second part of the mounting plate by the first connecting wires and electrically connected to the interconnection network by the second connecting wires.

[0033] According to one embodiment, the encapsulation can house at least one surface-mounted component and the interconnection network of the support is also configured to electrically couple said at least one surface-mounted component to the first electronic chip and the second electronic chip.

[0034] The surface of the support can allow for the attachment of several surface-mount components, which can then be electrically coupled to the first electronic chip and / or the second electronic chip. In particular, the support can allow for the connection of more surface-mount components than a mounting plate in a conventional package.

[0035] According to one embodiment, the first part is a central part and the second part is a peripheral part.

[0036] According to another aspect, a method for manufacturing a housing comprising is proposed: - a mounting plate comprising a first part capable of dissipating heat and a second part capable of transmitting and / or receiving electrical signals - the formation of a first electronic chip having a first semiconductor substrate and configured to generate a first amount of heat during operation, — the formation of a second electronic chip having a second semiconductor substrate and configured to dissipate a second quantity of heat during operation, the two semiconductor substrates being different and the second quantity of heat being less than the first quantity of heat, - thermal coupling of the first chip to the first part and electrical coupling of the first chip to the second chip and to the second part at least via connecting wires, - thermal coupling of the second chip to the first part and electrical coupling of the second chip to the second part via at least one first matrix of connecting beads, and - the formation of a coating housing at least the first chip and the second chip.

[0037] According to one embodiment, the method comprises: - a support structure having a mounting face and a fixing face opposite the mounting face, - a connection of the mounting face of the support to the first part and the second part of the mounting plate via the first matrix of connecting balls, - a connection of the mounting face of the support to the second chip via a second matrix of connecting balls, - the formation of an interconnection network on and in the support so as to electrically couple the first bead matrix, the second bead matrix and the first chip.

[0038] According to one embodiment, the method comprises a connection of at least one surface-mounted component to the first electronic chip and to the second electronic chip and a housing of said at least one surface-mounted component within the encapsulation.

[0039] According to one embodiment, the formation of the mounting plate includes the formation of a first central part and the formation of a second peripheral part.

[0040] The housing is advantageously of the flat and pinless type (so-called “QFN” housing).

[0041] Other advantages and features of the invention will become apparent upon examination of the detailed description of embodiments and implementations, which are by no means limiting, and the accompanying drawings in which:

[0042] [Fig.l];

[0043] [Fig.2] ; and

[0044] [Fig.3] schematically illustrate embodiments and implementation methods of the invention.

[0045] Fig. 1 schematically illustrates a cross-sectional view of a BT housing, here a so-called "QFN" housing, of the flat and pinless type, according to an embodiment of the invention.

[0046] The BT package includes a mounting plate SUB1 and an encapsulation RES housing a first electronic chip PL The first electronic chip PI can be, for example, an electronic chip made from a substrate SUBSTR1 whose material includes gallium nitride (GaN) or silicon carbide (SiC).

[0047] The first PI electronic chip has a rear face FL1 and a front face FH1. The first PI electronic chip is configured to dissipate an initial amount of heat during operation. Indeed, the front face FH1 of the first PI electronic chip typically includes electronic components, such as high-voltage transistors, which can generate a relatively large amount of heat. This initial amount of heat corresponds to a power dissipation of several watts, typically between 1 and 10 watts, for example, 5 watts. This initial amount of heat may require appropriate thermal dissipation to prevent any malfunction of the electronic components inside the package.

[0048] To this end, the SUB 1 mounting plate (of the type known to those skilled in the art as a "lead frame") has a central TPAD portion capable of dissipating heat, in particular the heat generated by the first PI electronic chip during its operation. The central TPAD portion of the SUB 1 mounting plate can be a metal plate, most often with a flat surface, made of a thermally conductive material. The material of the central TPAD portion can be, for example, copper (Cu) and can have a thermal conductivity of approximately 385 W / mK.

[0049] The rear face FL1 of the first electronic chip PI is fixed to a mounting face FMI of the central part TPAD of the mounting plate SUBI by a layer of thermally conductive adhesive GL known per se.

[0050] Furthermore, the SUBI mounting plate also has a peripheral portion SPAD1, SPAD2 capable of transmitting and / or receiving electrical signals. The peripheral portion SPAD1, SPAD2 of the SUBI mounting plate typically has electrical contacts located around the central portion TPAD. Such electrical contacts allow an electronic chip in the package, for example the first PI electronic chip, to be connected to a printed circuit board.

[0051] More specifically, the front face FH1 of the first electronic chip PI is electrically connected to an electrical contact SPAD2 located in the peripheral part of the mounting plate SUBI by first connecting wires WB1.

[0052] The RES encapsulation of the BT housing also houses a second electronic chip P2. The second electronic chip P2 is, for example, an electronic chip made from a substrate SUBSTR2, the material of which may include silicon (Si). The second electronic chip P2 has a back side FL2 and a front side FH2 containing electronic components, such as transistors. The second electronic chip P2 is configured to dissipate a second amount of heat during operation. This second amount of heat corresponds to a power dissipation of less than 1 Watt, for example, 0.6 Watts.

[0053] The BT housing also includes a SUB2 bracket. The SUB2 bracket has an FM2 mounting face and an FF mounting face opposite the FM2 mounting face.

[0054] The FF mounting face of the SUB2 support is fixed to the central part TPAD and the peripheral part SPAD1 of the SUBI mounting plate by a first matrix of BPI connecting balls (bumps). The connecting balls of the first BPI matrix are electrically and thermally conductive metallic balls.

[0055] The second electronic chip P2 is fixed to the mounting face FM2 of the support plate SUB2 by a second matrix of connecting balls BP2. The connecting balls of the second matrix BP2 are also electrically and thermally conductive metallic balls.

[0056] The second ball matrix BP2 typically allows the second electronic chip P2 to be connected to a mounting plate of a conventional ball matrix package, for example. The second chip P2, using, for example, CMOS technology, may have a BP2 matrix with connecting balls very close together in order to connect the electronic components of the second chip P2 to this type of package.

[0057] As an indication, the balls of the BP2 matrix can be spaced from each other by a distance of between 70 pm and 200 pm.

[0058] Conversely, the connecting balls of the first BPI matrix are more widely spaced and allow the connecting balls to be aligned with the electrical contacts of the peripheral part SPAD1. The first matrix of BPI connecting balls makes it possible to keep the SUB2 support fixed to the mounting plate SUBI, in particular to its central part TPAD, and also to maintain an electrical connection between the second electronic chip P2 and the electrical contacts SPAD1 located in the peripheral part SPAD1 of the mounting plate SUBI.

[0059] As an indication, the balls of the BPI matrix can be spaced between each other by a distance of between 0.4 mm and 0.8 mm.

[0060] In one variant (not shown in the figures), the second electronic chip P2 can be attached to the mounting face FM2 of the SUB2 support according to a mounting of Wirebonding. In this variant, the rear face FL2 of the second electronic chip P2 is attached to the mounting face FM2 of the SUB2 socket by a layer of adhesive. The front face FH2 of the second electronic chip P2 is electrically connected to the SUB2 socket by wirebonding.

[0061] The SUB2 support is, for example, a laminated substrate advantageously comprising an interconnection network INT between the mounting face FM2 and the fixing face FF. The interconnection network INT typically comprises conductive tracks, for example made of copper, integrated into one or more dielectric layers, which may be, for example, epoxy resin matrices optionally with glass fibers.

[0062] The conductive tracks of the INT interconnection network allow the transmission of signals between the second electronic chip and the electrical contacts located in the peripheral part SPAD1. More specifically, several conductive tracks can electrically and thermally connect the connecting balls of the first matrix BPI to the connecting balls of the second matrix BP2.

[0063] The first ball matrix BPI and the second ball matrix BP2, as described above, allow, particularly via the conductive tracks, heat transfer between the second electronic chip P2 and the central part TPAD of the mounting board SUBI. The heat generated by the first electronic chip PI and by the second electronic chip P2 during their operation can thus be dissipated outside the BT housing through the central part TPAD of the mounting board SUBI.

[0064] Furthermore, the front face FH1 of the first electronic chip PI is electrically connected to the interconnection network INT of the SUB2 support by means of second connecting wires WB2. Conductive tracks may also be provided to electrically connect the connecting balls of the first matrix BPI and the second matrix BP2 to the second connecting wires WB2. Thus, the interconnection network INT allows the first electronic chip PI, the second electronic chip P2, and the peripheral SPAD1 portion of the SUBI mounting board to be electrically coupled.

[0065] The SUB2 support therefore has a role as a connection interface between the second electronic chip P2 and the mounting plate SUBI of the BT housing since it allows signals to pass between the electrical contacts located in the peripheral part SPAD1 and the second chip P2 which is not normally designed to be assembled in a classic flat and pinless housing.

[0066] Consequently, the PI and P2 electronic chips can coexist in a single BT package and can, moreover, be electrically coupled together within it. The electrical coupling between the first PI chip and the second P2 chip makes it possible, in particular, to improve the impedance ratio between the two chips and thus to optimize signal transmission between these two chips.

[0067] Fig. 2 schematically illustrates a top view of the BT housing described above in relation to Fig. 1.

[0068] The first electronic chip PI is preferably connected to the nearest electrical contacts in the peripheral part SPAD2 of the mounting plate SUBI by the first connecting wires WB1.

[0069] The SUB2 support has contacts on its mounting face FM2 that can be electrically connected to the front face FH1 of the first electronic chip PI by means of connecting wires WB21. The mounting face FM2 may also include other contacts that can be electrically connected to the nearest electrical contacts in the peripheral part SPAD2 of the SUB1 mounting plate, by means of other connecting wires WB22.

[0070] The INT interconnection network allows the first electronic chip PI and the second electronic chip P2 to be electrically coupled, in particular via the connecting wires WB21. The INT interconnection network also allows the second electronic chip P2 and the peripheral SPAD1 part of the mounting board SUBI to be electrically coupled, in particular via the connecting wires WB22.

[0071] Furthermore, the BT housing herein also includes four surface-mount components, designated by the references SMD1 to SMD4, fixed to the FM2 mounting face of the SUB2 support. The surface-mount SMD components are, for example, passive electronic components such as capacitive elements, resistive elements, or inductive elements.

[0072] Surface-mount components (SMDs) can be soldered to electrical contacts on the surface of the SUB2 substrate and are electrically connected to the INT interconnection network. The INT interconnection network is further configured to electrically couple the SMDs to the first electronic chip PI and / or the second electronic chip P2.

[0073] Consequently, the surface of the SUB2 socket allows for the attachment of several surface-mount SMD components, which can then be electrically coupled to the first electronic chip PI and / or the second electronic chip P2 via the interconnect network INT. In particular, the SUB2 socket allows for the connection of more surface-mount SMD components than a mounting plate in a conventional flat, pinless package.

[0074] Figure 3 illustrates an example of a manufacturing process for a BT integrated circuit package as described above in relation to Figures 1 and 2.

[0075] The process includes a forming step 100 of the SUBI mounting plate. The forming step 100 includes, in particular, the forming of the central part TPAD of the SUBI mounting plate and the formation of the SPAD1 and SPAD2 electrical contacts of the peripheral part of the SUBI mounting plate.

[0076] The method also includes a forming step 101 of the first electronic chip PL. The rear face FL1 is fixed to the central part TPAD of the mounting plate SUB1 by a layer of thermally conductive adhesive GL. In this forming step 101, the front face FH1 of the first electronic chip PI is electrically connected to the electrical contacts SPAD2 by the first conductive wires WB1.

[0077] The method also includes a forming step 102 of the SUB2 support having a mounting face FM2 and a fixing face FF opposite the mounting face FM2. The forming step 102 of the SUB2 support plate includes, in particular, the formation of the interconnection network INT between the mounting face FM2 and the fixing face FF of the SUB2 support. In this step 102, the fixing face FF of the SUB2 support is fixed to the central part TPAD and to the peripheral part SPAD1 by the first matrix of connecting balls BPI.

[0078] The method also includes a forming step 103 of the second electronic chip P2 having a rear face FL2 and a front face FH2. The front face FH2 of the second electronic chip P2 typically comprises electronic components.

[0079] In this step 103, the front face FH2 is fixed, by soldering, to the mounting face FM2 of the SUB2 support by the second connecting ball matrix BP2. In this way, the second chip P2 is thermally coupled to the central part TPAD and electrically coupled to the peripheral part SPAD1 of the SUBI mounting plate via the first ball matrix BPI, the second ball matrix BP2 and the interconnection network INT.

[0080] Alternatively, the rear face FL2 of the second chip P2 could be fixed to the mounting face FM2 of the SUB2 support by a layer of glue and the front face FH2 is connected to the mounting face FM2 by soldering connecting wires.

[0081] The process includes a soldering step 104 of the WB21 connecting wires between the mounting face FM2 of the SUB2 support and the front face FH1 of the first electronic chip PL. Following the soldering described in step 103, the first BPI ball matrix, the second BP2 ball matrix and the first PI chip are electrically coupled by the INT interconnection network.

[0082] The formation step 103 of the second chip P2 can be carried out before the formation step 102 of the support SUB2, i.e. by first fixing the second chip P2 to the mounting face FM2 of the support SUB2 and then fixing the fixing face FF of the support SUB2 to the central part TPAD and to the peripheral part SPAD1 of the mounting plate SUBI.

[0083] Furthermore, the method may include a connection 104 of at least one SMD surface-mount component to the first chip PI and the second chip P2. In particular, the connection 104 includes soldering said at least one SMD surface-mount component to the mounting face FM2 of the SUB2 socket such that said at least one SMD surface-mount component is electrically coupled to the interconnect network INT.

[0084] The process includes a formation 105 of an RES coating. The RES coating, which can be, for example, resin, is formed around the first chip PI and the second chip P2 by molding techniques well known to those skilled in the art.

Claims

Claims

1. Housing (BT) comprising: - a mounting plate (SUBI) having a first part (TPAD) capable of dissipating heat and a second part (SPAD1, SPAD2) capable of transmitting and / or receiving electrical signals, - a coating (RES) housing at least a first electronic chip (PI) having a first semiconductor substrate (SUBST1) and configured to release a first quantity of heat in operation and a second electronic chip (P2) having a second semiconductor substrate (SUBST2) and configured to release a second quantity of heat in operation, the two semiconductor substrates (SUBST1, SUBST2) being different and the second quantity of heat being less than the first quantity of heat, the first chip (PI) being thermally coupled to the first part (TPAD) and electrically coupled to the second chip (P2) as well as to the second part (SPAD2) at least via connecting wires (WB1, WB2),the second chip (P2) being thermally coupled to the first part (TPAD) and electrically coupled to the second part (SPAD1) via at least a first matrix of connection balls (BPI).,

2.

3. Package (BT) according to claim 1, being of the flat type and without pins. Package (BT) according to any one of claims 1 or 2, in which the first substrate (SUBST1) comprises gallium nitride.

4. Package according to one of the preceding claims, in which the second substrate (SUBST2) comprises silicon.

5. Housing (BT) according to any one of the preceding claims, in which the first quantity of heat corresponds to a dissipated power of several Watts.

6. Housing (BT) according to any one of the preceding claims, in which the second quantity of heat corresponds to a dissipated power of less than 1 Watt.

7. Housing (BT) according to any one of the preceding claims, comprising a support (SUB2) having a mounting face (FM2) and a fixing face (FF) opposite the mounting face (FM2), the fixing face (FF) being connected to the first part (TPAD) and to the second part (SPAD1) of the mounting plate (SUBI) via the first matrix of connecting balls (BPI), the mounting face (FM2) being connected to the second die (P2) via a second matrix of connecting balls (BP2) and the support (SUB2) comprises an interconnection network (INT) configured to electrically couple the first matrix of balls (BPI), the second matrix of balls (BP2) and the first die (PI).

8. Package (BT) according to claim 7, in which the connecting wires comprise first connecting wires (WB1) and second connecting wires (WB2), the first electronic chip (PI) has a rear face (FL1) fixed to the first part (TPAD) of the mounting plate (SUBI) by a layer of thermally conductive glue (GL) and a front face (FH1) electrically connected to the second part (SPAD2) of the mounting plate (SUBI) by the first connecting wires (WB1) and electrically connected to the interconnection network (INT) by the second connecting wires (WB2).

9. Package according to any one of claims 7 or 8, wherein the coating also houses at least one surface mounted component (SMD) and the interconnection network (INT) of the support (SUB2) is also configured to electrically couple said at least one surface mounted component (SMD) to the first electronic chip (PI) and to the second electronic chip (P2).

10. Housing according to one of the preceding claims, in which the first part (TPAD) is a central part and the second part (SPAD1, SPAD2) is a peripheral part.

11. Method for manufacturing a package (BT) comprising: - forming a mounting plate (SUBI) having a first part (TPAD) capable of dissipating heat and a second part (SPAD1, SPAD2) capable of transmitting and / or receiving electrical signals, - forming a first electronic chip (PI) having a first semiconductor substrate (SUBST1) and configured to release a first quantity of heat in operation, - forming a second electronic chip (P2) having a second semiconductor substrate (SUBST2) and configured to release a second quantity of heat in operation, the two semiconductor substrates (SUBST1, SUBST2) being different and the second quantity of heat being less than the first quantity of heat, - thermal coupling of the first chip (PI) to the first part (TPAD) and an electrical coupling of the first chip to the second chip and to the second part (SPAD2) at least via bonding wires (WB1, WB2), - a thermal coupling of the second chip (P2) to the first part (TPAD) and an electrical coupling of the second chip to the second part (SPAD1) via at least a first matrix of bonding balls (BPI), and - a formation of a coating (RES) housing at least the first chip (PI) and the second chip (P2).

12. Method according to claim 11, comprising: - forming a support (SUB2) having a mounting face (FM2) and a fixing face (FF) opposite the mounting face (FM2), - connecting the fixing face (FF) of the support (SUB2) to the first part (TPAD) and to the second part (SPAD1) of the mounting plate (SUBI) via the first matrix of connecting balls (BPI), - connecting the mounting face (FM2) of the support (SUB2) to the second chip (P2) via a second matrix of connecting balls (BP2), - forming an interconnection network (INT) on and in the support (SB2) so as to couple the first matrix of balls (BPI), the second matrix of balls (BP2) and the first chip (PI).

13. A method according to claim 12, comprising connecting at least one surface mounted component (SMD) to the first electronic chip (PI) and to the second electronic chip (P2) and housing said at least one surface mounted component within the coating (RES).

14. Method according to one of claims 11 to 13, in which the formation of the mounting plate comprises the formation of a first central part (TPAD) and the formation of a second peripheral part (SPAD1, SPAD2).

15. Method according to one of claims 11 to 14, in which the housing (BT) is of the flat type and without pins.

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