Protection of an authentication process

Abstract

Protection of an authentication process This description relates to a protection process (200) of an authentication process (201) of an electronic device comprising a memory (102) comprising a set (E) of pairs ((ok(1), nok(1)), …, (ok(N), nok(N)) of memory cells of which at least a first pair ((ok(1), nok(1)) comprising a first memory cell (ok(1)) storing a first data (Init) and a second memory cell (no(k1)) storing a second data (Init), the first pair being designated as the active pair in which: - at each success of the authentication process (201), the first memory cell is rewritten with a third data (Random);- at each failure of the authentication process the second memory cell is rewritten with a fourth piece of data (Random), then a failure counter is incremented and fifth pieces of data (Init) are written in a second pair ((ok(2), nok(2))) of memory cells, the second pair becoming the active pair. Figure for the abbreviation: Fig. 3;

Description

Title of the invention: Protection of an authentication method Technical field

[0001] The present description relates generally to electronic systems and devices, and their use concerning the implementation of authentication methods. More particularly, the present description relates to the protection, or securing, of authentication methods. Prior art

[0002] A communication between two electronic devices, or circuits, may be preceded, for reasons of security and / or confidentiality, by an authentication phase. During this phase, an authentication method, implemented by the two devices, makes it possible to verify, for example, whether the two devices are authorized to exchange information together, or, for example, whether one device is authorized to use one or more services implemented by the other device. The authentication method is a means of protection against malicious devices trying to access data and / or functionalities of other devices, but it may be important to protect the implementation of an authentication method.

[0003] According to another example, an authentication method can make it possible to verify the identity of a user before using an electronic device or using one or more services implemented by the electronic device.

[0004] It would be desirable to be able to improve, at least in part, the known authentication methods for electronic devices, and in particular the known means of protection of the authentication methods. Summary of the invention

[0005] There is a need to protect authentication methods implemented by electronic devices.

[0006] There is a need to protect authentication methods against power cut attacks.

[0007] One embodiment overcomes all or part of the drawbacks of the known protection means of authentication methods.

[0008] One embodiment provides a method of protecting an electronic device and an authentication method against power cut attacks.

[0009] One embodiment provides a protection method for verifying the correct incrementation of a failure counter associated with an authentication method.

[0010] One embodiment provides a protection method implemented by a electronic device configured to implement an authentication method and comprising a memory, the memory comprising a set of pairs of memory cells including at least a first pair comprising a first memory cell storing a first piece of data and a second memory cell storing a second piece of data, the first pair being selected as the active pair in which: - each time the authentication process is implemented successfully, the first memory cell of said active pair is rewritten with a third piece of data; - at each implementation of the authentication method resulting in a failure, the second memory cell of said active pair is rewritten with a fourth data item, then a failure counter associated with the authentication method is incremented, and finally fifth data items are written into a first and a second memory cell of a second pair of memory cells different from the first pair, the second pair becoming the active pair.

[0011] Another embodiment provides an electronic device configured to implement an authentication method and a protection method, the electronic device comprising a memory comprising a set of pairs of memory cells including at least a first pair comprising a first memory cell storing a first data item and a second memory cell storing a second data item, the first pair being selected as the active pair in which: - each time the authentication process is implemented successfully, the first memory cell of said active pair is rewritten with a third piece of data; - at each implementation of the authentication method resulting in a failure, the second memory cell of said active pair is rewritten with a fourth data item, then a failure counter associated with the authentication method is incremented, and finally fifth data items are written into a first and a second memory cell of a second pair of memory cells different from the first pair, the second pair becoming the active pair.

[0012] According to one embodiment, in an initial state all the memory cells of the set are erased with the exception of the memory cells of the first pair, the first pair being the active pair.

[0013] According to one embodiment, when the set only comprises written memory cells and a new implementation of the authentication method results in a failure, a reset step is executed.

[0014] According to one embodiment, the memory is a non-volatile memory.

[0015] According to one embodiment, the memory is a flash type memory.

[0016] According to one embodiment, the first, second, and fifth data are all identical, and the third and fourth data are random data.

[0017] Another embodiment provides a computer program product implementing implements the process described above.

[0018] Another embodiment provides a computer-readable data recording medium comprising a computer program product described above. Brief Description of the Drawings

[0019] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0020] [Fig.l] represents an example of an electronic device;

[0021] [Fig.2] represents a block diagram illustrating the steps of an embodiment of a method for protecting an authentication method;

[0022] [Fig.3] represents a diagram illustrating in more detail the implementation of the method of realization of [Fig.2]; and

[0023] [Fig.4] represents a diagram illustrating in more detail an example of implementation of the embodiment of [Fig.2]. Description of the embodiments

[0024] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0025] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, no detailed explanation is given concerning the authentication methods to which the protection method applies. Indeed, most of the usual authentication methods are compatible with the described embodiments.

[0026] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0027] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0028] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0029] The embodiments described below relate to the protection of an electrical device electronics, and more particularly the protection of a failure counter associated with an authentication process against malicious attacks. Indeed, it may be useful to count the implementations of an authentication process resulting in a failure, whether consecutive or not, to, for example, prevent a malicious user from authenticating with the electronic device.

[0030] The use of such a counter is however vulnerable to various types of malicious attacks, including, for example, power cut attacks. Indeed, in certain cases, it may be sufficient to turn off the power supply of said failure counter to prevent it from incrementing.

[0031] The embodiments described below propose the implementation of a protection mechanism associated with the counter and making it possible to secure the incrementation of the counter. This mechanism comprises the rewriting and writing of specific data in memory before and after the incrementation of the counter after a failure of the authentication method. These rewriting and / or writing operations are described in detail in relation to [Fig. 3]. When a power cut occurs, it is sufficient, at the time of restarting the device, to check the state of this specific data to determine whether the last implementation of the authentication method resulted in a failure or a success.

[0032] [Fig. 1] represents, very schematically and in the form of blocks, an example of an electronic device to which the embodiments described in relation to Figures 2 and 3 can be applied.

[0033] The device 100 is an electronic device adapted to process data, and which is configured, for example, to implement an authentication method. An authentication method is a method during which a first device, or a user, identifies itself to a second device, for example by exchanging an identifier and a password, or, for example, by proving knowledge of secret information such as a password, a personal identification number (PIN) or even a random value. During the implementation of the authentication method, the device 100 can indifferently have the role of the first device or the second device, or only have an intermediary role between the first and second devices. In addition, and according to one embodiment, the device 100 and the authentication method are insensitive to covert channel attacks.

[0034] In the remainder of the description, the failure of an authentication method is referred to as the case where an authentication method is implemented but does not result in the authentication of the first device, or of the user, with the second device. In addition, the success of the authentication method is referred to as the case where the authentication method is implemented and results in the authentication of the first device with the second device.

[0035] The device 100 is, furthermore, configured to implement a failure counter associated with said authentication method. More particularly, each time the authentication method fails, the counter is incremented. According to one example, such a failure counter can allow the device 100 to prevent a new implementation of the authentication method after a number of failures, consecutive or not, defined beforehand.

[0036] The device 100 comprises a processor 101 (CPU) for processing data. According to one example, the device 100 may comprise several processors each adapted to process different types of data. According to a particular example, the device 100 may comprise a main processor and a secure processor adapted to process only sensitive data. According to one example, the processor 101 may be configured to implement the authentication method and / or the failure counter described above.

[0037] The device 100 further comprises one or more memories 102 (MEM) in which data, for example binary data, are stored. According to one example, the device 100 comprises several types of memories, such as a read-only memory, a volatile memory, and / or a non-volatile memory. According to one embodiment, the device 100 comprises a non-volatile memory, and according to a preferred example this non-volatile memory is a Flash type memory, that is to say a non-volatile memory retaining the data that it stores even after a power cut. In addition, certain Flash type memories have an error detection and / or correction mechanism.

[0038] The device 100 further comprises, optionally, one or more input / output circuits 103 (F0) enabling the device 100 to transmit and / or receive data and / or energy with one or more external electronic devices.

[0039] The device 100 further comprises one or more circuits 104 (ALIM) supporting the power supply of the device 100. According to one example, the circuits 104 may comprise one or more batteries, energy conversion circuits, charging circuits, etc.

[0040] The device 100 further comprises, optionally, one or more secure elements (SE) 105 (SE) allowing the management of sensitive data, such as the storage or use of this data, or allowing, for example, the implementation of the authentication method. According to one example, the secure element 105 may be configured to implement the authentication method and / or the failure counter described above. According to one example, the secure element 105 may comprise one or more own processors of the type of the processor 101, memories of the type of the memories 102, input / output circuits of the type circuits 103, and circuits implementing various functions of the type of circuits 106.

[0041] The device 100 further comprises one or more circuits 106 (FCT) implementing one or more functionalities of the device 100. According to one example, the circuits 106 may comprise specific data processing circuits, such as encryption circuits, or circuits for performing measurements, such as sensors. According to one example, the circuit(s) 106 may be configured to implement the authentication method and / or the failure counter described above.

[0042] The device 100 further comprises one or more communication buses 107 allowing all the circuits of the device 100 to communicate. In [Fig.l], a single bus 107 connecting the processor 101, the memory(ies) 102, and the circuits 103 to 106 is shown, but in practice, the device 100 may comprise several communication buses connecting these different elements.

[0043] According to a particular embodiment, the device 100 is adapted to implement at least one counter, for example by using the processor 101 or a dedicated circuit among the circuits 106.

[0044] According to another embodiment, the device 100 is a complex electronic system such as a programmable electronic device, such as a computer. According to yet another embodiment, the device 100 consists of a single processor, or microprocessor, and a memory.

[0045] According to one embodiment, the device 100 is a secure element comprising at least one processor and a non-volatile memory. According to a preferred embodiment, the device 100 is a secure controller, or microcontroller.

[0046] [Fig.2] is a block diagram illustrating a mode of implementation of a protection method 200, or protection mechanism, of an authentication method implemented by a device of the device 100 described in relation to [Fig.l].

[0047] The protection method 200 comprises the rewriting, and writing if necessary, of one or more data stored in a non-volatile memory of the electronic device, these data are also called tags (Tag). According to one embodiment, the data concerned is stored in a non-volatile memory of the electronic device. According to a preferred embodiment, the data concerned is stored in a flash type memory of the electronic device.

[0048] In the remainder of the description, an unwritten memory cell, or erased memory cell, is a memory cell whose contents have been erased and whose reading generates an error. In other words, an unwritten memory cell is a memory cell containing no data. A written memory cell is a memory cell containing data written during a write operation, and whose reading returns the value of the stored data.

[0049] Furthermore, in the remainder of the description, a write operation is called an operation during which data is written into an unwritten memory cell, or an erased memory cell, and a rewrite operation is called an operation during which data is written into a written memory cell, i.e. an operation during which data is reprogrammed in place of the data stored in the written memory cell, or a step during which a memory cell is rewritten with other data.

[0050] In addition, the method 200 uses a set E of memory cells of the non-volatile memory to be implemented. Each memory cell is associated with, or is located at, a memory address and is capable of storing data.

[0051] The set of memory cells E comprises N pairs of memory cells, N being a positive integer. Each pair of memory cells is denoted (ok(n), nok(n)), n being an integer varying from 1 to N. The first memory cell ok(n) of a pair is linked to the successes of the authentication method, and the second cell nok(n) of a pair is linked to the failures of the authentication method.

[0052] The N pairs included in the set E are addressed sequentially so that the pairs are selected successively. The current pair is designated as the active pair of the set. To be the active pair, a pair must have two written memory cells.

[0053] According to a particular example, the set E is a part of the non-volatile memory comprising twice N memory cells. According to a particular example, the memory cells of the same pair have consecutive addresses.

[0054] The protection method 200 comprises an initial step 201 (AUT) of implementing the authentication method resulting either in a failure (output N of the block of step 201) or in a success (output Y of the block of step 201).

[0055] When step 201 results in a success, the next step is a step 202 (REWRITE) during which a rewriting operation of the first memory cell ok(n) of the active pair linked to the successes of the authentication method is implemented.

[0056] When step 201 results in a failure, the following step is a step 203 (REWRITE) during which a rewriting operation of the second memory cell nok(n) of the active pair linked to the failures of the authentication method is implemented.

[0057] At a step 204 (INC CNT), subsequent to step 203, the failure counter associated with the authentication method implemented in step 201 is incremented.

[0058] At a step 205 (WRITE), subsequent to step 204, two write operations of another pair of memory cells (ok(n+l), nok(n+l)) are implemented.

[0059] [Fig.3] illustrates in more detail the rewrite and write operations implemented during steps 202, 203 and 205. [Fig.4] illustrates in more detail the advantages of method 200 in the face of a power cut attack.

[0060] An advantage of this embodiment is that as long as the implementations of the authentication method result in successes, only one rewrite operation is performed. In other words, a success of an authentication method does not result in the writing of data in memory cells not written to until then. The number of erase operations is therefore limited. This has the advantage of limiting the wear of certain memories such as memories for which an erase operation is necessary.

[0061] [Fig. 3] is a diagram illustrating a practical example of the steps of rewriting and writing the memory cells of the set E described in relation to [Fig. 2].

[0062] As described previously, steps 202, 203 and 205 comprise the rewriting, and writing if applicable, of one or more data stored in memory cells of a non-volatile memory of the electronic device.

[0063] The general operation of the method 200 is as follows.

[0064] Each time the authentication method is successful, the first memory cell ok(n) of the active pair (ok(n), nok(n)) is rewritten, and the second memory cell nok(n) is left unchanged, this is step 202 described in relation to [Fig.2]. More particularly, the pair (ok(n), nok(n)) being the active pair, the memory cells ok(n) and nok(n) are written memory cells, and a data item is rewritten in the memory cell ok(n) in place of the previous data item. The pair (ok(n), nok(n)) is always selected as the active pair.

[0065] Each time the authentication method fails, the second memory cell nok(n) of the active pair (ok(n), nok(n)) is rewritten, and the first memory cell ok(n) is left unchanged, this is step 203 described in relation to [Fig.2]. More particularly, a data item is rewritten in the memory cell nok(n) in place of the previous data item. The failure counter is incremented, then data is written in another pair (ok(i), nok(i)), i being an integer varying from 1 to N and being different from n, comprising only erased memory cells, this is step 205 described in relation to [Fig.2]. According to a particular embodiment, the other pair (ok(i), nok(i)) is the next pair of memory cells, i.e. the pair (ok(n+l modulo N), nok(n+l modulo N)). The pair (ok(i), nok(i)) then becomes the new active pair, and the pair (ok(n), nok(n)) is no longer the active pair.

[0066] According to a particular example, in an initial state (A), no authentication method has yet been implemented by the electronic device, and only a pair (ok(n), nok(n)) comprises written memory cells, for example the pair (ok(l), nok(l)). This pair (ok(l), nok(l)) is selected to be the active pair. According to an example, a fixed data Init is written in the memory cells ok(l), and nok(l). As a result, all the other memory cells of the other pairs of the set are erased, that is to say the cells of the pairs (ok(2), nok(2)) to (ok(N), nok(N)). In [Fig.3] and 4 the erased memory cells are designated by the reference Erased.

[0067] If the following implementation of the authentication method results in success, the following state is a state (B), on the contrary if the following implementation of the authentication method results in failure, the following state is a state (C).

[0068] In state (B), the previous implementation of the authentication method is successful, consequently step 202 of [Fig.2] is implemented. In other words, a Random data item is rewritten in the memory cell ok(l) in place of the fixed data item Init. No other rewriting or writing operation is implemented. The pair (ok(l), nok(l)) remains the active pair. According to a particular embodiment, then the Random data item is, for example, a random data item different from the fixed data item.

[0069] In state (C), the previous implementation of the authentication method is a failure, consequently steps 203 to 205 of [Fig.2] are implemented. In other words, a Random data item is rewritten in the memory cell nok(l). The failure counter is incremented by one unit. And finally, data are written in another pair of memory cells comprising erased memory cells, for example the pair (ok(2), nok(2)). The fixed data item Init is written in the memory cell ok(2) and in the memory cell nok(2). This pair (ok(2), nok(2)) becomes the active pair.

[0070] Furthermore, once all the pairs of memory cells are written, an operation of erasing the data written in all the memory cells of the set E is implemented, and data is written in the memory cells of a pair to return to the initial state (A). According to an alternative embodiment, the memory cells of the set E can be erased regularly by group. Indeed, for certain types of volatile memories, such as flash type memories, an operation of erasing data written in memory generally comprises the erasing of data written in an elementary group composed of several memory cells, called a page. Thus, each time a page of the set E is completely filled, an erasure operation takes place before writing new data in the page.

[0071] By using the protection method 200 described herein, it is possible to know whether the authentication method has been targeted by a power supply attack or not. In addition, this protection method also makes it possible to know whether the last implementation of the authentication method resulted in success or failure, even in the case where an attack by cutting off the power supply of the electronic device is executed. This is described in more detail in relation to [Fig. 4].

[0072] Furthermore, as stated above, the embodiment of the protection method may be a program product implemented by a programmable device or a computer. Furthermore, when the embodiment is a computer program product or a programmable device program product, it may be recorded in a data recording medium readable by a computer or by said programmable device.

[0073] [Fig. 4] comprises diagrams illustrating the state of the memory cells of the set E of the protection method after a power-down attack has been implemented and the device has been restarted. More particularly, [Fig. 4] comprises six diagrams (D), (E), (F), (G) (H) and (I) representing the different possible states that pairs of memory cells of the set (E) may have following a reset.

[0074] Diagram (D) represents the state preceding the implementation of the authentication method and preceding the execution of the attack. In the state of diagram (D), an initial data item Init has been written in the memory cells of the pair (ok(l), nok(l)) which is the active pair. In this example, the same data item Init is written in the two memory cells of the active pair at the time of its initialization, and a data item Random is rewritten in place of the data item Init in the corresponding memory cell during a rewriting step. According to one embodiment, the data Init and Random are different, it is thus possible to differentiate a written data item (Init) from a rewritten data item (Random). More particularly, and according to one embodiment, the data item Init is a data item with a fixed value, and the data item Random is a random data item. Other starting states can be envisaged.

[0075] Diagram (D) also represents the state obtained when the authentication method has been implemented and a power-down attack has been executed just before the rewriting step is performed, whether it is the rewriting step of the memory cell ok(l) or that of the memory cell nok(l). It is impossible to determine from observing this state whether the authentication method resulted in success or failure, as this method is insensitive to covert channel attacks. Thus, the attacker cannot deduce anything from his attack.

[0076] Diagram (E) represents the apparent state when the authentication method has resulted in success and a power cut attack has been executed during the step of rewriting the memory cell ok(l) with the Random data, i.e. during step 202 of [Fig.2]. The rewriting step having been interrupted by the attack, the memory cell ok(l) no longer stores the Init data, but its reading returns the Random data or an Err error. It is possible in this case to determine that the last implementation of the execution method is a success, because the data stored in the memory cell ok(l) is different from the Init data. Step rewriting of the memory cell ok(l) can be restarted, if necessary. In addition, a memory error detection and / or correction mechanism can be implemented here. The implementation of such a mechanism can be executed, optionally, as an alternative or in addition to the embodiment to determine whether the last implementation of the execution method resulted in success.

[0077] Diagram (F) represents the apparent state when the authentication method resulted in failure and a power-down attack was executed during the step of rewriting the memory cell nok(l) with the Random data, i.e. during the implementation of step 203 of [Fig.2]. The rewriting step having been interrupted by the attack, the memory cell nok(l) does not store the Init data, but its reading returns the Random data or an error.In this case, it is possible to determine that the last implementation of the execution method is a failure, because the data stored in the memory cell nok(l) is different from the Init data, and because the data stored in the memory cell ok(l) is the Init data. The step of rewriting the memory cell nok(l), the step of incrementing the counter and the steps of writing the following pair (ok(2), nok(2)) can be restarted. As previously, an error detection and / or correction mechanism can be implemented here.

[0078] Diagram (G) represents the apparent state when the authentication method has resulted in a failure and a power-down attack has been executed during the step of incrementing the failure counter associated with the authentication method, i.e., during the implementation of step 204 of [Fig. 2]. Since the incrementation step was interrupted by the attack, the value of the counter may not have been modified. In addition, the write operations of step 205 could not be implemented either. It is therefore possible in this case to determine that the last implementation of the execution method is a failure. Indeed, if the active couple has the Random data written in its second memory cell, that is to say the memory cell nok(l) here, and if the cells ok(2) and nok(2) are erased, this indicates that the active couple change step could not take place.The counter incrementation step and the writing steps of the next pair (ok(2), nok(2)) can be restarted. As before, an error detection and / or correction mechanism can be implemented here. It should be noted that if the counter incrementation could take place, the counter will be incremented twice for a single failure of the authentication process.

[0079] Diagram (H) represents the apparent state when the authentication process has resulted in a failure and a power-down attack has been executed during the step of writing the Init data into the ok(2) memory cell. The writing step having been interrupted by the attack, the ok(2) memory cell does not store the data Init, but the undetermined data Err, and reading the memory cell ok(2) returns an error or data different from the Init value. In this case, it is possible to determine that the last implementation of the execution method is a failure, since the memory cell nok(2) is erased. The writing steps of the following pair (ok(2), nok(2)) can be restarted. A step of reading the memory cell nok(2) is implemented to check whether the write operation was performed correctly. As before, an error detection and / or correction mechanism can be implemented here.

[0080] If the attack takes place during the counter incrementation step, the latter is incremented again at the next reset of the device.

[0081] Diagram (I) represents the apparent state when the authentication method has resulted in a failure and a power-down attack has been executed during the step of writing the Init data item into the nok(2) memory cell. The writing step having been interrupted by the attack, the nok(2) memory cell does not store the Init data item, and reading the nok(2) memory cell returns an error or data item different from the Init value. In this case, it is possible to determine that the last implementation of the execution method is a failure. The step of writing the Init data item into the nok(2) memory cell can be restarted. A step of reading the nok(2) memory cell is implemented to check whether the write operation has been performed correctly. As previously, an error detection and / or correction mechanism can be implemented here.

[0082] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0083] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. Protection method (200) implemented by an electronic device (100) configured to implement an authentication method (201) and comprising a memory (102), the memory (102) comprising a set (E) of pairs ((ok(l), nok(l)), (ok(N), nok(N)) of memory cells including at least a first pair ((ok(l), nok(l)) comprising a first memory cell (ok(l)) storing a first data item (Init) and a second memory cell (no(kl)) storing a second data item (Init), the first pair ((ok(l), nok(l)) being designated as the active pair in which: - at each implementation of the authentication method (201) resulting in a success the first memory cell (ok(l)) of said active pair is rewritten with a third data item (Random);- at each implementation of the authentication method resulting in a failure, the second memory cell (nok(l)) of said active pair is rewritten with a fourth data item (Random), then a failure counter associated with the authentication method is incremented, and finally fifth data items (Init) are written into a first and a second memory cell (ok(2), nok(2)) of a second pair ((ok(2), nok(2))) of memory cells different from the first pair ((ok(l), nok(l))), the second pair ((ok(2), nok(2))) becoming the active pair.;

2. Method according to claim 1, in which in an initial state all the memory cells of the set (E) are erased with the exception of the memory cells of the first pair ((ok(l), nok(l))), the first pair being the active pair.

3. Method according to claim 2, wherein when the set (E) comprises only written memory cells and a new implementation of the authentication method results in a failure, a reset step is executed.

4. A method according to any one of claims 1 to 3, wherein the memory (102) is a non-volatile memory.

5. The method of claim 4, wherein the memory (102) is a flash type memory.

6. A method according to any one of claims 1 to 5, wherein the first, second, and fifth data (Init) are all identical, and the third and fourth data (Random) are data random.

7. Computer program product implementing the method according to any one of claims 1 to 6.

8. A computer-readable data recording medium comprising a computer program product according to claim 7.

9. Electronic device (100) configured to implement an authentication method (201) and a protection method (200), the electronic device (100) comprising a memory (102) comprising a set (E) of pairs ((ok(l), nok(l)), (ok(N), nok(N)) of memory cells including at least a first pair ((ok(l), nok(l))) comprising a first memory cell (ok(l)) storing a first data item (Init) and a second memory cell (no(kl)) storing a second data item (Init), the first pair ((ok(l), nok(l))) being selected as the active pair in which: - at each implementation of the authentication method (201) resulting in a success the first memory cell (ok(l)) of said active pair is rewritten with a third data item (Random);- at each implementation of the authentication method resulting in a failure, the second memory cell (nok(l)) of said active pair is rewritten with a fourth data item (Bran(l-2)), then a failure counter associated with the authentication method is incremented, and finally, fifth data items (Init) are written into a first and a second memory cell (ok(2), nok(2)) of a second pair ((ok(2), nok(2))) of memory cells different from the first pair ((ok(l), nok(l))), the second pair ((ok(2), nok(2))) becoming the active pair.;

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