Quantum device for forming a matrix of quantum dots and associated manufacturing method
The quantum device addresses the challenges of electrostatic and chemical potential control in quantum computing by using a matrix of grids within a semiconductor layer, achieved through a self-aligned manufacturing method, resulting in efficient and controlled quantum dot operation without charged particles outside the dots.
Patent Information
- Application Number
- FR2022014000
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2022-12-20
- Publication Date
- 2025-05-23
- Estimated Expiration
- 2042-12-20
AI Technical Summary
Existing quantum computing devices struggle to achieve homogeneous electrostatic control and local control of chemical potential within quantum dots, while also ensuring the absence of charged particles outside the quantum dots, and require complex manufacturing processes with strict alignment constraints.
A quantum device comprising an active semiconductor layer with a matrix of quantum dots, where first, second, and fourth grids provide electrostatic control and ensure the absence of charged particles, and third grids allow local control of chemical potential, all achieved through a self-aligned manufacturing method using a single lithography level.
The device achieves homogeneous electrostatic control and local control of chemical potential within each quantum dot, ensuring the absence of charged particles outside the quantum dots, while simplifying the manufacturing process by eliminating the need for precise multi-level lithography alignment.
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Abstract
Description
Title of the invention: Quantum device intended to form a matrix of quantum dots and associated manufacturing method TECHNICAL FIELD OF THE INVENTION
[0001] The technical field of the invention is that of quantum computing.
[0002] The present invention relates to a semiconductor device comprising means for forming a matrix of quantum dots and in particular a device for controlling the chemical potential within each quantum dot and the coupling between adjacent quantum dots, this control being carried out locally, while guaranteeing the absence of charged particles outside the quantum dots. The present invention also relates to a manufacturing method for obtaining such a device. TECHNOLOGICAL BACKGROUND OF THE INVENTION
[0003] In the field of quantum computing, it is known to use quantum dots in which one or more charged particles can be trapped to be manipulated. For this, the confinement of the charged particles must be done in the three dimensions of space. In the state of the art, such confinement can be obtained in two ways (which can be used in combination): structurally (by alternating materials along at least one dimension of space) and / or electrostatically by applying a potential to a portion of conductive material (for example using a gate electrode). Generally, quantum dots are arranged in the form of a matrix of quantum dots which allows better interconnectivity between quantum dots and therefore, for example, more efficient execution of quantum error correction algorithms (see for example Flowler, Phys. Rev. A, 2012).
[0004] A quantum dot matrix has for example been proposed in the document Li et al., Science, 2018. In this document, the authors propose a structure comprising three grid levels: according to the rows, columns and diagonals of the quantum dot matrix, these grid levels making it possible to control the chemical potential in each quantum dot as well as the potential barriers (or tunnel coupling) between adjacent quantum dots. On the other hand, the device does not allow to completely control the position of the charged particles and, in particular, to prohibit the presence of the latter outside the quantum dots, that is to say between the rows and columns of the quantum dot matrix. In addition, the use of three grid levels implies a screening of the upper grid levels by the lower grid levels which results in a strong disparity between the different levels of grid (the first level grid appears continuous while the second and third level grids take the form of a dotted line).
[0005] Another architecture has been proposed in document FR3066297. In the latter, the active layer of the quantum dot matrix is structured so as to prohibit the presence of charged particles outside the quantum dots, i.e. between the rows and columns of the quantum dot matrix. Furthermore, the proposed device also comprises a plurality of grids for controlling the potential barriers between the adjacent quantum dots of the quantum dot matrix. On the other hand, given the difficulty of implementation, the proposed device does not comprise a grid allowing local control of the chemical potential within each quantum dot.In addition, the control of the grids is carried out using vias which allows good homogeneity between the grids, but on the other hand imposes very strict constraints in terms of relative alignment of the different levels of grids, and therefore a complex manufacturing process to implement making...
[0006] There is therefore a need for a device making it possible to obtain both homogeneous electrostatic control, local control (i.e. by a grid located above the element to be controlled) of the chemical potential within each quantum box and a means of guaranteeing the absence of electric charge between the rows and columns of the matrix. There is also a need for a method making it possible to obtain such a device without imposing very strict alignment constraints during manufacturing. Summary of the invention
[0007] The invention offers a solution to the problems mentioned above, by proposing a device making it possible to obtain both homogeneous electrostatic control, local control (i.e. by a grid located directly above the element to be controlled) of the chemical potential within each quantum box and a means of guaranteeing the absence of charged particles between the rows and columns of the matrix. It achieves this thanks in particular to the implementation of a method making it possible to produce the grids as well as the patterns between the rows and columns of the quantum box matrix in a self-aligned manner and on a single lithography level.
[0008] For this, a first aspect of the invention relates to a quantum device configured to form a matrix of quantum dots, the device comprising: • An active layer made of a semiconductor material; • A plurality of first grids arranged along a plurality of lines; • A plurality of second grids arranged in a plurality of columns perpendicular to the lines of the plurality of lines; • A plurality of third grids, each third grid of the plurality of third grids being arranged at the intersection of a row of the plurality of rows and a column of the plurality of columns, each third grid being separated from the nearest third grids, on a row by a first grid and on a column by a second grid; • A plurality of fourth grids, each fourth grid being arranged between two second grids along the rows and between two first grids along the columns.
[0009] Thanks to the device according to the invention, it is possible to obtain homogeneous electrostatic control making it possible in particular to guarantee the absence of electric charge between the rows and the columns of the matrix, a local control (i.e. by a grid located directly above the element to be controlled) of the chemical potential within each quantum box. More particularly, in the device according to the invention, a quantum box can be formed below each third grid so as to form a matrix of quantum boxes. Indeed, each first grid of the plurality of first grids makes it possible, when an electric potential is applied to it, to modify the potential barrier separating two parts of the active layer located under two adjacent third grids along the rows.Likewise, each second grid of the plurality of second grids allows, when an electric potential is applied thereto, to modify the potential barrier separating two parts of the active layer located under two adjacent third grids according to the columns. In addition, each fourth grid of the plurality of fourth grids allows, when an electric potential is applied thereto, to form a potential barrier guaranteeing the absence of charged particles below said grid, that is to say between the rows and the columns of the matrix. Furthermore, the first grids, the second grids and the fourth grids allow this modification to be carried out locally, the latter not being screened by a conductive layer (in other words, there is no conductive layer between the oxide of the first grids, the second grids and the fourth grids and the active layer).Also, by controlling the potential barriers exerted by the first grids, the second grids and the fourth grids, it is possible to achieve electrostatic confinement of the charged particles below the third grids of the plurality of third grids to form a quantum dot below each third grid.
[0010] Furthermore, in each quantum box, the charged particle(s) present are associated with a chemical potential. However, each third grid not being “screened” by a conductive layer (in other words, there is no conductive layer between the oxide of the third grids and the active layer), each third grid of the plurality of third grids allows, when an electrical potential is applied to it, to modify the chemical potential of the charged particles present in the quantum box. associated with the third grid considered.
[0011] In addition to the characteristics which have just been mentioned in the preceding paragraph, the device according to the first aspect of the invention may have one or more complementary characteristics among the following, considered individually or according to all technically possible combinations.
[0012] In one embodiment, the device is made from a “silicon on insulator” (or SOI) type substrate, the active layer being made in the silicon layer of the substrate located above the oxide.
[0013] In one embodiment, the device is made from a bulk silicon substrate. Advantageously, the substrate comprises an epitaxially grown silicon layer covered with a thermal oxide. In this embodiment, the active layer is made in the silicon layer, preferably epitaxially grown.
[0014] In one embodiment, the device is made from a Si / SiGe heterostructure, the active layer being made in the Si layer.
[0015] In one embodiment, the device is made from a Ge / SiGe heterostructure, the active layer being made in the Ge layer.
[0016] In one embodiment, the device comprises spacers arranged to separate each of the first grids, second grids, third grids and fourth grids from adjacent first grids, second grids, third grids and fourth grids.
[0017] In one embodiment, each first gate, second gate, third gate, and fourth gate comprises a gate electrode and a gate oxide, and the material of the electrode and gate oxide of the first gates, second gates, third gates, and fourth gates are the same.
[0018] In one embodiment, the oxide of the first, second, third and / or fourth grids is chosen from SiO2, HfO2 or Al2O3.
[0019] In one embodiment, the thickness of the oxide of the first gates, second gates, third gates and / or fourth gates is between 5 nm and 10 nm.
[0020] In one embodiment, the electrodes of the first grids, second grids, third grids and / or fourth grids are made of a conductive material chosen from Ti, TiN, poly-Si or even W.
[0021] A second aspect of the invention relates to a method of manufacturing a semiconductor device from a substrate comprising a semiconductor layer, called an active layer, at a first surface of said substrate (i.e. on a first surface of said substrate or close to the first surface of said substrate), the method comprising: • A step of depositing a first dielectric layer on the first surface; A step of depositing a support layer in a conductive or dielectric material on the first dielectric layer; A step of etching the support layer so as to form a matrix of first pillars forming a plurality of rows and a plurality of columns, the first pillars forming the fourth grids when the support layer is in a conductive material; A step of conformal deposition of a second dielectric layer on the matrix of first pillars, the thickness deposited being chosen so as to fill the space between each first pillar and its closest neighbors; A step of etching the second dielectric layer so as to expose the first dielectric layer between each first pillar of the matrix of first pillars along the diagonals of said matrix of first pillars; A step of depositing a first conductive layer so as to fill the openings made during the step of etching the second dielectric layer; a step of chemical-mechanical polishing of the structure obtained at the end of the previous step so as to obtain a matrix of second conductive pillars at the openings made during the step of etching the second dielectric layer, the polishing being stopped on the support layer so that the second conductive pillars are no longer in contact with each other at the end of this step and form the third grids; A step of selectively removing the second dielectric layer so as to retain on the first dielectric layer only the matrix of first pillars and the matrix of second pillars; A step of conformal deposition of a third dielectric layer on the matrix of first pillars and the matrix of second pillars, the thickness deposited being chosen so as to fill the space between each first pillar and the second conductive pillars closest to said first pillar; A step of etching the third dielectric layer so as to expose the first dielectric layer between each first pillar of the matrix of first pillars according to the rows and columns of said matrix of first pillars; A step of depositing a second conductive layer so as to fill the openings made during the step of etching the third dielectric layer; a step of chemical-mechanical polishing of the structure obtained at the end of the previous step, so as to obtain a matrix of third conductive pillars at the level of the openings made during the etching step of the third dielectric layer, the polishing being stopped on the support layer so that the third conductive pillars are not in contact with each other at the end of this step and form the first grids and the second grids; • When the material of the support layer is a dielectric material, a step of selectively removing the first pillars of the plurality of first pillars so as to expose the first dielectric layer at the location of said first pillars; • When the material of the support layer is a dielectric material, a step of depositing a third conductive layer in the space left by the first pillars during the previous selective removal step; • When the material of the support layer is a dielectric material, a step of mechanically-chemically polishing the structure obtained at the end of the previous step, so as to obtain a matrix of fourth conductive pillars at the location of the first pillars, the polishing being stopped such that the fourth conductive pillars are no longer in contact with each other at the end of this step.
[0022] Thanks to the method according to the invention, it is possible to obtain a device according to the invention by self-alignment by using only one level of lithography. The method is thus greatly simplified compared to the methods of the prior art in which several levels of lithography (and therefore for which precise alignment is necessary) and / or partial masking of the grids between them) are present.
[0023] In addition to the characteristics which have just been mentioned in the preceding paragraph, the method according to the second aspect of the invention may have one or more complementary characteristics among the following, considered individually or according to all technically possible combinations.
[0024] In one embodiment, the substrate is a “silicon on insulator” type substrate and the active layer is made in the silicon layer of the substrate located above the oxide.
[0025] In one embodiment, the material of the first dielectric layer is chosen from SiO2, HfO2 or even Al2O3.
[0026] In one embodiment, the distance d separating two neighboring first pillars and the height h of the first pillars at the end of the step of etching the support layer so as to form a matrix of first pillars are chosen so that h> d / 2.
[0027] In one embodiment, the method comprises, at the end of the step of etching the second dielectric layer, a step of chemical-mechanical polishing of the structure obtained at the end of the previous step.
[0028] In one embodiment, the method comprises, before the step of etching the third dielectric layer, a step of chemical-mechanical polishing of the structure obtained at the end of the previous step.
[0029] In one embodiment, the method comprises, after the step of chemical-mechanical polishing of the structure obtained at the end of the step of depositing a second conductive layer, a step of chemical-mechanical over-polishing of the structure obtained at the end of the previous chemical-mechanical polishing step.
[0030] The invention and its various applications will be better understood upon reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES
[0031] The figures are presented for information purposes only and in no way limit the invention.
[0032] [Fig. 1] shows a schematic representation of a device according to the invention.
[0033] [Fig. 2A] to [Fig. 2C] show a schematic representation of different substrates that can be used in a device or method according to the invention.
[0034] [Fig. 3] shows a schematic representation of an SOI type substrate used in a method according to the invention and used in the illustrations of the different steps of the method.
[0035] [Fig.4A] to [Fig.4J] show a schematic representation of the steps of the method according to the invention (the step(s) associated with each figure appearing in parentheses). DETAILED DESCRIPTION
[0036] Unless otherwise specified, the same element appearing in different figures has a single reference.
[0037] Auxiliary device for forming a matrix of auxiliary boxes
[0038] A first aspect of the invention illustrated in [Fig.l] relates to a quantum device DQ configured to form a matrix of quantum dots QD. For this, the device DQ comprises an active layer CA made of a semiconductor material. Preferably, this layer CA is a layer of silicon (Si) or germanium (Ge), but other semiconductor materials can be envisaged. It is in this active layer CA that the quantum dots QD will be formed. For the record, a quantum dot QD is formed by an electrostatic potential well in which it is possible to trap one or more charged particles, for example one or more holes or one or more electrons.
[0039] The QD device according to the invention also comprises a plurality of first grids G1 arranged along a plurality of lines LI, above the active layer CA. The device according to the invention also comprises a plurality of second grids G2 arranged along a plurality of columns CO perpendicular to the lines LI of the a plurality of lines LI, above the active layer CA. The device DQ according to the invention further comprises a plurality of third grids G3, each third grid G3 of the plurality of third grids G3 being arranged at the intersection of a line LI of the plurality of lines LI and a column CO of the plurality of columns CO, above the active layer CA, each third grid G3 being separated from the closest third grids G3, on a line LI by a first grid G1 and on a column CO by a second grid G2. Finally, the device DQ according to the invention comprises a plurality of fourth grids G4, each fourth grid G4 being arranged between two second grids G2 along the lines LI and between two first grids G1 along the columns CO, above the active layer CA.
[0040] Thus, in the DQ device according to the invention, a quantum dot QD may be formed below each third gate G3 so as to form a matrix of quantum dots QD. Indeed, each first gate G1 of the plurality of first gates G1 makes it possible, when an electrical potential is applied to it, to modify the potential barrier separating two parts of the active layer CA located under two adjacent third gates G3 along the lines. Similarly, each second gate G2 of the plurality of second gates G2 makes it possible, when an electrical potential is applied to it, to modify the potential barrier separating two parts of the active layer CA located under two adjacent third gates G3 along the columns CO.In addition, each fourth grid G4 of the plurality of fourth grids G4 allows, when an electric potential is applied to it, to form a potential barrier guaranteeing the absence of charged particles below said grids G4, that is to say between the rows and the columns of the matrix. In addition, the first grids G1, second grids G2 and the fourth grids G4 allow this modification to be carried out locally, the latter G1, G2, G4 being above the active layer CA (in other words, there is no conductive layer between the oxide of the first grids G1, the second grids G3 and the fourth grids G4 and the active layer CA).Also, by controlling the potential barriers exerted by the first G1 grids, the second G2 grids and the fourth G4 grids, it is possible to achieve electrostatic confinement of the charged particles below the third G3 grids of the plurality of third G3 grids to form a quantum dot QD under each third G3 grid.
[0041] Furthermore, in each quantum box QD, the charged particle(s) present are associated with a chemical potential. Now, each third gate G3 being above the part of the active layer CA in which a quantum box is formed (in other words, there is no conductive layer between the oxide of the third gates G3 and the active layer CA), each third gate G3 of the plurality of third gates G3 allows, when an electrical potential is applied to it, modify the chemical potential of the charged particles present in the quantum dot QD associated with the third grid G3 considered.
[0042] In one embodiment, the oxide of the first G1, second G2, third G3 and / or fourth G4 gates is chosen from SiO2, HfO2 or Al 2O3. In one embodiment, the thickness of the oxide of the first G1 gates, second G2 gates, third G3 gates and / or third G4 gates is between 5 nm and 10 nm. In one embodiment, the electrodes of the first G1 gates, second G2 gates, third G3 gates and / or fourth G3 gates are made of a conductive material chosen from Ti, TiN or W. In one embodiment, the device according to the invention is made in an SOI type substrate and the active layer is a silicon layer. In this embodiment, the first, second, third and fourth grids G1, G2, G3, G4 are in direct contact with the active layer CA.
[0043] In an alternative embodiment, the device is made from a bulk silicon substrate. Advantageously, the substrate comprises an epitaxial silicon layer (denoted 28Si in the figure) covered with a thermal oxide (denoted SiO2 in the figure), this epitaxial silicon layer being deposited on the intrinsic silicon layer (denoted 'Si in the figure) of the bulk silicon substrate. Such a substrate is illustrated in [Fig.2A]. In this embodiment, the active layer CA is made in the silicon layer, advantageously the epitaxial silicon layer. The dimensions indicated in the figure are of course given for purely illustrative purposes.
[0044] In an alternative embodiment, the device is made from a Si / SiGe heterostructure. A substrate comprising such a heterostructure is illustrated in [Fig.2B]. The latter comprises a layer whose Ge concentration evolves linearly (denoted Sii_xGex in the figure) on which rests a SiGe layer (denoted Sio.7Geo.3), a quantum well intended for electrons formed in a Si layer (denoted 28Si in the figure), a SiGe spacer (denoted Sio.7Geo.3 in the figure) located on the Si layer and a silicon layer (denoted Si Cap in the figure). In this embodiment, the active layer is made in the Si layer. The dimensions indicated in the figure are of course given for purely illustrative purposes.
[0045] In an alternative embodiment, the device is made from a Ge / SiGe heterostructure. A substrate comprising such a heterostructure is illustrated in [Fig.2C]. The latter comprises a layer whose Si concentration evolves linearly (denoted Si ixGcx in the figure) on which rests a layer of SiGe (denoted Sio.2Geo.8), a quantum well intended for the holes formed in a layer of Ge (denoted Ge in the figure), a spacer in SiGe (denoted Si0.2Ge0.8 in the figure) located on the layer of Ge and a layer of silicon (denoted Si Cap in the figure). In this embodiment, the active layer is made in the Ge layer. The dimensions indicated in the figure are of course given for purely illustrative purposes.
[0046] Method for manufacturing an anti-aging device comprising an array of islands
[0047] A second aspect of the invention illustrated in [Fig. 3] to [Fig. 4J] relates to a method for manufacturing a semiconductor device according to the invention from a substrate SB comprising a semiconductor layer, called active layer CA, on a first surface of said substrate SB or close to the first surface. Close to the first surface is understood to mean that the distance separating the active layer from the first surface is less than the distance separating the active layer from the second surface of the substrate opposite the first surface. Preferably, the distance separating the active layer CA from the first surface of the substrate SB is less than 500 nm, preferably less than 200 nm, or even less than 100 nm. In one embodiment, the thickness of the active layer CA is between 5 and 20 nm, for example equal to 10 nm.
[0048] In one embodiment, the active layer CA is made of silicon, the substrate preferably being a SOI (Silicon-On-Insulator) type substrate. In an alternative embodiment, the substrate is a SiMOS type substrate as described previously. In an alternative embodiment, the substrate comprises a Si / SiGe heterostructure as described previously at its first surface. In an alternative embodiment, the substrate comprises a Ge / SiGe heterostructure as described previously at its first surface.
[0049] The method according to the invention comprises a step E1 of depositing a first dielectric layer DI on the first surface. When the active layer CA is at this first surface (as illustrated in [Fig.3] to [Fig.4J], then this deposition is carried out on the active layer CA. In one embodiment, the material of the first dielectric layer DI is chosen from SiO2, HfO2 or even Al2O3. In one embodiment, the first dielectric layer DI is made of a high permittivity dielectric material. In one embodiment, the first dielectric layer DI comprises several dielectric sub-layers. For example, it comprises a first sub-layer of SiO2 ensuring good interface quality with the layer on which it is deposited (for example the active layer of Si), then a second sub-layer of HfO2 or Al2O3. This is of course only an example and other combinations can be envisaged.
[0050] The method then comprises a step E2 of depositing a support layer SP on the first dielectric layer DI. In one embodiment, the material of the support layer SP is a dielectric material, for example silicon nitride. In an alternative embodiment, the material of the support layer SP is a conductive material, for example a metal. The structure obtained at the end of these two steps is illustrated in [Fig.4A].
[0051] As illustrated in [Fig.4B], the method then comprises a step E3 of etching the support layer so as to form a matrix of first PI pillars forming a plurality of rows and a plurality of columns. Preferably, the distance d separating two neighboring first PI pillars and the height h of the first PI pillars are chosen so that h > d / 2. Preferably, the height h of the first pillars is between 50 nm and 500 nm, for example equal to 200 nm.
[0052] The method also comprises a step E4 of conformal deposition of a second dielectric layer D2 on the matrix of first pillars PI, the deposited thickness being chosen so as to fill the space between each first pillar PI and its closest neighbors. In one embodiment, the dielectric layer D2 is made of SiO2. In one embodiment, the second dielectric layer D2 comprises several dielectric sub-layers.
[0053] The method then comprises a step E5 of etching the second dielectric layer D2 so as to expose the first dielectric layer DI between each first pillar PI of the matrix of first pillars PI along the diagonals of said matrix of first pillars PI, the first dielectric layer DI serving as a stop layer for the etching. In an exemplary embodiment, the second dielectric layer D2 is a layer of SiO2 and the first dielectric layer DI (serving as a stop layer) is a layer of HfO2 or Al2O3. The structure obtained at the end of these two steps E4, E5 is illustrated in [Fig.4C], the exposed areas of the first dielectric layer DI being marked by a dotted circle in the top-to-bottom representation of the figure.
[0054] In one embodiment, the method also comprises a step E6 of chemical-mechanical polishing of the structure obtained at the end of the preceding step E5. Although optional, this step E6 makes it possible to flatten the surface of the structure and thus to improve the quality of the deposition of the first conductive layer described below. In addition, carrying out the chemical-mechanical polishing in two stages makes it possible to avoid any selectivity problem with the chemical-mechanical polishing carried out at the end of the deposition of the first conductive layer described below.
[0055] The method according to the invention then comprises a step E7 of depositing a first conductive layer so as to fill the openings made during step E5 of etching the second dielectric layer D2. Thus, at these openings, the conductive layer is in direct contact with the first dielectric layer DI. In one embodiment, the material of the conductive layer is chosen from Ti, TiN or even W.
[0056] The method according to the invention further comprises a step E8 of chemical-mechanical polishing of the structure obtained at the end of the previous step so as to obtain a matrix of second conductive PCI pillars at the openings made during of step E5 of etching the second dielectric layer D2. During this step E8, the polishing is stopped on the support layer SP so that the second PCI pillars are no longer in contact with each other at the end of this step E8. The structure obtained at the end of these two steps or three steps (when the optional chemical-mechanical polishing step E6 is implemented) is illustrated in [Fig.4D]. In the final structure obtained at the end of the method according to the invention, the second conductive PCI pillars will form the third grid G3 of [Fig.1] making it possible to control the chemical potential of the charged particles at the level of the quantum dots QD.
[0057] As illustrated in [Fig.4E], the method then comprises a step E9 of selective removal of the second dielectric layer D2 so as to retain on the first dielectric layer D1 only the matrix of first pillars PI and the matrix of second pillars PCI. During this removal step, the first dielectric layer DI is preserved and serves as a stop layer.
[0058] The method then comprises a step E10 of conformal deposition of a third dielectric layer D3 on the matrix of first pillars PI and on the matrix of second pillars PCI, the thickness deposited being chosen so as to fill the space between each first pillar PI and the second pillars PC2 closest to said first pillar PI.
[0059] The method also comprises a step El 1 of etching the third dielectric layer D3 so as to expose the first dielectric layer DI between each first pillar PI of the matrix of first pillars PI according to the rows and columns of said matrix of first pillars PI. The structure obtained at the end of these two steps is illustrated in [Fig.4F], the exposed areas of the first dielectric layer DI being marked by a dotted circle.
[0060] In one embodiment, the method comprises a step of chemical-mechanical polishing of the structure obtained at the end of the preceding step E1 1 (not shown in the figures). Although optional, this step makes it possible to flatten the surface of the structure and thus to improve the quality of the deposition of the second conductive layer C2 described below. In addition, carrying out the chemical-mechanical polishing in two stages makes it possible to avoid any selectivity problem with the chemical-mechanical polishing carried out at the end of the deposition of the second conductive layer C2 described below.
[0061] As illustrated in [Fig.4G], the method then comprises a step E12 of depositing a second conductive layer C2 so as to fill the openings made during the step E11 of etching the third dielectric layer D3. Thus, at these openings, the second conductive layer C2 is in direct contact with the first dielectric layer DI. In one embodiment, the material of the second conductive layer C2 is chosen from Ti, TiN or even W.
[0062] The method then comprises a step E13 of chemical-mechanical polishing of the structure obtained at the end of the previous step, so as to obtain a matrix of third conductive pillars PC2, said third conductive pillars PC2 being in direct contact with the first dielectric layer D1 at the openings made during the step El 1 of etching the third dielectric layer D3. During this step E13, the polishing is stopped on the support layer SP so that the third pillars PC2 are no longer connected to each other at the end of this step E13. In one embodiment, in order to ensure the correct disconnection of the third pillars from each other, a step E14 of chemical-mechanical over-polishing of the structure obtained at the end of the previous step E13 is implemented. The term “over-polishing” means continuing the polishing even though the stop layer has been reached.Indeed, the detection of the reaching of the stop layers by polishing is done automatically by physical detection of a polishing signal of the stop layer. However, if there are thickness non-uniformities at the scale of the plate, it is possible that the signal is detected while the stop layer has not been reached on the entire plate, but only on a part. The "over-polishing" therefore makes it possible to continue the polishing long enough after the signal has been detected so that all the areas of the plate are sufficiently polished. The structure obtained at the end of this step E13 or these two steps (when the optional over-polishing step E14 is implemented) is illustrated in [Fig.4H]. In the final structure, the third conductive pillars PC2 will form the first gates G1 and the second gates G2 of [Fig.l] making it possible to control the potential barrier between two adjacent QD quantum dots.
[0063] In the final structure, when the support material is a conductive material then, the first plurality of pillars PI will form the plurality of fourth grids G4 of [Fig.l] making it possible to control the absence of charge between the lines LI and the columns CO. When, on the other hand, the support material is a dielectric material, it is necessary to remove the first plurality of existing pillars PI to replace them with conductive pillars.
[0064] For this, as illustrated in [Fig.4I], the method comprises, when the material of the support layer SP is a dielectric material, a step E15 of selective removal of the first pillars PI of the plurality of first pillars PI so as to expose the first dielectric layer DI at the location of said first pillars PL. This removal step can be implemented by a selective wet etching method, for example based on H3PO4.
[0065] The method then comprises, when the material of the support layer SP is a dielectric material, a step E16 of depositing a third conductive layer in the space left by the first pillars PI during the step E15 of selective removal. previous.
[0066] The method finally comprises, when the material of the support layer SP is a dielectric material, a step E17 of chemical-mechanical polishing of the structure obtained at the end of the previous step, so as to obtain a matrix of fourth conductive pillars PC3 at the location of the first pillars PI, the polishing being stopped so that the fourth conductive pillars are no longer connected to each other at the end of this step. The structure obtained at the end of this step is illustrated in [Fig.4J]. In this final structure, the matrix of fourth pillars PC3 will form the plurality of fourth gates G4 of [Fig.l] making it possible to control the absence of charge between the rows LI and the columns CO.
[0067] As shown in [Fig.l] and [Fig.4J], in the device thus obtained, the third grids G3 preferably have a central symmetry and the distribution of the first grids G1 and second grids G2 adjacent to each third grid G3 is done according to this symmetry. Similarly, the first, second and third grids G1, G2, G3 are preferentially distributed symmetrically with respect to the axis associated with each row LI and the axis associated with each column CO.
Claims
1. Claims Method for manufacturing a quantum device (DQ) according to one of the preceding claims from a substrate (SB) comprising a semiconductor layer, called active layer (CA), at a first surface of said substrate (SB), the method comprising: - A step (El) of depositing a first dielectric layer (Dl) on the first surface; - A step (E2) of depositing a support layer (SP) in a conductive or dielectric material on the first dielectric layer (Dl); - A step (E3) of etching the support layer (SP) so as to form a matrix of first pillars (PI) forming a plurality of rows and a plurality of columns, the first pillars forming the fourth grids (G4) when the support layer (SP) is in a conductive material; - A step (E4) of conformal deposition of a second dielectric layer (D2) on the matrix of first pillars (PI), the thickness deposited being chosen so as to fill the space between each first pillar (PI) and its closest neighbors; - A step (E5) of etching the second dielectric layer (D2) so as to expose the first dielectric layer (D1) between each first pillar (PI) of the matrix of first pillars (PI) along the diagonals of said matrix of first pillars (PI); - A step (E7) of depositing a first conductive layer so as to fill the openings made during the step (E5) of etching the second dielectric layer (D2); - a step (E8) of chemical-mechanical polishing of the structure obtained at the end of the previous step so as to obtain a matrix of second conductive pillars (PCI) at the openings made during the step (E5) of etching the second dielectric layer (D2), the polishing being stopped on the support layer (SP) so that the second conductive pillars (PCI) are no longer in contact with each other at the end of this step (E8) and form the third grids (G3); - A step (E9) of selective removal of the second di- layer electrical (D2) so as to keep on the first dielectric layer (Dl) only the matrix of first pillars (PI) and the matrix of second pillars (PCI) conductors; A step (E10) of conformally depositing a third dielectric layer (D3) on the first pillar matrix (PI) and the second conductive pillar matrix (PCI), the deposited thickness being chosen so as to fill the space between each first pillar (PI) and the second conductive pillars (PC2) closest neighboring said first pillar (PI); A step (E11) of etching the third dielectric layer (D3) so as to expose the first dielectric layer (D1) between each first pillar (PI) of the first pillar matrix (PI) according to the rows and columns of said first pillar matrix (PI); A step (E12) of depositing a second conductive layer (C2) so as to fill the openings made during the step (E11) of etching the third dielectric layer (D3); a step (E13) of chemical-mechanical polishing of the structure obtained at the end of the previous step, so as to obtain a matrix of third conductive pillars (PC2) at the openings made during the step (E11) of etching the third dielectric layer (D3), the polishing being stopped on the support layer (SP) so that the third conductive pillars (PC2) are no longer in contact with each other at the end of this step (E13) and form the first grids (G1) and the second grids (G2); When the material of the support layer (SP) is a dielectric material, a step (El5) of selectively removing the first pillars (PI) of the plurality of first pillars (PI) so as to expose the first dielectric layer (Dl) at the location of said first pillars (PI); When the material of the support layer is a dielectric material, a step (El6) of depositing a third conductive layer in the space left by the first pillars (PI) during the previous selective removal step; When the material of the support layer is a dielectric material, a step (E17) of chemical-mechanical polishing of the structure obtained at the end of the previous step, so as to obtain a matrix of fourth conductive pillars (PC3) at the location of the first pillars (PI), the polishing being stopped so that the fourth conductive pillars are no longer connected to each other at the end of this step and form fourth grids (G4).
2. Method according to the preceding claim in which the substrate (SB) is an SOI type substrate and the active layer (CA) is produced in the silicon layer of the substrate (SB).
3. Method according to one of the preceding claims in which the material of the first dielectric layer (Dl) is chosen from SiO 2, HfO2 or Al2O3.
4. Method according to one of the preceding claims in which the distance d separating two neighboring first pillars (PI) and the height h of the first pillars (PI) at the end of the step (E3) of etching the support layer (SP) so as to form a matrix of first pillars (PI) are chosen so that h> d / 2.
5. Method according to one of the preceding claims comprising, at the end of the step (E5) of etching the second dielectric layer (D2), a step (E6) of chemical-mechanical polishing of the structure obtained at the end of the preceding step (E5).
6. Method according to one of the preceding claims comprising, before the step (El 1) of etching the third dielectric layer (D3), a step (El2) of chemical-mechanical polishing of the structure obtained at the end of the preceding step (Eli).
7. Method according to one of the preceding claims comprising, after the step (E13) of chemical-mechanical polishing of the structure obtained at the end of the step (E12) of depositing a second conductive layer (C2), a step (E14) of chemical-mechanical over-polishing of the structure obtained at the end of the preceding chemical-mechanical polishing step (E13).