Substrate comprising trenches and associated manufacturing methods

Abstract

Substrate comprising trenches and associated manufacturing method The invention relates to a substrate 3 comprising: • a first layer 30 based on a semiconductor material and comprising a front face and a rear face, • an assembly 36 of at least one layer surmounting the first layer 30 by the first face, and comprising a plurality of individual zones 331 for forming microelectronic components 40, characterized in that it comprises a plurality of hollow trenches 32 extending, along a thickness dimension of the substrate 3, at least over a portion of the first layer 30 extending to the front face of the first layer 30, the trenches 32 being delimited at least by a side wall 320 and a bottom wall 321 buried in the first layer 30, the trenches 32 forming a closed contour around at least one individual zone 331. Figure for the abstract: Fig.1A

Description

Title of the invention: Substrate comprising trenches and associated manufacturing methods Technical field

[0001] The present invention relates to the field of substrates intended for manufacturing electronic devices and more particularly microelectronic devices, these substrates ultimately making it possible to produce more efficiently devices based on components produced collectively. The invention finds advantageous, but not limiting, application in the manufacture of microelectronic devices. STATE OF THE ART

[0002] The collective production of microelectronic devices, and in particular chips, is a very common practice and is carried out on the basis of a substrate. This comprises zones each dedicated to the formation of a device, the latter comprising one or more components formed in such a zone. The substrates used for collective manufacturing may in particular be semiconductor substrates, for example of the semiconductor-on-insulator type, and in particular silicon-on-insulator SOI (abbreviated from the English Silicon-On-Insulator).

[0003] After the components of the different devices have been produced on the substrate, the devices are singled out, i.e. the substrate is divided into as many parts as there are final devices to be obtained. This singled out takes place at the very end of the component manufacturing cycle, and in particular after the deposition of the metal layers of the Back-end-of-line (abbreviated BEOL, which can be translated as end of manufacturing line).

[0004] The cutting of the substrate involved in singulation has many disadvantages. Firstly, it is generally time-consuming since the substrate must be sliced ​​successively in different directions. And depending on the techniques used, for example when using cutting plasmas, several passes may be necessary. In addition, the cutting can degrade the surface quality of the microelectronic devices, and the size of the cuts is generally several tens of micrometers in width, which consumes a significant surface area of ​​the substrate.

[0005] There is currently a need to obtain individualized microelectronic devices in an improved manner in a context of collective manufacturing on a substrate.

[0006] An object of the present invention is therefore to facilitate the manufacture of microelectronic devices from a substrate.

[0007] Other objects, characteristics and advantages of the present invention will appear from consideration of the following description and accompanying drawings. It is understood that other advantages may be incorporated. SUMMARY

[0008] To achieve this objective, according to one embodiment, a substrate is provided comprising: - a first layer based on a semiconductor material and comprising a front face and a rear face, - an assembly of at least one layer, surmounting the first layer by the front face, and comprising a plurality of individual zones for forming microelectronic components.

[0009] Advantageously, the substrate comprises a plurality of hollow trenches extending, along a thickness dimension of the substrate, at least over a portion of the first layer extending to the front face of the first layer, the trenches being delimited at least by a side wall and a bottom wall buried in the first layer, the trenches forming a closed contour around at least one individual zone.

[0010] Thus, the substrate comprises trenches preferably manufactured before the manufacture of the components forming the microelectronic devices.

[0011] This has several advantages. The singulation of microelectronic devices is prepared before their manufacture. This avoids the negative impact that current singulation processes have at the end of the process, in particular by eliminating any risk of degradation of the devices. On the other hand, the trenches can be made simultaneously with etching techniques, which is much less time-consuming than currently known chip cutting.

[0012] Generally speaking, the substrate presented here is intended to carry microelectronic components during different stages of their manufacture. After the manufacture of the components, the substrate is divided into as many parts as there are microelectronic devices to be formed from the components. However, thanks to the invention, this division is facilitated by the structure of the substrate. Indeed, trenches are previously formed so that, when the substrate is used to manufacture the components, they are already in place. At the end of the process, the trenches serve as division zones for the microelectronic devices. While the phase of singulating the devices is usually perceived as a step entirely subsequent to the manufacture of the components on the substrate, the present substrate structure combats this prejudice by anticipating this singulating by manufacturing the trenches upstream of that of the components.

[0013] Also, the size of the trenches is potentially very small in width, so that the space occupied by this singularization part can be greatly reduced in comparison with current techniques.

[0014] According to one example, at least the bottom wall and the side wall of the trenches are made of dielectric material. The walls made of dielectric materials being formed beforehand, they allow good insulation and / or passivation of the trenches and can in particular be implemented by high temperature processes (in particular thermal oxidation annealing) without impact on the components which are not yet formed.

[0015] A second aspect relates to a method of manufacturing the substrate according to the first aspect, comprising: - a supply of a support sub-substrate comprising at least a first layer based on a semiconductor material, the support sub-substrate having an exposed surface, - etching a plurality of trenches such that the trenches extend along a thickness dimension of the substrate from the exposed surface over a portion of the first layer, each trench being delimited by a side wall and a bottom wall buried in the first layer, the trenches forming a closed contour around at least one individual microelectronic component formation area, - a supply of a donor sub-substrate comprising a surface layer having an exposed surface, - an assembly of the support sub-substrate and the donor sub-substrate by their exposed surfaces so as to cover the trenches, each trench then being delimited by the side wall, the bottom wall, and an upper wall opposite the bottom wall.

[0016] This method thus allows the manufacture of the substrate which can then be used to obtain the microelectronic devices, by individualizing them. This method has the effects and advantages described in relation to the first aspect.

[0017] A third aspect relates to a method of manufacturing a microelectronic device comprising: - a supply of a substrate having a front exposed surface and a rear exposed surface, - thinning of the first layer from the rear face until the trenches are opened.

[0018] This method advantageously ultimately allows the microelectronic devices to be separated. By this thinning or at least partly thanks to it, the method allows each device to be individualized. BRIEF DESCRIPTION OF THE FIGURES

[0019] The aims, objects, as well as the characteristics and advantages of the invention will emerge more clearly from the detailed description of embodiments thereof, illustrated by the following accompanying drawings.

[0020] [Fig.lA] [Fig.lA] shows a cross-sectional view of a substrate carrying a plurality of components for forming microelectronic devices according to one embodiment.

[0021] [Fig.lB] [Fig.lB] shows a cross-sectional view of a substrate carrying a plurality of components for forming microelectronic devices according to another embodiment.

[0022] [Fig.2] [Fig.2] represents a partial view along section AA of the two preceding figures.

[0023] [Fig.3] [Fig.3] shows an example of the result of individualization of microelectronic devices from a substrate according to [Fig.1B].

[0024] [Fig.4A][Fig.4B][Fig.4C][Fig.4D][Fig.4E] Figures 4A to 4E represent cross-sectional views of steps of the method of manufacturing the substrate according to exemplary embodiments.

[0025] [Fig.5A][Fig.5B] Figures 5A and 5B show subsequent steps of the substrate manufacturing method according to exemplary embodiments.

[0026] [Fig.6A][Fig.6B][Fig.6C][Fig.6D][Fig.6E] Figures 6A to 6E illustrate successive steps from the fabrication of components on the substrate to the transfer of the substrate onto a support.

[0027] [Fig.7A][Fig.7B] Figures 7A and 7B represent an alternative to the sequence shown between Figures 6A and 6B.

[0028] The drawings are given as examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily on the scale of practical applications. In particular the relative dimensions of the sub-substrates and substrates, the layers, the trenches and the walls are not representative of reality. DETAILED DESCRIPTION

[0029] Before commencing a detailed review of embodiments of the invention, optional features are set out below which may optionally be used in combination or alternatively.

[0030] According to examples, the substrate is such that: - It comprises at least one microelectronic component 40 in the at least one individual zone 331; - complementary trenches 42 extend along the thickness dimension from an exposed face of the component 40 to the mouth of the trenches 32; - each trench 32 extends in the first layer 30 over at least 10%, and / or preferably over less than 50%, of the thickness dimension of the first layer 30; - the assembly 36 comprises a second layer 31 in contact with the front face of the first layer 30 and which, preferably, is a layer based on, and preferably made of, a material chosen from a dielectric material, for example an oxide, a semiconductor material or a piezoelectric material; - the assembly 36 comprises a third layer 33 surmounting the second layer 31 and which, preferably, is based on a material chosen from a semiconductor material or a piezoelectric material; - at least the bottom wall 321 and the side wall 320 are made of dielectric material; - at least the bottom wall 321 and the side wall 320 comprise a layer of a dielectric material completely covered by a metallic coating; - each trench 32 has at least one smallest transverse dimension less than 10 pm; - at least a portion of the trenches 32, and preferably each trench 32, has a shape ratio, of the trench dimension 32 according to the thickness dimension on the smallest transverse dimension to the thickness dimension, greater than or equal to 10; - the substrate 3 further comprises a mark 34 configured so as to allow the alignment of the substrate 3. - In one example, the trenches are parallel to each other along the thickness dimension of the substrate. Furthermore, they can be of the same dimension in depth in the substrate. - In one example, the trenches form a mesh in the substrate, preferably with two trench directions perpendicular to each other. Alternatively, the trenches may have a curved, e.g., circular profile around the individual component formation areas.

[0031] According to one example, the trenches are not filled with a solid material. Each groove is preferably filled with an electrically insulating gaseous atmosphere, for example air, nitrogen or argon, possibly at a pressure less than or equal to ambient pressure. This arrangement is advantageous for the resistance of the components to later stages with high thermal budgets, typically at least 1000°C.

[0032] According to one example, each trench is delimited by a bottom wall, a side wall and a top wall opposite the bottom wall. For at least one trench, and preferably for each trench, at least a portion of the side wall and the bottom wall may be made of the same material as that of the first layer. Alternatively, for at least one trench, and preferably for each trench, at least a portion of the side wall and the bottom wall may be made of a dielectric material, for example the same dielectric material as the walls of the trench. Thus, the electrical insulation of the side of the final microelectronic device is already achieved.

[0033] In the case where the substrate further comprises a mark configured so as to allow the alignment of the substrate, this makes it possible to further facilitate the manufacture of microelectronic devices, by facilitating the alignment of the substrate, and in particular for carrying out the photolithography steps necessary for the construction of the active areas of the circuits and the various conductive lines of the component manufacturing processes. For a CMOS type manufacturing process, the first building block is the insulation of the active areas of the transistors, so it is this which would align with these marks.

[0034] According to one example, the semiconductor material is chosen from the group consisting of silicon Si, germanium Ge, SiGe, a III-V material (for example GaN, InN, InGaAs, GaP, InP, InAs, AsGa...), a II-VI material, materials with a wide band gap, for example greater than 3 eV.

[0035] According to one example, the semiconductor material comprises, and preferably is, silicon.

[0036] According to one example, the piezoelectric material is selected from lithium tantalate (LiTaO3), lithium niobate (LiNbO3), potassium sodium niobate (KxNabx NbO3 or KNN), barium titanate (BaTiO3), quartz, lead zirconate titanate (PZT), a compound of lead magnesium niobate and lead titanate (PMN-PT), zinc oxide (ZnO), aluminum nitride (AIN) or aluminum scandium nitride (AIScN).

[0037] According to one example, the dielectric material is a semiconductor oxide, and preferably silica of chemical formula SiO2.

[0038] According to different possibilities, the method of manufacturing the substrate can comprise the following characteristics cumulatively or alternatively in any combination: - It comprises a formation of at least one microelectronic component 40 in the at least one individual zone after assembly of the support sub-substrate 1 and the donor sub-substrate 2. - It includes after the formation of at least one microelectronic component 40, a formation of complementary trenches 42 extending along the thickness dimension from an exposed face of the at least one component 40 to the mouth of the trenches 32; - following the etching of the plurality of trenches 32 and preferably before the assembly of the support sub-substrate 1 and the donor sub-substrate 2, the method comprises, for each trench 32, a formation of a dielectric material at least at the bottom wall 321 and the side wall 320; - the formation of a dielectric material at least at the bottom wall 321 and the side wall 320 of the plurality of trenches 32 comprises: • thermal oxidation so as to oxidize the semiconductor material of the first layer 10 at least at the bottom wall 321 and the side wall 320, and / or • a deposit of the dielectric material at least at the bottom wall 321 and the side wall 320. - The surface layer 21 of the donor sub-substrate is a layer based on, and preferably made of, a material chosen from a dielectric material, for example an oxide, a semiconductor material or a piezoelectric material; - the support sub-substrate 1 further comprises a surface layer 11 based on, and preferably made of, a dielectric material, for example an oxide, overlying the first layer 10, the surface layer having the exposed surface 1a, and / or the surface layer 21 of the donor sub-substrate is a layer based on, and preferably made of, a dielectric material, for example an oxide, overlying a layer 20 based on a material chosen from a semiconductor material or a piezoelectric material. - After assembling the support sub-substrate 1 and the donor sub-substrate 2, a thinning of the donor sub-substrate 2 is configured to expose the surface layer 20, 21. - a supply of a substrate 3 having a front exposed surface 3a and a rear exposed surface 3b, - thinning of the first layer 30 from the rear face 3b until the trenches 32 are opened.

[0039] According to one example, when at least the bottom wall and the side wall are made of dielectric material, the bottom wall of the plurality of trenches has a longitudinal dimension substantially between 50 nm and 600 nm, preferably substantially equal to 400 nm.

[0040] According to one example, when at least the bottom wall and the side wall are made of dielectric material, the side wall of the plurality of trenches has a transverse dimension substantially between 50 nm and 600 nm, preferably substantially equal to 400 nm.

[0041] According to one example, the surface layer of the donor sub-substrate is a layer based on, and preferably made of, a material chosen from a dielectric material, for example an oxide, a semiconductor material or a piezoelectric material.

[0042] By the phase of assembling the donor sub-substrate and the recipient sub-substrate, it is understood that the buried oxide layer of the substrate can come from the donor sub-substrate and / or the support sub-substrate.

[0043] According to one possibility, the substrate comprises at least one additional hollow trench extending, along a thickness dimension of the substrate 3, at least over a portion of the first layer 30 extending to the front face 3a of the first layer 30, the additional trench being delimited at least by a side wall and a bottom wall buried in the first layer 30, the additional trench forming a closed contour in an individual zone 331. These trenches can be formed in a similar manner, and in particular by etching, and at the same stage as the formation of the trenches 32. They can have the same dimension depending on the thickness of the substrate 3. They allow an internal cutout in the zone of the component 4, useful in particular if the latter is hollow. In particular, the surface available in the center can be used to place another microelectronic device there.

[0044] According to one example, the method comprises forming a weakening zone at a depth of the surface of the surface layer of the donor substrate, and then separating the donor substrate at the weakening zone.

[0045] According to different possibilities, the method of manufacturing the microelectronic devices from the substrate can comprise the following characteristics cumulatively or alternatively in any combination:

[0046] prior to thinning, there is included a transfer of the substrate 3 onto a support 41 from the face opposite the rear face 3b; the support 41 may be a semiconductor-based substrate or a support layer, in particular made of polymer, potentially with an adhesive surface for this transfer;

[0047] after the thinning, there is included a formation of a metallic coating 35 covering at least the upper wall 322 and the side wall 320 of the trenches 32.

[0048] By microelectronic device is meant any type of device produced using microelectronic means. These devices include, in particular, in addition to devices for purely electronic purposes, micromechanical or electromechanical devices, as well as optical or optoelectronic devices. It may be a device intended to provide an electronic, optical, mechanical, etc. function. It may It can also be an intermediate product, intended solely for the production of another microelectronic device. It can also be a structure of passive electrical interconnections.

[0049] It is specified that, in the context of the present invention, the term "on" or "above" does not necessarily mean "in contact with". Thus, for example, the deposition of a layer on another layer does not necessarily mean that the two layers are directly in contact with each other but it does mean that one of the layers at least partially covers the other by being either directly in contact with it, or by being separated from it by a film, yet another layer or another element.

[0050] A layer may also be composed of several sub-layers of the same material or of different materials.

[0051] An element “based on” a material A is understood to mean an element comprising this material A only or this material A and possibly other materials.

[0052] In the detailed description which follows, terms such as "longitudinal", "transverse" may be used. These terms must be interpreted relative to the substrate or the thickness dimension of the devices. Thus, a longitudinal dimension, a height, a depth or a thickness of an element or a layer means a dimension according to the thickness of the substrate which carries or contains it. A width, or even a section or a transverse dimension means a dimension perpendicular to the thickness of the substrate.

[0053] Certain parts of the substrate or device of the invention may have an electrical function. Some are used for electrical conduction properties and electrically conductive or equivalent means elements formed from at least one material having sufficient conductivity, in the application, to achieve the desired function. Other parts, on the contrary, are used for electrical insulation properties and all materials having sufficient resistivity to achieve this insulation are concerned and are in particular called dielectric or electrically insulating.

[0054] The word "dielectric" more particularly qualifies a material whose electrical conductivity is sufficiently low in the given application to serve as an insulator. In the present invention, a dielectric material preferably has a dielectric constant of less than 4.

[0055] The term "direct bonding" means bonding without the addition of adhesive material (in particular of the glue or polymer type) which consists of bringing relatively smooth surfaces into contact (with a root mean square roughness RMS, typically less than 5 Å, 10 10 m), for example carried out at room temperature and in an ambient atmosphere, in order to create adhesion between them.

[0056] According to one embodiment, the direct bonding of two substrates means that the bonding is obtained by the chemical bonds which are established between the two surfaces brought into contact. These chemical bonds may be, for example, Van der Waals bonds and / or strong, covalent chemical bonds, in particular when the bonding is assisted by plasma activation or followed by a strengthening heat treatment (typically 200°C to 1200°C for one hour).

[0057] Direct bonding can be achieved without requiring the application of significant pressure to the structure to be assembled. Light pressure may simply be applied to initiate bonding. Thermal annealing may also be carried out to strengthen the bonding.

[0058] A parameter “substantially equal / greater / less than” a given value means that this parameter is equal / greater / less than the given value, to within plus or minus 10%, or even plus or minus 5%, of this value.

[0059] The substrate 3 is now described according to several exemplary embodiments with reference to FIGS. 1A and 1B.

[0060] As for example illustrated by [Fig. 1A], the substrate 3 comprises a first layer 30, based on or made of a semiconductor material. According to one example, the semiconductor material comprises, and preferably is, silicon. The first layer 30 has a thickness for example substantially between 100 μm and 800 μm.

[0061] The substrate 3 further comprises an assembly 36 having at least one layer. [Fig. 1A] gives a purely indicative example of this assembly. In this embodiment, it comprises a second layer 31 and a third layer 33. However, the assembly 36 may comprise more than two layers, or one of the second layer and the third layer may comprise several sub-layers.

[0062] Conversely, the assembly may have only one layer of a single material; typically, this single layer may be made of a semiconducting (and not dielectric) material, such as silicon. It may be used to form a bonding interface during a transfer phase described later, in particular by plasma activation. At the same time, on its other side, this single layer comprises the individual areas for the components 40; this single layer may be produced and used as described for the third layer 33, but without the use of the second layer 32.

[0063] As illustrated by [Fig.lA], the second layer 31 may be based on or made of a dielectric material. According to one example, the dielectric material comprises, and preferably is, a semiconductor oxide, for example silica of formula SiO2. The second layer 31 forms a stack with the first layer 30, preferably by being in direct contact with it. The second layer 31 may be based on or made of a semiconductor material, a piezoelectric material or a metal. The second layer 31 may have a thickness L31, as shown in [Fig.5B], for example greater than or equal to 10 nm, preferably 100 nm. The thickness L31 may be less than or equal to 1000 nm.

[0064] According to one example, as illustrated by [Fig.1A], the second layer 31 is followed by a third layer 33 based on or made of a semiconductor material or a piezoelectric material. According to one example, the semiconductor material comprises, and preferably is, silicon. The third layer 33 has a thickness, for example, substantially between 10 nm and 1000 nm. The substrate 3 thus comprises a structure of the semiconductor-on-insulator type, and in particular of the silicon-on-insulator (SOI) type. Note that it may be provided that the second layer 31 is not topped with a third semiconductor layer.

[0065] In the following, unless explicitly stated otherwise, it is considered, without limitation, that the substrate 3 is an SOI substrate, the first layer 30 being made of monocrystalline or polycrystalline silicon, the second layer of SiO2 and the third layer of monocrystalline silicon.

[0066] The substrate 3 comprises hollow trenches 32 extending from the second layer 31 into the first layer 30. The trenches 32 may be parallel to each other. The trenches 32 preferably extend over a longitudinal dimension oriented in the direction of the thickness of the first 30 and second 31 layers, which corresponds to the thickness dimension of the substrate 3. The trenches 32 are buried in the substrate 3, that is to say they are not open and, at least on one of the exposed surfaces of the substrate, and in particular the rear face 3b of the substrate 3.

[0067] In the case of [Fig.lA], the trenches 32 form closed volumes insofar as their two ends are non-opening. According to an alternative embodiment, corresponding to [Fig.lB], one of the ends of the trenches 32 is open and, in particular, via the front face 3a. Indeed, in this case, complementary trenches 42 are formed by the exposed face of the components 40, at the level of the spaces 421, extending along the thickness dimension of the substrate 3 until they reach the trenches 32. Preferably, the complementary trenches 42 adopt the same distribution as that visible in [Fig. 2] for the trenches 32. In this configuration, for an individual zone 331, the components 40 and the underlying part of the substrate 3 of these components 40 are secured to the rest of the substrate 3 only by a portion of the substrate 3 located opposite the components 40, towards the face 3b of the substrate 3.

[0068] Since the trenches 32 are hollow, they are not filled with a solid material. They are preferably filled with a gaseous atmosphere such as air, nitrogen and / or argon, possibly at a pressure less than or equal to ambient pressure.

[0069] [Fig.2] provides an example of meshes produced by the trenches 32. In the case illustrated, parallel trenches along one direction of the plane of the substrate are present, as well as parallel trenches along a second direction of this plane, preferably perpendicular to the first. In this configuration, the trenches of the two directions intersect, forming zones 331 with a closed contour. Preferably, the entire substrate has such a composition of trenches, forming a sort of grid. This grid can make it possible to produce zones 331 of rectangular or even square shape. At the very least, the trenches make it possible to frame at least one zone 331 by forming a closed contour around this zone.

[0070] Preferably, the trenches are made simultaneously, by etching as described in more detail below. This allows for a limited production time, taking into account this overall manufacturing.

[0071] Furthermore, the trenches may be rectilinear or not depending on the outline that one wishes to give to the individual zones 331.

[0072] The depth dimension of the trenches 32 may be chosen so as to extend into a portion of the first layer 30 and over at least a portion of the thickness of the second layer 31, as for example illustrated in [Fig. 1A] and 1B. In a variant not shown, the trenches 32 may be flush with the surface of the first layer 30.

[0073] The depth dimension of the trenches shown is at least 10%, possibly at least 20%, or even at least 30% of the thickness of the first layer 30. Alternatively or in addition, this value may be less than 50%. Indeed, the individualization of the microelectronic devices which follows is achieved by thinning the first layer by its rear face, so that it is advantageous to have a significant trench depth as long as this does not hinder the resistance of the substrate 3.

[0074] The trenches 32 are delimited by a side wall 320, a bottom wall 321 and an upper wall 322 opposite the bottom wall 321. The bottom wall 321 is arranged towards the rear surface 3b of the substrate 3 and the upper wall 322 is arranged towards the front surface 3a of the substrate 3.

[0075] Among these walls, at least the bottom wall 321 and the side wall 320 may be made of dielectric material, for example SiO2. Thus, the trench 32 will be electrically insulated from the first layer 30. As illustrated in [Fig.lA] and [Fig.lB], all the walls of the trenches 32 may be made of dielectric material.

[0076] The electrical insulation of the trenches 32 can be done later during the process of manufacturing the microelectronic devices from the substrate 3, described later.

[0077] The trenches may have a minimum transverse dimension, i.e. a width substantially less than or equal to 10 μm, preferably substantially between 1 μm and 10 μm, or even less than 5 μm. Thus, the lateral dimension is low, which makes it possible to occupy little space for the singularization of the microelectronic devices of the substrate 3 in the main extension plane of the first 30 and second 31 layers, which can lead to a greater density of microelectronic devices on a substrate of conventional size. The longitudinal dimension of the trenches can be substantially less than or equal to 200 pm, preferably substantially between 50 and 150 pm, for example substantially equal to 100 pm.

[0078] The trenches 32 may have a form factor substantially greater than or equal to 5, and preferably greater than or equal to 10. By form factor, we mean the ratio between the longest dimension (depth according to the thickness of the substrate 3) on the shortest dimension (a dimension in the plane of extension of the layers 30, 31, 33.

[0079] As illustrated for example in [Fig.5B], the substrate 3 may comprise at least one mark or equivalently a reference mark 34 allowing the alignment of the substrate 3 with other elements. Thus, the placement of the trenches 32 during the manufacturing process of the microelectronic device is made more reliable. This reference mark 34 may be formed by one or more portion(s) of layer of dielectric material at the level of the first layer 30 and / or the second layer 31. Note that the person skilled in the art may well envisage other variants of reference mark, such as for example a marking arranged on the front surface 3a of the substrate 3.

[0080] Steps of the method of manufacturing the substrate 3 are now described with reference to the figures.

[0081] The method comprises providing a sub-substrate 1. The sub-substrate 1 comprises at least a first layer 10, intended to form the first layer 30 of the substrate 3 which will be obtained, as illustrated in [Fig.4A]. The sub-substrate 1 may further comprise, as for example illustrated in [Fig.4B], a surface layer 11 intended to form at least in part the second layer 31 of the substrate 3. The surface layer 11 is preferably based on or made of a dielectric material. The sub-substrate 1 further has an exposed surface 1a, at the level of the first layer 10 or the surface layer 11.

[0082] As for example illustrated by Figures 4C and 4D, the trenches 32 can be formed by etching, and preferably by deep reactive ion etching (commonly abbreviated DRIE, from the English “Deep Reactive Ion Etching”). To form the trenches 32, the etching step can comprise the application of a mask 12 comprising openings 120 from which the trenches 32 will be etched, as illustrated for example in [Fig.4C]. The mask 12 is preferably a resin mask. It is possible to provide for the mask to be hard, for example with the application of a resin mask 12 then the etching of the surface layer 11, removing this mask and etching the first layer 10 using the so-called “hard” oxide mask. thus formed. Note that the surface layer 11 can be removed after etching the trenches 32, and the trenches 32 electrically insulated by depositing a dielectric layer thereafter.

[0083] The etching is preferably configured to obtain the characteristics of the trenches 32 described previously, and in particular their dimensions. For example, the dimensions of the mask 12 and / or the etching time and speed are adjusted for this.

[0084] To form the trenches 32, the method may then comprise forming a dielectric material at least at the bottom wall 321 and the side wall 320, as illustrated for example in [Fig.4E].

[0085] This formation can be done by thermal oxidation, for example at a temperature of substantially 1050°C in an atmosphere comprising oxygen.

[0086] Alternatively or additionally, the dielectric material, for example silica SiO2, may be deposited at least at the walls 320, 321 of the trenches 32. This deposition may be a chemical vapor deposition (commonly abbreviated CVD) from gaseous precursors comprising oxygen and silicon, for example tetraethyl orthosilicate (commonly abbreviated TEOS) or silane of chemical formula SiH4, optionally combined with dioxygen. The deposition is for example a subatmospheric pressure CVD (commonly abbreviated SACVD), or a plasma-enhanced chemical phase deposition (commonly abbreviated PECVD).

[0087] Preferably, the mask 12 is removed prior to the formation of these walls made of dielectric material. In the case where the layer 11 serves as a hard mask, it is preferable to remove it as well.

[0088] Preferably, the formation of the walls 320, 321 is configured so that the walls 320, 321 of dielectric material have a dimension substantially between 50 nm and 600 nm, and preferably substantially equal to 400 nm. For the side wall 320, this dimension is the transverse dimension. For the bottom wall 321, this dimension is the longitudinal dimension. For example, the thermal oxidation time or the deposition time and / or the deposition rate can be adjusted for this.

[0089] The method may comprise, simultaneously or concomitantly with the etching of the trenches 32 and where appropriate with the formation of the walls in dielectric material, a step of forming the mark 34. For this, the mask may further comprise openings, not shown here, for etching for example openings 34' in the second layer 31 into the first layer 30, illustrated for example in [Fig.4D]. The openings 34' may be filled with the dielectric material during the formation of the walls. The formation of the mark 34 may be distinct from these steps, for example by applying a mask specific to this mark 34, etching and filling pleating of the openings 34'. If the formation of the mark 34 is separate from these steps, it is advantageously carried out before, to serve as a mark for the positioning of the trenches 32.

[0090] Following the formation of the trenches 32, these cavities can be covered to be buried during the assembly of the sub-substrate 1 with a donor sub-substrate 2. The method can therefore comprise the provision of a donor sub-substrate 2 having an exposed surface 2a.

[0091] As illustrated by Figures 5A and 5B, the support 1 and donor 2 sub-substrates can be assembled by bringing their respective surfaces 1a, 2a into contact by direct bonding. The donor substrate 2 can then be thinned, for example by cleavage using the process known as Smart-Cut®.

[0092] The assembly may for this purpose comprise, before bringing the surfaces 1a, 2a into contact, the formation of a weakening zone 22 at a non-zero depth of the surface 2a of the donor sub-substrate 2. This weakening zone 22 is for example formed by implantation of ions, such as hydrogen and / or helium ions. Note that any other technique for forming a weakening zone, and in particular any other technique used in the methods for producing SOI-type stacks, may be envisaged.

[0093] Following the assembly of the support sub-substrate 1 and the donor sub-substrate 2, the method may comprise the separation of a surface layer of the donor sub-substrate 2, at the level of the weakening zone 22, as in the examples illustrated in [Fig.5B]. This separation may be done thermally or mechanically, according to steps known to those skilled in the art.

[0094] Following separation, the surface 3a obtained may be irregular and damaged. Polishing, chemical smoothing, chemical and / or mechanical and / or thermal and / or ion beam healing based on atom clusters or based on monomers of the surface 3a may be carried out, so that the surface 3a has a crystalline quality and a roughness suitable for other subsequent processes. Any chemical mechanical polishing (CMP) or thermal method intended to smooth a surface based on semiconductors and in particular silicon may be envisaged.

[0095] According to one example, the donor sub-substrate 2 comprises a layer 20 based on or made of a semiconductor material, for example silicon and more particularly monocrystalline silicon. The donor sub-substrate 2 may further comprise a layer 21 based on or made of a dielectric material, for example silica SiO2.

[0096] According to an example which can be illustrated by figures 5A and 5B, the layer 21 can form the surface layer of the donor sub-substrate 2. In particular, it is possible to carry out direct bonding of semiconductor oxide, for example silicon oxide, against semiconductor oxide, for example silicon oxide. Following their assembly, the layer 21 and the layer 11 will form the second layer 31 of the substrate 3. Their respective thicknesses can therefore be chosen to obtain the desired thickness L31. According to this example, it is understood that the upper wall 322 of the trenches 32 and, where appropriate, the upper wall 322 of the grooves 35 can be formed from a dielectric material. The upper wall 322 of the trenches 32 can, for example, have a thickness substantially between 1 nm and 600 nm.

[0097] According to an alternative example not illustrated, the layer 20 can form the surface layer of the donor sub-substrate 2. A direct bonding of semiconductor oxide, for example silicon oxide, against semiconductor, and in particular silicon, can be carried out. Following their assembly, the layer 11 alone will form the second layer 31 of the substrate 3. Its thickness can therefore be chosen to obtain the desired thickness L3i. According to this example, it is understood that the upper wall 322 of the trenches 32 can be formed from a semiconductor material.

[0098] According to one example, the layer 20 can form the surface layer of the donor sub-substrate 2. Direct bonding of semiconductor or piezoelectric against semiconductor, and in particular silicon, can be carried out when the layer 20 is based on a semiconductor or piezoelectric material. Direct bonding of semiconductor oxide against semiconductor, and in particular silicon, can be carried out when the layer 20 is based on a dielectric material, and in particular an oxide, which is desired in a context of recourse to a weakening zone 22 formed by ion implantation, such as in [Fig.5A]. Following their assembly, the layer 20 will form the assembly 36 of the substrate 3. Its thickness can therefore be chosen to obtain the desired thickness which can be at least equal to the value described for L3b

[0099] Note that it is preferable to have for the assembly a thickness of dielectric material, and in particular oxide, of at least 10 nm at the bonding interface to avoid the appearance of defects.

[0100] According to another example, the layer 20 can still form the surface layer of the donor sub-substrate 2 and the support sub-substrate 1 does not have a surface layer 11 (in particular if it is not desired to have a dielectric layer at the bonding interface and in the trenches 32). In this case, the layer 20 can still be used for direct bonding of semiconductor or piezoelectric against semiconductor, and in particular silicon, when the layer 20 is based on a semiconductor (and in particular silicon) or piezoelectric material and when the exposed surface 1a of the support sub-substrate 1 is made of semiconductor (and in particular silicon).

[0101] Thus, a substrate 3 is obtained having trenches defining individual zones which can be singled out after the manufacture of the components. The substrate 3 can be provided in this way for manufacturing such components and have a structure such that in the example of [Fig.5B].

[0102] The method of manufacturing microelectronic device components 4 is now described with reference to FIGS. 6A to 7B.

[0103] In this method, the trenches 32 serve to delimit the individual zones 331. Components 40 are manufactured in these zones, preferably in a stack and without extending laterally beyond the individual zones 331, i.e. without overlapping the area where the trenches 32 are present.

[0104] The method may comprise a supply of the substrate 3. The method may comprise the deposition of component layers 40 (illustrated in [Fig.6A] for example), for example transistor, diode, memory point. This deposition may for example comprise the FEOL steps, corresponding to start of line steps.

[0105] As for example illustrated in [Fig.6A], the method may comprise the deposition of at least one portion of layer 401 on the front surface 3a of the substrate 3. In the following, it is considered, without limitation, that several layers 401 are deposited. Alternatively or in addition, one or more portions of these layers may be etched in the front exposed surface 3a of the substrate 3.

[0106] These components 40 may be metallic and may also in particular form metallic interconnection lines. Typically, these metallic portions 40 may be used to redistribute electrical signals. These metallic portions may also be designated metallization levels. There may be several metallic portions with interconnections between these portions. This deposition may for example comprise the BEOL steps.

[0107] In order to facilitate the handling of the substrate 3, the method may then comprise the mounting of a support 41 on the side of the exposed front surface 3a of the substrate 3, for example by means of a bonding 410 made on the previous deposits, as illustrated by [Fig.6B] for example. This also makes it possible to protect the deposits made on the front surface 3a of the substrate 3.

[0108] After the deposition of the metal portions forming the components 40 of each microelectronic device, if necessary after the mounting of the support 41, the method comprises a thinning of the substrate 3 by the rear face 3b so as to open the trenches 32, to achieve the configuration of [Fig. 6C]. This thinning can be carried out by any means within the reach of a person skilled in the art, which includes for example steps of grinding and chemical or chemical-mechanical polishing.

[0109] Optionally, this opening may also comprise one or more steps of etching at least one trench 32, in particular when the bottom wall 321 comprises a coating, and in particular a dielectric layer.

[0110] According to one example, from the rear surface 3b of the substrate 3, the first layer 30 can be etched until it is flush with, or exceeds, the bottom wall 321 of the trenches. 32. The bottom wall 321 of the trenches 32 is thus exposed. For this, the first layer 30 can be thinned and etched by selective etching of the material of the first layer 30 relative to the dielectric material of the walls 320, 321. According to one possibility, the etching can for example be selective etching of the silicon relative to the silica SiO2 in reactive ion etching using a precursor such as SF6. By “selective etching of a material A relative to a material B” is meant that the etching speed of the material A is 10 times, and preferably 100 times, higher than that of the material B. It is also possible to envisage carrying out partial mechanical thinning of the substrate 3 completed by selective plasma or chemical etching.

[0111] The wall of dielectric material can then be selectively etched relative to the material of the first layer 30, to open into the trench 32.

[0112] When the walls of the trenches 32 are not made of dielectric material, the method may comprise the formation of a dielectric layer at least at the level of the side wall 320 at this stage, according to the methods previously described with reference to the method of manufacturing the substrate 3.

[0113] As shown in [Fig.6D], it is possible, at this stage, to carry out additional steps via the rear face. In particular, a metal coating 35 can be produced, for example intended for electromagnetic protection of the microelectronic devices 4. For example, the coating can be made up of one or more metal layers, and in particular a stack of a layer of, or based on, titanium serving as a diffusion barrier and a layer of, or based on, copper serving as the main metal layer. It is understood that, after the separation of the devices 4, the side of the latter is isolated without additional steps. Deposition techniques can be used for this production. The coating 35 is at least formed so as to cover the side wall 320 of the trenches 32, and typically also covers the bottom wall 321.

[0114] Optionally, the coating 35 may extend to the surface of the substrate 3 by a portion 351 extending only over a part of the surface of the peripheral substrate 3, and in continuity with the coating 35 of the trenches 32.

[0115] Once the manufacturing steps taking place on the rear surface 3b of the substrate 3 have been completed, the support 41 can serve as a basis for finalizing the separation of the microelectronic devices 4. In this context, if this is useful, the support 41 can be reduced in thickness as illustrated by the transition from [Fig. 6D] to [Fig. 6E]. This may involve thinning using the techniques previously described for thinning the first layer 30 of the substrate 3.

[0116] In the configuration obtained in [Fig.6E], the microelectronic devices 4 are no longer linked together except by zones of material of low thickness in the second layer 31 and the third layer 33 and, on the other side of the components 40, by the support 41, or a residual part of the latter, with the bonding interface 410.

[0117] Their separation can be made easier.

[0118] According to a first option, an etching of the bottom of the trenches, that is to say of the upper wall 322, is carried out so as to cross the entire substrate 3 around the components 40 and to reach the support 41. Optionally, the latter can also be etched to single out the microelectronic devices 4. It can also be left as is to serve as a handle for handling the microelectronic devices 4. For this purpose, it can be arranged so that the bonding layer 410 has an adhesion force of each device 4 lower than an adhesion force of a device for subsequent and individual handling of the devices 4, such as a chip gripping and positioning device, generally called “pick and place”.

[0119] According to another option, advantage is taken of the support 41 to exert a stretching of the latter in the direction of the extension plane of the bonding interface 410. The latter mechanically stresses the substrate 3 and the zones where the trenches 32 are located form zones of weakness, therefore of concentration of stresses, at the level of which a rupture of the substrate 3 is triggered. In this context, it is advantageous to have a reduced distance between the upper wall 322 of the trenches 32 and the contact surface between the bonding layer 410 and the upper face of the components 40. Thus, the stretching forces in the plane are limited.

[0120] Figures 7A and 7B present an alternative case to the separation previously described. Indeed, based on the substrate variant described with reference to [Fig. 1B] and repeated in [Fig. 7B], the substrate 3 has complementary trenches 42 formed in the continuity of the trenches 32 so that the microelectronic devices 4 are already isolated from each other by the front face 3a of the substrate 3 before the opening of the trenches 32 by the rear face 3b.

[0121] In particular, on the basis of the result obtained in [Fig.6A], one or more etching steps can be carried out to form the complementary trenches 42 from the face of the substrate 3 at which the components 40 are present. Reference can be made to the etching examples given previously for these steps. Preferably, the complementary trenches 42 follow the same contour as that of the trenches 32.

[0122] Thanks to these complementary trenches 42, when the substrate 3 is transferred onto the support 41 as in [Fig.7B], it is understood that the execution of the steps corresponding to [Fig.7C] (possibly those of the steps of [Fig.7D] of [Fig.7E]) makes it possible to completely individualize the devices 4 which are simply held individually on the support 41 for subsequent individual handling.

[0123] It is recalled that the closed contours defined by the trenches 32 may have shapes different from the grid illustrated in [Fig.2], in particular by using trenches with a curvilinear profile. In addition, additional trenches may be produced within one or more individual zones 331, itself having a closed contour, so as to define a hollow zone for placing the components, for example with an annular profile. The manufacture of such additional trenches may be carried out at the same time as the trenches 32 and / or by implementing the same type of etching.

[0124] In view of the foregoing description, it is clear that the invention provides a substrate, its manufacturing method and a method of manufacturing a microelectronic device making it possible to facilitate the separation of microelectronic devices.

[0125] The present invention is not limited to the examples previously described. Many other variant embodiments are possible, for example by combining previously described characteristics, without departing from the scope of the invention. In addition, the characteristics described in relation to one aspect of the invention may be combined with another aspect of the invention. In particular, the substrate may have any characteristic resulting from its manufacturing method and conversely, this method may comprise any step configured to obtain a characteristic of the substrate. The method for manufacturing a microelectronic device may implement any characteristic of the substrate.

[0126] In the examples described, the semiconductor material is silicon. Note that the invention can be applied to other mono- or poly-crystalline semiconductors, possibly doped, and in particular to Si, Ge, SiGe, SiC, IILV material (for example AIN, GaN, InN, InGaAs, GaP, InP, InAs, AsGa, etc.) and ILVI material. The dielectric material can be a semiconductor oxide or nitride, for example SiO2, SiN, Al2O3. The piezoelectric material may, for example, be lithium tantalate (LiTaO3), lithium niobate (LiNbO3), potassium sodium niobate (KxNabxNbO3 or KNN), barium titanate (BaTiO3), quartz, lead zirconate titanate (PZT), a compound of lead magnesium niobate and lead titanate (PMN-PT), zinc oxide (ZnO), aluminum nitride (AIN) or aluminum scandium nitride (AIScN), other materials may naturally be considered.

Claims

Claims

1. Substrate (3) comprising: • a first layer (30) based on a semiconductor material and comprising a front face and a rear face, • an assembly (36) of at least one layer, surmounting the first layer (30) by the front face, and comprising a plurality of individual zones (331) for forming microelectronic components (40), characterized in that it comprises a plurality of hollow trenches (32) extending, along a thickness dimension of the substrate (3), at least over a portion of the first layer (30) going as far as the front face of the first layer (30), the trenches (32) being delimited at least by a side wall (320) and a bottom wall (321) buried in the first layer (30), the trenches (32) forming a closed contour around at least one individual zone (331), in that the assembly (36) comprises a second layer (31) in contact of the front face of the first layer (30) and which is a base layer,and preferably made of a material chosen from a dielectric material, for example an oxide, a semiconductor material or a piezoelectric material, and in that the assembly (36) comprises a third layer (33) covering the second layer (31) and which is based on a material chosen from a semiconductor material or a piezoelectric material.

2. Substrate according to the preceding claim, comprising at least one microelectronic component (40) in the at least one individual area (311).

3. Substrate according to the preceding claim, comprising complementary trenches (42) extending along the thickness dimension from an exposed face of the component (40) to the mouth of the trenches (32).

4. A substrate according to any preceding claim, wherein each trench (32) extends into the first layer (30) over at least 10%, and preferably less than 50%, of the thickness dimension of the first layer (30).

5. A substrate according to any preceding claim, in wherein at least the bottom wall (321) and the side wall (320) are made of dielectric material.

6. Substrate according to any one of the preceding claims, wherein at least the bottom wall (321) and the side wall (320) comprise a layer of a dielectric material integrally covered by a metallic coating.

7. A substrate according to any preceding claim, wherein each trench (32) has at least one smallest transverse dimension less than 10 µm.

8. A substrate according to any preceding claim, wherein at least a portion of the trenches (32), and preferably each trench (32), has an aspect ratio, of the trench dimension (32) along the thickness dimension to the smallest dimension transverse to the thickness dimension, greater than or equal to 10.

9. A method of manufacturing the substrate (3) according to any one of the preceding claims, comprising: • providing a support sub-substrate (1) comprising at least a first layer (10) based on a semiconductor material, the support sub-substrate (1) having an exposed surface (la), • etching a plurality of trenches (32) such that the trenches (32) extend along a thickness dimension of the substrate (3) from the exposed surface (la) over a portion of the first layer (10), each trench (32) being delimited by a side wall (320) and a bottom wall (321) buried in the first layer (10), the trenches (32) forming a closed contour around at least one individual zone (331) for forming microelectronic components (40), • providing a donor sub-substrate (2) comprising a surface layer (20, 21) having an exposed surface (2a),• an assembly of the support sub-substrate (1) and the donor sub-substrate (2) by their exposed surfaces (1a, 2a), so as to cover the trenches (32), each trench (32) then being delimited by the side wall (320), the bottom wall (321), and an upper wall (322) opposite the bottom wall (321).,

10. Method according to the preceding claim, comprising a formation of at least one microelectronic component (40) in the at least one individual zone (331) after assembly of the support sub-substrate (1) and the donor sub-substrate (2).

11. Method according to the preceding claim, comprising, after the formation of at least one microelectronic component (40), a formation of complementary trenches (42) extending along the thickness dimension from an exposed face of the at least one component (40) to the mouth of the trenches (32).

12. Method according to any one of the three preceding claims in which following the etching of the plurality of trenches (32) and preferably before the assembly of the support sub-substrate (1) and the donor sub-substrate (2), the method comprises, for each trench (32), a formation of a dielectric material at least at the bottom wall (321) and the side wall (320).

13. A method according to any one of the four preceding claims, wherein the surface layer (20, 21) of the donor sub-substrate is a layer based on, and preferably made of, a material chosen from a dielectric material, for example an oxide, a semiconductor material or a piezoelectric material.

14. Method according to any one of the five preceding claims, in which: • the support sub-substrate (1) further comprises a surface layer (11) based on, and preferably made of, a dielectric material, for example an oxide, overlying the first layer (10), the surface layer having the exposed surface (la), and / or • the surface layer (21) of the donor sub-substrate is a layer based on, and preferably made of, a dielectric material, for example an oxide, overlying a layer (20) based on a material chosen from a semiconductor material or a piezoelectric material.

15. A method according to any one of claims 9 to 14, comprising, after assembling the support sub-substrate (1) and the sub-substrate donor (2), a thinning of the donor sub-substrate (2) configured to expose the surface layer (20, 21).

16. A method of manufacturing a microelectronic device (4) comprising: • providing a substrate (3) according to claim 2 alone or in combination with any one of claims 3 to 8 or a substrate (3) manufactured by the method according to claim 10 alone or in combination with any one of claims 11 to 15, having a front exposed surface (3a) and a rear exposed surface (3b), • thinning the first layer (30) from the rear face (3b) until the trenches (32) are opened.

17. Method according to the preceding claim, comprising, prior to thinning, a transfer of the substrate (3) onto a support (41) from the face opposite the rear face (3b).

18. Method according to the preceding claim, after the transfer of the substrate (3) onto the support (41), an application of a force transverse to the thickness dimension of the substrate (3) onto the support (41) so as to divide the substrate (3) into as many microelectronic devices (4) as there are closed contours formed by the trenches (32).

19. A method according to any one of claims 16 to 18, comprising, after thinning, forming a metallic coating (35) covering at least the top wall (322) and the side wall (320) of the trenches (32).

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