Reset circuit

Abstract

Reset circuit The present description relates to a reset circuit for an electronic device comprising at least two electronic components, said reset circuit comprising: - a parity check circuit (303); - at least two first flip-flops (350) each comprising an output connected to at least one of said at least two electronic components; - at least two second flip-flops (301-1, 301-2, 301-3) each comprising at least one output connected to an input of said parity check circuit (303). Figure for abstract: Fig. 3

Description

Title of invention: Reset circuit Technical field

[0001] The present description relates generally to electronic systems and devices, and more particularly to the security of electronic systems and devices. The present description relates more specifically to the protection of electronic systems and devices against attacks by resetting all or part of an electronic system or device. Prior art

[0002] Many complex or semi-complex electronic systems and / or devices include one or more circuits adapted to implement a reset of the system or device. A reset of a device corresponds to the total shutdown of all or part of the electronic components included in the system or device. In addition, a reset interrupts all current operations, clears all recorded errors and all current software events, and allows the system or device to be returned to a known initial state.

[0003] It would be desirable to be able to improve, at least in part, certain aspects of the reset circuits used in electronic devices. Summary of the invention

[0004] There is a need for more efficient reset circuits for electronic systems or devices.

[0005] There is a need for reset circuits for electronic systems or devices adapted to detect a partial reset attack.

[0006] One embodiment overcomes all or part of the drawbacks of known reset circuits of electronic systems or devices.

[0007] One embodiment provides a reset circuit adapted to detect a partial reset attack.

[0008] One embodiment provides a reset circuit comprising a circuit adapted to detect anomalies.

[0009] One embodiment provides a reset circuit for an electronic device comprising at least two electronic components, said reset circuit comprising: - a parity check circuit; - at least two first flip-flops each comprising an output connected to at least one of said at least two electronic components; - at least two second flip-flops each comprising at least one connected output to an input of said parity check circuit.

[0010] According to one embodiment, the circuit further comprises a control circuit adapted to provide a reset command, said at least two first and second flip-flops being adapted to be controlled by said reset signal.

[0011] According to one embodiment, said at least two first and second flip-flops comprise at least one reset input receiving the reset command.

[0012] According to one embodiment, said at least two second flip-flops each comprise at least one input adapted to receive a supply voltage.

[0013] According to one embodiment, each of said at least two second flip-flops is placed at a distance less than a critical distance from at least one of said at least two first flip-flops.

[0014] According to one embodiment, said critical distance is the minimum length of a metal track for which a pulse is recognizable as being a control pulse by said at least two first flip-flops.

[0015] According to one embodiment, said pulse is recognizable as being a control pulse if its time duration is greater than a minimum duration, and / or if the value of its amplitude is greater than a minimum value.

[0016] According to one embodiment, at least one of said at least two second flip-flops is associated with several of said at least two first flip-flops.

[0017] According to one embodiment, said at least two first and second flip-flops are D-type flip-flops.

[0018] Another embodiment provides an electronic device comprising a reset circuit described above.

[0019] Another embodiment provides a method for detecting a partial reset attack using a reset circuit described previously.

[0020] According to one embodiment, when said at least two second flip-flops have different states, then said parity check circuit signals an anomaly.

[0021] According to one embodiment, when said parity check circuit signals an anomaly, said control circuit requests a reset of said device. Brief description of the drawings

[0022] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0023] [Fig.l] represents, very schematically and in the form of blocks, an embodiment of an electronic device;

[0024] [Fig.2] represents, schematically and partially in block form, an embodiment of a reset circuit;

[0025] [Fig.3] represents, schematically and partially in the form of blocks, a part of the embodiment of [Fig.2]; and

[0026] [Fig.4] represents, schematically and partially in the form of blocks, a variant of a part of the embodiment of [Fig.2]. Description of the embodiments

[0027] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0028] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0029] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0030] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0031] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0032] The embodiments described below relate to the protection of electronic systems and devices against partial reset attacks. In the remainder of the description, a partial reset attack is an attack during which an external user, for example a malicious user, forces a component or part of an electronic system or device to reset. A user can take advantage of the particular architecture of a reset circuit of an electronic system or device, to induce a local reset command, for example by using a magnetic coupling phenomenon. Such an architecture is described in relation to [Fig.l].

[0033] The embodiments relate more particularly to a reset circuit adapted to detect a partial reset attack.

[0034] [Fig.l] represents, very schematically and in the form of blocks, a mode of rea- lization of an electronic device 100.

[0035] The electronic device 100 is a complex or semi-complex electronic device comprising at least two electronic components, generally more than two electronic components. More particularly, in [Fig.l], the device 100 comprises N electronic components 101-1, 101-2, ..., 101-N, N being an integer greater than or equal to two.

[0036] Each electronic component 101-1, 101-2, ..., 101-N may be a unitary electronic component, a set of unitary electronic components, a simple electronic circuit, a set of simple electronic circuits, a unitary electronic module, or a set of unitary electronic modules.

[0037] In addition, each electronic component 101-1, ..., 101-N comprises a reset terminal RST-1, ..., RST-N adapted to receive a reset command. In practice and according to one example, each electronic component 101-1, ..., 101-N may comprise a reset flip-flop whose reset terminal forms the reset terminal RST-1, ..., RST-N of the component 101-1, ..., 101-N.

[0038] The device 100 further comprises a reset circuit 102 (RESET) according to one embodiment. The role of the reset circuit is to manage a reset operation of the device 100. During such an operation, all the components 101-1, 101-2, ..., 101-N of the device 100 are reset. For this purpose, the reset circuit 102 comprises at least one input IN_RST, and as many outputs OUT1_RST, OUT2_RST, ..., OUTN_RST as there are electronic components 101-1, 101-2, ..., 101-N included in the electronic device 100, i.e. N outputs OUT1_RST, OUT2_RST, ..., OUTN_RST in [Fig.l]. An embodiment of a reset circuit 102 is described in connection with Figures 2-4.

[0039] The IN_RST input is adapted to receive a reset request that may come from different sources. According to a first example, a request source may be, for example, a power monitoring signal, a command given by a user of the device 100, an internal control signal of the device 100, etc. According to one example, the circuit 102 may comprise several inputs of the type of the IN_RST input, each input being adapted, for example, to receive a reset request from a particular source.

[0040] Each output OUT1_RST, OUT2_RST, ..., OUTN_RST is adapted to provide a reset command to a component 101-1, 101-2, ..., 101-N. According to an example, in [Fig.l], the output OUTi_RST is adapted to provide a reset command to the component 101-i, i being an integer varying between 1 and N.

[0041] More particularly, the reset circuit 102 comprises: - a control circuit 1021 (RST CMD); - an anomaly detection circuit 1022 (Anomalous Detectors); and - synchronization circuits 1023-1 (RST Syn-1), 1023-2 (RST Syn-2), 1023-N (RST Syn-N), for example as many synchronization circuits 1023-1 to 1023-N as electronic components included in the electronic device 100, i.e. N flip-flops 1023-1, 1023-2, ..., 1023-N in [Fig.2].

[0042] The control circuit 1021 (RST CMD) comprises at least a first input connected, preferably connected, to the input IN_RST of the reset circuit 102, and a second input receiving an anomaly detection signal Anom. According to one example, if the reset circuit 102 comprises several inputs of the type of the input IN_RST, the control circuit 1021 comprises several inputs, each connected, preferably connected, to an input of the type of the input IN_RST. The control circuit 102 further comprises an output adapted to provide a reset command CMD_RST. According to one example, the reset command CMD_RST is a control pulse, i.e. a signal having a rising edge then a falling edge for a given duration. The reset command CMD_RST is intended to be sent to the reset terminals RST-1 to RST-N of components 101-1 to 101-N.

[0043] The anomaly detection circuit 1022 (Anomalous Detect) is adapted to detect a reset command received by an electronic component different from the reset command CMD_RST. According to one embodiment, the anomaly detection circuit 1022 is particularly adapted to detect a false reset command, also called an anomaly, received by only one or part of the components 101-1, 101-2, ..., 101-N. According to one example, when the reset command CMD_RST is a control pulse, a false reset command can be a control pulse of shorter duration. The anomaly detection circuit 1022 is adapted to provide the anomaly detection signal Anom to the control circuit 1021. The anomaly detection circuit is described in more detail in relation to FIGS. 3 and 4.

[0044] The synchronization circuits 1023-1 to 1023-N are optional. Their purpose is to synchronize the reset command to ensure that all the components receive the reset command at the same time. Indeed, the different components 101-1, ..., 101-N can operate using different clock signals and / or using different power supply modes. If two components 101-1, ..., 101-N operate using the same clock signal and the same power supply mode, they can share a synchronization circuit 1023-1, ..., 1023-N. Each circuit 1023-1, 1023-2, ..., 1023-N is adapted to receive, as input, the reset command CMD_RST and to transmit it, as output, to an output OUT1_RST, OUT2_RST, ..., OUTN_RST. According to an example, in [Fig.l], the circuit 1023-i is adapted to provide the reset command at the output OUTi_RST, and therefore to provide the reset command to component 101 -i, i varying between 1 and N.

[0045] During a partial reset attack, a malicious user can, for example, inject a false reset command at one of the reset terminals RST-1 to RST-N of the electronic components 101-1 to 101-N. The anomaly detection circuit 1022 is adapted to detect such a false command.

[0046] [Fig. 2] shows, schematically but in more detail, a reset circuit 200 of the type of the reset circuit 100 described in relation to [Fig. 1]. [Fig. 2] illustrates, more particularly and in more detail, a control circuit of the type of the control circuit 1021 described in relation to [Fig. 1].

[0047] As described in relation to [Fig.l], the reset circuit 200 comprises an anomaly detection circuit 201 of the type of the anomaly detection circuit 1022 described in relation to [Fig.l], and flip-flops 202-1, 202-2, ..., 202-N of the type of the flip-flops forming the reset terminal of the components 101-1 to 101-N described in relation to [Fig.l]. The anomaly detection circuit 1022 provides an anomaly detection signal Anom. The flip-flops 202-1, 202-2, ..., 202-N are connected, preferably connected, to outputs of the reset circuit 200 not shown in [Fig.2],

[0048] The other components and circuits described below are part of the control circuit of the reset circuit 200.

[0049] The control circuit comprises a logic gate 203 (OR) of the OR type adapted to receive, as input, the signal Anom, and reset requests Reql, ..., ReqK coming from sources internal to the device comprising the circuit 200. According to one example, in [Fig.2], the control circuit is adapted to receive K reset requests from internal sources, K being an integer greater than or equal to one. Here, a reset request having an internal source is called a reset request coming from a component of the device comprising the circuit 200. The logic gate 203 provides, as output, a signal 203_OUT corresponding to a first version of the reset command provided at the output of the control circuit. According to one example, the signal 203_OUT has a control pulse when one of the signals received at the input of the gate 203 has a control pulse.

[0050] The control circuit further comprises, optionally, a duration adjustment circuit 204 (An Stretch) adapted to receive, as input, the signal 203_OUT, and to provide, as output, a signal 204_OUT corresponding to a second version of the reset command provided as output of the control circuit. The duration adjustment circuit 204 makes it possible to carry out a temporal extension and / or compression of the signal 203_OUT that it receives as input. According to one example, the circuit 204 makes it possible to lengthen the duration of a control pulse transferred by the signal 203_OUT.

[0051] The control circuit further comprises a transistor T and a resistor R. The transistor T and the resistor R are arranged in series between a node for applying a supply voltage VDD and a node receiving a reference voltage, for example ground. More particularly, a first terminal of the resistor R is connected, preferably connected, to the node receiving the supply voltage VDD, and a second terminal of the resistor R is connected, preferably connected, to a first conduction terminal of the transistor T. A second conduction terminal of the transistor T is connected, preferably connected, to the node receiving the reference voltage. The control terminal of the transistor T receives the signal 204_OUT. According to one example, the transistor T is an N-channel metal-oxide gate field effect transistor, or NMOS transistor.

[0052] The middle node between transistor T and resistor R is connected to a node A. According to one example, node A is accessible to a user and can allow an external reset command to be sent.

[0053] The control circuit further comprises a buffer circuit 205 and an inverter circuit 206. An input of the buffer circuit is connected, preferably connected, to node A, and an output of the buffer circuit 205 is connected, preferably connected, to the input of the inverter circuit 206.

[0054] The control circuit further comprises a gate 207 (OR) of the OR type comprising two inputs. A first input is connected, preferably connected, to the output of the duration adjustment circuit 204, and therefore receives the signal 204_OUT. A second input is connected, preferably connected, to the output of the inverter circuit 206. The gate 207 further comprises an output providing a signal 207_OUT corresponding to a reset command.

[0055] The control circuit further comprises, optionally, a filtering circuit 208 (Spike Filt) adapted to receive, as input, the signal 207_OUT, and to provide, as output, a signal corresponding to the filtered reset command RST_CMD. According to one example, the filtering circuit 208 has the role of filtering the voltage spikes of too short duration present on the signal corresponding to the reset command CMD_RST.

[0056] The reset command CMD_RST is then supplied to all flip-flops 202-1, 202-2, ..., 202-N.

[0057] [Fig. 3] shows, schematically but in more detail, a part of a reset circuit of the type of the reset circuits 100 and 200 described in relation to Figures 1 and 2. [Fig. 3] illustrates, more particularly and in more detail, an anomaly detection circuit 300 of the type of the anomaly detection circuits 1022 and 201 described in relation to Figures 1 and 2. [Fig. 3] further illustrates flip-flops 350 of the reset circuit of the flip-flop type forming the reset terminal of the components 101-1, 101-2, 101-N and the flip-flops 202-1, 202-2, ..., 202-N described in relation to figures 1 and 2.

[0058] The anomaly detection circuit 300 comprises flip-flops of the same type as the flip-flops 350 of the reset circuit comprising the anomaly detection circuit 300. In the example shown in [Fig. 3], the anomaly detection circuit 300 comprises three flip-flops 301-1, 301-2 and 301-3. But more generally, the anomaly detection circuit 300 comprises M flip-flops, M being an integer greater than or equal to zero. According to one embodiment, M is less than or equal to the number of flip-flops 350 included in the reset circuit comprising the circuit 300. According to a preferred embodiment, M is equal to the number of flip-flops 350. Furthermore, in the example of [Fig. 3], the flip-flops 350 are four in number and are hatched.

[0059] According to one embodiment, the flip-flops 301-1 to 301-3 are arranged in the device comprising the reset circuit so as to be physically close to the flip-flops 350. Unlike the flip-flops 350, the flip-flops 301-1 to 301-3 are not associated with a component of the electronic device, but with one or more flip-flops 350. The role of a flip-flop 301-1 to 301-3 is to be close enough to a flip-flop 350 to receive a false reset command, or anomaly, at the same time as a flip-flop 350. In particular, a false reset command can be sent to a flip-flop 350 using a magnetic coupling phenomenon at the metal track providing the reset command to the flip-flop 350, a flip-flop 301-1 to 301-3 arranged close enough to the flip-flop 350 can thus be capable of receiving this same false command. reset.

[0060] According to one embodiment, each flip-flop 301-1 to 301-3 is arranged at a distance L, or length L, from one or more flip-flops 350, this distance being less than a critical distance Lcrit, or critical length Lcrit, so that a flip-flop 301-1 to 301-3 is considered close enough to a flip-flop 350. The critical distance Lcrit is defined as being the minimum distance from a metal track for which a control pulse of the reset command is recognizable as being a control pulse by the flip-flop. Here, a control pulse is a signal having a rising edge then a falling edge for a given duration, and whose duration is long enough to initiate the resetting of the flip-flop. It is also said that a control pulse is not recognizable by a flip-flop if its time duration is too short and / or if the value of its amplitude is not high enough to be detected.In other words, a pulse is recognizable as a control pulse if its time duration is greater than a minimum duration Tmin, and / or if the value of its amplitude is greater than a minimum value Vmin. For example, the duration . minimum Tmin is between 1 and 300 ps. For example, a control pulse may not be recognizable due to degradation of the metal track transmitting it.

[0061] According to one example, flip-flops 301-1 to 301-3 and flip-flops 350 are D-type flip-flops, i.e. flip-flops comprising: - a data reception terminal D; - an output Q terminal; - an inverted output terminal NQ, not shown in [Fig.3]; - a CK clock terminal; - a RESET reset terminal.

[0062] The RESET terminals of flip-flops 301-1 to 301-3 and flip-flops 350 are all adapted to receive a signal corresponding to the reset command CMD_RST defined previously.

[0063] Terminal D of each flip-flop 301-1 to 301-3 is adapted to receive a supply voltage VDD whose amplitude value corresponds to a high value for terminal D. In other words, the data received on terminal D is a logic "1".

[0064] The terminals D, Q and CK of the flip-flops 350 are, according to one example, connected to the components of the device with which the flip-flops 350 are associated, as described in relation to [Fig.l].

[0065] The anomaly detection circuit 300 further comprises a clock circuit 302 (CK Gen) adapted to provide a signal CK_Sig to the terminals CK of the flip-flops 301-1 to 301-3 of the anomaly detection circuit 300. More particularly, a rising edge of the signal CK_Sig is generated at each falling edge of the reset signal CMD_RST. The purpose of the signal CK_Sig is therefore to prepare the flip-flops 301-1 to 301-3 for the next reset.

[0066] The anomaly detection circuit 300 further comprises a parity check circuit 303 (PAR. CHECK) adapted to receive as input the outputs of all the flip-flops 301-1 to 301-3 of the anomaly detection circuit 300, and to provide as output an anomaly detection signal Anom. The role of the circuit 303 is to verify that all the outputs of the flip-flops 301-1 to 301-3 are equal. According to a preferred embodiment, the parity check circuit 303 is an architecture comprising logic gates of the EXCLUSIVE OR type, said architecture comprising M inputs, each input being connected, preferably connected, to an output Q of one of the M flip-flops 301-1 to 301-3.

[0067] The operation of the anomaly detection circuit 300 is as follows.

[0068] When the control circuit of the reset circuit requests a reset of the device, a reset command CMD_RST is sent to the RESET terminals of the flip-flops 350. All the flip-flops 301-1 to 301-3 also receive this command and their outputs remain at the same state. The circuit of parity check does not detect any difference, and the Anom signal does not indicate any anomalies. The reset process can continue without incident.

[0069] When a partial reset attack is executed, a false reset command is sent to the RESET terminal of one or more flip-flops 350. The flip-flop(s) 301-1 to 301-3 physically closest to the flip-flop 350 receiving the false command also receives this false command and has its output modified. The parity check circuit detects that one or more outputs of the flip-flops 301-1 to 301-3 are different from the other outputs, and the signal Anom indicates that an anomaly has been detected. In other words, the parity check circuit detects that the flip-flops 301-1 to 301-3 have different states, i.e., at least one of the flip-flops 301-1 to 301-3 has a different state from the others. According to one example, the control circuit of the reset circuit may request a reset of the device.

[0070] [Fig. 4] shows, schematically and in block form, an example of arrangement of flip-flops 401 of an anomaly detection circuit of the type of the anomaly description circuit 300 described in relation to [Fig. 3] and another example of embodiment of a parity check circuit of the type of the circuit 303 described in relation to [Fig. 3]. [Fig. 4] further illustrates hatched flip-flops 402 forming the reset terminals of the components 101-1 to 101-N.

[0071] In this example, the flip-flops 402 are arranged in the form of several branches having a common end. Each branch comprises one or more flip-flops 402. In the example of [Fig. 4], the flip-flops 402 are arranged in the form of three branches A, B and C. In practice, the different branches are metal tracks connected to the reset terminals of the flip-flops 402. In practice, each branch A, B, C can correspond to a domain or to a group of components of the electronic device comprising the anomaly detection circuit.

[0072] According to one embodiment, the flip-flops 401 are arranged in the following manner. Each branch of flip-flops 402 is associated with two flip-flops 401. A first flip-flop 401 is arranged on the side of a first end of the branch, and a second flip-flop is arranged on the side of a second end of the branch. In other words, the two flip-flops 401 are arranged on either side of the flip-flops 402 of the same branch.

[0073] Furthermore, according to one example, the parity circuit of the anomaly detection circuit is composed of several logic gates of the EXCLUSIVE OR type, each associated with a branch. In the example of [Fig. 4], the parity circuit comprises three logic gates 403-A, 403-B and 403-C, associated, respectively, with branches A, B and C. Each logic gate 403-A, 403-B and 403-C is adapted to receive as input the outputs of the flip-flops 401 of the branch A, B or C to which the logic gate is associated. Each logic gate 403-A, 403-B and 403-C is adapted to provide as output an anomaly signal Anom-A, Anom-B, Anom-C which can be sent to the control circuit of the reset circuit.

[0074] According to an alternative embodiment, the anomaly signals Anom-A, Anom-B, Anom-C are combined to provide only a single anomaly signal to the control circuit of the reset circuit.

[0075] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will occur to those skilled in the art. In particular, those skilled in the art will know how to choose the number of flip-flops included in the anomaly detection circuit based on various parameters. The greater the number of flip-flops, the more accurate the anomaly detection. The smaller the number of flip-flops, the more the cost and size of the anomaly detection circuit are minimized.

[0076] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. Reset circuit (102; 200) of an electronic device (100) comprising at least two electronic components (101-1, 101-2, ..., 101-N), said reset circuit (102; 200) comprising: - a parity check circuit (303; 403-A, 403-B, 403-C); - at least two first flip-flops (202-1, 202-2, ..., 202-N; 350; 402) each comprising an output connected to at least one of said at least two electronic components (101-1, 101-2, ..., 101-N); - at least two second flip-flops (301-1, 301-2, 301-3; 401) each comprising at least one output connected to an input of said parity check circuit (303; 403-A, 403-B, 403-C), each of said at least two second flip-flops (301-1, 301-2, 301-3; 401) being placed at a distance (L) less than a critical distance (Lcrit) from at least one of said at least two first flip-flops (202-1, 202-2, ..., 202-N; 350; 402), said critical distance (Lcrit) being the minimum length of a metal track for which a pulse is recognizable as being a control pulse by said at least two first flip-flops (202-1, 202-2, ..., 202-N; 350; 402).

2. Circuit according to claim 1, further comprising a control circuit (1021) adapted to provide a reset command (CMD_RST), said at least two first and second flip-flops being adapted to be controlled by said reset signal.

3. Circuit according to claim 2, wherein said at least two first and second flip-flops (202-1, 202-2, ..., 202-N; 301-1, 301-2, 301-3, 350; 401, 402) comprise at least one reset input (RESET) receiving the reset command (CMD_RST).

4. Circuit according to any one of claims 1 to 3, wherein said at least two second flip-flops (301-1, 301-2, 301-3; 401) each comprise at least one input (D) adapted to receive a supply voltage (VDD).

5. Circuit according to any one of claims 1 to 4, wherein said pulse is recognizable as being a control pulse if its time duration is greater than a minimum duration (Tmin), and / or if the value of its amplitude is greater than a minimum value (Vmin).

6. Circuit according to any one of claims 1 to 5, wherein at least one of said at least two second flip-flops (301-1, 301-2, 301-3; 401) is associated with several of said at least two first flip-flops (202-1, 202-2, ..., 202-N; 350; 402).

7. A circuit according to any one of claims 1 to 6, wherein said at least two first and second flip-flops (202-1, 202-2, ..., 202-N; 301-1, 301-2, 301-3, 350; 401, 402) are D-type flip-flops.

8. An electronic device comprising a reset circuit according to any one of claims 1 to 7.

9. A method of detecting a partial reset attack using a reset circuit according to any one of claims 1 to 7

10. d / . Method according to claim 9, wherein when said at least two second flip-flops (301-1, 301-2, 301-3; 401) have different states, then said parity check circuit (303; 403-A, 403-B, 403-C) signals an anomaly.

11. The method of claim 10, wherein when said parity check circuit (303; 403-A, 403-B, 403-C) signals an anomaly, said control circuit requests a reset of said device.

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